// ***** BEGIN LICENSE BLOCK *****  
// Source last modified: $Id: sbrqmfsk.s,v 1.1 2005/02/26 01:47:35 jrecker Exp $ 
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#define   CPTR        r0
#define DELAY       r1
#define DIDX        r2
#define OUTBUF      r3
#define K           r4
#define DOFF0       r5
#define DOFF1       r6
#define SUMLO       r7
#define SUMHI       r8
#define NCHANS      r9
#define COEF0       r10
#define DVAL0       r11
#define COEF1       r12
#define DVAL1       r14

#define RND_VAL  4

// void QMFSynthesisConv(int *cPtr, int *delay, int dIdx, short *outbuf, int nChans);
//   see comments in sbrqmf.c

        PUBLIC raac_QMFSynthesisConv
raac_QMFSynthesisConv:
  //bx lr
        stmfd   sp!, {r4-r11, r14}

        ldr     NCHANS,  [r13, #4*9]    // we saved 9 registers on stack
        mov     DOFF0, DIDX, lsl #7 // dOff0 = 128*dIdx
        subs    DOFF1, DOFF0, #1    // dOff1 = dOff0 - 1
        addlt   DOFF1, DOFF1, #1280 // if (dOff1 < 0) then dOff1 += 1280
        mov K, #64

SRC_Loop_Start:
        ldr     COEF0, [CPTR], #4
        ldr     COEF1, [CPTR], #4
        ldr     DVAL0, [DELAY, DOFF0, lsl #2]
        ldr     DVAL1, [DELAY, DOFF1, lsl #2]
        smull   SUMLO, SUMHI, COEF0, DVAL0
        subs    DOFF0, DOFF0, #256
        addlt   DOFF0, DOFF0, #1280
        smlal   SUMLO, SUMHI, COEF1, DVAL1
        subs    DOFF1, DOFF1, #256
        addlt   DOFF1, DOFF1, #1280

        ldr     COEF0, [CPTR], #4
        ldr     COEF1, [CPTR], #4
        ldr     DVAL0, [DELAY, DOFF0, lsl #2]
        ldr     DVAL1, [DELAY, DOFF1, lsl #2]
        smlal   SUMLO, SUMHI, COEF0, DVAL0
        subs    DOFF0, DOFF0, #256
        addlt   DOFF0, DOFF0, #1280
        smlal   SUMLO, SUMHI, COEF1, DVAL1
        subs    DOFF1, DOFF1, #256
        addlt   DOFF1, DOFF1, #1280

        ldr     COEF0, [CPTR], #4
        ldr     COEF1, [CPTR], #4
        ldr     DVAL0, [DELAY, DOFF0, lsl #2]
        ldr     DVAL1, [DELAY, DOFF1, lsl #2]
        smlal   SUMLO, SUMHI, COEF0, DVAL0
        subs    DOFF0, DOFF0, #256
        addlt   DOFF0, DOFF0, #1280
        smlal   SUMLO, SUMHI, COEF1, DVAL1
        subs    DOFF1, DOFF1, #256
        addlt   DOFF1, DOFF1, #1280

        ldr     COEF0, [CPTR], #4
        ldr     COEF1, [CPTR], #4
        ldr     DVAL0, [DELAY, DOFF0, lsl #2]
        ldr     DVAL1, [DELAY, DOFF1, lsl #2]
        smlal   SUMLO, SUMHI, COEF0, DVAL0
        subs    DOFF0, DOFF0, #256
        addlt   DOFF0, DOFF0, #1280
        smlal   SUMLO, SUMHI, COEF1, DVAL1
        subs    DOFF1, DOFF1, #256
        addlt   DOFF1, DOFF1, #1280

        ldr     COEF0, [CPTR], #4
        ldr     COEF1, [CPTR], #4
        ldr     DVAL0, [DELAY, DOFF0, lsl #2]
        ldr     DVAL1, [DELAY, DOFF1, lsl #2]
        smlal   SUMLO, SUMHI, COEF0, DVAL0
        subs    DOFF0, DOFF0, #256
        addlt   DOFF0, DOFF0, #1280
        smlal   SUMLO, SUMHI, COEF1, DVAL1
        subs    DOFF1, DOFF1, #256
        addlt   DOFF1, DOFF1, #1280

        add     DOFF0, DOFF0, #1
        sub     DOFF1, DOFF1, #1
        
        add     SUMHI, SUMHI, #RND_VAL
        mov     SUMHI, SUMHI, asr #3
        mov     SUMLO, SUMHI, asr #31
        cmp     SUMLO, SUMHI, asr #15
        eorne   SUMHI, SUMLO, #0x7f00   // takes 2 instructions for immediate value of 0x7fffffff
        eorne   SUMHI, SUMHI, #0x00ff
        strh    SUMHI, [OUTBUF, #0]
        add     OUTBUF, OUTBUF, NCHANS, lsl #1
   
        subs    K, K, #1
        bne     SRC_Loop_Start

        ldmfd   sp!, {r4-r11, pc}