// ***** BEGIN LICENSE BLOCK *****  
// Source last modified: $Id: sbrqmfak.s,v 1.1 2005/02/26 01:47:35 jrecker Exp $ 
// 
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#define CPTR0       r0
#define DELAY       r1
#define DIDX        r2
#define UBUF        r3
#define CPTR1       r4
#define K           r5
#define DOFF        r6
#define ULO0        r7
#define UHI0        r8
#define ULO1        r9
#define UHI1        r10
#define COEF0       r11
#define DVAL0       r12
#define COEF1       r14
#define DVAL1       r2   // overlay with DIDX

//void QMFAnalysisConv(int *cTab, int *delay, int dIdx, int *uBuf)
//   see comments in sbrqmf.c

        PUBLIC raac_QMFAnalysisConv
raac_QMFAnalysisConv:
  
        stmfd   sp!, {r4-r11, r14}

        mov     DOFF, DIDX, lsl #5      // dOff0 = 32*dIdx
        add     DOFF, DOFF, #31         // dOff0 = 32*dIdx + 31
        add     CPTR1, CPTR0, #4*(164)  // cPtr1 = cPtr0 + 164
        
        // special first pass (flip sign for cTab[384], cTab[512])
        ldr     COEF0, [CPTR0], #4
        ldr     COEF1, [CPTR0], #4
        ldr     DVAL0, [DELAY, DOFF, lsl #2]
        subs    DOFF, DOFF, #32
        addlt   DOFF, DOFF, #320
        ldr     DVAL1, [DELAY, DOFF, lsl #2]
        subs    DOFF, DOFF, #32
        addlt   DOFF, DOFF, #320
        smull   ULO0, UHI0, COEF0, DVAL0
        smull   ULO1, UHI1, COEF1, DVAL1

        ldr     COEF0, [CPTR0], #4
        ldr     COEF1, [CPTR0], #4
        ldr     DVAL0, [DELAY, DOFF, lsl #2]
        subs    DOFF, DOFF, #32
        addlt   DOFF, DOFF, #320
        ldr     DVAL1, [DELAY, DOFF, lsl #2]
        subs    DOFF, DOFF, #32
        addlt   DOFF, DOFF, #320
        smlal   ULO0, UHI0, COEF0, DVAL0
        smlal   ULO1, UHI1, COEF1, DVAL1

        ldr     COEF0, [CPTR0], #4
        ldr     COEF1, [CPTR1], #-4
        ldr     DVAL0, [DELAY, DOFF, lsl #2]
        subs    DOFF, DOFF, #32
        addlt   DOFF, DOFF, #320
        ldr     DVAL1, [DELAY, DOFF, lsl #2]
        subs    DOFF, DOFF, #32
        addlt   DOFF, DOFF, #320
        smlal   ULO0, UHI0, COEF0, DVAL0
        smlal   ULO1, UHI1, COEF1, DVAL1

        ldr     COEF0, [CPTR1], #-4
        ldr     COEF1, [CPTR1], #-4
        ldr     DVAL0, [DELAY, DOFF, lsl #2]
        subs    DOFF, DOFF, #32
        addlt   DOFF, DOFF, #320
        ldr     DVAL1, [DELAY, DOFF, lsl #2]
        subs    DOFF, DOFF, #32
        addlt   DOFF, DOFF, #320
        rsb     COEF0, COEF0, #0
        smlal   ULO0, UHI0, COEF0, DVAL0
        smlal   ULO1, UHI1, COEF1, DVAL1

        ldr     COEF0, [CPTR1], #-4
        ldr     COEF1, [CPTR1], #-4
        ldr     DVAL0, [DELAY, DOFF, lsl #2]
        subs    DOFF, DOFF, #32
        addlt   DOFF, DOFF, #320
        ldr     DVAL1, [DELAY, DOFF, lsl #2]
        subs    DOFF, DOFF, #32
        addlt   DOFF, DOFF, #320
        rsb     COEF0, COEF0, #0
        smlal   ULO0, UHI0, COEF0, DVAL0
        smlal   ULO1, UHI1, COEF1, DVAL1

        str     UHI1, [UBUF, #4*32]
        str     UHI0, [UBUF], #4
        sub     DOFF, DOFF, #1
        mov     K, #31

SRC_Loop_Startfak:
        ldr     COEF0, [CPTR0], #4
        ldr     COEF1, [CPTR0], #4
        ldr     DVAL0, [DELAY, DOFF, lsl #2]
        subs    DOFF, DOFF, #32
        addlt   DOFF, DOFF, #320
        ldr     DVAL1, [DELAY, DOFF, lsl #2]
        subs    DOFF, DOFF, #32
        addlt   DOFF, DOFF, #320
        smull   ULO0, UHI0, COEF0, DVAL0
        smull   ULO1, UHI1, COEF1, DVAL1

        ldr     COEF0, [CPTR0], #4
        ldr     COEF1, [CPTR0], #4
        ldr     DVAL0, [DELAY, DOFF, lsl #2]
        subs    DOFF, DOFF, #32
        addlt   DOFF, DOFF, #320
        ldr     DVAL1, [DELAY, DOFF, lsl #2]
        subs    DOFF, DOFF, #32
        addlt   DOFF, DOFF, #320
        smlal   ULO0, UHI0, COEF0, DVAL0
        smlal   ULO1, UHI1, COEF1, DVAL1

        ldr     COEF0, [CPTR0], #4
        ldr     COEF1, [CPTR1], #-4
        ldr     DVAL0, [DELAY, DOFF, lsl #2]
        subs    DOFF, DOFF, #32
        addlt   DOFF, DOFF, #320
        ldr     DVAL1, [DELAY, DOFF, lsl #2]
        subs    DOFF, DOFF, #32
        addlt   DOFF, DOFF, #320
        smlal   ULO0, UHI0, COEF0, DVAL0
        smlal   ULO1, UHI1, COEF1, DVAL1

        ldr     COEF0, [CPTR1], #-4
        ldr     COEF1, [CPTR1], #-4
        ldr     DVAL0, [DELAY, DOFF, lsl #2]
        subs    DOFF, DOFF, #32
        addlt   DOFF, DOFF, #320
        ldr     DVAL1, [DELAY, DOFF, lsl #2]
        subs    DOFF, DOFF, #32
        addlt   DOFF, DOFF, #320
        smlal   ULO0, UHI0, COEF0, DVAL0
        smlal   ULO1, UHI1, COEF1, DVAL1

        ldr     COEF0, [CPTR1], #-4
        ldr     COEF1, [CPTR1], #-4
        ldr     DVAL0, [DELAY, DOFF, lsl #2]
        subs    DOFF, DOFF, #32
        addlt   DOFF, DOFF, #320
        ldr     DVAL1, [DELAY, DOFF, lsl #2]
        subs    DOFF, DOFF, #32
        addlt   DOFF, DOFF, #320
        smlal   ULO0, UHI0, COEF0, DVAL0
        smlal   ULO1, UHI1, COEF1, DVAL1

        str     UHI1, [UBUF, #4*32]
        str     UHI0, [UBUF], #4
        sub     DOFF, DOFF, #1
        
        subs    K, K, #1
        bne     SRC_Loop_Startfak

        ldmfd   sp!, {r4-r11, pc}