; ; This file defines SFR names and bit names for Microchip's PIC18 processors. ; ; This file can be configured for different devices. ; At the beginning of the file there are definitions common for all devices ; Device-specific definitions are introduced by ; ; .devicename ; ; line. Also an optional directive ; ; .default devicename ; ; designates the default device name. ; .default 16C61 .16C432 ; http://www.microchip.com/download/lit/pline/picmicro/families/16c43x/41140a.pdf ; PIC16C432.pdf ; MEMORY MAP ; BANK_0 area DATA FSR_ 0x0000:0x0020 area DATA Gen_Purp 0x0020:0x0080 General Purpose Register area DATA MEM_Program 0x0080:0x0800 On-chip Program Memory ; BANK_1 ; area DATA FSR_ 0x0080:0x00A0 ; area DATA Gen_Purp 0x00A0:0x00C0 General Purpose Register ; area BSS RESERVED 0x00C0:0x00F0 ; area DATA Gen_Purp_BANK0 0x00F0:0x0100 Accesses 70h-7Fh ; area DATA MEM_Program 0x0100:0x0800 On-chip Program Memory ; Interrupt and reset vector assignments interrupt RESET 0x0000 RESET ; INPUT/OUTPUT PORTS ; BANK0 (0x0000:0x0080) BANK0:INDF 0x0000 INDF (not a physical register) BANK0:TMR0 0x0001 Timer0 Module's Register BANK0:PCL 0x0002 Program Counter's (PC) Least Significant Byte BANK0:STATUS 0x0003 STATUS REGISTER BANK0:STATUS.RP0 5 Register Bank Select bit 0 BANK0:STATUS.TO 4 Time-out bit BANK0:STATUS.PD 3 Power-down bit BANK0:STATUS.Z 2 Zero bit BANK0:STATUS.DC 1 Digit carry/borrow bit BANK0:STATUS.C 0 Carry/borrow bit BANK0:FSR 0x0004 Indirect data memory address pointer BANK0:PORTA 0x0005 PORTA REGISTER BANK0:PORTA.RA4 4 PORTA bit 4 BANK0:PORTA.RA3 3 PORTA bit 3 BANK0:PORTA.RA2 2 PORTA bit 2 BANK0:PORTA.LINRX 1 LIN bus Receive pin BANK0:PORTA.RA0 0 PORTA bit 0 BANK0:PORTB 0x0006 PORTB REGISTER BANK0:PORTB.RB7 7 PORTB bit 7 BANK0:PORTB.RB6 6 PORTB bit 6 BANK0:PORTB.RB5 5 PORTB bit 5 BANK0:PORTB.RB4 4 PORTB bit 4 BANK0:PORTB.RB3 3 PORTB bit 3 BANK0:PORTB.RB2 2 PORTB bit 2 BANK0:PORTB.RB1 1 PORTB bit 1 BANK0:PORTB.RB0 0 PORTB bit 0 BANK0:RESERVED0007 0x0007 RESERVED BANK0:RESERVED0008 0x0008 RESERVED BANK0:RESERVED0009 0x0009 RESERVED BANK0:PCLATH 0x000A Write buffer for upper 5 bits of program counter BANK0:INTCON 0x000B INTCON REGISTER BANK0:INTCON.GIE 7 Global Interrupt Enable bit BANK0:INTCON.PEIE 6 Peripheral Interrupt Enable bit BANK0:INTCON.T0IE 5 TMR0 Overflow Interrupt Enable bit BANK0:INTCON.INTE 4 RB0/INT External Interrupt Enable bit BANK0:INTCON.RBIE 3 RB Port Change Interrupt Enable bit BANK0:INTCON.T0IF 2 TMR0 Overflow Interrupt Flag bit BANK0:INTCON.INTF 1 RB0/INT External Interrupt Flag bit BANK0:INTCON.RBIF 0 RB Port Change Interrupt Flag bit BANK0:PIR1 0x000C PIR1 REGISTER BANK0:PIR1.CMIF 6 Comparator Interrupt Flag bit BANK0:RESERVED000D 0x000D RESERVED BANK0:RESERVED000E 0x000E RESERVED BANK0:RESERVED000F 0x000F RESERVED BANK0:RESERVED0010 0x0010 RESERVED BANK0:RESERVED0011 0x0011 RESERVED BANK0:RESERVED0012 0x0012 RESERVED BANK0:RESERVED0013 0x0013 RESERVED BANK0:RESERVED0014 0x0014 RESERVED BANK0:RESERVED0015 0x0015 RESERVED BANK0:RESERVED0016 0x0016 RESERVED BANK0:RESERVED0017 0x0017 RESERVED BANK0:RESERVED0018 0x0018 RESERVED BANK0:RESERVED0019 0x0019 RESERVED BANK0:RESERVED001A 0x001A RESERVED BANK0:RESERVED001B 0x001B RESERVED BANK0:RESERVED001C 0x001C RESERVED BANK0:RESERVED001D 0x001D RESERVED BANK0:RESERVED001E 0x001E RESERVED BANK0:CMCON 0x001F CMCON REGISTER BANK0:CMCON.C2OUT 7 Comparator 2 Output BANK0:CMCON.C1OUT 6 Comparator 1 Output BANK0:CMCON.CIS 3 Comparator Input Switch BANK0:CMCON.CM2 2 Comparator Mode 2 BANK0:CMCON.CM1 1 Comparator Mode 1 BANK0:CMCON.CM0 0 Comparator Mode 0 ; BANK1 (0x0080:0x0100) BANK1:INDF 0x0080 INDF (not a physical register) BANK1:OPTION 0x0081 OPTION REGISTER BANK1:OPTION.RBPU 7 PORTB Pull-up Enable bit BANK1:OPTION.INTEDG 6 Interrupt Edge Select bit BANK1:OPTION.T0CS 5 TMR0 Clock Source Select bit BANK1:OPTION.T0SE 4 TMR0 Source Edge Select bit BANK1:OPTION.PSA 3 Prescaler Assignment bit BANK1:OPTION.PS2 2 Prescaler Rate Select bit 2 BANK1:OPTION.PS1 1 Prescaler Rate Select bit 1 BANK1:OPTION.PS0 0 Prescaler Rate Select bit 0 BANK1:PCL 0x0082 Program Counter's (PC) Least Significant Byte BANK1:STATUS 0x0083 STATUS REGISTER BANK1:STATUS.RP1 6 Register Bank Select bit 1 BANK1:STATUS.RP0 5 Register Bank Select bit 0 BANK1:STATUS.TO 4 Time-out bit BANK1:STATUS.PD 3 Power-down bit BANK1:STATUS.Z 2 Zero bit BANK1:STATUS.DC 1 Digit carry/borrow bit BANK1:STATUS.C 0 Carry/borrow bit BANK1:FSR 0x0084 Indirect data memory address pointer BANK1:TRISA 0x0085 TRISA REGISTER BANK1:TRISA.TRISA4 4 TRISA bit 4 BANK1:TRISA.TRISA3 3 TRISA bit 3 BANK1:TRISA.TRISA2 2 TRISA bit 2 BANK1:TRISA.TLINRX 1 TLINRX must set to '1' at all times BANK1:TRISA.TRISA0 0 TRISA bit 0 BANK1:TRISB 0x0086 TRISB REGISTER BANK1:TRISB.TRISB7 7 TRISB bit 7 BANK1:TRISB.TRISB6 6 TRISB bit 6 BANK1:TRISB.TRISB5 5 TRISB bit 5 BANK1:TRISB.TRISB4 4 TRISB bit 4 BANK1:TRISB.TRISB3 3 TRISB bit 3 BANK1:TRISB.TRISB2 2 TRISB bit 2 BANK1:TRISB.TRISB1 1 TRISB bit 1 BANK1:TRISB.TRISB0 0 TRISB bit 0 BANK1:RESERVED0087 0x0087 RESERVED BANK1:RESERVED0088 0x0088 RESERVED BANK1:RESERVED0089 0x0089 RESERVED BANK1:PCLATH 0x008A Write buffer for upper 5 bits of program counter BANK1:INTCON 0x008B INTCON REGISTER BANK1:INTCON.GIE 7 Global Interrupt Enable bit BANK1:INTCON.PEIE 6 Peripheral Interrupt Enable bit BANK1:INTCON.T0IE 5 TMR0 Overflow Interrupt Enable bit BANK1:INTCON.INTE 4 RB0/INT External Interrupt Enable bit BANK1:INTCON.RBIE 3 RB Port Change Interrupt Enable bit BANK1:INTCON.T0IF 2 TMR0 Overflow Interrupt Flag bit BANK1:INTCON.INTF 1 RB0/INT External Interrupt Flag bit BANK1:INTCON.RBIF 0 RB Port Change Interrupt Flag bit BANK1:PIE1 0x008C PIE1 REGISTER BANK1:PIE1.CMIE 6 Comparator Interrupt Flag bit BANK1:RESERVED008D 0x008D RESERVED BANK1:PCON 0x008E PCON REGISTER BANK1:PCON.POR 1 Power-on Reset Status bit BANK1:PCON.BOD 0 Brown-out Reset Status bit BANK1:RESERVED008F 0x008F RESERVED BANK1:LININTF 0x0090 LININTF REGISTER BANK1:LININTF.LINTX 1 BANK1:LININTF.LINV 0 BANK1:RESERVED0091 0x0091 RESERVED BANK1:RESERVED0092 0x0092 RESERVED BANK1:RESERVED0093 0x0093 RESERVED BANK1:RESERVED0094 0x0094 RESERVED BANK1:RESERVED0095 0x0095 RESERVED BANK1:RESERVED0096 0x0096 RESERVED BANK1:RESERVED0097 0x0097 RESERVED BANK1:RESERVED0098 0x0098 RESERVED BANK1:RESERVED0099 0x0099 RESERVED BANK1:RESERVED009A 0x009A RESERVED BANK1:RESERVED009B 0x009B RESERVED BANK1:RESERVED009C 0x009C RESERVED BANK1:RESERVED009D 0x009D RESERVED BANK1:RESERVED009E 0x009E RESERVED BANK1:VRCON 0x009F VRCON REGISTER BANK1:VRCON.VREN 7 VREF Enable BANK1:VRCON.VROE 6 VREF Output Enable BANK1:VRCON.VRR 5 VREF Range Selection BANK1:VRCON.VR3 3 VREF Value Selection 3 BANK1:VRCON.VR2 2 VREF Value Selection 2 BANK1:VRCON.VR1 1 VREF Value Selection 1 BANK1:VRCON.VR0 0 VREF Value Selection 0 .16C433 ; http://www.microchip.com/download/lit/pline/picmicro/families/16c43x/41139a.pdf ; PIC16C433.pdf ; MEMORY MAP ; BANK_0 area DATA FSR_ 0x0000:0x0020 area DATA Gen_Purp 0x0020:0x0080 General Purpose Register area DATA MEM_Program 0x0080:0x0800 On-chip Program Memory ; BANK_1 ; area DATA FSR_ 0x0080:0x00A0 ; area DATA Gen_Purp 0x00A0:0x00C0 General Purpose Register ; area BSS RESERVED 0x00C0:0x00F0 ; area DATA Gen_Purp_BANK0 0x00F0:0x0100 Mapped in Bank 0 ; area DATA MEM_Program 0x0100:0x0800 On-chip Program Memory ; Interrupt and reset vector assignments interrupt RESET 0x0000 RESET ; INPUT/OUTPUT PORTS ; BANK0 (0x0000:0x0080) BANK0:INDF 0x0000 INDF (not a physical register) BANK0:TMR0 0x0001 Timer0 module's register BANK0:PCL 0x0002 Program Counter's (PC) Least Significant Byte BANK0:STATUS 0x0003 STATUS REGISTER BANK0:STATUS.RP0 5 Register Bank Select bit BANK0:STATUS.TO 4 Time-out bit BANK0:STATUS.PD 3 Power-down bit BANK0:STATUS.Z 2 Zero bit BANK0:STATUS.DC 1 Digit Carry/borrow bit BANK0:STATUS.C 0 Carry/borrow bit BANK0:FSR 0x0004 Indirect data memory address pointer BANK0:GPIO 0x0005 GPIO REGISTER BANK0:GPIO.LINTX 7 BANK0:GPIO.LINRX 6 BANK0:GPIO.GP5 5 BANK0:GPIO.GP4 4 BANK0:GPIO.GP3 3 BANK0:GPIO.GP2 2 BANK0:GPIO.GP1 1 BANK0:GPIO.GP0 0 BANK0:RESERVED0006 0x0006 RESERVED BANK0:RESERVED0007 0x0007 RESERVED BANK0:RESERVED0008 0x0008 RESERVED BANK0:RESERVED0009 0x0009 RESERVED BANK0:PCLATH 0x000A Write Buffer for the upper 5 bits of the Program Counter BANK0:INTCON 0x000B INTCON REGISTER BANK0:INTCON.GIE 7 Global Interrupt Enable bit BANK0:INTCON.PEIE 6 Peripheral Interrupt Enable bit BANK0:INTCON.T0IE 5 TMR0 Overflow Interrupt Enable bit BANK0:INTCON.INTE 4 INT External Interrupt Enable bit BANK0:INTCON.GPIE 3 GPIO Interrupt-on-Change Enable bit BANK0:INTCON.T0IF 2 TMR0 Overflow Interrupt Flag bit BANK0:INTCON.INTF 1 RB0/INT External Interrupt Flag bit BANK0:INTCON.GPIF 0 GPIO Interrupt-on-Change Flag bit BANK0:PIR1 0x000C PIR1 REGISTER BANK0:PIR1.ADIF 6 A/D Converter Interrupt Flag bit BANK0:RESERVED000D 0x000D RESERVED BANK0:RESERVED000E 0x000E RESERVED BANK0:RESERVED000F 0x000F RESERVED BANK0:RESERVED0010 0x0010 RESERVED BANK0:RESERVED0011 0x0011 RESERVED BANK0:RESERVED0012 0x0012 RESERVED BANK0:RESERVED0013 0x0013 RESERVED BANK0:RESERVED0014 0x0014 RESERVED BANK0:RESERVED0015 0x0015 RESERVED BANK0:RESERVED0016 0x0016 RESERVED BANK0:RESERVED0017 0x0017 RESERVED BANK0:RESERVED0018 0x0018 RESERVED BANK0:RESERVED0019 0x0019 RESERVED BANK0:RESERVED001A 0x001A RESERVED BANK0:RESERVED001B 0x001B RESERVED BANK0:RESERVED001C 0x001C RESERVED BANK0:RESERVED001D 0x001D RESERVED BANK0:ADRES 0x001E A/D Result Register BANK0:ADCON0 0x001F ADCON0 REGISTER BANK0:ADCON0.ADCS1 7 A/D Conversion Clock Select bit 1 BANK0:ADCON0.ADCS0 6 A/D Conversion Clock Select bit 0 BANK0:ADCON0.CHS1 4 Analog Channel Select bit 1 BANK0:ADCON0.CHS0 3 Analog Channel Select bit 0 BANK0:ADCON0.GO_DONE 2 A/D Conversion Status bit BANK0:ADCON0.ADON 0 A/D On bit ; BANK1 (0x0080:0x0100) BANK1:BANK1 BANK1:INDF 0x0080 INDF (not a physical register) BANK1:OPTION 0x0081 OPTION REGISTER BANK1:OPTION.GPPU 7 Weak Pull-up Enable bit BANK1:OPTION.INTEDG 6 Interrupt Edge Select bit BANK1:OPTION.T0CS 5 TMR0 Clock Source Select bit BANK1:OPTION.T0SE 4 TMR0 Source Edge Select bit BANK1:OPTION.PSA 3 Prescaler Assignment bit BANK1:OPTION.PS2 2 Prescaler Rate Select bit 2 BANK1:OPTION.PS1 1 Prescaler Rate Select bit 1 BANK1:OPTION.PS0 0 Prescaler Rate Select bit 0 BANK1:PCL 0x0082 Program Counter's (PC) Least Significant Byte BANK1:STATUS 0x0083 STATUS REGISTER BANK1:STATUS.RP0 5 Register Bank Select bit BANK1:STATUS.TO 4 Time-out bit BANK1:STATUS.PD 3 Power-down bit BANK1:STATUS.Z 2 Zero bit BANK1:STATUS.DC 1 Digit Carry/borrow bit BANK1:STATUS.C 0 Carry/borrow bit BANK1:FSR 0x0084 Indirect data memory address pointer BANK1:TRIS 0x0085 GPIO Data Direction Register BANK1:RESERVED0086 0x0086 RESERVED BANK1:RESERVED0087 0x0087 RESERVED BANK1:RESERVED0088 0x0088 RESERVED BANK1:RESERVED0089 0x0089 RESERVED BANK1:PCLATH 0x008A Write Buffer for the upper 5 bits of the PC BANK1:INTCON 0x008B INTCON REGISTER BANK1:INTCON.GIE 7 Global Interrupt Enable bit BANK1:INTCON.PEIE 6 Peripheral Interrupt Enable bit BANK1:INTCON.T0IE 5 TMR0 Overflow Interrupt Enable bit BANK1:INTCON.INTE 4 INT External Interrupt Enable bit BANK1:INTCON.GPIE 3 GPIO Interrupt-on-Change Enable bit BANK1:INTCON.T0IF 2 TMR0 Overflow Interrupt Flag bit BANK1:INTCON.INTF 1 RB0/INT External Interrupt Flag bit BANK1:INTCON.GPIF 0 GPIO Interrupt-on-Change Flag bit BANK1:PIE1 0x008C PIE1 REGISTER BANK1:PIE1.ADIE 6 A/D Converter Interrupt Enable bit BANK1:RESERVED008D 0x008D RESERVED BANK1:PCON 0x008E PCON REGISTER BANK1:PCON.POR 1 Power-on Reset Status bit BANK1:OSCCAL 0x008F OSCCAL REGISTER BANK1:OSCCAL.CAL3 7 Fine Calibration 3 BANK1:OSCCAL.CAL2 6 Fine Calibration 2 BANK1:OSCCAL.CAL1 5 Fine Calibration 1 BANK1:OSCCAL.CAL0 4 Fine Calibration 0 BANK1:OSCCAL.CALFST 3 Calibration Fast BANK1:OSCCAL.CALSLW 2 Calibration Slow BANK1:RESERVED0090 0x0090 RESERVED BANK1:RESERVED0091 0x0091 RESERVED BANK1:RESERVED0092 0x0092 RESERVED BANK1:RESERVED0093 0x0093 RESERVED BANK1:RESERVED0094 0x0094 RESERVED BANK1:RESERVED0095 0x0095 RESERVED BANK1:RESERVED0096 0x0096 RESERVED BANK1:RESERVED0097 0x0097 RESERVED BANK1:RESERVED0098 0x0098 RESERVED BANK1:RESERVED0099 0x0099 RESERVED BANK1:RESERVED009A 0x009A RESERVED BANK1:RESERVED009B 0x009B RESERVED BANK1:RESERVED009C 0x009C RESERVED BANK1:RESERVED009D 0x009D RESERVED BANK1:RESERVED009E 0x009E RESERVED BANK1:ADCON1 0x009F ADCON1 REGISTER BANK1:ADCON1.PCFG2 2 A/D Port Configuration Control bit 2 BANK1:ADCON1.PCFG1 1 A/D Port Configuration Control bit 1 BANK1:ADCON1.PCFG0 0 A/D Port Configuration Control bit 0 .16C505 ; http://www.microchip.com/download/lit/pline/picmicro/families/16c5x/40192c.pdf ; PIC16C505.pdf ; MEMORY MAP ; BANK_0 area DATA FSR_ 0x0000:0x0008 area DATA Gen_Purp 0x0008:0x0020 General Purpose Register area DATA MEM_Program 0x0020:0x0400 On-chip Program Memory ; BANK_1 ; area DATA FSR_ 0x0020:0x0028 ; area DATA Gen_Purp 0x0028:0x0040 General Purpose Register ; area DATA MEM_Program 0x0040:0x0400 On-chip Program Memory ; BANK_2 ; area DATA FSR_ 0x0040:0x0048 ; area DATA Gen_Purp 0x0048:0x0060 General Purpose Register ; area DATA MEM_Program 0x0060:0x0400 On-chip Program Memory ; BANK_3 ; area DATA FSR_ 0x0060:0x0068 ; area DATA Gen_Purp 0x0068:0x0080 General Purpose Register ; area DATA MEM_Program 0x0080:0x0400 On-chip Program Memory ; Interrupt and reset vector assignments interrupt RESET 0x0000 RESET ; INPUT/OUTPUT PORTS ; BANK0 (0x0000:0x0020) BANK0:INDF 0x0000 INDF (not a physical register) BANK0:TMR0 0x0001 8-bit real-time clock/counter BANK0:PCL 0x0002 Low order 8 bits of PC BANK0:STATUS 0x0003 STATUS REGISTER BANK0:STATUS.RBWUF 7 I/O reset bit BANK0:STATUS.PAO 5 Program page preselect bits BANK0:STATUS.TO 4 Time-out bit BANK0:STATUS.PD 3 Power-down bit BANK0:STATUS.Z 2 Zero bit BANK0:STATUS.DC 1 Digit carry/borrow bit BANK0:STATUS.C 0 Carry/borrow bit BANK0:FSR 0x0004 Indirect data memory address pointer BANK0:OSCCAL 0x0005 OSCCAL REGISTER BANK0:OSCCAL.CAL5 7 Calibration 5 BANK0:OSCCAL.CAL4 6 Calibration 4 BANK0:OSCCAL.CAL3 5 Calibration 3 BANK0:OSCCAL.CAL2 4 Calibration 2 BANK0:OSCCAL.CAL1 3 Calibration 1 BANK0:OSCCAL.CAL0 2 Calibration 0 BANK0:PORTB 0x0006 PORTB REGISTER BANK0:PORTB.RB5 5 PORTB bit 5 BANK0:PORTB.RB4 4 PORTB bit 4 BANK0:PORTB.RB3 3 PORTB bit 3 BANK0:PORTB.RB2 2 PORTB bit 2 BANK0:PORTB.RB1 1 PORTB bit 1 BANK0:PORTB.RB0 0 PORTB bit 0 BANK0:PORTC 0x0007 PORTC REGISTER BANK0:PORTC.RC5 5 PORTC bit 5 BANK0:PORTC.RC4 4 PORTC bit 4 BANK0:PORTC.RC3 3 PORTC bit 3 BANK0:PORTC.RC2 2 PORTC bit 2 BANK0:PORTC.RC1 1 PORTC bit 1 BANK0:PORTC.RC0 0 PORTC bit 0 ; BANK1 (0x0020:0x0040) BANK1:INDF 0x0020 INDF (not a physical register) BANK1:TMR0 0x0021 8-bit real-time clock/counter BANK1:PCL 0x0022 Low order 8 bits of PC BANK1:STATUS 0x0023 STATUS REGISTER BANK1:STATUS.RBWUF 7 I/O reset bit BANK1:STATUS.PAO 5 Program page preselect bits BANK1:STATUS.TO 4 Time-out bit BANK1:STATUS.PD 3 Power-down bit BANK1:STATUS.Z 2 Zero bit BANK1:STATUS.DC 1 Digit carry/borrow bit BANK1:STATUS.C 0 Carry/borrow bit BANK1:FSR 0x0024 Indirect data memory address pointer BANK1:OSCCAL 0x0025 OSCCAL REGISTER BANK1:OSCCAL.CAL5 7 Calibration 5 BANK1:OSCCAL.CAL4 6 Calibration 4 BANK1:OSCCAL.CAL3 5 Calibration 3 BANK1:OSCCAL.CAL2 4 Calibration 2 BANK1:OSCCAL.CAL1 3 Calibration 1 BANK1:OSCCAL.CAL0 2 Calibration 0 BANK1:PORTB 0x0026 PORTB REGISTER BANK1:PORTB.RB5 5 PORTB bit 5 BANK1:PORTB.RB4 4 PORTB bit 4 BANK1:PORTB.RB3 3 PORTB bit 3 BANK1:PORTB.RB2 2 PORTB bit 2 BANK1:PORTB.RB1 1 PORTB bit 1 BANK1:PORTB.RB0 0 PORTB bit 0 BANK1:PORTC 0x0027 PORTC REGISTER BANK1:PORTC.RC5 5 PORTC bit 5 BANK1:PORTC.RC4 4 PORTC bit 4 BANK1:PORTC.RC3 3 PORTC bit 3 BANK1:PORTC.RC2 2 PORTC bit 2 BANK1:PORTC.RC1 1 PORTC bit 1 BANK1:PORTC.RC0 0 PORTC bit 0 ; BANK2 (0x0040:0x0060) BANK2:INDF 0x0040 INDF (not a physical register) BANK2:TMR0 0x0041 8-bit real-time clock/counter BANK2:PCL 0x0042 Low order 8 bits of PC BANK2:STATUS 0x0043 STATUS REGISTER BANK2:STATUS.RBWUF 7 I/O reset bit BANK2:STATUS.PAO 5 Program page preselect bits BANK2:STATUS.TO 4 Time-out bit BANK2:STATUS.PD 3 Power-down bit BANK2:STATUS.Z 2 Zero bit BANK2:STATUS.DC 1 Digit carry/borrow bit BANK2:STATUS.C 0 Carry/borrow bit BANK2:FSR 0x0044 Indirect data memory address pointer BANK2:OSCCAL 0x0045 OSCCAL REGISTER BANK2:OSCCAL.CAL5 7 Calibration 5 BANK2:OSCCAL.CAL4 6 Calibration 4 BANK2:OSCCAL.CAL3 5 Calibration 3 BANK2:OSCCAL.CAL2 4 Calibration 2 BANK2:OSCCAL.CAL1 3 Calibration 1 BANK2:OSCCAL.CAL0 2 Calibration 0 BANK2:PORTB 0x0046 PORTB REGISTER BANK2:PORTB.RB5 5 PORTB bit 5 BANK2:PORTB.RB4 4 PORTB bit 4 BANK2:PORTB.RB3 3 PORTB bit 3 BANK2:PORTB.RB2 2 PORTB bit 2 BANK2:PORTB.RB1 1 PORTB bit 1 BANK2:PORTB.RB0 0 PORTB bit 0 BANK2:PORTC 0x0047 PORTC REGISTER BANK2:PORTC.RC5 5 PORTC bit 5 BANK2:PORTC.RC4 4 PORTC bit 4 BANK2:PORTC.RC3 3 PORTC bit 3 BANK2:PORTC.RC2 2 PORTC bit 2 BANK2:PORTC.RC1 1 PORTC bit 1 BANK2:PORTC.RC0 0 PORTC bit 0 ; BANK3 (0x0060:0x0080) BANK3:INDF 0x0060 INDF (not a physical register) BANK3:TMR0 0x0061 8-bit real-time clock/counter BANK3:PCL 0x0062 Low order 8 bits of PC BANK3:STATUS 0x0063 STATUS REGISTER BANK3:STATUS.RBWUF 7 I/O reset bit BANK3:STATUS.PAO 5 Program page preselect bits BANK3:STATUS.TO 4 Time-out bit BANK3:STATUS.PD 3 Power-down bit BANK3:STATUS.Z 2 Zero bit BANK3:STATUS.DC 1 Digit carry/borrow bit BANK3:STATUS.C 0 Carry/borrow bit BANK3:FSR 0x0064 Indirect data memory address pointer BANK3:OSCCAL 0x0065 OSCCAL REGISTER BANK3:OSCCAL.CAL5 7 Calibration 5 BANK3:OSCCAL.CAL4 6 Calibration 4 BANK3:OSCCAL.CAL3 5 Calibration 3 BANK3:OSCCAL.CAL2 4 Calibration 2 BANK3:OSCCAL.CAL1 3 Calibration 1 BANK3:OSCCAL.CAL0 2 Calibration 0 BANK3:PORTB 0x0066 PORTB REGISTER BANK3:PORTB.RB5 5 PORTB bit 5 BANK3:PORTB.RB4 4 PORTB bit 4 BANK3:PORTB.RB3 3 PORTB bit 3 BANK3:PORTB.RB2 2 PORTB bit 2 BANK3:PORTB.RB1 1 PORTB bit 1 BANK3:PORTB.RB0 0 PORTB bit 0 BANK3:PORTC 0x0067 PORTC REGISTER BANK3:PORTC.RC5 5 PORTC bit 5 BANK3:PORTC.RC4 4 PORTC bit 4 BANK3:PORTC.RC3 3 PORTC bit 3 BANK3:PORTC.RC2 2 PORTC bit 2 BANK3:PORTC.RC1 1 PORTC bit 1 BANK3:PORTC.RC0 0 PORTC bit 0 .16F72 ; http://www.microchip.com/download/lit/pline/picmicro/families/16f7x/39597a.pdf ; PIC16F72.pdf ; MEMORY MAP ; BANK_0 area DATA FSR_ 0x0000:0x0020 area DATA Gen_Purp 0x0020:0x0080 General Purpose Register area DATA MEM_Program 0x0080:0x0800 On-chip Program Memory ; BANK_1 ; area DATA FSR_ 0x0080:0x00A0 ; area DATA Gen_Purp 0x00A0:0x00C0 General Purpose Register ; area DATA Gen_Purp_BANK0 0x00C0:0x0100 accesses 40h-7Fh ; area DATA MEM_Program 0x0100:0x0800 On-chip Program Memory ; BANK_2 ; area DATA FSR_ 0x0100:0x0110 ; area BSS RESERVED 0x0110:0x0120 ; area DATA Gen_Purp_BANK0 0x0120:0x0180 accesses 20h-7Fh ; area DATA MEM_Program 0x0180:0x0800 On-chip Program Memory ; BANK_3 ; area DATA FSR_ 0x0180:0x018D ; area BSS RESERVED 0x018D:0x01A0 ; area DATA Gen_Purp_BANK0 0x01A0:0x0200 accesses A0h-7Fh ; area DATA MEM_Program 0x0200:0x0800 On-chip Program Memory ; Interrupt and reset vector assignments interrupt RESET 0x0000 RESET ; INPUT/OUTPUT PORTS ; BANK0 (0x0000:0x0080) BANK0:INDF 0x0000 INDF (not a physical register) BANK0:TMR0 0x0001 Timer0 module's register BANK0:PCL 0x0002 Program Counter's (PC) Least Significant Byte BANK0:STATUS 0x0003 STATUS REGISTER BANK0:STATUS.IRP 7 Register Bank Select bit BANK0:STATUS.RP1 6 Register Bank Select bit 1 BANK0:STATUS.RP0 5 Register Bank Select bit 0 BANK0:STATUS.TO 4 Time-out bit BANK0:STATUS.PD 3 Power-down bit BANK0:STATUS.Z 2 Zero bit BANK0:STATUS.DC 1 Digit carry/borrow bit BANK0:STATUS.C 0 Carry/borrow bit BANK0:FSR 0x0004 Indirect data memory address pointer BANK0:PORTA 0x0005 PORTA REGISTER BANK0:PORTA.RA5 5 PORTA bit 5 (not implemented on the 28-pin devices) BANK0:PORTA.RA4 4 PORTA bit 4 BANK0:PORTA.RA3 3 PORTA bit 3 BANK0:PORTA.RA2 2 PORTA bit 2 BANK0:PORTA.RA1 1 PORTA bit 1 BANK0:PORTA.RA0 0 PORTA bit 0 BANK0:PORTB 0x0006 PORTB REGISTER BANK0:PORTB.RB7 7 PORTB bit 7 BANK0:PORTB.RB6 6 PORTB bit 6 BANK0:PORTB.RB5 5 PORTB bit 5 BANK0:PORTB.RB4 4 PORTB bit 4 BANK0:PORTB.RB3 3 PORTB bit 3 BANK0:PORTB.RB2 2 PORTB bit 2 BANK0:PORTB.RB1 1 PORTB bit 1 BANK0:PORTB.RB0 0 PORTB bit 0 BANK0:PORTC 0x0007 PORTC REGISTER BANK0:PORTC.RC7 7 PORTC bit 7 BANK0:PORTC.RC6 6 PORTC bit 6 BANK0:PORTC.RC5 5 PORTC bit 5 BANK0:PORTC.RC4 4 PORTC bit 4 BANK0:PORTC.RC3 3 PORTC bit 3 BANK0:PORTC.RC2 2 PORTC bit 2 BANK0:PORTC.RC1 1 PORTC bit 1 BANK0:PORTC.RC0 0 PORTC bit 0 BANK0:RESERVED0008 0x0008 RESERVED BANK0:RESERVED0009 0x0009 RESERVED BANK0:PCLATH 0x000A Write Buffer for the upper 5 bits of the Program Counter BANK0:INTCON 0x000B INTCON REGISTER BANK0:INTCON.GIE 7 Global Interrupt Enable bit BANK0:INTCON.PEIE 6 Peripheral Interrupt Enable bit BANK0:INTCON.TMR0IE 5 TMR0 Overflow Interrupt Enable bit BANK0:INTCON.INTE 4 RB0/INT External Interrupt Enable bit BANK0:INTCON.RBIE 3 RB Port Change Interrupt Enable bit BANK0:INTCON.TMR0IF 2 TMR0 Overflow Interrupt Flag bit BANK0:INTCON.INTF 1 RB0/INT External Interrupt Flag bit BANK0:INTCON.RBIF 0 RB Port Change Interrupt Flag bit BANK0:PIR1 0x000C PIR1 REGISTER BANK0:PIR1.ADIF 6 A/D Converter Interrupt Flag bit BANK0:PIR1.SSPIF 3 Synchronous Serial Port Interrupt Flag bit BANK0:PIR1.CCP1IF 2 CCP1 Interrupt Flag bit BANK0:PIR1.TMR2IF 1 TMR2 to PR2 Match Interrupt Flag bit BANK0:PIR1.TMR1IF 0 TMR1 Overflow Interrupt Flag bit BANK0:RESERVED000D 0x000D RESERVED BANK0:TMR1L 0x000E Holding register for the Least Significant Byte of the 16-bit TMR1 register BANK0:TMR1H 0x000F Holding register for the Most Significant Byte of the 16-bit TMR1 register BANK0:T1CON 0x0010 TIMER1 CONTROL REGISTER BANK0:T1CON.T1CKPS1 5 Timer1 Input Clock Prescale Select bit 1 BANK0:T1CON.T1CKPS0 4 Timer1 Input Clock Prescale Select bit 0 BANK0:T1CON.T1OSCEN 3 Timer1 Oscillator Enable Control bit BANK0:T1CON.T1SYNC 2 Timer1 External Clock Input Synchronization Control bit BANK0:T1CON.TMR1CS 1 Timer1 Clock Source Select bit BANK0:T1CON.TMR1ON 0 Timer1 On bit BANK0:TMR2 0x0011 Timer2 module's register BANK0:T2CON 0x0012 TIMER2 CONTROL REGISTER BANK0:T2CON.TOUTPS3 6 Timer2 Output Postscale Select bit 3 BANK0:T2CON.TOUTPS2 5 Timer2 Output Postscale Select bit 2 BANK0:T2CON.TOUTPS1 4 Timer2 Output Postscale Select bit 1 BANK0:T2CON.TOUTPS0 3 Timer2 Output Postscale Select bit 0 BANK0:T2CON.TMR2ON 2 Timer2 On bit BANK0:T2CON.T2CKPS1 1 Timer2 Clock Prescale Select bit 1 BANK0:T2CON.T2CKPS0 0 Timer2 Clock Prescale Select bit 0 BANK0:SSPBUF 0x0013 Synchronous Serial Port Receive Buffer/Transmit Register BANK0:SSPCON 0x0014 SYNC SERIAL PORT CONTROL REGISTER BANK0:SSPCON.WCOL 7 Write Collision Detect bit BANK0:SSPCON.SSPOV 6 Receive Overflow Indicator bit BANK0:SSPCON.SSPEN 5 Synchronous Serial Port Enable bit BANK0:SSPCON.CKP 4 Clock Polarity Select bit BANK0:SSPCON.SSPM3 3 Synchronous Serial Port Mode Select bit 3 BANK0:SSPCON.SSPM2 2 Synchronous Serial Port Mode Select bit 2 BANK0:SSPCON.SSPM1 1 Synchronous Serial Port Mode Select bit 1 BANK0:SSPCON.SSPM0 0 Synchronous Serial Port Mode Select bit 0 BANK0:CCPR1L 0x0015 Capture/Compare/PWM Register1 (LSB) BANK0:CCPR1H 0x0016 Capture/Compare/PWM Register1 (MSB) BANK0:CCP1CON 0x0017 CCP1CON REGISTER BANK0:CCP1CON.CCP1X 5 PWM Least Significant bit BANK0:CCP1CON.CCP1Y 4 PWM Least Significant bit BANK0:CCP1CON.CCP1M3 3 CCP1 Mode Select bit 3 BANK0:CCP1CON.CCP1M2 2 CCP1 Mode Select bit 2 BANK0:CCP1CON.CCP1M1 1 CCP1 Mode Select bit 1 BANK0:CCP1CON.CCP1M0 0 CCP1 Mode Select bit 0 BANK0:RESERVED0018 0x0018 RESERVED BANK0:RESERVED0019 0x0019 RESERVED BANK0:RESERVED001A 0x001A RESERVED BANK0:RESERVED001B 0x001B RESERVED BANK0:RESERVED001C 0x001C RESERVED BANK0:RESERVED001D 0x001D RESERVED BANK0:ADRES 0x001E A/D Result Register BANK0:ADCON0 0x001F ADCON0 REGISTER BANK0:ADCON0.ADCS1 7 A/D Conversion Clock Select bit 1 BANK0:ADCON0.ADCS0 6 A/D Conversion Clock Select bit 0 BANK0:ADCON0.CHS2 5 Analog Channel Select bit 2 BANK0:ADCON0.CHS1 4 Analog Channel Select bit 1 BANK0:ADCON0.CHS0 3 Analog Channel Select bit 0 BANK0:ADCON0.GO_DONE 2 A/D Conversion Status bit BANK0:ADCON0.ADON 0 A/D On bit ; BANK1 (0x0080:0x0100) BANK1:INDF 0x0080 INDF (not a physical register) BANK1:OPTION 0x0081 OPTION REGISTER BANK1:OPTION.RBPU 7 PORTB Pull-up Enable bit BANK1:OPTION.INTEDG 6 Interrupt Edge Select bit BANK1:OPTION.T0CS 5 TMR0 Clock Source Select bit BANK1:OPTION.T0SE 4 TMR0 Source Edge Select bit BANK1:OPTION.PSA 3 Prescaler Assignment bit BANK1:OPTION.PS2 2 Prescaler Rate Select bit 2 BANK1:OPTION.PS1 1 Prescaler Rate Select bit 1 BANK1:OPTION.PS0 0 Prescaler Rate Select bit 0 BANK1:PCL 0x0082 Program Counter's (PC) Least Significant Byte BANK1:STATUS 0x0083 STATUS REGISTER BANK1:STATUS.IRP 7 Register Bank Select bit BANK1:STATUS.RP1 6 Register Bank Select bit 1 BANK1:STATUS.RP0 5 Register Bank Select bit 0 BANK1:STATUS.TO 4 Time-out bit BANK1:STATUS.PD 3 Power-down bit BANK1:STATUS.Z 2 Zero bit BANK1:STATUS.DC 1 Digit carry/borrow bit BANK1:STATUS.C 0 Carry/borrow bit BANK1:FSR 0x0084 Indirect data memory address pointer BANK1:TRISA 0x0085 PORTA Data Direction Register BANK1:TRISA.TRISA5 5 PORTA Data Direction Register bit 5 BANK1:TRISA.TRISA4 4 PORTA Data Direction Register bit 4 BANK1:TRISA.TRISA3 3 PORTA Data Direction Register bit 3 BANK1:TRISA.TRISA2 2 PORTA Data Direction Register bit 2 BANK1:TRISA.TRISA1 1 PORTA Data Direction Register bit 1 BANK1:TRISA.TRISA0 0 PORTA Data Direction Register bit 0 BANK1:TRISB 0x0086 PORTB Data Direction Register BANK1:TRISB.TRISB7 7 PORTB Data Direction Register bit 7 BANK1:TRISB.TRISB6 6 PORTB Data Direction Register bit 6 BANK1:TRISB.TRISB5 5 PORTB Data Direction Register bit 5 BANK1:TRISB.TRISB4 4 PORTB Data Direction Register bit 4 BANK1:TRISB.TRISB3 3 PORTB Data Direction Register bit 3 BANK1:TRISB.TRISB2 2 PORTB Data Direction Register bit 2 BANK1:TRISB.TRISB1 1 PORTB Data Direction Register bit 1 BANK1:TRISB.TRISB0 0 PORTB Data Direction Register bit 0 BANK1:TRISC 0x0087 PORTC Data Direction Register BANK1:TRISC.TRISC7 7 PORTC Data Direction Register bit 7 BANK1:TRISC.TRISC6 6 PORTC Data Direction Register bit 6 BANK1:TRISC.TRISC5 5 PORTC Data Direction Register bit 5 BANK1:TRISC.TRISC4 4 PORTC Data Direction Register bit 4 BANK1:TRISC.TRISC3 3 PORTC Data Direction Register bit 3 BANK1:TRISC.TRISC2 2 PORTC Data Direction Register bit 2 BANK1:TRISC.TRISC1 1 PORTC Data Direction Register bit 1 BANK1:TRISC.TRISC0 0 PORTC Data Direction Register bit 0 BANK1:RESERVED0088 0x0088 RESERVED BANK1:RESERVED0089 0x0089 RESERVED BANK1:PCLATH 0x008A Write Buffer for the upper 5 bits of the Program Counter BANK1:INTCON 0x008B INTCON REGISTER BANK1:INTCON.GIE 7 Global Interrupt Enable bit BANK1:INTCON.PEIE 6 Peripheral Interrupt Enable bit BANK1:INTCON.TMR0IE 5 TMR0 Overflow Interrupt Enable bit BANK1:INTCON.INTE 4 RB0/INT External Interrupt Enable bit BANK1:INTCON.RBIE 3 RB Port Change Interrupt Enable bit BANK1:INTCON.TMR0IF 2 TMR0 Overflow Interrupt Flag bit BANK1:INTCON.INTF 1 RB0/INT External Interrupt Flag bit BANK1:INTCON.RBIF 0 RB Port Change Interrupt Flag bit BANK1:PIE1 0x008C PIE1 REGISTER BANK1:PIE1.ADIE 6 A/D Converter Interrupt Enable bit BANK1:PIE1.SSPIE 3 Synchronous Serial Port Interrupt Enable bit BANK1:PIE1.CCP1IE 2 CCP1 Interrupt Enable bit BANK1:PIE1.TMR2IE 1 TMR2 to PR2 Match Interrupt Enable bit BANK1:PIE1.TMR1IE 0 TMR1 Overflow Interrupt Enable bit BANK1:RESERVED008D 0x008D RESERVED BANK1:PCON 0x008E PCON REGISTER BANK1:PCON.POR 1 Power-on Reset Status bit BANK1:PCON.BOR 0 Brown-out Reset Status bit BANK1:RESERVED008F 0x008F RESERVED BANK1:RESERVED0090 0x0090 RESERVED BANK1:RESERVED0091 0x0091 RESERVED BANK1:PR2 0x0092 Timer2 Period Register BANK1:SSPADD 0x0093 Synchronous Serial Port (I2C mode) Address Register BANK1:SSPSTAT 0x0094 SYNC SERIAL PORT STATUS REGISTER BANK1:SSPSTAT.SMP 7 SPI data input sample phase BANK1:SSPSTAT.CKE 6 SPI Clock Edge Select BANK1:SSPSTAT.D_A 5 Data/Address bit (I2C mode only) BANK1:SSPSTAT.P 4 Stop bit (I2C mode only) BANK1:SSPSTAT.S 3 Start bit (I2C mode only) BANK1:SSPSTAT.R_W 2 Read/Write bit information (I2C mode only) BANK1:SSPSTAT.UA 1 Update Address (I2C mode only) BANK1:SSPSTAT.BF 0 Buffer Full Status bit BANK1:RESERVED0095 0x0095 RESERVED BANK1:RESERVED0096 0x0096 RESERVED BANK1:RESERVED0097 0x0097 RESERVED BANK1:RESERVED0098 0x0098 RESERVED BANK1:RESERVED0099 0x0099 RESERVED BANK1:RESERVED009A 0x009A RESERVED BANK1:RESERVED009B 0x009B RESERVED BANK1:RESERVED009C 0x009C RESERVED BANK1:RESERVED009D 0x009D RESERVED BANK1:RESERVED009E 0x009E RESERVED BANK1:ADCON1 0x009F ADCON1 REGISTER BANK1:ADCON1.PCFG2 2 A/D Port Configuration Control bit 2 BANK1:ADCON1.PCFG1 1 A/D Port Configuration Control bit 1 BANK1:ADCON1.PCFG0 0 A/D Port Configuration Control bit 0 ; BANK2 (0x0100:0x0180) BANK2:INDF 0x0100 INDF (not a physical register) BANK2:TMR0 0x0101 Timer0 module's register BANK2:PCL 0x0102 Program Counter's (PC) Least Significant Byte BANK2:STATUS 0x0103 STATUS REGISTER BANK2:STATUS.IRP 7 Register Bank Select bit BANK2:STATUS.RP1 6 Register Bank Select bit 1 BANK2:STATUS.RP0 5 Register Bank Select bit 0 BANK2:STATUS.TO 4 Time-out bit BANK2:STATUS.PD 3 Power-down bit BANK2:STATUS.Z 2 Zero bit BANK2:STATUS.DC 1 Digit carry/borrow bit BANK2:STATUS.C 0 Carry/borrow bit BANK2:FSR 0x0104 Indirect data memory address pointer BANK2:RESERVED0105 0x0105 RESERVED BANK2:PORTB 0x0106 PORTB REGISTER BANK2:PORTB.RB7 7 PORTB bit 7 BANK2:PORTB.RB6 6 PORTB bit 6 BANK2:PORTB.RB5 5 PORTB bit 5 BANK2:PORTB.RB4 4 PORTB bit 4 BANK2:PORTB.RB3 3 PORTB bit 3 BANK2:PORTB.RB2 2 PORTB bit 2 BANK2:PORTB.RB1 1 PORTB bit 1 BANK2:PORTB.RB0 0 PORTB bit 0 BANK2:RESERVED0107 0x0107 RESERVED BANK2:RESERVED0108 0x0108 RESERVED BANK2:RESERVED0109 0x0109 RESERVED BANK2:PCLATH 0x010A Write Buffer for the upper 5 bits of the Program Counter BANK2:INTCON 0x010B INTCON REGISTER BANK2:INTCON.GIE 7 Global Interrupt Enable bit BANK2:INTCON.PEIE 6 Peripheral Interrupt Enable bit BANK2:INTCON.TMR0IE 5 TMR0 Overflow Interrupt Enable bit BANK2:INTCON.INTE 4 RB0/INT External Interrupt Enable bit BANK2:INTCON.RBIE 3 RB Port Change Interrupt Enable bit BANK2:INTCON.TMR0IF 2 TMR0 Overflow Interrupt Flag bit BANK2:INTCON.INTF 1 RB0/INT External Interrupt Flag bit BANK2:INTCON.RBIF 0 RB Port Change Interrupt Flag bit BANK2:PMDATL 0x010C Data Register Low Byte BANK2:PMADRL 0x010D Address Register Low Byte BANK2:PMDATH 0x010E Data Register High Byte BANK2:PMADRH 0x010F Address Register High Byte ; BANK3 (0x0180:0x0200) BANK3:INDF 0x0180 INDF (not a physical register) BANK3:OPTION 0x0181 OPTION REGISTER BANK3:OPTION.RBPU 7 PORTB Pull-up Enable bit BANK3:OPTION.INTEDG 6 Interrupt Edge Select bit BANK3:OPTION.T0CS 5 TMR0 Clock Source Select bit BANK3:OPTION.T0SE 4 TMR0 Source Edge Select bit BANK3:OPTION.PSA 3 Prescaler Assignment bit BANK3:OPTION.PS2 2 Prescaler Rate Select bit 2 BANK3:OPTION.PS1 1 Prescaler Rate Select bit 1 BANK3:OPTION.PS0 0 Prescaler Rate Select bit 0 BANK3:PCL 0x0182 Program Counter's (PC) Least Significant Byte BANK3:STATUS 0x0183 STATUS REGISTER BANK3:STATUS.IRP 7 Register Bank Select bit BANK3:STATUS.RP1 6 Register Bank Select bit 1 BANK3:STATUS.RP0 5 Register Bank Select bit 0 BANK3:STATUS.TO 4 Time-out bit BANK3:STATUS.PD 3 Power-down bit BANK3:STATUS.Z 2 Zero bit BANK3:STATUS.DC 1 Digit carry/borrow bit BANK3:STATUS.C 0 Carry/borrow bit BANK3:FSR 0x0184 Indirect data memory address pointer BANK3:RESERVED0185 0x0185 RESERVED BANK3:TRISB 0x0186 PORTB Data Direction Register BANK3:TRISB.TRISB7 7 PORTB Data Direction Register bit 7 BANK3:TRISB.TRISB6 6 PORTB Data Direction Register bit 6 BANK3:TRISB.TRISB5 5 PORTB Data Direction Register bit 5 BANK3:TRISB.TRISB4 4 PORTB Data Direction Register bit 4 BANK3:TRISB.TRISB3 3 PORTB Data Direction Register bit 3 BANK3:TRISB.TRISB2 2 PORTB Data Direction Register bit 2 BANK3:TRISB.TRISB1 1 PORTB Data Direction Register bit 1 BANK3:TRISB.TRISB0 0 PORTB Data Direction Register bit 0 BANK3:RESERVED0187 0x0187 RESERVED BANK3:RESERVED0188 0x0188 RESERVED BANK3:RESERVED0189 0x0189 RESERVED BANK3:PCLATH 0x018A Write Buffer for the upper 5 bits of the Program Counter BANK3:INTCON 0x018B INTCON REGISTER BANK3:INTCON.GIE 7 Global Interrupt Enable bit BANK3:INTCON.PEIE 6 Peripheral Interrupt Enable bit BANK3:INTCON.TMR0IE 5 TMR0 Overflow Interrupt Enable bit BANK3:INTCON.INTE 4 RB0/INT External Interrupt Enable bit BANK3:INTCON.RBIE 3 RB Port Change Interrupt Enable bit BANK3:INTCON.TMR0IF 2 TMR0 Overflow Interrupt Flag bit BANK3:INTCON.INTF 1 RB0/INT External Interrupt Flag bit BANK3:INTCON.RBIF 0 RB Port Change Interrupt Flag bit BANK3:PMCON1 0x018C PROGRAM MEMORY CONTROL REGISTER 1 BANK3:PMCON1.RD 0 Read Control bit .16F84A ; http://www.microchip.com/download/lit/pline/picmicro/families/16f8x/35007b.pdf ; PIC16F84A.pdf ; MEMORY MAP ; BANK_0 area DATA FSR_ 0x0000:0x000C area DATA Gen_Purp 0x000C:0x0050 General Purpose Register (SRAM) area DATA MEM_Program 0x0050:0x0400 On-chip Program Memory ; BANK_1 ; area DATA FSR_ 0x0080:0x008C ; area DATA Gen_Purp_BANK0 0x008C:0x00D0 Mapped (accesses) in Bank 0 ; area DATA MEM_Program 0x00D0:0x0400 On-chip Program Memory ; Interrupt and reset vector assignments interrupt RESET 0x0000 RESET ; INPUT/OUTPUT PORTS ; BANK0 (0x0000:0x0050) BANK0:INDF 0x0000 INDF (not a physical register) BANK0:TMR0 0x0001 Timer0 module's register BANK0:PCL 0x0002 Low Order 8 bits of the Program Counter (PC) BANK0:STATUS 0x0003 STATUS REGISTER BANK0:STATUS.IRP 7 Register Bank Select bit BANK0:STATUS.RP1 6 Register Bank Select bit 1 BANK0:STATUS.RP0 5 Register Bank Select bit 0 BANK0:STATUS.TO 4 Time-out bit BANK0:STATUS.PD 3 Power-down bit BANK0:STATUS.Z 2 Zero bit BANK0:STATUS.DC 1 Digit carry/borrow bit BANK0:STATUS.C 0 Carry/borrow bit BANK0:FSR 0x0004 Indirect Data Memory Address Pointer 0 BANK0:PORTA 0x0005 PORTA REGISTER BANK0:PORTA.RA4_T0CKI 4 PORTA bit 4 /external clock input for TMR0 BANK0:PORTA.RA3 3 PORTA bit 3 BANK0:PORTA.RA2 2 PORTA bit 2 BANK0:PORTA.RA1 1 PORTA bit 1 BANK0:PORTA.RA0 0 PORTA bit 0 BANK0:PORTB 0x0006 PORTB REGISTER BANK0:PORTB.RB7 7 PORTB bit 7 BANK0:PORTB.RB6 6 PORTB bit 6 BANK0:PORTB.RB5 5 PORTB bit 5 BANK0:PORTB.RB4 4 PORTB bit 4 BANK0:PORTB.RB3 3 PORTB bit 3 BANK0:PORTB.RB2 2 PORTB bit 2 BANK0:PORTB.RB1 1 PORTB bit 1 BANK0:PORTB.RB0 0 PORTB bit 0 BANK0:RESERVED0007 0x0007 RESERVED BANK0:EEDATA 0x0008 EEPROM Data Register BANK0:EEADR 0x0009 EEPROM Address Register BANK0:PCLATH 0x000A Write Buffer for upper 5 bits of the PC BANK0:INTCON 0x000B INTCON REGISTER BANK0:INTCON.GIE 7 Global Interrupt Enable bit BANK0:INTCON.EEIE 6 EE Write Complete Interrupt Enable bit BANK0:INTCON.T0IE 5 TMR0 Overflow Interrupt Enable bit BANK0:INTCON.INTE 4 RB0/INT External Interrupt Enable bit BANK0:INTCON.RBIE 3 RB Port Change Interrupt Enable bit BANK0:INTCON.T0IF 2 TMR0 Overflow Interrupt Flag bit BANK0:INTCON.INTF 1 RB0/INT External Interrupt Flag bit BANK0:INTCON.RBIF 0 RB Port Change Interrupt Flag bit ; BANK1 (0x0080:0x00D0) BANK1:INDF 0x0080 INDF (not a physical register) BANK1:OPTION 0x0081 OPTION REGISTER BANK1:OPTION.RBPU 7 PORTB Pull-up Enable bit BANK1:OPTION.INTEDG 6 Interrupt Edge Select bit BANK1:OPTION.T0CS 5 TMR0 Clock Source Select bit BANK1:OPTION.T0SE 4 TMR0 Source Edge Select bit BANK1:OPTION.PSA 3 Prescaler Assignment bit BANK1:OPTION.PS2 2 Prescaler Rate Select bit 2 BANK1:OPTION.PS1 1 Prescaler Rate Select bit 1 BANK1:OPTION.PS0 0 Prescaler Rate Select bit 0 BANK1:PCL 0x0082 Low order 8 bits of Program Counter (PC) BANK1:STATUS 0x0083 STATUS REGISTER BANK1:STATUS.IRP 7 Register Bank Select bit BANK1:STATUS.RP1 6 Register Bank Select bit 1 BANK1:STATUS.RP0 5 Register Bank Select bit 0 BANK1:STATUS.TO 4 Time-out bit BANK1:STATUS.PD 3 Power-down bit BANK1:STATUS.Z 2 Zero bit BANK1:STATUS.DC 1 Digit carry/borrow bit BANK1:STATUS.C 0 Carry/borrow bit BANK1:FSR 0x0084 Indirect data memory address pointer 0 BANK1:TRISA 0x0085 PORTA Data Direction Register BANK1:TRISA.TRISA4 4 PORTA Data Direction Register bit 4 BANK1:TRISA.TRISA3 3 PORTA Data Direction Register bit 3 BANK1:TRISA.TRISA2 2 PORTA Data Direction Register bit 2 BANK1:TRISA.TRISA1 1 PORTA Data Direction Register bit 1 BANK1:TRISA.TRISA0 0 PORTA Data Direction Register bit 0 BANK1:TRISB 0x0086 PORTB Data Direction Register BANK1:TRISB.TRISB7 7 PORTB Data Direction Register bit 7 BANK1:TRISB.TRISB6 6 PORTB Data Direction Register bit 6 BANK1:TRISB.TRISB5 5 PORTB Data Direction Register bit 5 BANK1:TRISB.TRISB4 4 PORTB Data Direction Register bit 4 BANK1:TRISB.TRISB3 3 PORTB Data Direction Register bit 3 BANK1:TRISB.TRISB2 2 PORTB Data Direction Register bit 2 BANK1:TRISB.TRISB1 1 PORTB Data Direction Register bit 1 BANK1:TRISB.TRISB0 0 PORTB Data Direction Register bit 0 BANK1:RESERVED0087 0x0087 RESERVED BANK1:EECON1 0x0088 EECON1 REGISTER BANK1:EECON1.EEIF 4 EEPROM Write Operation Interrupt Flag bit BANK1:EECON1.WRERR 3 EEPROM Error Flag bit BANK1:EECON1.WREN 2 EEPROM Write Enable bit BANK1:EECON1.WR 1 Write Control bit BANK1:EECON1.RD 0 Read Control bit BANK1:EECON2 0x0089 EEPROM Control Register 2 (not a physical register) BANK1:PCLATH 0x008A Write buffer for upper 5 bits of the PC BANK1:INTCON 0x008B INTCON REGISTER BANK1:INTCON.GIE 7 Global Interrupt Enable bit BANK1:INTCON.EEIE 6 EE Write Complete Interrupt Enable bit BANK1:INTCON.T0IE 5 TMR0 Overflow Interrupt Enable bit BANK1:INTCON.INTE 4 RB0/INT External Interrupt Enable bit BANK1:INTCON.RBIE 3 RB Port Change Interrupt Enable bit BANK1:INTCON.T0IF 2 TMR0 Overflow Interrupt Flag bit BANK1:INTCON.INTF 1 RB0/INT External Interrupt Flag bit BANK1:INTCON.RBIF 0 RB Port Change Interrupt Flag bit .16F872 ; http://www.microchip.com/download/lit/pline/picmicro/families/16f87x/30221b.pdf ; PIC16F872.pdf ; MEMORY MAP ; BANK_0 area DATA FSR_ 0x0000:0x0020 area DATA Gen_Purp 0x0020:0x0080 General Purpose Register area DATA MEM_Program 0x0080:0x0800 On-chip Program Memory ; BANK_1 ; area DATA FSR_ 0x0080:0x00A0 ; area DATA Gen_Purp 0x00A0:0x00C0 General Purpose Register ; area BSS RESERVED 0x00C0:0x00F0 ; area DATA Gen_Purp_BANK0 0x00F0:0x0100 accesses 70h-7Fh ; area DATA MEM_Program 0x0100:0x0800 On-chip Program Memory ; BANK_2 ; area DATA FSR_ 0x0100:0x0110 ; area BSS RESERVED 0x0110:0x0120 ; area DATA Gen_Purp_BANK0 0x0120:0x0180 accesses 20h-7Fh ; area DATA MEM_Program 0x0180:0x0800 On-chip Program Memory ; BANK_3 ; area DATA FSR_ 0x0180:0x018E ; area BSS RESERVED 0x018E:0x01A0 ; area DATA Gen_Purp_BANK00 0x01A0:0x01C0 accesses A0h-BFh ; area BSS RESERVED 0x01C0:0x01F0 ; area DATA Gen_Purp_BANK01 0x01F0:0x0200 accesses 70h-7Fh ; area DATA MEM_Program 0x0200:0x0800 On-chip Program Memory ; Interrupt and reset vector assignments interrupt RESET 0x0000 RESET ; INPUT/OUTPUT PORTS ; BANK0 (0x0000:0x0080) BANK0:INDF 0x0000 INDF (not a physical register) BANK0:TMR0 0x0001 Timer0 module's register BANK0:PCL 0x0002 Program Counter's (PC) Least Significant Byte BANK0:STATUS 0x0003 STATUS REGISTER BANK0:STATUS.IRP 7 RegIster Bank Select bit BANK0:STATUS.RP1 6 Register Bank Select bit 1 BANK0:STATUS.RP0 5 Register Bank Select bit 0 BANK0:STATUS.TO 4 Time-out bit BANK0:STATUS.PD 3 Power-down bit BANK0:STATUS.Z 2 Zero bit BANK0:STATUS.DC 1 Digit carry/borrow bit BANK0:STATUS.C 0 Carry/borrow bit BANK0:FSR 0x0004 Indirect data memory address pointer BANK0:PORTA 0x0005 PORTA register BANK0:PORTA.RA5 5 PORTA bit 5 BANK0:PORTA.RA4 4 PORTA bit 4 BANK0:PORTA.RA3 3 PORTA bit 3 BANK0:PORTA.RA2 2 PORTA bit 2 BANK0:PORTA.RA1 1 PORTA bit 1 BANK0:PORTA.RA0 0 PORTA bit 0 BANK0:PORTB 0x0006 PORTB register BANK0:PORTB.RB7 7 PORTB bit 7 BANK0:PORTB.RB6 6 PORTB bit 6 BANK0:PORTB.RB5 5 PORTB bit 5 BANK0:PORTB.RB4 4 PORTB bit 4 BANK0:PORTB.RB3 3 PORTB bit 3 BANK0:PORTB.RB2 2 PORTB bit 2 BANK0:PORTB.RB1 1 PORTB bit 1 BANK0:PORTB.RB0 0 PORTB bit 0 BANK0:PORTC 0x0007 PORTC register BANK0:PORTC.RC7 7 PORTC bit 7 BANK0:PORTC.RC6 6 PORTC bit 6 BANK0:PORTC.RC5 5 PORTC bit 5 BANK0:PORTC.RC4 4 PORTC bit 4 BANK0:PORTC.RC3 3 PORTC bit 3 BANK0:PORTC.RC2 2 PORTC bit 2 BANK0:PORTC.RC1 1 PORTC bit 1 BANK0:PORTC.RC0 0 PORTC bit 0 BANK0:RESERVED0008 0x0008 RESERVED BANK0:RESERVED0009 0x0009 RESERVED BANK0:PCLATH 0x000A Write Buffer for the upper 5 bits of the Program Counter BANK0:INTCON 0x000B INTCON REGISTER BANK0:INTCON.GIE 7 Global Interrupt Enable bit BANK0:INTCON.PEIE 6 Peripheral Interrupt Enable bit BANK0:INTCON.TMR0IE 5 TMR0 Overflow Interrupt Enable bit BANK0:INTCON.INTE 4 RB0/INT External Interrupt Enable bit BANK0:INTCON.RBIE 3 RB Port Change Interrupt Enable bit BANK0:INTCON.TMR0IF 2 TMR0 Overflow Interrupt Flag bit BANK0:INTCON.INTF 1 RB0/INT External Interrupt Flag bit BANK0:INTCON.RBIF 0 RB Port Change Interrupt Flag bit BANK0:PIR1 0x000C PIR1 REGISTER BANK0:PIR1.ADIF 6 A/D Converter Interrupt Flag bit BANK0:PIR1.SSPIF 3 Synchronous Serial Port (SSP) Interrupt Flag BANK0:PIR1.CCP1IF 2 CCP1 Interrupt Flag bit BANK0:PIR1.TMR2IF 1 TMR2 to PR2 Match Interrupt Flag bit BANK0:PIR1.TMR1IF 0 TMR1 Overflow Interrupt Flag bit BANK0:PIR2 0x000D PIR2 REGISTER BANK0:PIR2.EEIF 4 EEPROM Write Operation Interrupt Flag bit BANK0:PIR2.BCLIF 3 Bus Collision Interrupt Flag bit BANK0:TMR1L 0x000E Holding register for the Least Significant Byte of the 16-bit TMR1 register BANK0:TMR1H 0x000F Holding register for the Most Significant Byte of the 16-bit TMR1 register BANK0:T1CON 0x0010 TIMER1 CONTROL REGISTER BANK0:T1CON.T1CKPS1 5 Timer1 Input Clock Prescale Select bit 1 BANK0:T1CON.T1CKPS0 4 Timer1 Input Clock Prescale Select bit 0 BANK0:T1CON.T1OSCEN 3 Timer1 Oscillator Enable Control bit BANK0:T1CON.T1SYNC 2 Timer1 External Clock Input Synchronization Control bit BANK0:T1CON.TMR1CS 1 Timer1 Clock Source Select bit BANK0:T1CON.TMR1ON 0 Timer1 On bit BANK0:TMR2 0x0011 Timer2 module's register BANK0:T2CON 0x0012 TIMER2 CONTROL REGISTER BANK0:T2CON.TOUTPS3 6 Timer2 Output Postscale Select bit 3 BANK0:T2CON.TOUTPS2 5 Timer2 Output Postscale Select bit 2 BANK0:T2CON.TOUTPS1 4 Timer2 Output Postscale Select bit 1 BANK0:T2CON.TOUTPS0 3 Timer2 Output Postscale Select bit 0 BANK0:T2CON.TMR2ON 2 Timer2 On bit BANK0:T2CON.T2CKPS1 1 Timer2 Clock Prescale Select bit 1 BANK0:T2CON.T2CKPS0 0 Timer2 Clock Prescale Select bit 0 BANK0:SSPBUF 0x0013 Synchronous Serial Port Receive Buffer/Transmit Register BANK0:SSPCON 0x0014 SYNC SERIAL PORT CONTROL REGISTER BANK0:SSPCON.WCOL 7 Write Collision Detect bit BANK0:SSPCON.SSPOV 6 Receive Overflow Indicator bit BANK0:SSPCON.SSPEN 5 Synchronous Serial Port Enable bit BANK0:SSPCON.CKP 4 Clock Polarity Select bit BANK0:SSPCON.SSPM3 3 Synchronous Serial Port Mode Select bit 3 BANK0:SSPCON.SSPM2 2 Synchronous Serial Port Mode Select bit 2 BANK0:SSPCON.SSPM1 1 Synchronous Serial Port Mode Select bit 1 BANK0:SSPCON.SSPM0 0 Synchronous Serial Port Mode Select bit 0 BANK0:CCPR1L 0x0015 Capture/Compare/PWM1 (LSB) BANK0:CCPR1H 0x0016 Capture/Compare/PWM1 (MSB) BANK0:CCP1CON 0x0017 CCP1CON REGISTER BANK0:CCP1CON.CCP1X 5 PWM Least Significant bit BANK0:CCP1CON.CCP1Y 4 PWM Least Significant bit BANK0:CCP1CON.CCP1M3 3 CCP1 Mode Select bit 3 BANK0:CCP1CON.CCP1M2 2 CCP1 Mode Select bit 2 BANK0:CCP1CON.CCP1M1 1 CCP1 Mode Select bit 1 BANK0:CCP1CON.CCP1M0 0 CCP1 Mode Select bit 0 BANK0:RESERVED0018 0x0018 RESERVED BANK0:RESERVED0019 0x0019 RESERVED BANK0:RESERVED001A 0x001A RESERVED BANK0:RESERVED001B 0x001B RESERVED BANK0:RESERVED001C 0x001C RESERVED BANK0:RESERVED001D 0x001D RESERVED BANK0:ADRESH 0x001E A/D Result Register High Byte BANK0:ADCON0 0x001F ADCON0 REGISTER BANK0:ADCON0.ADCS1 7 A/D Conversion Clock Select bit 1 BANK0:ADCON0.ADCS0 6 A/D Conversion Clock Select bit 0 BANK0:ADCON0.CHS2 5 Analog Channel Select bit 2 BANK0:ADCON0.CHS1 4 Analog Channel Select bit 1 BANK0:ADCON0.CHS0 3 Analog Channel Select bit 0 BANK0:ADCON0.GO_DONE 2 A/D Conversion Status bit BANK0:ADCON0.ADON 0 A/D On bit ; BANK1 (0x0080:0x0100) BANK1:INDF 0x0080 INDF (not a physical register) BANK1:OPTION 0x0081 OPTION REGISTER BANK1:OPTION.RBPU 7 PORTB Pull-up Enable bit BANK1:OPTION.INTEDG 6 Interrupt Edge Select bit BANK1:OPTION.T0CS 5 TMR0 Clock Source Select bit BANK1:OPTION.T0SE 4 TMR0 Source Edge Select bit BANK1:OPTION.PSA 3 Prescaler Assignment bit BANK1:OPTION.PS2 2 Prescaler Rate Select bit 2 BANK1:OPTION.PS1 1 Prescaler Rate Select bit 1 BANK1:OPTION.PS0 0 Prescaler Rate Select bit 0 BANK1:PCL 0x0082 Program Counter's (PC) Least Significant Byte BANK1:STATUS 0x0083 STATUS REGISTER BANK1:STATUS.IRP 7 RegIster Bank Select bit BANK1:STATUS.RP1 6 Register Bank Select bit 1 BANK1:STATUS.RP0 5 Register Bank Select bit 0 BANK1:STATUS.TO 4 Time-out bit BANK1:STATUS.PD 3 Power-down bit BANK1:STATUS.Z 2 Zero bit BANK1:STATUS.DC 1 Digit carry/borrow bit BANK1:STATUS.C 0 Carry/borrow bit BANK1:FSR 0x0084 Indirect data memory address pointer BANK1:TRISA 0x0085 PORTA Data Direction Register BANK1:TRISA.TRISA5 5 PORTA Data Direction Register bit 5 BANK1:TRISA.TRISA4 4 PORTA Data Direction Register bit 4 BANK1:TRISA.TRISA3 3 PORTA Data Direction Register bit 3 BANK1:TRISA.TRISA2 2 PORTA Data Direction Register bit 2 BANK1:TRISA.TRISA1 1 PORTA Data Direction Register bit 1 BANK1:TRISA.TRISA0 0 PORTA Data Direction Register bit 0 BANK1:TRISB 0x0086 PORTB Data Direction Register BANK1:TRISB.TRISB7 7 PORTB Data Direction Register bit 7 BANK1:TRISB.TRISB6 6 PORTB Data Direction Register bit 6 BANK1:TRISB.TRISB5 5 PORTB Data Direction Register bit 5 BANK1:TRISB.TRISB4 4 PORTB Data Direction Register bit 4 BANK1:TRISB.TRISB3 3 PORTB Data Direction Register bit 3 BANK1:TRISB.TRISB2 2 PORTB Data Direction Register bit 2 BANK1:TRISB.TRISB1 1 PORTB Data Direction Register bit 1 BANK1:TRISB.TRISB0 0 PORTB Data Direction Register bit 0 BANK1:TRISC 0x0087 PORTC Data Direction Register BANK1:TRISC.TRISC7 7 PORTC Data Direction Register bit 7 BANK1:TRISC.TRISC6 6 PORTC Data Direction Register bit 6 BANK1:TRISC.TRISC5 5 PORTC Data Direction Register bit 5 BANK1:TRISC.TRISC4 4 PORTC Data Direction Register bit 4 BANK1:TRISC.TRISC3 3 PORTC Data Direction Register bit 3 BANK1:TRISC.TRISC2 2 PORTC Data Direction Register bit 2 BANK1:TRISC.TRISC1 1 PORTC Data Direction Register bit 1 BANK1:TRISC.TRISC0 0 PORTC Data Direction Register bit 0 BANK1:RESERVED0088 0x0088 RESERVED BANK1:RESERVED0089 0x0089 RESERVED BANK1:PCLATH 0x008A Write Buffer for the upper 5 bits of the Program Counter BANK1:INTCON 0x008B INTCON REGISTER BANK1:INTCON.GIE 7 Global Interrupt Enable bit BANK1:INTCON.PEIE 6 Peripheral Interrupt Enable bit BANK1:INTCON.TMR0IE 5 TMR0 Overflow Interrupt Enable bit BANK1:INTCON.INTE 4 RB0/INT External Interrupt Enable bit BANK1:INTCON.RBIE 3 RB Port Change Interrupt Enable bit BANK1:INTCON.TMR0IF 2 TMR0 Overflow Interrupt Flag bit BANK1:INTCON.INTF 1 RB0/INT External Interrupt Flag bit BANK1:INTCON.RBIF 0 RB Port Change Interrupt Flag bit BANK1:PIE1 0x008C PIE1 REGISTER BANK1:PIE1.ADIE 6 A/D Converter Interrupt Enable bit BANK1:PIE1.SSPIE 3 Synchronous Serial Port Interrupt Enable bit BANK1:PIE1.CCP1IE 2 CCP1 Interrupt Enable bit BANK1:PIE1.TMR2IE 1 TMR2 to PR2 Match Interrupt Enable bit BANK1:PIE1.TMR1IE 0 TMR1 Overflow Interrupt Enable bit BANK1:PIE2 0x008D PIE2 REGISTER BANK1:PIE2.EEIE 4 EEPROM Write Operation Interrupt Enable BANK1:PIE2.BCLIE 3 Bus Collision Interrupt Enable bit BANK1:PCON 0x008E PCON REGISTER BANK1:PCON.POR 1 Power-on Reset Status bit BANK1:PCON.BOR 0 Brown-out Reset Status bit BANK1:RESERVED008F 0x008F RESERVED BANK1:RESERVED0090 0x0090 RESERVED BANK1:SSPCON2 0x0091 SYNC SERIAL PORT CONTROL REGISTER2 BANK1:SSPCON2.GCEN 7 General Call Enable bit (In I2C Slave mode only) BANK1:SSPCON2.ACKSTAT 6 Acknowledge Status bit (In I2C Master mode only) BANK1:SSPCON2.ACKDT 5 Acknowledge Data bit (In I2C Master mode only) BANK1:SSPCON2.ACKEN 4 Acknowledge Sequence Enable bit (In I2C Master mode only) BANK1:SSPCON2.RCEN 3 Receive Enable bit (In I2C Master mode only) BANK1:SSPCON2.PEN 2 STOP Condition Enable bit (In I2C Master mode only) BANK1:SSPCON2.RSEN 1 Repeated START Condition Enabled bit (In I2C Master mode only) BANK1:SSPCON2.SEN 0 START Condition Enabled bit (In I2C Master mode only) BANK1:PR2 0x0092 Timer2 Period Register BANK1:SSPADD 0x0093 Synchronous Serial Port (I2C mode) Address Register BANK1:SSPSTAT 0x0094 SYNC SERIAL PORT STATUS REGISTER BANK1:SSPSTAT.SMP 7 Sample bit BANK1:SSPSTAT.CKE 6 SPI Clock Edge Select bit BANK1:SSPSTAT.D_A 5 Data/Address bit (I2C mode only) BANK1:SSPSTAT.P 4 STOP bit (I2C mode only) BANK1:SSPSTAT.S 3 START bit (I2C mode only) BANK1:SSPSTAT.R_W 2 Read/Write bit information (I2C mode only) BANK1:SSPSTAT.UA 1 Update Address bit (10-bit I2C mode only) BANK1:SSPSTAT.BF 0 Buffer Full Status bit BANK1:RESERVED0095 0x0095 RESERVED BANK1:RESERVED0096 0x0096 RESERVED BANK1:RESERVED0097 0x0097 RESERVED BANK1:RESERVED0098 0x0098 RESERVED BANK1:RESERVED0099 0x0099 RESERVED BANK1:RESERVED009A 0x009A RESERVED BANK1:RESERVED009B 0x009B RESERVED BANK1:RESERVED009C 0x009C RESERVED BANK1:RESERVED009D 0x009D RESERVED BANK1:ADRESL 0x009E A/D Result Register Low Byte BANK1:ADCON1 0x009F ADCON1 REGISTER BANK1:ADCON1.ADFM 7 A/D Result format select BANK1:ADCON1.PCFG3 3 A/D Port Configuration Control bit 3 BANK1:ADCON1.PCFG2 2 A/D Port Configuration Control bit 2 BANK1:ADCON1.PCFG1 1 A/D Port Configuration Control bit 1 BANK1:ADCON1.PCFG0 0 A/D Port Configuration Control bit 0 ; BANK2 (0x0100:0x0180) BANK2:INDF 0x0100 INDF (not a physical register) BANK2:TMR0 0x0101 Timer0 module's register BANK2:PCL 0x0102 Program Counter's (PC) Least Significant Byte BANK2:STATUS 0x0103 STATUS REGISTER BANK2:STATUS.IRP 7 RegIster Bank Select bit BANK2:STATUS.RP1 6 Register Bank Select bit 1 BANK2:STATUS.RP0 5 Register Bank Select bit 0 BANK2:STATUS.TO 4 Time-out bit BANK2:STATUS.PD 3 Power-down bit BANK2:STATUS.Z 2 Zero bit BANK2:STATUS.DC 1 Digit carry/borrow bit BANK2:STATUS.C 0 Carry/borrow bit BANK2:FSR 0x0104 Indirect data memory address pointer BANK2:RESERVED0105 0x0105 RESERVED BANK2:PORTB 0x0106 PORTB register BANK2:PORTB.RB7 7 PORTB bit 7 BANK2:PORTB.RB6 6 PORTB bit 6 BANK2:PORTB.RB5 5 PORTB bit 5 BANK2:PORTB.RB4 4 PORTB bit 4 BANK2:PORTB.RB3 3 PORTB bit 3 BANK2:PORTB.RB2 2 PORTB bit 2 BANK2:PORTB.RB1 1 PORTB bit 1 BANK2:PORTB.RB0 0 PORTB bit 0 BANK2:RESERVED0107 0x0107 RESERVED BANK2:RESERVED0108 0x0108 RESERVED BANK2:RESERVED0109 0x0109 RESERVED BANK2:PCLATH 0x010A Write Buffer for the upper 5 bits of the Program Counter BANK2:INTCON 0x010B INTCON REGISTER BANK2:INTCON.GIE 7 Global Interrupt Enable bit BANK2:INTCON.PEIE 6 Peripheral Interrupt Enable bit BANK2:INTCON.TMR0IE 5 TMR0 Overflow Interrupt Enable bit BANK2:INTCON.INTE 4 RB0/INT External Interrupt Enable bit BANK2:INTCON.RBIE 3 RB Port Change Interrupt Enable bit BANK2:INTCON.TMR0IF 2 TMR0 Overflow Interrupt Flag bit BANK2:INTCON.INTF 1 RB0/INT External Interrupt Flag bit BANK2:INTCON.RBIF 0 RB Port Change Interrupt Flag bit BANK2:EEDATA 0x010C EEPROM data register Low Byte BANK2:EEADR 0x010D EEPROM address register Low Byte BANK2:EEDATH 0x010E EEPROM data register high byte BANK2:EEADRH 0x010F EEPROM address register high byte ; BANK3 (0x0180:0x0200) BANK3:INDF 0x0180 INDF (not a physical register) BANK3:OPTION 0x0181 OPTION REGISTER BANK3:OPTION.RBPU 7 PORTB Pull-up Enable bit BANK3:OPTION.INTEDG 6 Interrupt Edge Select bit BANK3:OPTION.T0CS 5 TMR0 Clock Source Select bit BANK3:OPTION.T0SE 4 TMR0 Source Edge Select bit BANK3:OPTION.PSA 3 Prescaler Assignment bit BANK3:OPTION.PS2 2 Prescaler Rate Select bit 2 BANK3:OPTION.PS1 1 Prescaler Rate Select bit 1 BANK3:OPTION.PS0 0 Prescaler Rate Select bit 0 BANK3:PCL 0x0182 Program Counter's (PC) Least Significant Byte BANK3:STATUS 0x0183 STATUS REGISTER BANK3:STATUS.IRP 7 RegIster Bank Select bit BANK3:STATUS.RP1 6 Register Bank Select bit 1 BANK3:STATUS.RP0 5 Register Bank Select bit 0 BANK3:STATUS.TO 4 Time-out bit BANK3:STATUS.PD 3 Power-down bit BANK3:STATUS.Z 2 Zero bit BANK3:STATUS.DC 1 Digit carry/borrow bit BANK3:STATUS.C 0 Carry/borrow bit BANK3:FSR 0x0184 Indirect data memory address pointer BANK3:RESERVED0185 0x0185 RESERVED BANK3:TRISB 0x0186 PORTB Data Direction Register BANK3:TRISB.TRISB7 7 PORTB Data Direction Register bit 7 BANK3:TRISB.TRISB6 6 PORTB Data Direction Register bit 6 BANK3:TRISB.TRISB5 5 PORTB Data Direction Register bit 5 BANK3:TRISB.TRISB4 4 PORTB Data Direction Register bit 4 BANK3:TRISB.TRISB3 3 PORTB Data Direction Register bit 3 BANK3:TRISB.TRISB2 2 PORTB Data Direction Register bit 2 BANK3:TRISB.TRISB1 1 PORTB Data Direction Register bit 1 BANK3:TRISB.TRISB0 0 PORTB Data Direction Register bit 0 BANK3:RESERVED0187 0x0187 RESERVED BANK3:RESERVED0188 0x0188 RESERVED BANK3:RESERVED0189 0x0189 RESERVED BANK3:PCLATH 0x018A Write Buffer for the upper 5 bits of the Program Counter BANK3:INTCON 0x018B INTCON REGISTER BANK3:INTCON.GIE 7 Global Interrupt Enable bit BANK3:INTCON.PEIE 6 Peripheral Interrupt Enable bit BANK3:INTCON.TMR0IE 5 TMR0 Overflow Interrupt Enable bit BANK3:INTCON.INTE 4 RB0/INT External Interrupt Enable bit BANK3:INTCON.RBIE 3 RB Port Change Interrupt Enable bit BANK3:INTCON.TMR0IF 2 TMR0 Overflow Interrupt Flag bit BANK3:INTCON.INTF 1 RB0/INT External Interrupt Flag bit BANK3:INTCON.RBIF 0 RB Port Change Interrupt Flag bit BANK3:EECON1 0x018C EECON1 REGISTER BANK3:EECON1.EEPGD 7 Program/Data EEPROM Select bit BANK3:EECON1.WRERR 3 EEPROM Error Flag bit BANK3:EECON1.WREN 2 EEPROM Write Enable bit BANK3:EECON1.WR 1 Write Control bit BANK3:EECON1.RD 0 Read Control bit BANK3:EECON2 0x018D EEPROM control register2 (not a physical register) .16HV540 ; http://www.microchip.com/download/lit/pline/picmicro/families/16c5x/40197b.pdf ; PIC16HV540.pdf ; MEMORY MAP area DATA FSR_ 0x0000:0x0007 area DATA Gen_Purp 0x0007:0x0020 General Purpose Register area DATA MEM_Program 0x0020:0x01FF On-chip Program Memory ; Interrupt and reset vector assignments interrupt RESET 0x01FF RESET ; INPUT/OUTPUT PORTS INDF 0x0000 INDF (not a physical register) TMR0 0x0001 8-bit real-time clock/counter PCL 0x0002 Low order 8 bits of PC STATUS 0x0003 STATUS REGISTER STATUS.PCWUF 7 Pin Change Reset bit STATUS.TO 4 Time-out bit STATUS.PD 3 Power-down bit STATUS.Z 2 Zero bit STATUS.DC 1 Digit carry/borrow bit STATUS.C 0 Carry/borrow bit FSR 0x0004 Indirect data memory address pointer PORTA 0x0005 PORTA REGISTER PORTA.RA3 3 PORTA bit 3 PORTA.RA2 2 PORTA bit 2 PORTA.RA1 1 PORTA bit 1 PORTA.RA0 0 PORTA bit 0 PORTB 0x0006 PORTB REGISTER PORTB.RB7 7 PORTB bit 7 PORTB.RB6 6 PORTB bit 6 PORTB.RB5 5 PORTB bit 5 PORTB.RB4 4 PORTB bit 4 PORTB.RB3 3 PORTB bit 3 PORTB.RB2 2 PORTB bit 2 PORTB.RB1 1 PORTB bit 1 PORTB.RB0 0 PORTB bit 0 .16C554 ; http://www.microchip.com/download/lit/pline/picmicro/families/16c55x/40143c.pdf ; PIC16C554_8.pdf ; MEMORY MAP ; BANK_0 area DATA FSR_ 0x0000:0x0020 area DATA Gen_Purp 0x0020:0x0070 General Purpose Register area BSS RESERVED 0x0070:0x0080 area DATA MEM_Program 0x0080:0x0200 On-chip Program Memory ; BANK_1 ; area DATA FSR_ 0x0080:0x008F ; area BSS RESERVED 0x008F:0x0100 ; area DATA MEM_Program 0x0100:0x0200 On-chip Program Memory ; Interrupt and reset vector assignments interrupt RESET 0x0000 RESET ; INPUT/OUTPUT PORTS ; BANK0 (0x0000:0x0080) BANK0:INDF 0x0000 INDF (not a physical register) BANK0:TMR0 0x0001 Timer0 Module's Register BANK0:PCL 0x0002 Program Counter's (PC) Least Significant Byte BANK0:STATUS 0x0003 STATUS REGISTER BANK0:STATUS.IRP 7 Register Bank Select bit BANK0:STATUS.RP1 6 Register Bank Select bit 1 BANK0:STATUS.RP0 5 Register Bank Select bit 0 BANK0:STATUS.TO 4 Time-out bit BANK0:STATUS.PD 3 Power-down bit BANK0:STATUS.Z 2 Zero bit BANK0:STATUS.DC 1 Digit carry/borrow bit BANK0:STATUS.C 0 Carry/borrow bit BANK0:FSR 0x0004 Indirect data memory address pointer BANK0:PORTA 0x0005 PORTA REGISTER BANK0:PORTA.RA4 4 PORTA bit 4 BANK0:PORTA.RA3 3 PORTA bit 3 BANK0:PORTA.RA2 2 PORTA bit 2 BANK0:PORTA.RA1 1 PORTA bit 1 BANK0:PORTA.RA0 0 PORTA bit 0 BANK0:PORTB 0x0006 PORTB REGISTER BANK0:PORTB.RB7 7 PORTB bit 7 BANK0:PORTB.RB6 6 PORTB bit 6 BANK0:PORTB.RB5 5 PORTB bit 5 BANK0:PORTB.RB4 4 PORTB bit 4 BANK0:PORTB.RB3 3 PORTB bit 3 BANK0:PORTB.RB2 2 PORTB bit 2 BANK0:PORTB.RB1 1 PORTB bit 1 BANK0:PORTB.RB0 0 PORTB bit 0 BANK0:RESERVED0007 0x0007 RESERVED BANK0:RESERVED0008 0x0008 RESERVED BANK0:RESERVED0009 0x0009 RESERVED BANK0:PCLATH 0x000A Write buffer for upper 5 bits of program counter BANK0:INTCON 0x000B INTCON REGISTER BANK0:INTCON.GIE 7 Global Interrupt Enable bit BANK0:INTCON.T0IE 5 TMR0 Overflow Interrupt Enable bit BANK0:INTCON.INTE 4 RB0/INT External Interrupt Enable bit BANK0:INTCON.RBIE 3 RB Port Change Interrupt Enable bit BANK0:INTCON.T0IF 2 TMR0 Overflow Interrupt Flag bit BANK0:INTCON.INTF 1 RB0/INT External Interrupt Flag bit BANK0:INTCON.RBIF 0 RB Port Change Interrupt Flag bit BANK0:RESERVED000C 0x000C RESERVED BANK0:RESERVED000D 0x000D RESERVED BANK0:RESERVED000E 0x000E RESERVED BANK0:RESERVED000F 0x000F RESERVED BANK0:RESERVED0010 0x0010 RESERVED BANK0:RESERVED0011 0x0011 RESERVED BANK0:RESERVED0012 0x0012 RESERVED BANK0:RESERVED0013 0x0013 RESERVED BANK0:RESERVED0014 0x0014 RESERVED BANK0:RESERVED0015 0x0015 RESERVED BANK0:RESERVED0016 0x0016 RESERVED BANK0:RESERVED0017 0x0017 RESERVED BANK0:RESERVED0018 0x0018 RESERVED BANK0:RESERVED0019 0x0019 RESERVED BANK0:RESERVED001A 0x001A RESERVED BANK0:RESERVED001B 0x001B RESERVED BANK0:RESERVED001C 0x001C RESERVED BANK0:RESERVED001D 0x001D RESERVED BANK0:RESERVED001E 0x001E RESERVED BANK0:RESERVED001F 0x001F RESERVED ; BANK1 (0x0080:0x0100) BANK1:INDF 0x0080 INDF (not a physical register) BANK1:OPTION 0x0081 OPTION REGISTER BANK1:OPTION.RBPU 7 PORTB Pull-up Enable bit BANK1:OPTION.INTEDG 6 Interrupt Edge Select bit BANK1:OPTION.T0CS 5 TMR0 Clock Source Select bit BANK1:OPTION.T0SE 4 TMR0 Source Edge Select bit BANK1:OPTION.PSA 3 Prescaler Assignment bit BANK1:OPTION.PS2 2 Prescaler Rate Select bit 2 BANK1:OPTION.PS1 1 Prescaler Rate Select bit 1 BANK1:OPTION.PS0 0 Prescaler Rate Select bit 0 BANK1:PCL 0x0082 Program Counter's (PC) Least Significant Byte BANK1:STATUS 0x0083 STATUS REGISTER BANK1:STATUS.RP0 5 Register Bank Select bit 0 BANK1:STATUS.TO 4 Time-out bit BANK1:STATUS.PD 3 Power-down bit BANK1:STATUS.Z 2 Zero bit BANK1:STATUS.DC 1 Digit carry/borrow bit BANK1:STATUS.C 0 Carry/borrow bit BANK1:FSR 0x0084 Indirect data memory address pointer BANK1:TRISA 0x0085 TRISA REGISTER BANK1:TRISA.TRISA4 4 TRISA bit 4 BANK1:TRISA.TRISA3 3 TRISA bit 3 BANK1:TRISA.TRISA2 2 TRISA bit 2 BANK1:TRISA.TRISA1 1 TRISA bit 1 BANK1:TRISA.TRISA0 0 TRISA bit 0 BANK1:TRISB 0x0086 TRISB REGISTER BANK1:TRISB.TRISB7 7 TRISB bit 7 BANK1:TRISB.TRISB6 6 TRISB bit 6 BANK1:TRISB.TRISB5 5 TRISB bit 5 BANK1:TRISB.TRISB4 4 TRISB bit 4 BANK1:TRISB.TRISB3 3 TRISB bit 3 BANK1:TRISB.TRISB2 2 TRISB bit 2 BANK1:TRISB.TRISB1 1 TRISB bit 1 BANK1:TRISB.TRISB0 0 TRISB bit 0 BANK1:RESERVED0087 0x0087 RESERVED BANK1:RESERVED0088 0x0088 RESERVED BANK1:RESERVED0089 0x0089 RESERVED BANK1:PCLATH 0x008A Write buffer for upper 5 bits of program counter BANK1:INTCON 0x008B INTCON REGISTER BANK1:INTCON.GIE 7 Global Interrupt Enable bit BANK1:INTCON.T0IE 5 TMR0 Overflow Interrupt Enable bit BANK1:INTCON.INTE 4 RB0/INT External Interrupt Enable bit BANK1:INTCON.RBIE 3 RB Port Change Interrupt Enable bit BANK1:INTCON.T0IF 2 TMR0 Overflow Interrupt Flag bit BANK1:INTCON.INTF 1 RB0/INT External Interrupt Flag bit BANK1:INTCON.RBIF 0 RB Port Change Interrupt Flag bit BANK1:RESERVED008C 0x008C RESERVED BANK1:RESERVED008D 0x008D RESERVED BANK1:PCON 0x008E PCON REGISTER BANK1:PCON.POR 1 Power-on Reset Status bit .16C558 ; http://www.microchip.com/download/lit/pline/picmicro/families/16c55x/40143c.pdf ; PIC16C554_8.pdf ; MEMORY MAP ; BANK_0 area DATA FSR_ 0x0000:0x0020 area DATA Gen_Purp 0x0020:0x0080 General Purpose Register area DATA MEM_Program 0x0080:0x0800 On-chip Program Memory ; BANK_1 ; area DATA FSR_ 0x0080:0x00A0 ; area DATA Gen_Purp 0x00A0:0x00C0 General Purpose Register ; area BSS RESERVED 0x00C0:0x0100 ; area DATA MEM_Program 0x0100:0x0800 On-chip Program Memory ; Interrupt and reset vector assignments interrupt RESET 0x0000 RESET ; INPUT/OUTPUT PORTS ; BANK0 (0x0000:0x0080) BANK0:INDF 0x0000 INDF (not a physical register) BANK0:TMR0 0x0001 Timer0 Module's Register BANK0:PCL 0x0002 Program Counter's (PC) Least Significant Byte BANK0:STATUS 0x0003 STATUS REGISTER BANK0:STATUS.IRP 7 Register Bank Select bit BANK0:STATUS.RP1 6 Register Bank Select bit 1 BANK0:STATUS.RP0 5 Register Bank Select bit 0 BANK0:STATUS.TO 4 Time-out bit BANK0:STATUS.PD 3 Power-down bit BANK0:STATUS.Z 2 Zero bit BANK0:STATUS.DC 1 Digit carry/borrow bit BANK0:STATUS.C 0 Carry/borrow bit BANK0:FSR 0x0004 Indirect data memory address pointer BANK0:PORTA 0x0005 PORTA REGISTER BANK0:PORTA.RA4 4 PORTA bit 4 BANK0:PORTA.RA3 3 PORTA bit 3 BANK0:PORTA.RA2 2 PORTA bit 2 BANK0:PORTA.RA1 1 PORTA bit 1 BANK0:PORTA.RA0 0 PORTA bit 0 BANK0:PORTB 0x0006 PORTB REGISTER BANK0:PORTB.RB7 7 PORTB bit 7 BANK0:PORTB.RB6 6 PORTB bit 6 BANK0:PORTB.RB5 5 PORTB bit 5 BANK0:PORTB.RB4 4 PORTB bit 4 BANK0:PORTB.RB3 3 PORTB bit 3 BANK0:PORTB.RB2 2 PORTB bit 2 BANK0:PORTB.RB1 1 PORTB bit 1 BANK0:PORTB.RB0 0 PORTB bit 0 BANK0:RESERVED0007 0x0007 RESERVED BANK0:RESERVED0008 0x0008 RESERVED BANK0:RESERVED0009 0x0009 RESERVED BANK0:PCLATH 0x000A Write buffer for upper 5 bits of program counter BANK0:INTCON 0x000B INTCON REGISTER BANK0:INTCON.GIE 7 Global Interrupt Enable bit BANK0:INTCON.T0IE 5 TMR0 Overflow Interrupt Enable bit BANK0:INTCON.INTE 4 RB0/INT External Interrupt Enable bit BANK0:INTCON.RBIE 3 RB Port Change Interrupt Enable bit BANK0:INTCON.T0IF 2 TMR0 Overflow Interrupt Flag bit BANK0:INTCON.INTF 1 RB0/INT External Interrupt Flag bit BANK0:INTCON.RBIF 0 RB Port Change Interrupt Flag bit BANK0:RESERVED000C 0x000C RESERVED BANK0:RESERVED000D 0x000D RESERVED BANK0:RESERVED000E 0x000E RESERVED BANK0:RESERVED000F 0x000F RESERVED BANK0:RESERVED0010 0x0010 RESERVED BANK0:RESERVED0011 0x0011 RESERVED BANK0:RESERVED0012 0x0012 RESERVED BANK0:RESERVED0013 0x0013 RESERVED BANK0:RESERVED0014 0x0014 RESERVED BANK0:RESERVED0015 0x0015 RESERVED BANK0:RESERVED0016 0x0016 RESERVED BANK0:RESERVED0017 0x0017 RESERVED BANK0:RESERVED0018 0x0018 RESERVED BANK0:RESERVED0019 0x0019 RESERVED BANK0:RESERVED001A 0x001A RESERVED BANK0:RESERVED001B 0x001B RESERVED BANK0:RESERVED001C 0x001C RESERVED BANK0:RESERVED001D 0x001D RESERVED BANK0:RESERVED001E 0x001E RESERVED BANK0:RESERVED001F 0x001F RESERVED ; BANK1 (0x0080:0x0100) BANK1:INDF 0x0080 INDF (not a physical register) BANK1:OPTION 0x0081 OPTION REGISTER BANK1:OPTION.RBPU 7 PORTB Pull-up Enable bit BANK1:OPTION.INTEDG 6 Interrupt Edge Select bit BANK1:OPTION.T0CS 5 TMR0 Clock Source Select bit BANK1:OPTION.T0SE 4 TMR0 Source Edge Select bit BANK1:OPTION.PSA 3 Prescaler Assignment bit BANK1:OPTION.PS2 2 Prescaler Rate Select bit 2 BANK1:OPTION.PS1 1 Prescaler Rate Select bit 1 BANK1:OPTION.PS0 0 Prescaler Rate Select bit 0 BANK1:PCL 0x0082 Program Counter's (PC) Least Significant Byte BANK1:STATUS 0x0083 STATUS REGISTER BANK1:STATUS.RP0 5 Register Bank Select bit 0 BANK1:STATUS.TO 4 Time-out bit BANK1:STATUS.PD 3 Power-down bit BANK1:STATUS.Z 2 Zero bit BANK1:STATUS.DC 1 Digit carry/borrow bit BANK1:STATUS.C 0 Carry/borrow bit BANK1:FSR 0x0084 Indirect data memory address pointer BANK1:TRISA 0x0085 TRISA REGISTER BANK1:TRISA.TRISA4 4 TRISA bit 4 BANK1:TRISA.TRISA3 3 TRISA bit 3 BANK1:TRISA.TRISA2 2 TRISA bit 2 BANK1:TRISA.TRISA1 1 TRISA bit 1 BANK1:TRISA.TRISA0 0 TRISA bit 0 BANK1:TRISB 0x0086 TRISB REGISTER BANK1:TRISB.TRISB7 7 TRISB bit 7 BANK1:TRISB.TRISB6 6 TRISB bit 6 BANK1:TRISB.TRISB5 5 TRISB bit 5 BANK1:TRISB.TRISB4 4 TRISB bit 4 BANK1:TRISB.TRISB3 3 TRISB bit 3 BANK1:TRISB.TRISB2 2 TRISB bit 2 BANK1:TRISB.TRISB1 1 TRISB bit 1 BANK1:TRISB.TRISB0 0 TRISB bit 0 BANK1:RESERVED0087 0x0087 RESERVED BANK1:RESERVED0088 0x0088 RESERVED BANK1:RESERVED0089 0x0089 RESERVED BANK1:PCLATH 0x008A Write buffer for upper 5 bits of program counter BANK1:INTCON 0x008B INTCON REGISTER BANK1:INTCON.GIE 7 Global Interrupt Enable bit BANK1:INTCON.T0IE 5 TMR0 Overflow Interrupt Enable bit BANK1:INTCON.INTE 4 RB0/INT External Interrupt Enable bit BANK1:INTCON.RBIE 3 RB Port Change Interrupt Enable bit BANK1:INTCON.T0IF 2 TMR0 Overflow Interrupt Flag bit BANK1:INTCON.INTF 1 RB0/INT External Interrupt Flag bit BANK1:INTCON.RBIF 0 RB Port Change Interrupt Flag bit BANK1:RESERVED008C 0x008C RESERVED BANK1:RESERVED008D 0x008D RESERVED BANK1:PCON 0x008E PCON REGISTER BANK1:PCON.POR 1 Power-on Reset Status bit .16C54 ; http://www.microchip.com/download/lit/pline/picmicro/families/16c5x/30453d.pdf ; PIC16C5X.pdf ; MEMORY MAP area DATA FSR_ 0x0000:0x0007 area DATA Gen_Purp 0x0007:0x0020 General Purpose Register area DATA MEM_Program0 0x0020:0x01FF On-chip Program Memory (Page 0) ; Interrupt and reset vector assignments interrupt RESET 0x01FF RESET ; INPUT/OUTPUT PORTS INDF 0x0000 INDF (not a physical register) TMR0 0x0001 Timer0 Module Register PCL 0x0002 Low order 8 bits of PC STATUS 0x0003 STATUS REGISTER STATUS.PA1 6 Program page preselect bit 1 STATUS.PA0 5 Program page preselect bit 0 STATUS.TO 4 Time-out bit STATUS.PD 3 Power-down bit STATUS.Z 2 Zero bit STATUS.DC 1 Digit carry/borrow bit STATUS.C 0 Carry/borrow bit FSR 0x0004 Indirect data memory address pointer PORTA 0x0005 PORTA REGISTER PORTA.RA3 3 PORTA bit 3 PORTA.RA2 2 PORTA bit 2 PORTA.RA1 1 PORTA bit 1 PORTA.RA0 0 PORTA bit 0 PORTB 0x0006 PORTB REGISTER PORTB.RB7 7 PORTB bit 7 PORTB.RB6 6 PORTB bit 6 PORTB.RB5 5 PORTB bit 5 PORTB.RB4 4 PORTB bit 4 PORTB.RB3 3 PORTB bit 3 PORTB.RB2 2 PORTB bit 2 PORTB.RB1 1 PORTB bit 1 PORTB.RB0 0 PORTB bit 0 .16C55 ; http://www.microchip.com/download/lit/pline/picmicro/families/16c5x/30453d.pdf ; PIC16C5X.pdf ; MEMORY MAP area DATA FSR_ 0x0000:0x0008 area DATA Gen_Purp 0x0008:0x0020 General Purpose Register area DATA MEM_Program0 0x0020:0x01FF On-chip Program Memory (Page 0) ; Interrupt and reset vector assignments interrupt RESET 0x01FF RESET ; INPUT/OUTPUT PORTS INDF 0x0000 INDF (not a physical register) TMR0 0x0001 Timer0 Module Register PCL 0x0002 Low order 8 bits of PC STATUS 0x0003 STATUS REGISTER STATUS.PA1 6 Program page preselect bit 1 STATUS.PA0 5 Program page preselect bit 0 STATUS.TO 4 Time-out bit STATUS.PD 3 Power-down bit STATUS.Z 2 Zero bit STATUS.DC 1 Digit carry/borrow bit STATUS.C 0 Carry/borrow bit FSR 0x0004 Indirect data memory address pointer PORTA 0x0005 PORTA REGISTER PORTA.RA3 3 PORTA bit 3 PORTA.RA2 2 PORTA bit 2 PORTA.RA1 1 PORTA bit 1 PORTA.RA0 0 PORTA bit 0 PORTB 0x0006 PORTB REGISTER PORTB.RB7 7 PORTB bit 7 PORTB.RB6 6 PORTB bit 6 PORTB.RB5 5 PORTB bit 5 PORTB.RB4 4 PORTB bit 4 PORTB.RB3 3 PORTB bit 3 PORTB.RB2 2 PORTB bit 2 PORTB.RB1 1 PORTB bit 1 PORTB.RB0 0 PORTB bit 0 PORTC 0x0007 PORTC REGISTER PORTC.RC7 7 PORTC bit 7 PORTC.RC6 6 PORTC bit 6 PORTC.RC5 5 PORTC bit 5 PORTC.RC4 4 PORTC bit 4 PORTC.RC3 3 PORTC bit 3 PORTC.RC2 2 PORTC bit 2 PORTC.RC1 1 PORTC bit 1 PORTC.RC0 0 PORTC bit 0 .16C56 ; http://www.microchip.com/download/lit/pline/picmicro/families/16c5x/30453d.pdf ; PIC16C5X.pdf ; MEMORY MAP area DATA FSR_ 0x0000:0x0007 area DATA Gen_Purp 0x0007:0x0020 General Purpose Register area DATA MEM_Program0 0x0020:0x0200 On-chip Program Memory (Page 0) area DATA MEM_Program1 0x0200:0x03FF On-chip Program Memory (Page 1) ; Interrupt and reset vector assignments interrupt RESET 0x03FF RESET ; INPUT/OUTPUT PORTS INDF 0x0000 INDF (not a physical register) TMR0 0x0001 Timer0 Module Register PCL 0x0002 Low order 8 bits of PC STATUS 0x0003 STATUS REGISTER STATUS.PA1 6 Program page preselect bit 1 STATUS.PA0 5 Program page preselect bit 0 STATUS.TO 4 Time-out bit STATUS.PD 3 Power-down bit STATUS.Z 2 Zero bit STATUS.DC 1 Digit carry/borrow bit STATUS.C 0 Carry/borrow bit FSR 0x0004 Indirect data memory address pointer PORTA 0x0005 PORTA REGISTER PORTA.RA3 3 PORTA bit 3 PORTA.RA2 2 PORTA bit 2 PORTA.RA1 1 PORTA bit 1 PORTA.RA0 0 PORTA bit 0 PORTB 0x0006 PORTB REGISTER PORTB.RB7 7 PORTB bit 7 PORTB.RB6 6 PORTB bit 6 PORTB.RB5 5 PORTB bit 5 PORTB.RB4 4 PORTB bit 4 PORTB.RB3 3 PORTB bit 3 PORTB.RB2 2 PORTB bit 2 PORTB.RB1 1 PORTB bit 1 PORTB.RB0 0 PORTB bit 0 .16C57 ; http://www.microchip.com/download/lit/pline/picmicro/families/16c5x/30453d.pdf ; PIC16C5X.pdf ; MEMORY MAP ; BANK_0 area DATA FSR_ 0x0000:0x0008 area DATA Gen_Purp 0x0008:0x0020 General Purpose Register area DATA MEM_Program0 0x0020:0x0200 On-chip Program Memory (Page 0) area DATA MEM_Program1 0x0200:0x0400 On-chip Program Memory (Page 1) area DATA MEM_Program2 0x0400:0x0600 On-chip Program Memory (Page 2) area DATA MEM_Program3 0x0600:0x07FF On-chip Program Memory (Page 3) ; BANK_1 ; area DATA FSR_ 0x0020:0x0028 ; area DATA Gen_Purp 0x0028:0x0040 General Purpose Register ; area DATA MEM_Program0 0x0040:0x0200 On-chip Program Memory (Page 0) ; area DATA MEM_Program1 0x0200:0x0400 On-chip Program Memory (Page 1) ; area DATA MEM_Program2 0x0400:0x0600 On-chip Program Memory (Page 2) ; area DATA MEM_Program3 0x0600:0x07FF On-chip Program Memory (Page 3) ; BANK_2 ; area DATA FSR_ 0x0040:0x0048 ; area DATA Gen_Purp 0x0048:0x0060 General Purpose Register ; area DATA MEM_Program0 0x0060:0x0200 On-chip Program Memory (Page 0) ; area DATA MEM_Program1 0x0200:0x0400 On-chip Program Memory (Page 1) ; area DATA MEM_Program2 0x0400:0x0600 On-chip Program Memory (Page 2) ; area DATA MEM_Program3 0x0600:0x07FF On-chip Program Memory (Page 3) ; BANK_3 ; area DATA FSR_ 0x0060:0x0068 ; area DATA Gen_Purp 0x0068:0x0080 General Purpose Register ; area DATA MEM_Program0 0x0080:0x0200 On-chip Program Memory (Page 0) ; area DATA MEM_Program1 0x0200:0x0400 On-chip Program Memory (Page 1) ; area DATA MEM_Program2 0x0400:0x0600 On-chip Program Memory (Page 2) ; area DATA MEM_Program3 0x0600:0x07FF On-chip Program Memory (Page 3) ; Interrupt and reset vector assignments interrupt RESET 0x07FF RESET ; INPUT/OUTPUT PORTS ; BANK0 (0x0000:0x0020) BANK0:INDF 0x0000 INDF (not a physical register) BANK0:TMR0 0x0001 Timer0 Module Register BANK0:PCL 0x0002 Low order 8 bits of PC BANK0:STATUS 0x0003 STATUS REGISTER BANK0:STATUS.PA1 6 Program page preselect bit 1 BANK0:STATUS.PA0 5 Program page preselect bit 0 BANK0:STATUS.TO 4 Time-out bit BANK0:STATUS.PD 3 Power-down bit BANK0:STATUS.Z 2 Zero bit BANK0:STATUS.DC 1 Digit carry/borrow bit BANK0:STATUS.C 0 Carry/borrow bit BANK0:FSR 0x0004 Indirect data memory address pointer BANK0:PORTA 0x0005 PORTA REGISTER BANK0:PORTA.RA3 3 PORTA bit 3 BANK0:PORTA.RA2 2 PORTA bit 2 BANK0:PORTA.RA1 1 PORTA bit 1 BANK0:PORTA.RA0 0 PORTA bit 0 BANK0:PORTB 0x0006 PORTB REGISTER BANK0:PORTB.RB7 7 PORTB bit 7 BANK0:PORTB.RB6 6 PORTB bit 6 BANK0:PORTB.RB5 5 PORTB bit 5 BANK0:PORTB.RB4 4 PORTB bit 4 BANK0:PORTB.RB3 3 PORTB bit 3 BANK0:PORTB.RB2 2 PORTB bit 2 BANK0:PORTB.RB1 1 PORTB bit 1 BANK0:PORTB.RB0 0 PORTB bit 0 BANK0:PORTC 0x0007 PORTC REGISTER BANK0:PORTC.RC7 7 PORTC bit 7 BANK0:PORTC.RC6 6 PORTC bit 6 BANK0:PORTC.RC5 5 PORTC bit 5 BANK0:PORTC.RC4 4 PORTC bit 4 BANK0:PORTC.RC3 3 PORTC bit 3 BANK0:PORTC.RC2 2 PORTC bit 2 BANK0:PORTC.RC1 1 PORTC bit 1 BANK0:PORTC.RC0 0 PORTC bit 0 ; BANK1 (0x0020:0x0040) BANK1:INDF 0x0020 INDF (not a physical register) BANK1:TMR0 0x0021 Timer0 Module Register BANK1:PCL 0x0022 Low order 8 bits of PC BANK1:STATUS 0x0023 STATUS REGISTER BANK1:STATUS.PA1 6 Program page preselect bit 1 BANK1:STATUS.PA0 5 Program page preselect bit 0 BANK1:STATUS.TO 4 Time-out bit BANK1:STATUS.PD 3 Power-down bit BANK1:STATUS.Z 2 Zero bit BANK1:STATUS.DC 1 Digit carry/borrow bit BANK1:STATUS.C 0 Carry/borrow bit BANK1:FSR 0x0024 Indirect data memory address pointer BANK1:PORTA 0x0025 PORTA REGISTER BANK1:PORTA.RA3 3 PORTA bit 3 BANK1:PORTA.RA2 2 PORTA bit 2 BANK1:PORTA.RA1 1 PORTA bit 1 BANK1:PORTA.RA0 0 PORTA bit 0 BANK1:PORTB 0x0026 PORTB REGISTER BANK1:PORTB.RB7 7 PORTB bit 7 BANK1:PORTB.RB6 6 PORTB bit 6 BANK1:PORTB.RB5 5 PORTB bit 5 BANK1:PORTB.RB4 4 PORTB bit 4 BANK1:PORTB.RB3 3 PORTB bit 3 BANK1:PORTB.RB2 2 PORTB bit 2 BANK1:PORTB.RB1 1 PORTB bit 1 BANK1:PORTB.RB0 0 PORTB bit 0 BANK1:PORTC 0x0027 PORTC REGISTER BANK1:PORTC.RC7 7 PORTC bit 7 BANK1:PORTC.RC6 6 PORTC bit 6 BANK1:PORTC.RC5 5 PORTC bit 5 BANK1:PORTC.RC4 4 PORTC bit 4 BANK1:PORTC.RC3 3 PORTC bit 3 BANK1:PORTC.RC2 2 PORTC bit 2 BANK1:PORTC.RC1 1 PORTC bit 1 BANK1:PORTC.RC0 0 PORTC bit 0 ; BANK2 (0x0040:0x0060) BANK2:INDF 0x0040 INDF (not a physical register) BANK2:TMR0 0x0041 Timer0 Module Register BANK2:PCL 0x0042 Low order 8 bits of PC BANK2:STATUS 0x0043 STATUS REGISTER BANK2:STATUS.PA1 6 Program page preselect bit 1 BANK2:STATUS.PA0 5 Program page preselect bit 0 BANK2:STATUS.TO 4 Time-out bit BANK2:STATUS.PD 3 Power-down bit BANK2:STATUS.Z 2 Zero bit BANK2:STATUS.DC 1 Digit carry/borrow bit BANK2:STATUS.C 0 Carry/borrow bit BANK2:FSR 0x0044 Indirect data memory address pointer BANK2:PORTA 0x0045 PORTA REGISTER BANK2:PORTA.RA3 3 PORTA bit 3 BANK2:PORTA.RA2 2 PORTA bit 2 BANK2:PORTA.RA1 1 PORTA bit 1 BANK2:PORTA.RA0 0 PORTA bit 0 BANK2:PORTB 0x0046 PORTB REGISTER BANK2:PORTB.RB7 7 PORTB bit 7 BANK2:PORTB.RB6 6 PORTB bit 6 BANK2:PORTB.RB5 5 PORTB bit 5 BANK2:PORTB.RB4 4 PORTB bit 4 BANK2:PORTB.RB3 3 PORTB bit 3 BANK2:PORTB.RB2 2 PORTB bit 2 BANK2:PORTB.RB1 1 PORTB bit 1 BANK2:PORTB.RB0 0 PORTB bit 0 BANK2:PORTC 0x0047 PORTC REGISTER BANK2:PORTC.RC7 7 PORTC bit 7 BANK2:PORTC.RC6 6 PORTC bit 6 BANK2:PORTC.RC5 5 PORTC bit 5 BANK2:PORTC.RC4 4 PORTC bit 4 BANK2:PORTC.RC3 3 PORTC bit 3 BANK2:PORTC.RC2 2 PORTC bit 2 BANK2:PORTC.RC1 1 PORTC bit 1 BANK2:PORTC.RC0 0 PORTC bit 0 ; BANK3 (0x0060:0x0080) BANK3:INDF 0x0060 INDF (not a physical register) BANK3:TMR0 0x0061 Timer0 Module Register BANK3:PCL 0x0062 Low order 8 bits of PC BANK3:STATUS 0x0063 STATUS REGISTER BANK3:STATUS.PA1 6 Program page preselect bit 1 BANK3:STATUS.PA0 5 Program page preselect bit 0 BANK3:STATUS.TO 4 Time-out bit BANK3:STATUS.PD 3 Power-down bit BANK3:STATUS.Z 2 Zero bit BANK3:STATUS.DC 1 Digit carry/borrow bit BANK3:STATUS.C 0 Carry/borrow bit BANK3:FSR 0x0064 Indirect data memory address pointer BANK3:PORTA 0x0065 PORTA REGISTER BANK3:PORTA.RA3 3 PORTA bit 3 BANK3:PORTA.RA2 2 PORTA bit 2 BANK3:PORTA.RA1 1 PORTA bit 1 BANK3:PORTA.RA0 0 PORTA bit 0 BANK3:PORTB 0x0066 PORTB REGISTER BANK3:PORTB.RB7 7 PORTB bit 7 BANK3:PORTB.RB6 6 PORTB bit 6 BANK3:PORTB.RB5 5 PORTB bit 5 BANK3:PORTB.RB4 4 PORTB bit 4 BANK3:PORTB.RB3 3 PORTB bit 3 BANK3:PORTB.RB2 2 PORTB bit 2 BANK3:PORTB.RB1 1 PORTB bit 1 BANK3:PORTB.RB0 0 PORTB bit 0 BANK3:PORTC 0x0067 PORTC REGISTER BANK3:PORTC.RC7 7 PORTC bit 7 BANK3:PORTC.RC6 6 PORTC bit 6 BANK3:PORTC.RC5 5 PORTC bit 5 BANK3:PORTC.RC4 4 PORTC bit 4 BANK3:PORTC.RC3 3 PORTC bit 3 BANK3:PORTC.RC2 2 PORTC bit 2 BANK3:PORTC.RC1 1 PORTC bit 1 BANK3:PORTC.RC0 0 PORTC bit 0 .16C58 ; http://www.microchip.com/download/lit/pline/picmicro/families/16c5x/30453d.pdf ; PIC16C5X.pdf ; MEMORY MAP ; BANK_0 area DATA FSR_ 0x0000:0x0007 area DATA Gen_Purp 0x0007:0x0020 General Purpose Register area DATA MEM_Program0 0x0020:0x0200 On-chip Program Memory (Page 0) area DATA MEM_Program1 0x0200:0x0400 On-chip Program Memory (Page 1) area DATA MEM_Program2 0x0400:0x0600 On-chip Program Memory (Page 2) area DATA MEM_Program3 0x0600:0x07FF On-chip Program Memory (Page 3) ; BANK_1 ; area DATA FSR_ 0x0020:0x0027 ; area DATA Gen_Purp 0x0027:0x0040 General Purpose Register ; area DATA MEM_Program0 0x0040:0x0200 On-chip Program Memory (Page 0) ; area DATA MEM_Program1 0x0200:0x0400 On-chip Program Memory (Page 1) ; area DATA MEM_Program2 0x0400:0x0600 On-chip Program Memory (Page 2) ; area DATA MEM_Program3 0x0600:0x07FF On-chip Program Memory (Page 3) ; BANK_2 ; area DATA FSR_ 0x0040:0x0047 ; area DATA Gen_Purp 0x0047:0x0060 General Purpose Register ; area DATA MEM_Program0 0x0060:0x0200 On-chip Program Memory (Page 0) ; area DATA MEM_Program1 0x0200:0x0400 On-chip Program Memory (Page 1) ; area DATA MEM_Program2 0x0400:0x0600 On-chip Program Memory (Page 2) ; area DATA MEM_Program3 0x0600:0x07FF On-chip Program Memory (Page 3) ; BANK_3 ; area DATA FSR_ 0x0060:0x0067 ; area DATA Gen_Purp 0x0067:0x0080 General Purpose Register ; area DATA MEM_Program0 0x0080:0x0200 On-chip Program Memory (Page 0) ; area DATA MEM_Program1 0x0200:0x0400 On-chip Program Memory (Page 1) ; area DATA MEM_Program2 0x0400:0x0600 On-chip Program Memory (Page 2) ; area DATA MEM_Program3 0x0600:0x07FF On-chip Program Memory (Page 3) ; Interrupt and reset vector assignments interrupt RESET 0x07FF RESET ; INPUT/OUTPUT PORTS ; BANK0 (0x0000:0x0020) BANK0:INDF 0x0000 INDF (not a physical register) BANK0:TMR0 0x0001 Timer0 Module Register BANK0:PCL 0x0002 Low order 8 bits of PC BANK0:STATUS 0x0003 STATUS REGISTER BANK0:STATUS.PA1 6 Program page preselect bit 1 BANK0:STATUS.PA0 5 Program page preselect bit 0 BANK0:STATUS.TO 4 Time-out bit BANK0:STATUS.PD 3 Power-down bit BANK0:STATUS.Z 2 Zero bit BANK0:STATUS.DC 1 Digit carry/borrow bit BANK0:STATUS.C 0 Carry/borrow bit BANK0:FSR 0x0004 Indirect data memory address pointer BANK0:PORTA 0x0005 PORTA REGISTER BANK0:PORTA.RA3 3 PORTA bit 3 BANK0:PORTA.RA2 2 PORTA bit 2 BANK0:PORTA.RA1 1 PORTA bit 1 BANK0:PORTA.RA0 0 PORTA bit 0 BANK0:PORTB 0x0006 PORTB REGISTER BANK0:PORTB.RB7 7 PORTB bit 7 BANK0:PORTB.RB6 6 PORTB bit 6 BANK0:PORTB.RB5 5 PORTB bit 5 BANK0:PORTB.RB4 4 PORTB bit 4 BANK0:PORTB.RB3 3 PORTB bit 3 BANK0:PORTB.RB2 2 PORTB bit 2 BANK0:PORTB.RB1 1 PORTB bit 1 BANK0:PORTB.RB0 0 PORTB bit 0 ; BANK1 (0x0020:0x0040) BANK1:INDF 0x0020 INDF (not a physical register) BANK1:TMR0 0x0021 Timer0 Module Register BANK1:PCL 0x0022 Low order 8 bits of PC BANK1:STATUS 0x0023 STATUS REGISTER BANK1:STATUS.PA1 6 Program page preselect bit 1 BANK1:STATUS.PA0 5 Program page preselect bit 0 BANK1:STATUS.TO 4 Time-out bit BANK1:STATUS.PD 3 Power-down bit BANK1:STATUS.Z 2 Zero bit BANK1:STATUS.DC 1 Digit carry/borrow bit BANK1:STATUS.C 0 Carry/borrow bit BANK1:FSR 0x0024 Indirect data memory address pointer BANK1:PORTA 0x0025 PORTA REGISTER BANK1:PORTA.RA3 3 PORTA bit 3 BANK1:PORTA.RA2 2 PORTA bit 2 BANK1:PORTA.RA1 1 PORTA bit 1 BANK1:PORTA.RA0 0 PORTA bit 0 BANK1:PORTB 0x0026 PORTB REGISTER BANK1:PORTB.RB7 7 PORTB bit 7 BANK1:PORTB.RB6 6 PORTB bit 6 BANK1:PORTB.RB5 5 PORTB bit 5 BANK1:PORTB.RB4 4 PORTB bit 4 BANK1:PORTB.RB3 3 PORTB bit 3 BANK1:PORTB.RB2 2 PORTB bit 2 BANK1:PORTB.RB1 1 PORTB bit 1 BANK1:PORTB.RB0 0 PORTB bit 0 ; BANK2 (0x0040:0x0060) BANK2:INDF 0x0040 INDF (not a physical register) BANK2:TMR0 0x0041 Timer0 Module Register BANK2:PCL 0x0042 Low order 8 bits of PC BANK2:STATUS 0x0043 STATUS REGISTER BANK2:STATUS.PA1 6 Program page preselect bit 1 BANK2:STATUS.PA0 5 Program page preselect bit 0 BANK2:STATUS.TO 4 Time-out bit BANK2:STATUS.PD 3 Power-down bit BANK2:STATUS.Z 2 Zero bit BANK2:STATUS.DC 1 Digit carry/borrow bit BANK2:STATUS.C 0 Carry/borrow bit BANK2:FSR 0x0044 Indirect data memory address pointer BANK2:PORTA 0x0045 PORTA REGISTER BANK2:PORTA.RA3 3 PORTA bit 3 BANK2:PORTA.RA2 2 PORTA bit 2 BANK2:PORTA.RA1 1 PORTA bit 1 BANK2:PORTA.RA0 0 PORTA bit 0 BANK2:PORTB 0x0046 PORTB REGISTER BANK2:PORTB.RB7 7 PORTB bit 7 BANK2:PORTB.RB6 6 PORTB bit 6 BANK2:PORTB.RB5 5 PORTB bit 5 BANK2:PORTB.RB4 4 PORTB bit 4 BANK2:PORTB.RB3 3 PORTB bit 3 BANK2:PORTB.RB2 2 PORTB bit 2 BANK2:PORTB.RB1 1 PORTB bit 1 BANK2:PORTB.RB0 0 PORTB bit 0 ; BANK3 (0x0060:0x0080) BANK3:INDF 0x0060 INDF (not a physical register) BANK3:TMR0 0x0061 Timer0 Module Register BANK3:PCL 0x0062 Low order 8 bits of PC BANK3:STATUS 0x0063 STATUS REGISTER BANK3:STATUS.PA1 6 Program page preselect bit 1 BANK3:STATUS.PA0 5 Program page preselect bit 0 BANK3:STATUS.TO 4 Time-out bit BANK3:STATUS.PD 3 Power-down bit BANK3:STATUS.Z 2 Zero bit BANK3:STATUS.DC 1 Digit carry/borrow bit BANK3:STATUS.C 0 Carry/borrow bit BANK3:FSR 0x0064 Indirect data memory address pointer BANK3:PORTA 0x0065 PORTA REGISTER BANK3:PORTA.RA3 3 PORTA bit 3 BANK3:PORTA.RA2 2 PORTA bit 2 BANK3:PORTA.RA1 1 PORTA bit 1 BANK3:PORTA.RA0 0 PORTA bit 0 BANK3:PORTB 0x0066 PORTB REGISTER BANK3:PORTB.RB7 7 PORTB bit 7 BANK3:PORTB.RB6 6 PORTB bit 6 BANK3:PORTB.RB5 5 PORTB bit 5 BANK3:PORTB.RB4 4 PORTB bit 4 BANK3:PORTB.RB3 3 PORTB bit 3 BANK3:PORTB.RB2 2 PORTB bit 2 BANK3:PORTB.RB1 1 PORTB bit 1 BANK3:PORTB.RB0 0 PORTB bit 0 .16CR54 ; http://www.microchip.com/download/lit/pline/picmicro/families/16c5x/30453d.pdf ; PIC16C5X.pdf ; MEMORY MAP area DATA FSR_ 0x0000:0x0007 area DATA Gen_Purp 0x0007:0x0020 General Purpose Register area DATA MEM_Program0 0x0020:0x01FF On-chip Program Memory (Page 0) ; Interrupt and reset vector assignments interrupt RESET 0x01FF RESET ; INPUT/OUTPUT PORTS INDF 0x0000 INDF (not a physical register) TMR0 0x0001 Timer0 Module Register PCL 0x0002 Low order 8 bits of PC STATUS 0x0003 STATUS REGISTER STATUS.PA1 6 Program page preselect bit 1 STATUS.PA0 5 Program page preselect bit 0 STATUS.TO 4 Time-out bit STATUS.PD 3 Power-down bit STATUS.Z 2 Zero bit STATUS.DC 1 Digit carry/borrow bit STATUS.C 0 Carry/borrow bit FSR 0x0004 Indirect data memory address pointer PORTA 0x0005 PORTA REGISTER PORTA.RA3 3 PORTA bit 3 PORTA.RA2 2 PORTA bit 2 PORTA.RA1 1 PORTA bit 1 PORTA.RA0 0 PORTA bit 0 PORTB 0x0006 PORTB REGISTER PORTB.RB7 7 PORTB bit 7 PORTB.RB6 6 PORTB bit 6 PORTB.RB5 5 PORTB bit 5 PORTB.RB4 4 PORTB bit 4 PORTB.RB3 3 PORTB bit 3 PORTB.RB2 2 PORTB bit 2 PORTB.RB1 1 PORTB bit 1 PORTB.RB0 0 PORTB bit 0 .16CR56 ; http://www.microchip.com/download/lit/pline/picmicro/families/16c5x/30453d.pdf ; PIC16C5X.pdf ; MEMORY MAP area DATA FSR_ 0x0000:0x0007 area DATA Gen_Purp 0x0007:0x0020 General Purpose Register area DATA MEM_Program0 0x0020:0x0200 On-chip Program Memory (Page 0) area DATA MEM_Program1 0x0200:0x03FF On-chip Program Memory (Page 1) ; Interrupt and reset vector assignments interrupt RESET 0x03FF RESET ; INPUT/OUTPUT PORTS INDF 0x0000 INDF (not a physical register) TMR0 0x0001 Timer0 Module Register PCL 0x0002 Low order 8 bits of PC STATUS 0x0003 STATUS REGISTER STATUS.PA1 6 Program page preselect bit 1 STATUS.PA0 5 Program page preselect bit 0 STATUS.TO 4 Time-out bit STATUS.PD 3 Power-down bit STATUS.Z 2 Zero bit STATUS.DC 1 Digit carry/borrow bit STATUS.C 0 Carry/borrow bit FSR 0x0004 Indirect data memory address pointer PORTA 0x0005 PORTA REGISTER PORTA.RA3 3 PORTA bit 3 PORTA.RA2 2 PORTA bit 2 PORTA.RA1 1 PORTA bit 1 PORTA.RA0 0 PORTA bit 0 PORTB 0x0006 PORTB REGISTER PORTB.RB7 7 PORTB bit 7 PORTB.RB6 6 PORTB bit 6 PORTB.RB5 5 PORTB bit 5 PORTB.RB4 4 PORTB bit 4 PORTB.RB3 3 PORTB bit 3 PORTB.RB2 2 PORTB bit 2 PORTB.RB1 1 PORTB bit 1 PORTB.RB0 0 PORTB bit 0 .16CR57 ; http://www.microchip.com/download/lit/pline/picmicro/families/16c5x/30453d.pdf ; PIC16C5X.pdf ; MEMORY MAP ; BANK_0 area DATA FSR_ 0x0000:0x0008 area DATA Gen_Purp 0x0008:0x0020 General Purpose Register area DATA MEM_Program0 0x0020:0x0200 On-chip Program Memory (Page 0) area DATA MEM_Program1 0x0200:0x0400 On-chip Program Memory (Page 1) area DATA MEM_Program2 0x0400:0x0600 On-chip Program Memory (Page 2) area DATA MEM_Program3 0x0600:0x07FF On-chip Program Memory (Page 3) ; BANK_1 ; area DATA FSR_ 0x0020:0x0028 ; area DATA Gen_Purp 0x0028:0x0040 General Purpose Register ; area DATA MEM_Program0 0x0040:0x0200 On-chip Program Memory (Page 0) ; area DATA MEM_Program1 0x0200:0x0400 On-chip Program Memory (Page 1) ; area DATA MEM_Program2 0x0400:0x0600 On-chip Program Memory (Page 2) ; area DATA MEM_Program3 0x0600:0x07FF On-chip Program Memory (Page 3) ; BANK_2 ; area DATA FSR_ 0x0040:0x0048 ; area DATA Gen_Purp 0x0048:0x0060 General Purpose Register ; area DATA MEM_Program0 0x0060:0x0200 On-chip Program Memory (Page 0) ; area DATA MEM_Program1 0x0200:0x0400 On-chip Program Memory (Page 1) ; area DATA MEM_Program2 0x0400:0x0600 On-chip Program Memory (Page 2) ; area DATA MEM_Program3 0x0600:0x07FF On-chip Program Memory (Page 3) ; BANK_3 ; area DATA FSR_ 0x0060:0x0068 ; area DATA Gen_Purp 0x0068:0x0080 General Purpose Register ; area DATA MEM_Program0 0x0080:0x0200 On-chip Program Memory (Page 0) ; area DATA MEM_Program1 0x0200:0x0400 On-chip Program Memory (Page 1) ; area DATA MEM_Program2 0x0400:0x0600 On-chip Program Memory (Page 2) ; area DATA MEM_Program3 0x0600:0x07FF On-chip Program Memory (Page 3) ; Interrupt and reset vector assignments interrupt RESET 0x07FF RESET ; INPUT/OUTPUT PORTS ; BANK0 (0x0000:0x0020) BANK0:INDF 0x0000 INDF (not a physical register) BANK0:TMR0 0x0001 Timer0 Module Register BANK0:PCL 0x0002 Low order 8 bits of PC BANK0:STATUS 0x0003 STATUS REGISTER BANK0:STATUS.PA1 6 Program page preselect bit 1 BANK0:STATUS.PA0 5 Program page preselect bit 0 BANK0:STATUS.TO 4 Time-out bit BANK0:STATUS.PD 3 Power-down bit BANK0:STATUS.Z 2 Zero bit BANK0:STATUS.DC 1 Digit carry/borrow bit BANK0:STATUS.C 0 Carry/borrow bit BANK0:FSR 0x0004 Indirect data memory address pointer BANK0:PORTA 0x0005 PORTA REGISTER BANK0:PORTA.RA3 3 PORTA bit 3 BANK0:PORTA.RA2 2 PORTA bit 2 BANK0:PORTA.RA1 1 PORTA bit 1 BANK0:PORTA.RA0 0 PORTA bit 0 BANK0:PORTB 0x0006 PORTB REGISTER BANK0:PORTB.RB7 7 PORTB bit 7 BANK0:PORTB.RB6 6 PORTB bit 6 BANK0:PORTB.RB5 5 PORTB bit 5 BANK0:PORTB.RB4 4 PORTB bit 4 BANK0:PORTB.RB3 3 PORTB bit 3 BANK0:PORTB.RB2 2 PORTB bit 2 BANK0:PORTB.RB1 1 PORTB bit 1 BANK0:PORTB.RB0 0 PORTB bit 0 BANK0:PORTC 0x0007 PORTC REGISTER BANK0:PORTC.RC7 7 PORTC bit 7 BANK0:PORTC.RC6 6 PORTC bit 6 BANK0:PORTC.RC5 5 PORTC bit 5 BANK0:PORTC.RC4 4 PORTC bit 4 BANK0:PORTC.RC3 3 PORTC bit 3 BANK0:PORTC.RC2 2 PORTC bit 2 BANK0:PORTC.RC1 1 PORTC bit 1 BANK0:PORTC.RC0 0 PORTC bit 0 ; BANK1 (0x0020:0x0040) BANK1:INDF 0x0020 INDF (not a physical register) BANK1:TMR0 0x0021 Timer0 Module Register BANK1:PCL 0x0022 Low order 8 bits of PC BANK1:STATUS 0x0023 STATUS REGISTER BANK1:STATUS.PA1 6 Program page preselect bit 1 BANK1:STATUS.PA0 5 Program page preselect bit 0 BANK1:STATUS.TO 4 Time-out bit BANK1:STATUS.PD 3 Power-down bit BANK1:STATUS.Z 2 Zero bit BANK1:STATUS.DC 1 Digit carry/borrow bit BANK1:STATUS.C 0 Carry/borrow bit BANK1:FSR 0x0024 Indirect data memory address pointer BANK1:PORTA 0x0025 PORTA REGISTER BANK1:PORTA.RA3 3 PORTA bit 3 BANK1:PORTA.RA2 2 PORTA bit 2 BANK1:PORTA.RA1 1 PORTA bit 1 BANK1:PORTA.RA0 0 PORTA bit 0 BANK1:PORTB 0x0026 PORTB REGISTER BANK1:PORTB.RB7 7 PORTB bit 7 BANK1:PORTB.RB6 6 PORTB bit 6 BANK1:PORTB.RB5 5 PORTB bit 5 BANK1:PORTB.RB4 4 PORTB bit 4 BANK1:PORTB.RB3 3 PORTB bit 3 BANK1:PORTB.RB2 2 PORTB bit 2 BANK1:PORTB.RB1 1 PORTB bit 1 BANK1:PORTB.RB0 0 PORTB bit 0 BANK1:PORTC 0x0027 PORTC REGISTER BANK1:PORTC.RC7 7 PORTC bit 7 BANK1:PORTC.RC6 6 PORTC bit 6 BANK1:PORTC.RC5 5 PORTC bit 5 BANK1:PORTC.RC4 4 PORTC bit 4 BANK1:PORTC.RC3 3 PORTC bit 3 BANK1:PORTC.RC2 2 PORTC bit 2 BANK1:PORTC.RC1 1 PORTC bit 1 BANK1:PORTC.RC0 0 PORTC bit 0 ; BANK2 (0x0040:0x0060) BANK2:INDF 0x0040 INDF (not a physical register) BANK2:TMR0 0x0041 Timer0 Module Register BANK2:PCL 0x0042 Low order 8 bits of PC BANK2:STATUS 0x0043 STATUS REGISTER BANK2:STATUS.PA1 6 Program page preselect bit 1 BANK2:STATUS.PA0 5 Program page preselect bit 0 BANK2:STATUS.TO 4 Time-out bit BANK2:STATUS.PD 3 Power-down bit BANK2:STATUS.Z 2 Zero bit BANK2:STATUS.DC 1 Digit carry/borrow bit BANK2:STATUS.C 0 Carry/borrow bit BANK2:FSR 0x0044 Indirect data memory address pointer BANK2:PORTA 0x0045 PORTA REGISTER BANK2:PORTA.RA3 3 PORTA bit 3 BANK2:PORTA.RA2 2 PORTA bit 2 BANK2:PORTA.RA1 1 PORTA bit 1 BANK2:PORTA.RA0 0 PORTA bit 0 BANK2:PORTB 0x0046 PORTB REGISTER BANK2:PORTB.RB7 7 PORTB bit 7 BANK2:PORTB.RB6 6 PORTB bit 6 BANK2:PORTB.RB5 5 PORTB bit 5 BANK2:PORTB.RB4 4 PORTB bit 4 BANK2:PORTB.RB3 3 PORTB bit 3 BANK2:PORTB.RB2 2 PORTB bit 2 BANK2:PORTB.RB1 1 PORTB bit 1 BANK2:PORTB.RB0 0 PORTB bit 0 BANK2:PORTC 0x0047 PORTC REGISTER BANK2:PORTC.RC7 7 PORTC bit 7 BANK2:PORTC.RC6 6 PORTC bit 6 BANK2:PORTC.RC5 5 PORTC bit 5 BANK2:PORTC.RC4 4 PORTC bit 4 BANK2:PORTC.RC3 3 PORTC bit 3 BANK2:PORTC.RC2 2 PORTC bit 2 BANK2:PORTC.RC1 1 PORTC bit 1 BANK2:PORTC.RC0 0 PORTC bit 0 ; BANK3 (0x0060:0x0080) BANK3:INDF 0x0060 INDF (not a physical register) BANK3:TMR0 0x0061 Timer0 Module Register BANK3:PCL 0x0062 Low order 8 bits of PC BANK3:STATUS 0x0063 STATUS REGISTER BANK3:STATUS.PA1 6 Program page preselect bit 1 BANK3:STATUS.PA0 5 Program page preselect bit 0 BANK3:STATUS.TO 4 Time-out bit BANK3:STATUS.PD 3 Power-down bit BANK3:STATUS.Z 2 Zero bit BANK3:STATUS.DC 1 Digit carry/borrow bit BANK3:STATUS.C 0 Carry/borrow bit BANK3:FSR 0x0064 Indirect data memory address pointer BANK3:PORTA 0x0065 PORTA REGISTER BANK3:PORTA.RA3 3 PORTA bit 3 BANK3:PORTA.RA2 2 PORTA bit 2 BANK3:PORTA.RA1 1 PORTA bit 1 BANK3:PORTA.RA0 0 PORTA bit 0 BANK3:PORTB 0x0066 PORTB REGISTER BANK3:PORTB.RB7 7 PORTB bit 7 BANK3:PORTB.RB6 6 PORTB bit 6 BANK3:PORTB.RB5 5 PORTB bit 5 BANK3:PORTB.RB4 4 PORTB bit 4 BANK3:PORTB.RB3 3 PORTB bit 3 BANK3:PORTB.RB2 2 PORTB bit 2 BANK3:PORTB.RB1 1 PORTB bit 1 BANK3:PORTB.RB0 0 PORTB bit 0 BANK3:PORTC 0x0067 PORTC REGISTER BANK3:PORTC.RC7 7 PORTC bit 7 BANK3:PORTC.RC6 6 PORTC bit 6 BANK3:PORTC.RC5 5 PORTC bit 5 BANK3:PORTC.RC4 4 PORTC bit 4 BANK3:PORTC.RC3 3 PORTC bit 3 BANK3:PORTC.RC2 2 PORTC bit 2 BANK3:PORTC.RC1 1 PORTC bit 1 BANK3:PORTC.RC0 0 PORTC bit 0 .16CR58 ; http://www.microchip.com/download/lit/pline/picmicro/families/16c5x/30453d.pdf ; PIC16C5X.pdf ; MEMORY MAP ; BANK_0 area DATA FSR_ 0x0000:0x0007 area DATA Gen_Purp 0x0007:0x0020 General Purpose Register area DATA MEM_Program0 0x0020:0x0200 On-chip Program Memory (Page 0) area DATA MEM_Program1 0x0200:0x0400 On-chip Program Memory (Page 1) area DATA MEM_Program2 0x0400:0x0600 On-chip Program Memory (Page 2) area DATA MEM_Program3 0x0600:0x07FF On-chip Program Memory (Page 3) ; BANK_1 ; area DATA FSR_ 0x0020:0x0027 ; area DATA Gen_Purp 0x0027:0x0040 General Purpose Register ; area DATA MEM_Program0 0x0040:0x0200 On-chip Program Memory (Page 0) ; area DATA MEM_Program1 0x0200:0x0400 On-chip Program Memory (Page 1) ; area DATA MEM_Program2 0x0400:0x0600 On-chip Program Memory (Page 2) ; area DATA MEM_Program3 0x0600:0x07FF On-chip Program Memory (Page 3) ; BANK_2 ; area DATA FSR_ 0x0040:0x0047 ; area DATA Gen_Purp 0x0047:0x0060 General Purpose Register ; area DATA MEM_Program0 0x0060:0x0200 On-chip Program Memory (Page 0) ; area DATA MEM_Program1 0x0200:0x0400 On-chip Program Memory (Page 1) ; area DATA MEM_Program2 0x0400:0x0600 On-chip Program Memory (Page 2) ; area DATA MEM_Program3 0x0600:0x07FF On-chip Program Memory (Page 3) ; BANK_3 ; area DATA FSR_ 0x0060:0x0067 ; area DATA Gen_Purp 0x0067:0x0080 General Purpose Register ; area DATA MEM_Program0 0x0080:0x0200 On-chip Program Memory (Page 0) ; area DATA MEM_Program1 0x0200:0x0400 On-chip Program Memory (Page 1) ; area DATA MEM_Program2 0x0400:0x0600 On-chip Program Memory (Page 2) ; area DATA MEM_Program3 0x0600:0x07FF On-chip Program Memory (Page 3) ; Interrupt and reset vector assignments interrupt RESET 0x07FF RESET ; INPUT/OUTPUT PORTS ; BANK0 (0x0000:0x0020) BANK0:INDF 0x0000 INDF (not a physical register) BANK0:TMR0 0x0001 Timer0 Module Register BANK0:PCL 0x0002 Low order 8 bits of PC BANK0:STATUS 0x0003 STATUS REGISTER BANK0:STATUS.PA1 6 Program page preselect bit 1 BANK0:STATUS.PA0 5 Program page preselect bit 0 BANK0:STATUS.TO 4 Time-out bit BANK0:STATUS.PD 3 Power-down bit BANK0:STATUS.Z 2 Zero bit BANK0:STATUS.DC 1 Digit carry/borrow bit BANK0:STATUS.C 0 Carry/borrow bit BANK0:FSR 0x0004 Indirect data memory address pointer BANK0:PORTA 0x0005 PORTA REGISTER BANK0:PORTA.RA3 3 PORTA bit 3 BANK0:PORTA.RA2 2 PORTA bit 2 BANK0:PORTA.RA1 1 PORTA bit 1 BANK0:PORTA.RA0 0 PORTA bit 0 BANK0:PORTB 0x0006 PORTB REGISTER BANK0:PORTB.RB7 7 PORTB bit 7 BANK0:PORTB.RB6 6 PORTB bit 6 BANK0:PORTB.RB5 5 PORTB bit 5 BANK0:PORTB.RB4 4 PORTB bit 4 BANK0:PORTB.RB3 3 PORTB bit 3 BANK0:PORTB.RB2 2 PORTB bit 2 BANK0:PORTB.RB1 1 PORTB bit 1 BANK0:PORTB.RB0 0 PORTB bit 0 ; BANK1 (0x0020:0x0040) BANK1:INDF 0x0020 INDF (not a physical register) BANK1:TMR0 0x0021 Timer0 Module Register BANK1:PCL 0x0022 Low order 8 bits of PC BANK1:STATUS 0x0023 STATUS REGISTER BANK1:STATUS.PA1 6 Program page preselect bit 1 BANK1:STATUS.PA0 5 Program page preselect bit 0 BANK1:STATUS.TO 4 Time-out bit BANK1:STATUS.PD 3 Power-down bit BANK1:STATUS.Z 2 Zero bit BANK1:STATUS.DC 1 Digit carry/borrow bit BANK1:STATUS.C 0 Carry/borrow bit BANK1:FSR 0x0024 Indirect data memory address pointer BANK1:PORTA 0x0025 PORTA REGISTER BANK1:PORTA.RA3 3 PORTA bit 3 BANK1:PORTA.RA2 2 PORTA bit 2 BANK1:PORTA.RA1 1 PORTA bit 1 BANK1:PORTA.RA0 0 PORTA bit 0 BANK1:PORTB 0x0026 PORTB REGISTER BANK1:PORTB.RB7 7 PORTB bit 7 BANK1:PORTB.RB6 6 PORTB bit 6 BANK1:PORTB.RB5 5 PORTB bit 5 BANK1:PORTB.RB4 4 PORTB bit 4 BANK1:PORTB.RB3 3 PORTB bit 3 BANK1:PORTB.RB2 2 PORTB bit 2 BANK1:PORTB.RB1 1 PORTB bit 1 BANK1:PORTB.RB0 0 PORTB bit 0 ; BANK2 (0x0040:0x0060) BANK2:INDF 0x0040 INDF (not a physical register) BANK2:TMR0 0x0041 Timer0 Module Register BANK2:PCL 0x0042 Low order 8 bits of PC BANK2:STATUS 0x0043 STATUS REGISTER BANK2:STATUS.PA1 6 Program page preselect bit 1 BANK2:STATUS.PA0 5 Program page preselect bit 0 BANK2:STATUS.TO 4 Time-out bit BANK2:STATUS.PD 3 Power-down bit BANK2:STATUS.Z 2 Zero bit BANK2:STATUS.DC 1 Digit carry/borrow bit BANK2:STATUS.C 0 Carry/borrow bit BANK2:FSR 0x0044 Indirect data memory address pointer BANK2:PORTA 0x0045 PORTA REGISTER BANK2:PORTA.RA3 3 PORTA bit 3 BANK2:PORTA.RA2 2 PORTA bit 2 BANK2:PORTA.RA1 1 PORTA bit 1 BANK2:PORTA.RA0 0 PORTA bit 0 BANK2:PORTB 0x0046 PORTB REGISTER BANK2:PORTB.RB7 7 PORTB bit 7 BANK2:PORTB.RB6 6 PORTB bit 6 BANK2:PORTB.RB5 5 PORTB bit 5 BANK2:PORTB.RB4 4 PORTB bit 4 BANK2:PORTB.RB3 3 PORTB bit 3 BANK2:PORTB.RB2 2 PORTB bit 2 BANK2:PORTB.RB1 1 PORTB bit 1 BANK2:PORTB.RB0 0 PORTB bit 0 ; BANK3 (0x0060:0x0080) BANK3:INDF 0x0060 INDF (not a physical register) BANK3:TMR0 0x0061 Timer0 Module Register BANK3:PCL 0x0062 Low order 8 bits of PC BANK3:STATUS 0x0063 STATUS REGISTER BANK3:STATUS.PA1 6 Program page preselect bit 1 BANK3:STATUS.PA0 5 Program page preselect bit 0 BANK3:STATUS.TO 4 Time-out bit BANK3:STATUS.PD 3 Power-down bit BANK3:STATUS.Z 2 Zero bit BANK3:STATUS.DC 1 Digit carry/borrow bit BANK3:STATUS.C 0 Carry/borrow bit BANK3:FSR 0x0064 Indirect data memory address pointer BANK3:PORTA 0x0065 PORTA REGISTER BANK3:PORTA.RA3 3 PORTA bit 3 BANK3:PORTA.RA2 2 PORTA bit 2 BANK3:PORTA.RA1 1 PORTA bit 1 BANK3:PORTA.RA0 0 PORTA bit 0 BANK3:PORTB 0x0066 PORTB REGISTER BANK3:PORTB.RB7 7 PORTB bit 7 BANK3:PORTB.RB6 6 PORTB bit 6 BANK3:PORTB.RB5 5 PORTB bit 5 BANK3:PORTB.RB4 4 PORTB bit 4 BANK3:PORTB.RB3 3 PORTB bit 3 BANK3:PORTB.RB2 2 PORTB bit 2 BANK3:PORTB.RB1 1 PORTB bit 1 BANK3:PORTB.RB0 0 PORTB bit 0 .16C62B ; http://www.microchip.com/download/lit/pline/picmicro/families/16c6x/35008b.pdf ; PIC16C62B_72B.pdf ; MEMORY MAP ; BANK_0 area DATA FSR_ 0x0000:0x0020 area DATA Gen_Purp 0x0020:0x0080 General Purpose Register area DATA MEM_Program 0x0080:0x0800 On-chip Program Memory ; BANK_1 ; area DATA FSR_ 0x0080:0x00A0 ; area DATA Gen_Purp 0x00A0:0x00C0 General Purpose Register ; area BSS RESERVED 0x00C0:0x0100 ; area DATA MEM_Program 0x0100:0x0800 On-chip Program Memory ; Interrupt and reset vector assignments interrupt RESET 0x0000 RESET ; INPUT/OUTPUT PORTS ; BANK0 (0x0000:0x0080) BANK0:INDF 0x0000 INDF (not a physical register) BANK0:TMR0 0x0001 Timer0 module's register BANK0:PCL 0x0002 Program Counter's (PC) Least Significant Byte BANK0:STATUS 0x0003 STATUS REGISTER BANK0:STATUS.IRP 7 Register Bank Select bit BANK0:STATUS.RP1 6 Register Bank Select bit 1 BANK0:STATUS.RP0 5 Register Bank Select bit 0 BANK0:STATUS.TO 4 Time-out bit BANK0:STATUS.PD 3 Power-down bit BANK0:STATUS.Z 2 Zero bit BANK0:STATUS.DC 1 Digit carry/borrow bit BANK0:STATUS.C 0 Carry/borrow bit BANK0:FSR 0x0004 Indirect data memory address pointer BANK0:PORTA 0x0005 PORTA REGISTER BANK0:PORTA.RA5 5 PORTA bit 5 BANK0:PORTA.RA4 4 PORTA bit 4 BANK0:PORTA.RA3 3 PORTA bit 3 BANK0:PORTA.RA2 2 PORTA bit 2 BANK0:PORTA.RA1 1 PORTA bit 1 BANK0:PORTA.RA0 0 PORTA bit 0 BANK0:PORTB 0x0006 PORTB REGISTER BANK0:PORTB.RB7 7 PORTB bit 7 BANK0:PORTB.RB6 6 PORTB bit 6 BANK0:PORTB.RB5 5 PORTB bit 5 BANK0:PORTB.RB4 4 PORTB bit 4 BANK0:PORTB.RB3 3 PORTB bit 3 BANK0:PORTB.RB2 2 PORTB bit 2 BANK0:PORTB.RB1 1 PORTB bit 1 BANK0:PORTB.RB0 0 PORTB bit 0 BANK0:PORTC 0x0007 PORTC REGISTER BANK0:PORTC.RC7 7 PORTC bit 7 BANK0:PORTC.RC6 6 PORTC bit 6 BANK0:PORTC.RC5 5 PORTC bit 5 BANK0:PORTC.RC4 4 PORTC bit 4 BANK0:PORTC.RC3 3 PORTC bit 3 BANK0:PORTC.RC2 2 PORTC bit 2 BANK0:PORTC.RC1 1 PORTC bit 1 BANK0:PORTC.RC0 0 PORTC bit 0 BANK0:RESERVED0008 0x0008 RESERVED BANK0:RESERVED0009 0x0009 RESERVED BANK0:PCLATH 0x000A Write Buffer for the upper 5 bits of the Program Counter BANK0:INTCON 0x000B INTCON REGISTER BANK0:INTCON.GIE 7 Global Interrupt Enable bit BANK0:INTCON.PEIE 6 Peripheral Interrupt Enable bit BANK0:INTCON.T0IE 5 TMR0 Overflow Interrupt Enable bit BANK0:INTCON.INTE 4 RB0/INT External Interrupt Enable bit BANK0:INTCON.RBIE 3 RB Port Change Interrupt Enable bit BANK0:INTCON.T0IF 2 TMR0 Overflow Interrupt Flag bit BANK0:INTCON.INTF 1 RB0/INT External Interrupt Flag bit BANK0:INTCON.RBIF 0 RB Port Change Interrupt Flag bit BANK0:PIR1 0x000C PIR1 REGISTER BANK0:PIR1.SSPIF 3 Synchronous Serial Port Interrupt Flag bit BANK0:PIR1.CCP1IF 2 CCP1 Interrupt Flag bit BANK0:PIR1.TMR2IF 1 TMR2 to PR2 Match Interrupt Flag bit BANK0:PIR1.TMR1IF 0 TMR1 Overflow Interrupt Flag bit BANK0:RESERVED000D 0x000D RESERVED BANK0:TMR1L 0x000E Holding register for the Least Significant Byte of the 16-bit TMR1 register BANK0:TMR1H 0x000F Holding register for the Most Significant Byte of the 16-bit TMR1 register BANK0:T1CON 0x0010 TIMER1 CONTROL REGISTER BANK0:T1CON.T1CKPS1 5 Timer1 Input Clock Prescale Select bit 1 BANK0:T1CON.T1CKPS0 4 Timer1 Input Clock Prescale Select bit 0 BANK0:T1CON.T1OSCEN 3 Timer1 Oscillator Enable Control bit BANK0:T1CON.T1SYNC 2 Timer1 External Clock Input Synchronization Control bit BANK0:T1CON.TMR1CS 1 Timer1 Clock Source Select bit BANK0:T1CON.TMR1ON 0 Timer1 On bit BANK0:TMR2 0x0011 Timer2 module's register BANK0:T2CON 0x0012 TIMER2 CONTROL REGISTER BANK0:T2CON.TOUTPS3 6 Timer2 Output Postscale Select bit 3 BANK0:T2CON.TOUTPS2 5 Timer2 Output Postscale Select bit 2 BANK0:T2CON.TOUTPS1 4 Timer2 Output Postscale Select bit 1 BANK0:T2CON.TOUTPS0 3 Timer2 Output Postscale Select bit 0 BANK0:T2CON.TMR2ON 2 Timer2 On bit BANK0:T2CON.T2CKPS1 1 Timer2 Clock Prescale Select bit 1 BANK0:T2CON.T2CKPS0 0 Timer2 Clock Prescale Select bit 0 BANK0:SSPBUF 0x0013 Synchronous Serial Port Receive Buffer/Transmit Register BANK0:SSPCON 0x0014 SYNC SERIAL PORT CONTROL REGISTER BANK0:SSPCON.WCOL 7 Write Collision Detect bit BANK0:SSPCON.SSPOV 6 Receive Overflow Indicator bit BANK0:SSPCON.SSPEN 5 Synchronous Serial Port Enable bit BANK0:SSPCON.CKP 4 Clock Polarity Select bit BANK0:SSPCON.SSPM3 3 Synchronous Serial Port Mode Select bit 3 BANK0:SSPCON.SSPM2 2 Synchronous Serial Port Mode Select bit 2 BANK0:SSPCON.SSPM1 1 Synchronous Serial Port Mode Select bit 1 BANK0:SSPCON.SSPM0 0 Synchronous Serial Port Mode Select bit 0 BANK0:CCPR1L 0x0015 Capture/Compare/PWM Register1 (LSB) BANK0:CCPR1H 0x0016 Capture/Compare/PWM Register1 (MSB) BANK0:CCP1CON 0x0017 CCP1CON REGISTER BANK0:CCP1CON.CCP1X 5 PWM Least Significant bit BANK0:CCP1CON.CCP1Y 4 PWM Least Significant bit BANK0:CCP1CON.CCP1M3 3 CCP1 Mode Select bit 3 BANK0:CCP1CON.CCP1M2 2 CCP1 Mode Select bit 2 BANK0:CCP1CON.CCP1M1 1 CCP1 Mode Select bit 1 BANK0:CCP1CON.CCP1M0 0 CCP1 Mode Select bit 0 BANK0:RESERVED0018 0x0018 RESERVED BANK0:RESERVED0019 0x0019 RESERVED BANK0:RESERVED001A 0x001A RESERVED BANK0:RESERVED001B 0x001B RESERVED BANK0:RESERVED001C 0x001C RESERVED BANK0:RESERVED001D 0x001D RESERVED BANK0:RESERVED001E 0x001E RESERVED BANK0:RESERVED001F 0x001F RESERVED ; BANK1 (0x0080:0x0100) BANK1:INDF 0x0080 INDF (not a physical register) BANK1:OPTION 0x0081 OPTION REGISTER BANK1:OPTION.RBPU 7 PORTB Pull-up Enable bit BANK1:OPTION.INTEDG 6 Interrupt Edge Select bit BANK1:OPTION.T0CS 5 TMR0 Clock Source Select bit BANK1:OPTION.T0SE 4 TMR0 Source Edge Select bit BANK1:OPTION.PSA 3 Prescaler Assignment bit BANK1:OPTION.PS2 2 Prescaler Rate Select bit 2 BANK1:OPTION.PS1 1 Prescaler Rate Select bit 1 BANK1:OPTION.PS0 0 Prescaler Rate Select bit 0 BANK1:PCL 0x0082 Program Counter's (PC) Least Significant Byte BANK1:STATUS 0x0083 STATUS REGISTER BANK1:STATUS.IRP 7 Register Bank Select bit BANK1:STATUS.RP1 6 Register Bank Select bit 1 BANK1:STATUS.RP0 5 Register Bank Select bit 0 BANK1:STATUS.TO 4 Time-out bit BANK1:STATUS.PD 3 Power-down bit BANK1:STATUS.Z 2 Zero bit BANK1:STATUS.DC 1 Digit carry/borrow bit BANK1:STATUS.C 0 Carry/borrow bit BANK1:FSR 0x0084 Indirect data memory address pointer BANK1:TRISA 0x0085 PORTA Data Direction Register BANK1:TRISA.TRISA5 5 PORTA Data Direction Register bit 5 BANK1:TRISA.TRISA4 4 PORTA Data Direction Register bit 4 BANK1:TRISA.TRISA3 3 PORTA Data Direction Register bit 3 BANK1:TRISA.TRISA2 2 PORTA Data Direction Register bit 2 BANK1:TRISA.TRISA1 1 PORTA Data Direction Register bit 1 BANK1:TRISA.TRISA0 0 PORTA Data Direction Register bit 0 BANK1:TRISB 0x0086 PORTB Data Direction Register BANK1:TRISB.TRISB7 7 PORTB Data Direction Register bit 7 BANK1:TRISB.TRISB6 6 PORTB Data Direction Register bit 6 BANK1:TRISB.TRISB5 5 PORTB Data Direction Register bit 5 BANK1:TRISB.TRISB4 4 PORTB Data Direction Register bit 4 BANK1:TRISB.TRISB3 3 PORTB Data Direction Register bit 3 BANK1:TRISB.TRISB2 2 PORTB Data Direction Register bit 2 BANK1:TRISB.TRISB1 1 PORTB Data Direction Register bit 1 BANK1:TRISB.TRISB0 0 PORTB Data Direction Register bit 0 BANK1:TRISC 0x0087 PORTC Data Direction Register BANK1:TRISC.TRISC7 7 PORTC Data Direction Register bit 7 BANK1:TRISC.TRISC6 6 PORTC Data Direction Register bit 6 BANK1:TRISC.TRISC5 5 PORTC Data Direction Register bit 5 BANK1:TRISC.TRISC4 4 PORTC Data Direction Register bit 4 BANK1:TRISC.TRISC3 3 PORTC Data Direction Register bit 3 BANK1:TRISC.TRISC2 2 PORTC Data Direction Register bit 2 BANK1:TRISC.TRISC1 1 PORTC Data Direction Register bit 1 BANK1:TRISC.TRISC0 0 PORTC Data Direction Register bit 0 BANK1:RESERVED0088 0x0088 RESERVED BANK1:RESERVED0089 0x0089 RESERVED BANK1:PCLATH 0x008A Write Buffer for the upper 5 bits of the Program Counter BANK1:INTCON 0x008B INTCON REGISTER BANK1:INTCON.GIE 7 Global Interrupt Enable bit BANK1:INTCON.PEIE 6 Peripheral Interrupt Enable bit BANK1:INTCON.T0IE 5 TMR0 Overflow Interrupt Enable bit BANK1:INTCON.INTE 4 RB0/INT External Interrupt Enable bit BANK1:INTCON.RBIE 3 RB Port Change Interrupt Enable bit BANK1:INTCON.T0IF 2 TMR0 Overflow Interrupt Flag bit BANK1:INTCON.INTF 1 RB0/INT External Interrupt Flag bit BANK1:INTCON.RBIF 0 RB Port Change Interrupt Flag bit BANK1:PIE1 0x008C PIE1 REGISTER BANK1:PIE1.SSPIE 3 Synchronous Serial Port Interrupt Enable bit BANK1:PIE1.CCP1IE 2 CCP1 Interrupt Enable bit BANK1:PIE1.TMR2IE 1 TMR2 to PR2 Match Interrupt Enable bit BANK1:PIE1.TMR1IE 0 TMR1 Overflow Interrupt Enable bit BANK1:RESERVED008D 0x008D RESERVED BANK1:PCON 0x008E PCON REGISTER BANK1:PCON.POR 1 Power-on Reset Status bit BANK1:PCON.BOR 0 Brown-out Reset Status bit BANK1:RESERVED008F 0x008F RESERVED BANK1:RESERVED0090 0x0090 RESERVED BANK1:RESERVED0091 0x0091 RESERVED BANK1:PR2 0x0092 Timer2 Period Register BANK1:SSPADD 0x0093 Synchronous Serial Port (I 2 C mode) Address Register BANK1:SSPSTAT 0x0094 SYNC SERIAL PORT STATUS REGISTER BANK1:SSPSTAT.SMP 7 SPI data input sample phase BANK1:SSPSTAT.CKE 6 SPI Clock Edge Select BANK1:SSPSTAT.D_A 5 Data/Address bit (I2C mode only) BANK1:SSPSTAT.P 4 Stop bit (I2C mode only) BANK1:SSPSTAT.S 3 Start bit (I2C mode only) BANK1:SSPSTAT.R_W 2 Read/Write bit information (I2C mode only) BANK1:SSPSTAT.UA 1 Update Address (I2C mode only) BANK1:SSPSTAT.BF 0 Buffer Full Status bit BANK1:RESERVED0095 0x0095 RESERVED BANK1:RESERVED0096 0x0096 RESERVED BANK1:RESERVED0097 0x0097 RESERVED BANK1:RESERVED0098 0x0098 RESERVED BANK1:RESERVED0099 0x0099 RESERVED BANK1:RESERVED009A 0x009A RESERVED BANK1:RESERVED009B 0x009B RESERVED BANK1:RESERVED009C 0x009C RESERVED BANK1:RESERVED009D 0x009D RESERVED BANK1:RESERVED009E 0x009E RESERVED BANK1:RESERVED009F 0x009F RESERVED .16C72A ; http://www.microchip.com/download/lit/pline/picmicro/families/16c6x/35008b.pdf ; PIC16C62B_72B.pdf ; MEMORY MAP ; BANK_0 area DATA FSR_ 0x0000:0x0020 area DATA Gen_Purp 0x0020:0x0080 General Purpose Register area DATA MEM_Program 0x0080:0x0800 On-chip Program Memory ; BANK_1 ; area DATA FSR_ 0x0080:0x00A0 ; area DATA Gen_Purp 0x00A0:0x00C0 General Purpose Register ; area BSS RESERVED 0x00C0:0x0100 ; area DATA MEM_Program 0x0100:0x0800 On-chip Program Memory ; Interrupt and reset vector assignments interrupt RESET 0x0000 RESET ; INPUT/OUTPUT PORTS ; BANK0 (0x0000:0x0080) BANK0:INDF 0x0000 INDF (not a physical register) BANK0:TMR0 0x0001 Timer0 module's register BANK0:PCL 0x0002 Program Counter's (PC) Least Significant Byte BANK0:STATUS 0x0003 STATUS REGISTER BANK0:STATUS.IRP 7 Register Bank Select bit BANK0:STATUS.RP1 6 Register Bank Select bit 1 BANK0:STATUS.RP0 5 Register Bank Select bit 0 BANK0:STATUS.TO 4 Time-out bit BANK0:STATUS.PD 3 Power-down bit BANK0:STATUS.Z 2 Zero bit BANK0:STATUS.DC 1 Digit carry/borrow bit BANK0:STATUS.C 0 Carry/borrow bit BANK0:FSR 0x0004 Indirect data memory address pointer BANK0:PORTA 0x0005 PORTA REGISTER BANK0:PORTA.RA5 5 PORTA bit 5 BANK0:PORTA.RA4 4 PORTA bit 4 BANK0:PORTA.RA3 3 PORTA bit 3 BANK0:PORTA.RA2 2 PORTA bit 2 BANK0:PORTA.RA1 1 PORTA bit 1 BANK0:PORTA.RA0 0 PORTA bit 0 BANK0:PORTB 0x0006 PORTB REGISTER BANK0:PORTB.RB7 7 PORTB bit 7 BANK0:PORTB.RB6 6 PORTB bit 6 BANK0:PORTB.RB5 5 PORTB bit 5 BANK0:PORTB.RB4 4 PORTB bit 4 BANK0:PORTB.RB3 3 PORTB bit 3 BANK0:PORTB.RB2 2 PORTB bit 2 BANK0:PORTB.RB1 1 PORTB bit 1 BANK0:PORTB.RB0 0 PORTB bit 0 BANK0:PORTC 0x0007 PORTC REGISTER BANK0:PORTC.RC7 7 PORTC bit 7 BANK0:PORTC.RC6 6 PORTC bit 6 BANK0:PORTC.RC5 5 PORTC bit 5 BANK0:PORTC.RC4 4 PORTC bit 4 BANK0:PORTC.RC3 3 PORTC bit 3 BANK0:PORTC.RC2 2 PORTC bit 2 BANK0:PORTC.RC1 1 PORTC bit 1 BANK0:PORTC.RC0 0 PORTC bit 0 BANK0:RESERVED0008 0x0008 RESERVED BANK0:RESERVED0009 0x0009 RESERVED BANK0:PCLATH 0x000A Write Buffer for the upper 5 bits of the Program Counter BANK0:INTCON 0x000B INTCON REGISTER BANK0:INTCON.GIE 7 Global Interrupt Enable bit BANK0:INTCON.PEIE 6 Peripheral Interrupt Enable bit BANK0:INTCON.T0IE 5 TMR0 Overflow Interrupt Enable bit BANK0:INTCON.INTE 4 RB0/INT External Interrupt Enable bit BANK0:INTCON.RBIE 3 RB Port Change Interrupt Enable bit BANK0:INTCON.T0IF 2 TMR0 Overflow Interrupt Flag bit BANK0:INTCON.INTF 1 RB0/INT External Interrupt Flag bit BANK0:INTCON.RBIF 0 RB Port Change Interrupt Flag bit BANK0:PIR1 0x000C PIR1 REGISTER BANK0:PIR1.ADIF 6 A/D Converter Interrupt Flag bit (NOT IN PIC16C62B) BANK0:PIR1.SSPIF 3 Synchronous Serial Port Interrupt Flag bit BANK0:PIR1.CCP1IF 2 CCP1 Interrupt Flag bit BANK0:PIR1.TMR2IF 1 TMR2 to PR2 Match Interrupt Flag bit BANK0:PIR1.TMR1IF 0 TMR1 Overflow Interrupt Flag bit BANK0:RESERVED000D 0x000D RESERVED BANK0:TMR1L 0x000E Holding register for the Least Significant Byte of the 16-bit TMR1 register BANK0:TMR1H 0x000F Holding register for the Most Significant Byte of the 16-bit TMR1 register BANK0:T1CON 0x0010 TIMER1 CONTROL REGISTER BANK0:T1CON.T1CKPS1 5 Timer1 Input Clock Prescale Select bit 1 BANK0:T1CON.T1CKPS0 4 Timer1 Input Clock Prescale Select bit 0 BANK0:T1CON.T1OSCEN 3 Timer1 Oscillator Enable Control bit BANK0:T1CON.T1SYNC 2 Timer1 External Clock Input Synchronization Control bit BANK0:T1CON.TMR1CS 1 Timer1 Clock Source Select bit BANK0:T1CON.TMR1ON 0 Timer1 On bit BANK0:TMR2 0x0011 Timer2 module's register BANK0:T2CON 0x0012 TIMER2 CONTROL REGISTER BANK0:T2CON.TOUTPS3 6 Timer2 Output Postscale Select bit 3 BANK0:T2CON.TOUTPS2 5 Timer2 Output Postscale Select bit 2 BANK0:T2CON.TOUTPS1 4 Timer2 Output Postscale Select bit 1 BANK0:T2CON.TOUTPS0 3 Timer2 Output Postscale Select bit 0 BANK0:T2CON.TMR2ON 2 Timer2 On bit BANK0:T2CON.T2CKPS1 1 Timer2 Clock Prescale Select bit 1 BANK0:T2CON.T2CKPS0 0 Timer2 Clock Prescale Select bit 0 BANK0:SSPBUF 0x0013 Synchronous Serial Port Receive Buffer/Transmit Register BANK0:SSPCON 0x0014 SYNC SERIAL PORT CONTROL REGISTER BANK0:SSPCON.WCOL 7 Write Collision Detect bit BANK0:SSPCON.SSPOV 6 Receive Overflow Indicator bit BANK0:SSPCON.SSPEN 5 Synchronous Serial Port Enable bit BANK0:SSPCON.CKP 4 Clock Polarity Select bit BANK0:SSPCON.SSPM3 3 Synchronous Serial Port Mode Select bit 3 BANK0:SSPCON.SSPM2 2 Synchronous Serial Port Mode Select bit 2 BANK0:SSPCON.SSPM1 1 Synchronous Serial Port Mode Select bit 1 BANK0:SSPCON.SSPM0 0 Synchronous Serial Port Mode Select bit 0 BANK0:CCPR1L 0x0015 Capture/Compare/PWM Register1 (LSB) BANK0:CCPR1H 0x0016 Capture/Compare/PWM Register1 (MSB) BANK0:CCP1CON 0x0017 CCP1CON REGISTER BANK0:CCP1CON.CCP1X 5 PWM Least Significant bit BANK0:CCP1CON.CCP1Y 4 PWM Least Significant bit BANK0:CCP1CON.CCP1M3 3 CCP1 Mode Select bit 3 BANK0:CCP1CON.CCP1M2 2 CCP1 Mode Select bit 2 BANK0:CCP1CON.CCP1M1 1 CCP1 Mode Select bit 1 BANK0:CCP1CON.CCP1M0 0 CCP1 Mode Select bit 0 BANK0:RESERVED0018 0x0018 RESERVED BANK0:RESERVED0019 0x0019 RESERVED BANK0:RESERVED001A 0x001A RESERVED BANK0:RESERVED001B 0x001B RESERVED BANK0:RESERVED001C 0x001C RESERVED BANK0:RESERVED001D 0x001D RESERVED BANK0:ADRES 0x001E A/D Result Register BANK0:ADCON0 0x001F ADCON0 REGISTER BANK0:ADCON0.ADCS1 7 A/D Conversion Clock Select bit 1 BANK0:ADCON0.ADCS0 6 A/D Conversion Clock Select bit 0 BANK0:ADCON0.CHS2 5 Analog Channel Select bit 2 BANK0:ADCON0.CHS1 4 Analog Channel Select bit 1 BANK0:ADCON0.CHS0 3 Analog Channel Select bit 0 BANK0:ADCON0.GO_DONE 2 A/D Conversion Status bit BANK0:ADCON0.ADON 0 A/D On bit ; BANK1 (0x0080:0x0100) BANK1:INDF 0x0080 INDF (not a physical register) BANK1:OPTION 0x0081 OPTION REGISTER BANK1:OPTION.RBPU 7 PORTB Pull-up Enable bit BANK1:OPTION.INTEDG 6 Interrupt Edge Select bit BANK1:OPTION.T0CS 5 TMR0 Clock Source Select bit BANK1:OPTION.T0SE 4 TMR0 Source Edge Select bit BANK1:OPTION.PSA 3 Prescaler Assignment bit BANK1:OPTION.PS2 2 Prescaler Rate Select bit 2 BANK1:OPTION.PS1 1 Prescaler Rate Select bit 1 BANK1:OPTION.PS0 0 Prescaler Rate Select bit 0 BANK1:PCL 0x0082 Program Counter's (PC) Least Significant Byte BANK1:STATUS 0x0083 STATUS REGISTER BANK1:STATUS.IRP 7 Register Bank Select bit BANK1:STATUS.RP1 6 Register Bank Select bit 1 BANK1:STATUS.RP0 5 Register Bank Select bit 0 BANK1:STATUS.TO 4 Time-out bit BANK1:STATUS.PD 3 Power-down bit BANK1:STATUS.Z 2 Zero bit BANK1:STATUS.DC 1 Digit carry/borrow bit BANK1:STATUS.C 0 Carry/borrow bit BANK1:FSR 0x0084 Indirect data memory address pointer BANK1:TRISA 0x0085 PORTA Data Direction Register BANK1:TRISA.TRISA5 5 PORTA Data Direction Register bit 5 BANK1:TRISA.TRISA4 4 PORTA Data Direction Register bit 4 BANK1:TRISA.TRISA3 3 PORTA Data Direction Register bit 3 BANK1:TRISA.TRISA2 2 PORTA Data Direction Register bit 2 BANK1:TRISA.TRISA1 1 PORTA Data Direction Register bit 1 BANK1:TRISA.TRISA0 0 PORTA Data Direction Register bit 0 BANK1:TRISB 0x0086 PORTB Data Direction Register BANK1:TRISB.TRISB7 7 PORTB Data Direction Register bit 7 BANK1:TRISB.TRISB6 6 PORTB Data Direction Register bit 6 BANK1:TRISB.TRISB5 5 PORTB Data Direction Register bit 5 BANK1:TRISB.TRISB4 4 PORTB Data Direction Register bit 4 BANK1:TRISB.TRISB3 3 PORTB Data Direction Register bit 3 BANK1:TRISB.TRISB2 2 PORTB Data Direction Register bit 2 BANK1:TRISB.TRISB1 1 PORTB Data Direction Register bit 1 BANK1:TRISB.TRISB0 0 PORTB Data Direction Register bit 0 BANK1:TRISC 0x0087 PORTC Data Direction Register BANK1:TRISC.TRISC7 7 PORTC Data Direction Register bit 7 BANK1:TRISC.TRISC6 6 PORTC Data Direction Register bit 6 BANK1:TRISC.TRISC5 5 PORTC Data Direction Register bit 5 BANK1:TRISC.TRISC4 4 PORTC Data Direction Register bit 4 BANK1:TRISC.TRISC3 3 PORTC Data Direction Register bit 3 BANK1:TRISC.TRISC2 2 PORTC Data Direction Register bit 2 BANK1:TRISC.TRISC1 1 PORTC Data Direction Register bit 1 BANK1:TRISC.TRISC0 0 PORTC Data Direction Register bit 0 BANK1:RESERVED0088 0x0088 RESERVED BANK1:RESERVED0089 0x0089 RESERVED BANK1:PCLATH 0x008A Write Buffer for the upper 5 bits of the Program Counter BANK1:INTCON 0x008B INTCON REGISTER BANK1:INTCON.GIE 7 Global Interrupt Enable bit BANK1:INTCON.PEIE 6 Peripheral Interrupt Enable bit BANK1:INTCON.T0IE 5 TMR0 Overflow Interrupt Enable bit BANK1:INTCON.INTE 4 RB0/INT External Interrupt Enable bit BANK1:INTCON.RBIE 3 RB Port Change Interrupt Enable bit BANK1:INTCON.T0IF 2 TMR0 Overflow Interrupt Flag bit BANK1:INTCON.INTF 1 RB0/INT External Interrupt Flag bit BANK1:INTCON.RBIF 0 RB Port Change Interrupt Flag bit BANK1:PIE1 0x008C PIE1 REGISTER BANK1:PIE1.ADIE 6 A/D Converter Interrupt Enable bit (NOT IN PIC16C62B) BANK1:PIE1.SSPIE 3 Synchronous Serial Port Interrupt Enable bit BANK1:PIE1.CCP1IE 2 CCP1 Interrupt Enable bit BANK1:PIE1.TMR2IE 1 TMR2 to PR2 Match Interrupt Enable bit BANK1:PIE1.TMR1IE 0 TMR1 Overflow Interrupt Enable bit BANK1:RESERVED008D 0x008D RESERVED BANK1:PCON 0x008E PCON REGISTER BANK1:PCON.POR 1 Power-on Reset Status bit BANK1:PCON.BOR 0 Brown-out Reset Status bit BANK1:RESERVED008F 0x008F RESERVED BANK1:RESERVED0090 0x0090 RESERVED BANK1:RESERVED0091 0x0091 RESERVED BANK1:PR2 0x0092 Timer2 Period Register BANK1:SSPADD 0x0093 Synchronous Serial Port (I 2 C mode) Address Register BANK1:SSPSTAT 0x0094 SYNC SERIAL PORT STATUS REGISTER BANK1:SSPSTAT.SMP 7 SPI data input sample phase BANK1:SSPSTAT.CKE 6 SPI Clock Edge Select BANK1:SSPSTAT.D_A 5 Data/Address bit (I2C mode only) BANK1:SSPSTAT.P 4 Stop bit (I2C mode only) BANK1:SSPSTAT.S 3 Start bit (I2C mode only) BANK1:SSPSTAT.R_W 2 Read/Write bit information (I2C mode only) BANK1:SSPSTAT.UA 1 Update Address (I2C mode only) BANK1:SSPSTAT.BF 0 Buffer Full Status bit BANK1:RESERVED0095 0x0095 RESERVED BANK1:RESERVED0096 0x0096 RESERVED BANK1:RESERVED0097 0x0097 RESERVED BANK1:RESERVED0098 0x0098 RESERVED BANK1:RESERVED0099 0x0099 RESERVED BANK1:RESERVED009A 0x009A RESERVED BANK1:RESERVED009B 0x009B RESERVED BANK1:RESERVED009C 0x009C RESERVED BANK1:RESERVED009D 0x009D RESERVED BANK1:RESERVED009E 0x009E RESERVED BANK1:ADCON1 0x009F ADCON1 REGISTER BANK1:ADCON1.PCFG2 2 A/D Port Configuration Control bit 2 BANK1:ADCON1.PCFG1 1 A/D Port Configuration Control bit 1 BANK1:ADCON1.PCFG0 0 A/D Port Configuration Control bit 0 .16C620 ; http://www.microchip.com/download/lit/pline/picmicro/families/16c62x/30235h.pdf ; PIC16C62X.pdf ; MEMORY MAP ; BANK_0 area DATA FSR_ 0x0000:0x0020 area DATA Gen_Purp 0x0020:0x0070 General Purpose Register area BSS RESERVED 0x0070:0x0080 area DATA MEM_Program 0x0080:0x0200 On-chip Program Memory ; BANK_1 ; area DATA FSR_ 0x0080:0x00A0 ; area BSS RESERVED 0x00A0:0x0100 ; area DATA MEM_Program 0x0100:0x0200 On-chip Program Memory ; Interrupt and reset vector assignments interrupt RESET 0x0000 RESET ; INPUT/OUTPUT PORTS ; BANK0 (0x0000:0x0080) BANK0:INDF 0x0000 INDF (not a physical register) BANK0:TMR0 0x0001 Timer0 module's register BANK0:PCL 0x0002 Program Counter's (PC) Least Significant Byte BANK0:STATUS 0x0003 STATUS REGISTER BANK0:STATUS.RP0 5 Register Bank Select bit 0 BANK0:STATUS.TO 4 Time-out bit BANK0:STATUS.PD 3 Power-down bit BANK0:STATUS.Z 2 Zero bit BANK0:STATUS.DC 1 Digit carry/borrow bit BANK0:STATUS.C 0 Carry/borrow bit BANK0:FSR 0x0004 Indirect data memory address pointer BANK0:PORTA 0x0005 PORTA REGISTER BANK0:PORTA.RA4 4 PORTA bit 4 BANK0:PORTA.RA3 3 PORTA bit 3 BANK0:PORTA.RA2 2 PORTA bit 2 BANK0:PORTA.RA1 1 PORTA bit 1 BANK0:PORTA.RA0 0 PORTA bit 0 BANK0:PORTB 0x0006 PORTB REGISTER BANK0:PORTB.RB7 7 PORTB bit 7 BANK0:PORTB.RB6 6 PORTB bit 6 BANK0:PORTB.RB5 5 PORTB bit 5 BANK0:PORTB.RB4 4 PORTB bit 4 BANK0:PORTB.RB3 3 PORTB bit 3 BANK0:PORTB.RB2 2 PORTB bit 2 BANK0:PORTB.RB1 1 PORTB bit 1 BANK0:PORTB.RB0 0 PORTB bit 0 BANK0:RESERVED0007 0x0007 RESERVED BANK0:RESERVED0008 0x0008 RESERVED BANK0:RESERVED0009 0x0009 RESERVED BANK0:PCLATH 0x000A Write Buffer for the upper 5 bits of the Program Counter BANK0:INTCON 0x000B INTCON REGISTER BANK0:INTCON.GIE 7 Global Interrupt Enable bit BANK0:INTCON.PEIE 6 Peripheral Interrupt Enable bit BANK0:INTCON.T0IE 5 TMR0 Overflow Interrupt Enable bit BANK0:INTCON.INTE 4 RB0/INT External Interrupt Enable bit BANK0:INTCON.RBIE 3 RB Port Change Interrupt Enable bit BANK0:INTCON.T0IF 2 TMR0 Overflow Interrupt Flag bit BANK0:INTCON.INTF 1 RB0/INT External Interrupt Flag bit BANK0:INTCON.RBIF 0 RB Port Change Interrupt Flag bit BANK0:PIR1 0x000C PIR1 REGISTER BANK0:PIR1.CMIF 6 Comparator Interrupt Flag bit BANK0:RESERVED000D 0x000D RESERVED BANK0:RESERVED000E 0x000E RESERVED BANK0:RESERVED000F 0x000F RESERVED BANK0:RESERVED0010 0x0010 RESERVED BANK0:RESERVED0011 0x0011 RESERVED BANK0:RESERVED0012 0x0012 RESERVED BANK0:RESERVED0013 0x0013 RESERVED BANK0:RESERVED0014 0x0014 RESERVED BANK0:RESERVED0015 0x0015 RESERVED BANK0:RESERVED0016 0x0016 RESERVED BANK0:RESERVED0017 0x0017 RESERVED BANK0:RESERVED0018 0x0018 RESERVED BANK0:RESERVED0019 0x0019 RESERVED BANK0:RESERVED001A 0x001A RESERVED BANK0:RESERVED001B 0x001B RESERVED BANK0:RESERVED001C 0x001C RESERVED BANK0:RESERVED001D 0x001D RESERVED BANK0:RESERVED001E 0x001E RESERVED BANK0:CMCON 0x001F CMCON REGISTER BANK0:CMCON.C2OUT 7 Comparator 2 output BANK0:CMCON.C1OUT 6 Comparator 1 output BANK0:CMCON.CIS 3 Comparator Input Switch BANK0:CMCON.CM2 2 Comparator mode 2 BANK0:CMCON.CM1 1 Comparator mode 1 BANK0:CMCON.CM0 0 Comparator mode 0 ; BANK1 (0x0080:0x0100) BANK1:INDF 0x0080 INDF (not a physical register) BANK1:OPTION 0x0081 OPTION REGISTER BANK1:OPTION.RBPU 7 PORTB Pull-up Enable bit BANK1:OPTION.INTEDG 6 Interrupt Edge Select bit BANK1:OPTION.T0CS 5 TMR0 Clock Source Select bit BANK1:OPTION.T0SE 4 TMR0 Source Edge Select bit BANK1:OPTION.PSA 3 Prescaler Assignment bit BANK1:OPTION.PS2 2 Prescaler Rate Select bit 2 BANK1:OPTION.PS1 1 Prescaler Rate Select bit 1 BANK1:OPTION.PS0 0 Prescaler Rate Select bit 0 BANK1:PCL 0x0082 Program Counter's (PC) Least Significant Byte BANK1:STATUS 0x0083 STATUS REGISTER BANK1:STATUS.RP0 5 Register Bank Select bit 0 BANK1:STATUS.TO 4 Time-out bit BANK1:STATUS.PD 3 Power-down bit BANK1:STATUS.Z 2 Zero bit BANK1:STATUS.DC 1 Digit carry/borrow bit BANK1:STATUS.C 0 Carry/borrow bit BANK1:FSR 0x0084 Indirect data memory address pointer BANK1:TRISA 0x0085 PORTA Data Direction Register BANK1:TRISA.TRISA4 4 PORTA Data Direction Register bit 4 BANK1:TRISA.TRISA3 3 PORTA Data Direction Register bit 3 BANK1:TRISA.TRISA2 2 PORTA Data Direction Register bit 2 BANK1:TRISA.TRISA1 1 PORTA Data Direction Register bit 1 BANK1:TRISA.TRISA0 0 PORTA Data Direction Register bit 0 BANK1:TRISB 0x0086 PORTB Data Direction Register BANK1:TRISB.TRISB7 7 PORTB Data Direction Register bit 7 BANK1:TRISB.TRISB6 6 PORTB Data Direction Register bit 6 BANK1:TRISB.TRISB5 5 PORTB Data Direction Register bit 5 BANK1:TRISB.TRISB4 4 PORTB Data Direction Register bit 4 BANK1:TRISB.TRISB3 3 PORTB Data Direction Register bit 3 BANK1:TRISB.TRISB2 2 PORTB Data Direction Register bit 2 BANK1:TRISB.TRISB1 1 PORTB Data Direction Register bit 1 BANK1:TRISB.TRISB0 0 PORTB Data Direction Register bit 0 BANK1:RESERVED0087 0x0087 RESERVED BANK1:RESERVED0088 0x0088 RESERVED BANK1:RESERVED0089 0x0089 RESERVED BANK1:PCLATH 0x008A Write Buffer for the upper 5 bits of Program Counter BANK1:INTCON 0x008B INTCON REGISTER BANK1:INTCON.GIE 7 Global Interrupt Enable bit BANK1:INTCON.PEIE 6 Peripheral Interrupt Enable bit BANK1:INTCON.T0IE 5 TMR0 Overflow Interrupt Enable bit BANK1:INTCON.INTE 4 RB0/INT External Interrupt Enable bit BANK1:INTCON.RBIE 3 RB Port Change Interrupt Enable bit BANK1:INTCON.T0IF 2 TMR0 Overflow Interrupt Flag bit BANK1:INTCON.INTF 1 RB0/INT External Interrupt Flag bit BANK1:INTCON.RBIF 0 RB Port Change Interrupt Flag bit BANK1:PIE1 0x008C PIE1 REGISTER BANK1:PIE1.CMIE 6 BANK1:RESERVED008D 0x008D RESERVED BANK1:PCON 0x008E PCON REGISTER BANK1:PCON.POR 1 Power-on Reset Status bit BANK1:PCON.BOR 0 Brown-out Reset Status bit BANK1:RESERVED008F 0x008F RESERVED BANK1:RESERVED0090 0x0090 RESERVED BANK1:RESERVED0091 0x0091 RESERVED BANK1:RESERVED0092 0x0092 RESERVED BANK1:RESERVED0093 0x0093 RESERVED BANK1:RESERVED0094 0x0094 RESERVED BANK1:RESERVED0095 0x0095 RESERVED BANK1:RESERVED0096 0x0096 RESERVED BANK1:RESERVED0097 0x0097 RESERVED BANK1:RESERVED0098 0x0098 RESERVED BANK1:RESERVED0099 0x0099 RESERVED BANK1:RESERVED009A 0x009A RESERVED BANK1:RESERVED009B 0x009B RESERVED BANK1:RESERVED009C 0x009C RESERVED BANK1:RESERVED009D 0x009D RESERVED BANK1:RESERVED009E 0x009E RESERVED BANK1:VRCON 0x009F VRCON REGISTER BANK1:VRCON.VREN 7 VREF Enable BANK1:VRCON.VROE 6 VREF Output Enable BANK1:VRCON.VRR 5 VREF Range selection BANK1:VRCON.VR3 3 VREF value selection 3 BANK1:VRCON.VR2 2 VREF value selection 2 BANK1:VRCON.VR1 1 VREF value selection 1 BANK1:VRCON.VR0 0 VREF value selection 0 .16C620A ; http://www.microchip.com/download/lit/pline/picmicro/families/16c62x/30235h.pdf ; PIC16C62X.pdf ; MEMORY MAP ; BANK_0 area DATA FSR_ 0x0000:0x0020 area DATA Gen_Purp1 0x0020:0x0070 General Purpose Register area DATA Gen_Purp2 0x0070:0x0080 General Purpose Register area DATA MEM_Program 0x0080:0x0200 On-chip Program Memory ; BANK_1 ; area DATA FSR_ 0x0080:0x00A0 ; area BSS RESERVED 0x00A0:0x00F0 ; area DATA Gen_Purp_BANK0 0x00F0:0x0100 Accesses 70h-7Fh ; area DATA MEM_Program 0x0100:0x0200 On-chip Program Memory ; Interrupt and reset vector assignments interrupt RESET 0x0000 RESET ; INPUT/OUTPUT PORTS ; BANK0 (0x0000:0x0080) BANK0:INDF 0x0000 INDF (not a physical register) BANK0:TMR0 0x0001 Timer0 module's register BANK0:PCL 0x0002 Program Counter's (PC) Least Significant Byte BANK0:STATUS 0x0003 STATUS REGISTER BANK0:STATUS.RP0 5 Register Bank Select bit 0 BANK0:STATUS.TO 4 Time-out bit BANK0:STATUS.PD 3 Power-down bit BANK0:STATUS.Z 2 Zero bit BANK0:STATUS.DC 1 Digit carry/borrow bit BANK0:STATUS.C 0 Carry/borrow bit BANK0:FSR 0x0004 Indirect data memory address pointer BANK0:PORTA 0x0005 PORTA REGISTER BANK0:PORTA.RA4 4 PORTA bit 4 BANK0:PORTA.RA3 3 PORTA bit 3 BANK0:PORTA.RA2 2 PORTA bit 2 BANK0:PORTA.RA1 1 PORTA bit 1 BANK0:PORTA.RA0 0 PORTA bit 0 BANK0:PORTB 0x0006 PORTB REGISTER BANK0:PORTB.RB7 7 PORTB bit 7 BANK0:PORTB.RB6 6 PORTB bit 6 BANK0:PORTB.RB5 5 PORTB bit 5 BANK0:PORTB.RB4 4 PORTB bit 4 BANK0:PORTB.RB3 3 PORTB bit 3 BANK0:PORTB.RB2 2 PORTB bit 2 BANK0:PORTB.RB1 1 PORTB bit 1 BANK0:PORTB.RB0 0 PORTB bit 0 BANK0:RESERVED0007 0x0007 RESERVED BANK0:RESERVED0008 0x0008 RESERVED BANK0:RESERVED0009 0x0009 RESERVED BANK0:PCLATH 0x000A Write Buffer for the upper 5 bits of the Program Counter BANK0:INTCON 0x000B INTCON REGISTER BANK0:INTCON.GIE 7 Global Interrupt Enable bit BANK0:INTCON.PEIE 6 Peripheral Interrupt Enable bit BANK0:INTCON.T0IE 5 TMR0 Overflow Interrupt Enable bit BANK0:INTCON.INTE 4 RB0/INT External Interrupt Enable bit BANK0:INTCON.RBIE 3 RB Port Change Interrupt Enable bit BANK0:INTCON.T0IF 2 TMR0 Overflow Interrupt Flag bit BANK0:INTCON.INTF 1 RB0/INT External Interrupt Flag bit BANK0:INTCON.RBIF 0 RB Port Change Interrupt Flag bit BANK0:PIR1 0x000C PIR1 REGISTER BANK0:PIR1.CMIF 6 Comparator Interrupt Flag bit BANK0:RESERVED000D 0x000D RESERVED BANK0:RESERVED000E 0x000E RESERVED BANK0:RESERVED000F 0x000F RESERVED BANK0:RESERVED0010 0x0010 RESERVED BANK0:RESERVED0011 0x0011 RESERVED BANK0:RESERVED0012 0x0012 RESERVED BANK0:RESERVED0013 0x0013 RESERVED BANK0:RESERVED0014 0x0014 RESERVED BANK0:RESERVED0015 0x0015 RESERVED BANK0:RESERVED0016 0x0016 RESERVED BANK0:RESERVED0017 0x0017 RESERVED BANK0:RESERVED0018 0x0018 RESERVED BANK0:RESERVED0019 0x0019 RESERVED BANK0:RESERVED001A 0x001A RESERVED BANK0:RESERVED001B 0x001B RESERVED BANK0:RESERVED001C 0x001C RESERVED BANK0:RESERVED001D 0x001D RESERVED BANK0:RESERVED001E 0x001E RESERVED BANK0:CMCON 0x001F CMCON REGISTER BANK0:CMCON.C2OUT 7 Comparator 2 output BANK0:CMCON.C1OUT 6 Comparator 1 output BANK0:CMCON.CIS 3 Comparator Input Switch BANK0:CMCON.CM2 2 Comparator mode 2 BANK0:CMCON.CM1 1 Comparator mode 1 BANK0:CMCON.CM0 0 Comparator mode 0 ; BANK1 (0x0080:0x0100) BANK1:INDF 0x0080 INDF (not a physical register) BANK1:OPTION 0x0081 OPTION REGISTER BANK1:OPTION.RBPU 7 PORTB Pull-up Enable bit BANK1:OPTION.INTEDG 6 Interrupt Edge Select bit BANK1:OPTION.T0CS 5 TMR0 Clock Source Select bit BANK1:OPTION.T0SE 4 TMR0 Source Edge Select bit BANK1:OPTION.PSA 3 Prescaler Assignment bit BANK1:OPTION.PS2 2 Prescaler Rate Select bit 2 BANK1:OPTION.PS1 1 Prescaler Rate Select bit 1 BANK1:OPTION.PS0 0 Prescaler Rate Select bit 0 BANK1:PCL 0x0082 Program Counter's (PC) Least Significant Byte BANK1:STATUS 0x0083 STATUS REGISTER BANK1:STATUS.RP0 5 Register Bank Select bit 0 BANK1:STATUS.TO 4 Time-out bit BANK1:STATUS.PD 3 Power-down bit BANK1:STATUS.Z 2 Zero bit BANK1:STATUS.DC 1 Digit carry/borrow bit BANK1:STATUS.C 0 Carry/borrow bit BANK1:FSR 0x0084 Indirect data memory address pointer BANK1:TRISA 0x0085 PORTA Data Direction Register BANK1:TRISA.TRISA4 4 PORTA Data Direction Register bit 4 BANK1:TRISA.TRISA3 3 PORTA Data Direction Register bit 3 BANK1:TRISA.TRISA2 2 PORTA Data Direction Register bit 2 BANK1:TRISA.TRISA1 1 PORTA Data Direction Register bit 1 BANK1:TRISA.TRISA0 0 PORTA Data Direction Register bit 0 BANK1:TRISB 0x0086 PORTB Data Direction Register BANK1:TRISB.TRISB7 7 PORTB Data Direction Register bit 7 BANK1:TRISB.TRISB6 6 PORTB Data Direction Register bit 6 BANK1:TRISB.TRISB5 5 PORTB Data Direction Register bit 5 BANK1:TRISB.TRISB4 4 PORTB Data Direction Register bit 4 BANK1:TRISB.TRISB3 3 PORTB Data Direction Register bit 3 BANK1:TRISB.TRISB2 2 PORTB Data Direction Register bit 2 BANK1:TRISB.TRISB1 1 PORTB Data Direction Register bit 1 BANK1:TRISB.TRISB0 0 PORTB Data Direction Register bit 0 BANK1:RESERVED0087 0x0087 RESERVED BANK1:RESERVED0088 0x0088 RESERVED BANK1:RESERVED0089 0x0089 RESERVED BANK1:PCLATH 0x008A Write Buffer for the upper 5 bits of Program Counter BANK1:INTCON 0x008B INTCON REGISTER BANK1:INTCON.GIE 7 Global Interrupt Enable bit BANK1:INTCON.PEIE 6 Peripheral Interrupt Enable bit BANK1:INTCON.T0IE 5 TMR0 Overflow Interrupt Enable bit BANK1:INTCON.INTE 4 RB0/INT External Interrupt Enable bit BANK1:INTCON.RBIE 3 RB Port Change Interrupt Enable bit BANK1:INTCON.T0IF 2 TMR0 Overflow Interrupt Flag bit BANK1:INTCON.INTF 1 RB0/INT External Interrupt Flag bit BANK1:INTCON.RBIF 0 RB Port Change Interrupt Flag bit BANK1:PIE1 0x008C PIE1 REGISTER BANK1:PIE1.CMIE 6 Comparator Interrupt Enable bit BANK1:RESERVED008D 0x008D RESERVED BANK1:PCON 0x008E PCON REGISTER BANK1:PCON.POR 1 Power-on Reset Status bit BANK1:PCON.BOR 0 Brown-out Reset Status bit BANK1:RESERVED008F 0x008F RESERVED BANK1:RESERVED0090 0x0090 RESERVED BANK1:RESERVED0091 0x0091 RESERVED BANK1:RESERVED0092 0x0092 RESERVED BANK1:RESERVED0093 0x0093 RESERVED BANK1:RESERVED0094 0x0094 RESERVED BANK1:RESERVED0095 0x0095 RESERVED BANK1:RESERVED0096 0x0096 RESERVED BANK1:RESERVED0097 0x0097 RESERVED BANK1:RESERVED0098 0x0098 RESERVED BANK1:RESERVED0099 0x0099 RESERVED BANK1:RESERVED009A 0x009A RESERVED BANK1:RESERVED009B 0x009B RESERVED BANK1:RESERVED009C 0x009C RESERVED BANK1:RESERVED009D 0x009D RESERVED BANK1:RESERVED009E 0x009E RESERVED BANK1:VRCON 0x009F VRCON REGISTER BANK1:VRCON.VREN 7 VREF Enable BANK1:VRCON.VROE 6 VREF Output Enable BANK1:VRCON.VRR 5 VREF Range selection BANK1:VRCON.VR3 3 VREF value selection 3 BANK1:VRCON.VR2 2 VREF value selection 2 BANK1:VRCON.VR1 1 VREF value selection 1 BANK1:VRCON.VR0 0 VREF value selection 0 .16C621 ; http://www.microchip.com/download/lit/pline/picmicro/families/16c62x/30235h.pdf ; PIC16C62X.pdf ; MEMORY MAP ; BANK_0 area DATA FSR_ 0x0000:0x0020 area DATA Gen_Purp 0x0020:0x0070 General Purpose Register area BSS RESERVED 0x0070:0x0080 area DATA MEM_Program 0x0080:0x0400 On-chip Program Memory ; BANK_1 ; area DATA FSR_ 0x0080:0x00A0 ; area BSS RESERVED 0x00A0:0x0100 ; area DATA MEM_Program 0x0100:0x0400 On-chip Program Memory ; Interrupt and reset vector assignments interrupt RESET 0x0000 RESET ; INPUT/OUTPUT PORTS ; BANK0 (0x0000:0x0080) BANK0:INDF 0x0000 INDF (not a physical register) BANK0:TMR0 0x0001 Timer0 module's register BANK0:PCL 0x0002 Program Counter's (PC) Least Significant Byte BANK0:STATUS 0x0003 STATUS REGISTER BANK0:STATUS.RP0 5 Register Bank Select bit 0 BANK0:STATUS.TO 4 Time-out bit BANK0:STATUS.PD 3 Power-down bit BANK0:STATUS.Z 2 Zero bit BANK0:STATUS.DC 1 Digit carry/borrow bit BANK0:STATUS.C 0 Carry/borrow bit BANK0:FSR 0x0004 Indirect data memory address pointer BANK0:PORTA 0x0005 PORTA REGISTER BANK0:PORTA.RA4 4 PORTA bit 4 BANK0:PORTA.RA3 3 PORTA bit 3 BANK0:PORTA.RA2 2 PORTA bit 2 BANK0:PORTA.RA1 1 PORTA bit 1 BANK0:PORTA.RA0 0 PORTA bit 0 BANK0:PORTB 0x0006 PORTB REGISTER BANK0:PORTB.RB7 7 PORTB bit 7 BANK0:PORTB.RB6 6 PORTB bit 6 BANK0:PORTB.RB5 5 PORTB bit 5 BANK0:PORTB.RB4 4 PORTB bit 4 BANK0:PORTB.RB3 3 PORTB bit 3 BANK0:PORTB.RB2 2 PORTB bit 2 BANK0:PORTB.RB1 1 PORTB bit 1 BANK0:PORTB.RB0 0 PORTB bit 0 BANK0:RESERVED0007 0x0007 RESERVED BANK0:RESERVED0008 0x0008 RESERVED BANK0:RESERVED0009 0x0009 RESERVED BANK0:PCLATH 0x000A Write Buffer for the upper 5 bits of the Program Counter BANK0:INTCON 0x000B INTCON REGISTER BANK0:INTCON.GIE 7 Global Interrupt Enable bit BANK0:INTCON.PEIE 6 Peripheral Interrupt Enable bit BANK0:INTCON.T0IE 5 TMR0 Overflow Interrupt Enable bit BANK0:INTCON.INTE 4 RB0/INT External Interrupt Enable bit BANK0:INTCON.RBIE 3 RB Port Change Interrupt Enable bit BANK0:INTCON.T0IF 2 TMR0 Overflow Interrupt Flag bit BANK0:INTCON.INTF 1 RB0/INT External Interrupt Flag bit BANK0:INTCON.RBIF 0 RB Port Change Interrupt Flag bit BANK0:PIR1 0x000C PIR1 REGISTER BANK0:PIR1.CMIF 6 Comparator Interrupt Flag bit BANK0:RESERVED000D 0x000D RESERVED BANK0:RESERVED000E 0x000E RESERVED BANK0:RESERVED000F 0x000F RESERVED BANK0:RESERVED0010 0x0010 RESERVED BANK0:RESERVED0011 0x0011 RESERVED BANK0:RESERVED0012 0x0012 RESERVED BANK0:RESERVED0013 0x0013 RESERVED BANK0:RESERVED0014 0x0014 RESERVED BANK0:RESERVED0015 0x0015 RESERVED BANK0:RESERVED0016 0x0016 RESERVED BANK0:RESERVED0017 0x0017 RESERVED BANK0:RESERVED0018 0x0018 RESERVED BANK0:RESERVED0019 0x0019 RESERVED BANK0:RESERVED001A 0x001A RESERVED BANK0:RESERVED001B 0x001B RESERVED BANK0:RESERVED001C 0x001C RESERVED BANK0:RESERVED001D 0x001D RESERVED BANK0:RESERVED001E 0x001E RESERVED BANK0:CMCON 0x001F CMCON REGISTER BANK0:CMCON.C2OUT 7 Comparator 2 output BANK0:CMCON.C1OUT 6 Comparator 1 output BANK0:CMCON.CIS 3 Comparator Input Switch BANK0:CMCON.CM2 2 Comparator mode 2 BANK0:CMCON.CM1 1 Comparator mode 1 BANK0:CMCON.CM0 0 Comparator mode 0 ; BANK1 (0x0080:0x0100) BANK1:INDF 0x0080 INDF (not a physical register) BANK1:OPTION 0x0081 OPTION REGISTER BANK1:OPTION.RBPU 7 PORTB Pull-up Enable bit BANK1:OPTION.INTEDG 6 Interrupt Edge Select bit BANK1:OPTION.T0CS 5 TMR0 Clock Source Select bit BANK1:OPTION.T0SE 4 TMR0 Source Edge Select bit BANK1:OPTION.PSA 3 Prescaler Assignment bit BANK1:OPTION.PS2 2 Prescaler Rate Select bit 2 BANK1:OPTION.PS1 1 Prescaler Rate Select bit 1 BANK1:OPTION.PS0 0 Prescaler Rate Select bit 0 BANK1:PCL 0x0082 Program Counter's (PC) Least Significant Byte BANK1:STATUS 0x0083 STATUS REGISTER BANK1:STATUS.RP0 5 Register Bank Select bit 0 BANK1:STATUS.TO 4 Time-out bit BANK1:STATUS.PD 3 Power-down bit BANK1:STATUS.Z 2 Zero bit BANK1:STATUS.DC 1 Digit carry/borrow bit BANK1:STATUS.C 0 Carry/borrow bit BANK1:FSR 0x0084 Indirect data memory address pointer BANK1:TRISA 0x0085 PORTA Data Direction Register BANK1:TRISA.TRISA4 4 PORTA Data Direction Register bit 4 BANK1:TRISA.TRISA3 3 PORTA Data Direction Register bit 3 BANK1:TRISA.TRISA2 2 PORTA Data Direction Register bit 2 BANK1:TRISA.TRISA1 1 PORTA Data Direction Register bit 1 BANK1:TRISA.TRISA0 0 PORTA Data Direction Register bit 0 BANK1:TRISB 0x0086 PORTB Data Direction Register BANK1:TRISB.TRISB7 7 PORTB Data Direction Register bit 7 BANK1:TRISB.TRISB6 6 PORTB Data Direction Register bit 6 BANK1:TRISB.TRISB5 5 PORTB Data Direction Register bit 5 BANK1:TRISB.TRISB4 4 PORTB Data Direction Register bit 4 BANK1:TRISB.TRISB3 3 PORTB Data Direction Register bit 3 BANK1:TRISB.TRISB2 2 PORTB Data Direction Register bit 2 BANK1:TRISB.TRISB1 1 PORTB Data Direction Register bit 1 BANK1:TRISB.TRISB0 0 PORTB Data Direction Register bit 0 BANK1:RESERVED0087 0x0087 RESERVED BANK1:RESERVED0088 0x0088 RESERVED BANK1:RESERVED0089 0x0089 RESERVED BANK1:PCLATH 0x008A Write Buffer for the upper 5 bits of Program Counter BANK1:INTCON 0x008B INTCON REGISTER BANK1:INTCON.GIE 7 Global Interrupt Enable bit BANK1:INTCON.PEIE 6 Peripheral Interrupt Enable bit BANK1:INTCON.T0IE 5 TMR0 Overflow Interrupt Enable bit BANK1:INTCON.INTE 4 RB0/INT External Interrupt Enable bit BANK1:INTCON.RBIE 3 RB Port Change Interrupt Enable bit BANK1:INTCON.T0IF 2 TMR0 Overflow Interrupt Flag bit BANK1:INTCON.INTF 1 RB0/INT External Interrupt Flag bit BANK1:INTCON.RBIF 0 RB Port Change Interrupt Flag bit BANK1:PIE1 0x008C PIE1 REGISTER BANK1:PIE1.CMIE 6 Comparator Interrupt Enable bit BANK1:RESERVED008D 0x008D RESERVED BANK1:PCON 0x008E PCON REGISTER BANK1:PCON.POR 1 Power-on Reset Status bit BANK1:PCON.BOR 0 Brown-out Reset Status bit BANK1:RESERVED008F 0x008F RESERVED BANK1:RESERVED0090 0x0090 RESERVED BANK1:RESERVED0091 0x0091 RESERVED BANK1:RESERVED0092 0x0092 RESERVED BANK1:RESERVED0093 0x0093 RESERVED BANK1:RESERVED0094 0x0094 RESERVED BANK1:RESERVED0095 0x0095 RESERVED BANK1:RESERVED0096 0x0096 RESERVED BANK1:RESERVED0097 0x0097 RESERVED BANK1:RESERVED0098 0x0098 RESERVED BANK1:RESERVED0099 0x0099 RESERVED BANK1:RESERVED009A 0x009A RESERVED BANK1:RESERVED009B 0x009B RESERVED BANK1:RESERVED009C 0x009C RESERVED BANK1:RESERVED009D 0x009D RESERVED BANK1:RESERVED009E 0x009E RESERVED BANK1:VRCON 0x009F VRCON REGISTER BANK1:VRCON.VREN 7 VREF Enable BANK1:VRCON.VROE 6 VREF Output Enable BANK1:VRCON.VRR 5 VREF Range selection BANK1:VRCON.VR3 3 VREF value selection 3 BANK1:VRCON.VR2 2 VREF value selection 2 BANK1:VRCON.VR1 1 VREF value selection 1 BANK1:VRCON.VR0 0 VREF value selection 0 .16C621A ; http://www.microchip.com/download/lit/pline/picmicro/families/16c62x/30235h.pdf ; PIC16C62X.pdf ; MEMORY MAP ; BANK_0 area DATA FSR_ 0x0000:0x0020 area DATA Gen_Purp1 0x0020:0x0070 General Purpose Register area DATA Gen_Purp2 0x0070:0x0080 General Purpose Register area DATA MEM_Program 0x0080:0x0400 On-chip Program Memory ; BANK_1 ; area DATA FSR_ 0x0080:0x00A0 ; area BSS RESERVED 0x00A0:0x00F0 ; area DATA Gen_Purp_BANK0 0x00F0:0x0100 Accesses 70h-7Fh ; area DATA MEM_Program 0x0100:0x0400 On-chip Program Memory ; Interrupt and reset vector assignments interrupt RESET 0x0000 RESET ; INPUT/OUTPUT PORTS ; BANK0 (0x0000:0x0080) BANK0:INDF 0x0000 INDF (not a physical register) BANK0:TMR0 0x0001 Timer0 module's register BANK0:PCL 0x0002 Program Counter's (PC) Least Significant Byte BANK0:STATUS 0x0003 STATUS REGISTER BANK0:STATUS.RP0 5 Register Bank Select bit 0 BANK0:STATUS.TO 4 Time-out bit BANK0:STATUS.PD 3 Power-down bit BANK0:STATUS.Z 2 Zero bit BANK0:STATUS.DC 1 Digit carry/borrow bit BANK0:STATUS.C 0 Carry/borrow bit BANK0:FSR 0x0004 Indirect data memory address pointer BANK0:PORTA 0x0005 PORTA REGISTER BANK0:PORTA.RA4 4 PORTA bit 4 BANK0:PORTA.RA3 3 PORTA bit 3 BANK0:PORTA.RA2 2 PORTA bit 2 BANK0:PORTA.RA1 1 PORTA bit 1 BANK0:PORTA.RA0 0 PORTA bit 0 BANK0:PORTB 0x0006 PORTB REGISTER BANK0:PORTB.RB7 7 PORTB bit 7 BANK0:PORTB.RB6 6 PORTB bit 6 BANK0:PORTB.RB5 5 PORTB bit 5 BANK0:PORTB.RB4 4 PORTB bit 4 BANK0:PORTB.RB3 3 PORTB bit 3 BANK0:PORTB.RB2 2 PORTB bit 2 BANK0:PORTB.RB1 1 PORTB bit 1 BANK0:PORTB.RB0 0 PORTB bit 0 BANK0:RESERVED0007 0x0007 RESERVED BANK0:RESERVED0008 0x0008 RESERVED BANK0:RESERVED0009 0x0009 RESERVED BANK0:PCLATH 0x000A Write Buffer for the upper 5 bits of the Program Counter BANK0:INTCON 0x000B INTCON REGISTER BANK0:INTCON.GIE 7 Global Interrupt Enable bit BANK0:INTCON.PEIE 6 Peripheral Interrupt Enable bit BANK0:INTCON.T0IE 5 TMR0 Overflow Interrupt Enable bit BANK0:INTCON.INTE 4 RB0/INT External Interrupt Enable bit BANK0:INTCON.RBIE 3 RB Port Change Interrupt Enable bit BANK0:INTCON.T0IF 2 TMR0 Overflow Interrupt Flag bit BANK0:INTCON.INTF 1 RB0/INT External Interrupt Flag bit BANK0:INTCON.RBIF 0 RB Port Change Interrupt Flag bit BANK0:PIR1 0x000C PIR1 REGISTER BANK0:PIR1.CMIF 6 Comparator Interrupt Flag bit BANK0:RESERVED000D 0x000D RESERVED BANK0:RESERVED000E 0x000E RESERVED BANK0:RESERVED000F 0x000F RESERVED BANK0:RESERVED0010 0x0010 RESERVED BANK0:RESERVED0011 0x0011 RESERVED BANK0:RESERVED0012 0x0012 RESERVED BANK0:RESERVED0013 0x0013 RESERVED BANK0:RESERVED0014 0x0014 RESERVED BANK0:RESERVED0015 0x0015 RESERVED BANK0:RESERVED0016 0x0016 RESERVED BANK0:RESERVED0017 0x0017 RESERVED BANK0:RESERVED0018 0x0018 RESERVED BANK0:RESERVED0019 0x0019 RESERVED BANK0:RESERVED001A 0x001A RESERVED BANK0:RESERVED001B 0x001B RESERVED BANK0:RESERVED001C 0x001C RESERVED BANK0:RESERVED001D 0x001D RESERVED BANK0:RESERVED001E 0x001E RESERVED BANK0:CMCON 0x001F CMCON REGISTER BANK0:CMCON.C2OUT 7 Comparator 2 output BANK0:CMCON.C1OUT 6 Comparator 1 output BANK0:CMCON.CIS 3 Comparator Input Switch BANK0:CMCON.CM2 2 Comparator mode 2 BANK0:CMCON.CM1 1 Comparator mode 1 BANK0:CMCON.CM0 0 Comparator mode 0 ; BANK1 (0x0080:0x0100) BANK1:INDF 0x0080 INDF (not a physical register) BANK1:OPTION 0x0081 OPTION REGISTER BANK1:OPTION.RBPU 7 PORTB Pull-up Enable bit BANK1:OPTION.INTEDG 6 Interrupt Edge Select bit BANK1:OPTION.T0CS 5 TMR0 Clock Source Select bit BANK1:OPTION.T0SE 4 TMR0 Source Edge Select bit BANK1:OPTION.PSA 3 Prescaler Assignment bit BANK1:OPTION.PS2 2 Prescaler Rate Select bit 2 BANK1:OPTION.PS1 1 Prescaler Rate Select bit 1 BANK1:OPTION.PS0 0 Prescaler Rate Select bit 0 BANK1:PCL 0x0082 Program Counter's (PC) Least Significant Byte BANK1:STATUS 0x0083 STATUS REGISTER BANK1:STATUS.RP0 5 Register Bank Select bit 0 BANK1:STATUS.TO 4 Time-out bit BANK1:STATUS.PD 3 Power-down bit BANK1:STATUS.Z 2 Zero bit BANK1:STATUS.DC 1 Digit carry/borrow bit BANK1:STATUS.C 0 Carry/borrow bit BANK1:FSR 0x0084 Indirect data memory address pointer BANK1:TRISA 0x0085 PORTA Data Direction Register BANK1:TRISA.TRISA4 4 PORTA Data Direction Register bit 4 BANK1:TRISA.TRISA3 3 PORTA Data Direction Register bit 3 BANK1:TRISA.TRISA2 2 PORTA Data Direction Register bit 2 BANK1:TRISA.TRISA1 1 PORTA Data Direction Register bit 1 BANK1:TRISA.TRISA0 0 PORTA Data Direction Register bit 0 BANK1:TRISB 0x0086 PORTB Data Direction Register BANK1:TRISB.TRISB7 7 PORTB Data Direction Register bit 7 BANK1:TRISB.TRISB6 6 PORTB Data Direction Register bit 6 BANK1:TRISB.TRISB5 5 PORTB Data Direction Register bit 5 BANK1:TRISB.TRISB4 4 PORTB Data Direction Register bit 4 BANK1:TRISB.TRISB3 3 PORTB Data Direction Register bit 3 BANK1:TRISB.TRISB2 2 PORTB Data Direction Register bit 2 BANK1:TRISB.TRISB1 1 PORTB Data Direction Register bit 1 BANK1:TRISB.TRISB0 0 PORTB Data Direction Register bit 0 BANK1:RESERVED0087 0x0087 RESERVED BANK1:RESERVED0088 0x0088 RESERVED BANK1:RESERVED0089 0x0089 RESERVED BANK1:PCLATH 0x008A Write Buffer for the upper 5 bits of Program Counter BANK1:INTCON 0x008B INTCON REGISTER BANK1:INTCON.GIE 7 Global Interrupt Enable bit BANK1:INTCON.PEIE 6 Peripheral Interrupt Enable bit BANK1:INTCON.T0IE 5 TMR0 Overflow Interrupt Enable bit BANK1:INTCON.INTE 4 RB0/INT External Interrupt Enable bit BANK1:INTCON.RBIE 3 RB Port Change Interrupt Enable bit BANK1:INTCON.T0IF 2 TMR0 Overflow Interrupt Flag bit BANK1:INTCON.INTF 1 RB0/INT External Interrupt Flag bit BANK1:INTCON.RBIF 0 RB Port Change Interrupt Flag bit BANK1:PIE1 0x008C PIE1 REGISTER BANK1:PIE1.CMIE 6 Comparator Interrupt Enable bit BANK1:RESERVED008D 0x008D RESERVED BANK1:PCON 0x008E PCON REGISTER BANK1:PCON.POR 1 Power-on Reset Status bit BANK1:PCON.BOR 0 Brown-out Reset Status bit BANK1:RESERVED008F 0x008F RESERVED BANK1:RESERVED0090 0x0090 RESERVED BANK1:RESERVED0091 0x0091 RESERVED BANK1:RESERVED0092 0x0092 RESERVED BANK1:RESERVED0093 0x0093 RESERVED BANK1:RESERVED0094 0x0094 RESERVED BANK1:RESERVED0095 0x0095 RESERVED BANK1:RESERVED0096 0x0096 RESERVED BANK1:RESERVED0097 0x0097 RESERVED BANK1:RESERVED0098 0x0098 RESERVED BANK1:RESERVED0099 0x0099 RESERVED BANK1:RESERVED009A 0x009A RESERVED BANK1:RESERVED009B 0x009B RESERVED BANK1:RESERVED009C 0x009C RESERVED BANK1:RESERVED009D 0x009D RESERVED BANK1:RESERVED009E 0x009E RESERVED BANK1:VRCON 0x009F VRCON REGISTER BANK1:VRCON.VREN 7 VREF Enable BANK1:VRCON.VROE 6 VREF Output Enable BANK1:VRCON.VRR 5 VREF Range selection BANK1:VRCON.VR3 3 VREF value selection 3 BANK1:VRCON.VR2 2 VREF value selection 2 BANK1:VRCON.VR1 1 VREF value selection 1 BANK1:VRCON.VR0 0 VREF value selection 0 .16C622 ; http://www.microchip.com/download/lit/pline/picmicro/families/16c62x/30235h.pdf ; PIC16C62X.pdf ; MEMORY MAP ; BANK_0 area DATA FSR_ 0x0000:0x0020 area DATA Gen_Purp 0x0020:0x0080 General Purpose Register area DATA MEM_Program 0x0080:0x0800 On-chip Program Memory ; BANK_1 ; area DATA FSR_ 0x0080:0x00A0 ; area DATA Gen_Purp 0x00A0:0x00C0 General Purpose Register ; area BSS RESERVED 0x00C0:0x0100 ; area DATA MEM_Program 0x0100:0x0800 On-chip Program Memory ; Interrupt and reset vector assignments interrupt RESET 0x0000 RESET ; INPUT/OUTPUT PORTS ; BANK0 (0x0000:0x0080) BANK0:INDF 0x0000 INDF (not a physical register) BANK0:TMR0 0x0001 Timer0 module's register BANK0:PCL 0x0002 Program Counter's (PC) Least Significant Byte BANK0:STATUS 0x0003 STATUS REGISTER BANK0:STATUS.RP0 5 Register Bank Select bit 0 BANK0:STATUS.TO 4 Time-out bit BANK0:STATUS.PD 3 Power-down bit BANK0:STATUS.Z 2 Zero bit BANK0:STATUS.DC 1 Digit carry/borrow bit BANK0:STATUS.C 0 Carry/borrow bit BANK0:FSR 0x0004 Indirect data memory address pointer BANK0:PORTA 0x0005 PORTA REGISTER BANK0:PORTA.RA4 4 PORTA bit 4 BANK0:PORTA.RA3 3 PORTA bit 3 BANK0:PORTA.RA2 2 PORTA bit 2 BANK0:PORTA.RA1 1 PORTA bit 1 BANK0:PORTA.RA0 0 PORTA bit 0 BANK0:PORTB 0x0006 PORTB REGISTER BANK0:PORTB.RB7 7 PORTB bit 7 BANK0:PORTB.RB6 6 PORTB bit 6 BANK0:PORTB.RB5 5 PORTB bit 5 BANK0:PORTB.RB4 4 PORTB bit 4 BANK0:PORTB.RB3 3 PORTB bit 3 BANK0:PORTB.RB2 2 PORTB bit 2 BANK0:PORTB.RB1 1 PORTB bit 1 BANK0:PORTB.RB0 0 PORTB bit 0 BANK0:RESERVED0007 0x0007 RESERVED BANK0:RESERVED0008 0x0008 RESERVED BANK0:RESERVED0009 0x0009 RESERVED BANK0:PCLATH 0x000A Write Buffer for the upper 5 bits of the Program Counter BANK0:INTCON 0x000B INTCON REGISTER BANK0:INTCON.GIE 7 Global Interrupt Enable bit BANK0:INTCON.PEIE 6 Peripheral Interrupt Enable bit BANK0:INTCON.T0IE 5 TMR0 Overflow Interrupt Enable bit BANK0:INTCON.INTE 4 RB0/INT External Interrupt Enable bit BANK0:INTCON.RBIE 3 RB Port Change Interrupt Enable bit BANK0:INTCON.T0IF 2 TMR0 Overflow Interrupt Flag bit BANK0:INTCON.INTF 1 RB0/INT External Interrupt Flag bit BANK0:INTCON.RBIF 0 RB Port Change Interrupt Flag bit BANK0:PIR1 0x000C PIR1 REGISTER BANK0:PIR1.CMIF 6 Comparator Interrupt Flag bit BANK0:RESERVED000D 0x000D RESERVED BANK0:RESERVED000E 0x000E RESERVED BANK0:RESERVED000F 0x000F RESERVED BANK0:RESERVED0010 0x0010 RESERVED BANK0:RESERVED0011 0x0011 RESERVED BANK0:RESERVED0012 0x0012 RESERVED BANK0:RESERVED0013 0x0013 RESERVED BANK0:RESERVED0014 0x0014 RESERVED BANK0:RESERVED0015 0x0015 RESERVED BANK0:RESERVED0016 0x0016 RESERVED BANK0:RESERVED0017 0x0017 RESERVED BANK0:RESERVED0018 0x0018 RESERVED BANK0:RESERVED0019 0x0019 RESERVED BANK0:RESERVED001A 0x001A RESERVED BANK0:RESERVED001B 0x001B RESERVED BANK0:RESERVED001C 0x001C RESERVED BANK0:RESERVED001D 0x001D RESERVED BANK0:RESERVED001E 0x001E RESERVED BANK0:CMCON 0x001F CMCON REGISTER BANK0:CMCON.C2OUT 7 Comparator 2 output BANK0:CMCON.C1OUT 6 Comparator 1 output BANK0:CMCON.CIS 3 Comparator Input Switch BANK0:CMCON.CM2 2 Comparator mode 2 BANK0:CMCON.CM1 1 Comparator mode 1 BANK0:CMCON.CM0 0 Comparator mode 0 ; BANK1 (0x0080:0x0100) BANK1:INDF 0x0080 INDF (not a physical register) BANK1:OPTION 0x0081 OPTION REGISTER BANK1:OPTION.RBPU 7 PORTB Pull-up Enable bit BANK1:OPTION.INTEDG 6 Interrupt Edge Select bit BANK1:OPTION.T0CS 5 TMR0 Clock Source Select bit BANK1:OPTION.T0SE 4 TMR0 Source Edge Select bit BANK1:OPTION.PSA 3 Prescaler Assignment bit BANK1:OPTION.PS2 2 Prescaler Rate Select bit 2 BANK1:OPTION.PS1 1 Prescaler Rate Select bit 1 BANK1:OPTION.PS0 0 Prescaler Rate Select bit 0 BANK1:PCL 0x0082 Program Counter's (PC) Least Significant Byte BANK1:STATUS 0x0083 STATUS REGISTER BANK1:STATUS.RP0 5 Register Bank Select bit 0 BANK1:STATUS.TO 4 Time-out bit BANK1:STATUS.PD 3 Power-down bit BANK1:STATUS.Z 2 Zero bit BANK1:STATUS.DC 1 Digit carry/borrow bit BANK1:STATUS.C 0 Carry/borrow bit BANK1:FSR 0x0084 Indirect data memory address pointer BANK1:TRISA 0x0085 PORTA Data Direction Register BANK1:TRISA.TRISA4 4 PORTA Data Direction Register bit 4 BANK1:TRISA.TRISA3 3 PORTA Data Direction Register bit 3 BANK1:TRISA.TRISA2 2 PORTA Data Direction Register bit 2 BANK1:TRISA.TRISA1 1 PORTA Data Direction Register bit 1 BANK1:TRISA.TRISA0 0 PORTA Data Direction Register bit 0 BANK1:TRISB 0x0086 PORTB Data Direction Register BANK1:TRISB.TRISB7 7 PORTB Data Direction Register bit 7 BANK1:TRISB.TRISB6 6 PORTB Data Direction Register bit 6 BANK1:TRISB.TRISB5 5 PORTB Data Direction Register bit 5 BANK1:TRISB.TRISB4 4 PORTB Data Direction Register bit 4 BANK1:TRISB.TRISB3 3 PORTB Data Direction Register bit 3 BANK1:TRISB.TRISB2 2 PORTB Data Direction Register bit 2 BANK1:TRISB.TRISB1 1 PORTB Data Direction Register bit 1 BANK1:TRISB.TRISB0 0 PORTB Data Direction Register bit 0 BANK1:RESERVED0087 0x0087 RESERVED BANK1:RESERVED0088 0x0088 RESERVED BANK1:RESERVED0089 0x0089 RESERVED BANK1:PCLATH 0x008A Write Buffer for the upper 5 bits of Program Counter BANK1:INTCON 0x008B INTCON REGISTER BANK1:INTCON.GIE 7 Global Interrupt Enable bit BANK1:INTCON.PEIE 6 Peripheral Interrupt Enable bit BANK1:INTCON.T0IE 5 TMR0 Overflow Interrupt Enable bit BANK1:INTCON.INTE 4 RB0/INT External Interrupt Enable bit BANK1:INTCON.RBIE 3 RB Port Change Interrupt Enable bit BANK1:INTCON.T0IF 2 TMR0 Overflow Interrupt Flag bit BANK1:INTCON.INTF 1 RB0/INT External Interrupt Flag bit BANK1:INTCON.RBIF 0 RB Port Change Interrupt Flag bit BANK1:PIE1 0x008C PIE1 REGISTER BANK1:PIE1.CMIE 6 Comparator Interrupt Enable bit BANK1:RESERVED008D 0x008D RESERVED BANK1:PCON 0x008E PCON REGISTER BANK1:PCON.POR 1 Power-on Reset Status bit BANK1:PCON.BOR 0 Brown-out Reset Status bit BANK1:RESERVED008F 0x008F RESERVED BANK1:RESERVED0090 0x0090 RESERVED BANK1:RESERVED0091 0x0091 RESERVED BANK1:RESERVED0092 0x0092 RESERVED BANK1:RESERVED0093 0x0093 RESERVED BANK1:RESERVED0094 0x0094 RESERVED BANK1:RESERVED0095 0x0095 RESERVED BANK1:RESERVED0096 0x0096 RESERVED BANK1:RESERVED0097 0x0097 RESERVED BANK1:RESERVED0098 0x0098 RESERVED BANK1:RESERVED0099 0x0099 RESERVED BANK1:RESERVED009A 0x009A RESERVED BANK1:RESERVED009B 0x009B RESERVED BANK1:RESERVED009C 0x009C RESERVED BANK1:RESERVED009D 0x009D RESERVED BANK1:RESERVED009E 0x009E RESERVED BANK1:VRCON 0x009F VRCON REGISTER BANK1:VRCON.VREN 7 VREF Enable BANK1:VRCON.VROE 6 VREF Output Enable BANK1:VRCON.VRR 5 VREF Range selection BANK1:VRCON.VR3 3 VREF value selection 3 BANK1:VRCON.VR2 2 VREF value selection 2 BANK1:VRCON.VR1 1 VREF value selection 1 BANK1:VRCON.VR0 0 VREF value selection 0 .16C622A ; http://www.microchip.com/download/lit/pline/picmicro/families/16c62x/30235h.pdf ; PIC16C62X.pdf ; MEMORY MAP ; BANK_0 area DATA FSR_ 0x0000:0x0020 area DATA Gen_Purp1 0x0020:0x0070 General Purpose Register area DATA Gen_Purp2 0x0070:0x0080 General Purpose Register area DATA MEM_Program 0x0080:0x0800 On-chip Program Memory ; BANK_1 ; area DATA FSR_ 0x0080:0x00A0 ; area DATA Gen_Purp 0x00A0:0x00C0 ; area BSS RESERVED 0x00C0:0x00F0 ; area DATA Gen_Purp_BANK0 0x00F0:0x0100 Accesses 70h-7Fh ; area DATA MEM_Program 0x0100:0x0800 On-chip Program Memory ; Interrupt and reset vector assignments interrupt RESET 0x0000 RESET ; INPUT/OUTPUT PORTS ; BANK0 (0x0000:0x0080) BANK0:INDF 0x0000 INDF (not a physical register) BANK0:TMR0 0x0001 Timer0 module's register BANK0:PCL 0x0002 Program Counter's (PC) Least Significant Byte BANK0:STATUS 0x0003 STATUS REGISTER BANK0:STATUS.RP0 5 Register Bank Select bit 0 BANK0:STATUS.TO 4 Time-out bit BANK0:STATUS.PD 3 Power-down bit BANK0:STATUS.Z 2 Zero bit BANK0:STATUS.DC 1 Digit carry/borrow bit BANK0:STATUS.C 0 Carry/borrow bit BANK0:FSR 0x0004 Indirect data memory address pointer BANK0:PORTA 0x0005 PORTA REGISTER BANK0:PORTA.RA4 4 PORTA bit 4 BANK0:PORTA.RA3 3 PORTA bit 3 BANK0:PORTA.RA2 2 PORTA bit 2 BANK0:PORTA.RA1 1 PORTA bit 1 BANK0:PORTA.RA0 0 PORTA bit 0 BANK0:PORTB 0x0006 PORTB REGISTER BANK0:PORTB.RB7 7 PORTB bit 7 BANK0:PORTB.RB6 6 PORTB bit 6 BANK0:PORTB.RB5 5 PORTB bit 5 BANK0:PORTB.RB4 4 PORTB bit 4 BANK0:PORTB.RB3 3 PORTB bit 3 BANK0:PORTB.RB2 2 PORTB bit 2 BANK0:PORTB.RB1 1 PORTB bit 1 BANK0:PORTB.RB0 0 PORTB bit 0 BANK0:RESERVED0007 0x0007 RESERVED BANK0:RESERVED0008 0x0008 RESERVED BANK0:RESERVED0009 0x0009 RESERVED BANK0:PCLATH 0x000A Write Buffer for the upper 5 bits of the Program Counter BANK0:INTCON 0x000B INTCON REGISTER BANK0:INTCON.GIE 7 Global Interrupt Enable bit BANK0:INTCON.PEIE 6 Peripheral Interrupt Enable bit BANK0:INTCON.T0IE 5 TMR0 Overflow Interrupt Enable bit BANK0:INTCON.INTE 4 RB0/INT External Interrupt Enable bit BANK0:INTCON.RBIE 3 RB Port Change Interrupt Enable bit BANK0:INTCON.T0IF 2 TMR0 Overflow Interrupt Flag bit BANK0:INTCON.INTF 1 RB0/INT External Interrupt Flag bit BANK0:INTCON.RBIF 0 RB Port Change Interrupt Flag bit BANK0:PIR1 0x000C PIR1 REGISTER BANK0:PIR1.CMIF 6 Comparator Interrupt Flag bit BANK0:RESERVED000D 0x000D RESERVED BANK0:RESERVED000E 0x000E RESERVED BANK0:RESERVED000F 0x000F RESERVED BANK0:RESERVED0010 0x0010 RESERVED BANK0:RESERVED0011 0x0011 RESERVED BANK0:RESERVED0012 0x0012 RESERVED BANK0:RESERVED0013 0x0013 RESERVED BANK0:RESERVED0014 0x0014 RESERVED BANK0:RESERVED0015 0x0015 RESERVED BANK0:RESERVED0016 0x0016 RESERVED BANK0:RESERVED0017 0x0017 RESERVED BANK0:RESERVED0018 0x0018 RESERVED BANK0:RESERVED0019 0x0019 RESERVED BANK0:RESERVED001A 0x001A RESERVED BANK0:RESERVED001B 0x001B RESERVED BANK0:RESERVED001C 0x001C RESERVED BANK0:RESERVED001D 0x001D RESERVED BANK0:RESERVED001E 0x001E RESERVED BANK0:CMCON 0x001F CMCON REGISTER BANK0:CMCON.C2OUT 7 Comparator 2 output BANK0:CMCON.C1OUT 6 Comparator 1 output BANK0:CMCON.CIS 3 Comparator Input Switch BANK0:CMCON.CM2 2 Comparator mode 2 BANK0:CMCON.CM1 1 Comparator mode 1 BANK0:CMCON.CM0 0 Comparator mode 0 ; BANK1 (0x0080:0x0100) BANK1:INDF 0x0080 INDF (not a physical register) BANK1:OPTION 0x0081 OPTION REGISTER BANK1:OPTION.RBPU 7 PORTB Pull-up Enable bit BANK1:OPTION.INTEDG 6 Interrupt Edge Select bit BANK1:OPTION.T0CS 5 TMR0 Clock Source Select bit BANK1:OPTION.T0SE 4 TMR0 Source Edge Select bit BANK1:OPTION.PSA 3 Prescaler Assignment bit BANK1:OPTION.PS2 2 Prescaler Rate Select bit 2 BANK1:OPTION.PS1 1 Prescaler Rate Select bit 1 BANK1:OPTION.PS0 0 Prescaler Rate Select bit 0 BANK1:PCL 0x0082 Program Counter's (PC) Least Significant Byte BANK1:STATUS 0x0083 STATUS REGISTER BANK1:STATUS.RP0 5 Register Bank Select bit 0 BANK1:STATUS.TO 4 Time-out bit BANK1:STATUS.PD 3 Power-down bit BANK1:STATUS.Z 2 Zero bit BANK1:STATUS.DC 1 Digit carry/borrow bit BANK1:STATUS.C 0 Carry/borrow bit BANK1:FSR 0x0084 Indirect data memory address pointer BANK1:TRISA 0x0085 PORTA Data Direction Register BANK1:TRISA.TRISA4 4 PORTA Data Direction Register bit 4 BANK1:TRISA.TRISA3 3 PORTA Data Direction Register bit 3 BANK1:TRISA.TRISA2 2 PORTA Data Direction Register bit 2 BANK1:TRISA.TRISA1 1 PORTA Data Direction Register bit 1 BANK1:TRISA.TRISA0 0 PORTA Data Direction Register bit 0 BANK1:TRISB 0x0086 PORTB Data Direction Register BANK1:TRISB.TRISB7 7 PORTB Data Direction Register bit 7 BANK1:TRISB.TRISB6 6 PORTB Data Direction Register bit 6 BANK1:TRISB.TRISB5 5 PORTB Data Direction Register bit 5 BANK1:TRISB.TRISB4 4 PORTB Data Direction Register bit 4 BANK1:TRISB.TRISB3 3 PORTB Data Direction Register bit 3 BANK1:TRISB.TRISB2 2 PORTB Data Direction Register bit 2 BANK1:TRISB.TRISB1 1 PORTB Data Direction Register bit 1 BANK1:TRISB.TRISB0 0 PORTB Data Direction Register bit 0 BANK1:RESERVED0087 0x0087 RESERVED BANK1:RESERVED0088 0x0088 RESERVED BANK1:RESERVED0089 0x0089 RESERVED BANK1:PCLATH 0x008A Write Buffer for the upper 5 bits of Program Counter BANK1:INTCON 0x008B INTCON REGISTER BANK1:INTCON.GIE 7 Global Interrupt Enable bit BANK1:INTCON.PEIE 6 Peripheral Interrupt Enable bit BANK1:INTCON.T0IE 5 TMR0 Overflow Interrupt Enable bit BANK1:INTCON.INTE 4 RB0/INT External Interrupt Enable bit BANK1:INTCON.RBIE 3 RB Port Change Interrupt Enable bit BANK1:INTCON.T0IF 2 TMR0 Overflow Interrupt Flag bit BANK1:INTCON.INTF 1 RB0/INT External Interrupt Flag bit BANK1:INTCON.RBIF 0 RB Port Change Interrupt Flag bit BANK1:PIE1 0x008C PIE1 REGISTER BANK1:PIE1.CMIE 6 Comparator Interrupt Enable bit BANK1:RESERVED008D 0x008D RESERVED BANK1:PCON 0x008E PCON REGISTER BANK1:PCON.POR 1 Power-on Reset Status bit BANK1:PCON.BOR 0 Brown-out Reset Status bit BANK1:RESERVED008F 0x008F RESERVED BANK1:RESERVED0090 0x0090 RESERVED BANK1:RESERVED0091 0x0091 RESERVED BANK1:RESERVED0092 0x0092 RESERVED BANK1:RESERVED0093 0x0093 RESERVED BANK1:RESERVED0094 0x0094 RESERVED BANK1:RESERVED0095 0x0095 RESERVED BANK1:RESERVED0096 0x0096 RESERVED BANK1:RESERVED0097 0x0097 RESERVED BANK1:RESERVED0098 0x0098 RESERVED BANK1:RESERVED0099 0x0099 RESERVED BANK1:RESERVED009A 0x009A RESERVED BANK1:RESERVED009B 0x009B RESERVED BANK1:RESERVED009C 0x009C RESERVED BANK1:RESERVED009D 0x009D RESERVED BANK1:RESERVED009E 0x009E RESERVED BANK1:VRCON 0x009F VRCON REGISTER BANK1:VRCON.VREN 7 VREF Enable BANK1:VRCON.VROE 6 VREF Output Enable BANK1:VRCON.VRR 5 VREF Range selection BANK1:VRCON.VR3 3 VREF value selection 3 BANK1:VRCON.VR2 2 VREF value selection 2 BANK1:VRCON.VR1 1 VREF value selection 1 BANK1:VRCON.VR0 0 VREF value selection 0 .16CR620A ; http://www.microchip.com/download/lit/pline/picmicro/families/16c62x/30235h.pdf ; PIC16C62X.pdf ; MEMORY MAP ; BANK_0 area DATA FSR_ 0x0000:0x0020 area DATA Gen_Purp1 0x0020:0x0070 General Purpose Register area DATA Gen_Purp2 0x0070:0x0080 General Purpose Register area DATA MEM_Program 0x0080:0x0200 On-chip Program Memory ; BANK_1 ; area DATA FSR_ 0x0080:0x00A0 ; area BSS RESERVED 0x00A0:0x00F0 ; area DATA Gen_Purp_BANK0 0x00F0:0x0100 Accesses 70h-7Fh ; area DATA MEM_Program 0x0100:0x0200 On-chip Program Memory ; Interrupt and reset vector assignments interrupt RESET 0x0000 RESET ; INPUT/OUTPUT PORTS ; BANK0 (0x0000:0x0080) BANK0:INDF 0x0000 INDF (not a physical register) BANK0:TMR0 0x0001 Timer0 module's register BANK0:PCL 0x0002 Program Counter's (PC) Least Significant Byte BANK0:STATUS 0x0003 STATUS REGISTER BANK0:STATUS.RP0 5 Register Bank Select bit 0 BANK0:STATUS.TO 4 Time-out bit BANK0:STATUS.PD 3 Power-down bit BANK0:STATUS.Z 2 Zero bit BANK0:STATUS.DC 1 Digit carry/borrow bit BANK0:STATUS.C 0 Carry/borrow bit BANK0:FSR 0x0004 Indirect data memory address pointer BANK0:PORTA 0x0005 PORTA REGISTER BANK0:PORTA.RA4 4 PORTA bit 4 BANK0:PORTA.RA3 3 PORTA bit 3 BANK0:PORTA.RA2 2 PORTA bit 2 BANK0:PORTA.RA1 1 PORTA bit 1 BANK0:PORTA.RA0 0 PORTA bit 0 BANK0:PORTB 0x0006 PORTB REGISTER BANK0:PORTB.RB7 7 PORTB bit 7 BANK0:PORTB.RB6 6 PORTB bit 6 BANK0:PORTB.RB5 5 PORTB bit 5 BANK0:PORTB.RB4 4 PORTB bit 4 BANK0:PORTB.RB3 3 PORTB bit 3 BANK0:PORTB.RB2 2 PORTB bit 2 BANK0:PORTB.RB1 1 PORTB bit 1 BANK0:PORTB.RB0 0 PORTB bit 0 BANK0:RESERVED0007 0x0007 RESERVED BANK0:RESERVED0008 0x0008 RESERVED BANK0:RESERVED0009 0x0009 RESERVED BANK0:PCLATH 0x000A Write Buffer for the upper 5 bits of the Program Counter BANK0:INTCON 0x000B INTCON REGISTER BANK0:INTCON.GIE 7 Global Interrupt Enable bit BANK0:INTCON.PEIE 6 Peripheral Interrupt Enable bit BANK0:INTCON.T0IE 5 TMR0 Overflow Interrupt Enable bit BANK0:INTCON.INTE 4 RB0/INT External Interrupt Enable bit BANK0:INTCON.RBIE 3 RB Port Change Interrupt Enable bit BANK0:INTCON.T0IF 2 TMR0 Overflow Interrupt Flag bit BANK0:INTCON.INTF 1 RB0/INT External Interrupt Flag bit BANK0:INTCON.RBIF 0 RB Port Change Interrupt Flag bit BANK0:PIR1 0x000C PIR1 REGISTER BANK0:PIR1.CMIF 6 Comparator Interrupt Flag bit BANK0:RESERVED000D 0x000D RESERVED BANK0:RESERVED000E 0x000E RESERVED BANK0:RESERVED000F 0x000F RESERVED BANK0:RESERVED0010 0x0010 RESERVED BANK0:RESERVED0011 0x0011 RESERVED BANK0:RESERVED0012 0x0012 RESERVED BANK0:RESERVED0013 0x0013 RESERVED BANK0:RESERVED0014 0x0014 RESERVED BANK0:RESERVED0015 0x0015 RESERVED BANK0:RESERVED0016 0x0016 RESERVED BANK0:RESERVED0017 0x0017 RESERVED BANK0:RESERVED0018 0x0018 RESERVED BANK0:RESERVED0019 0x0019 RESERVED BANK0:RESERVED001A 0x001A RESERVED BANK0:RESERVED001B 0x001B RESERVED BANK0:RESERVED001C 0x001C RESERVED BANK0:RESERVED001D 0x001D RESERVED BANK0:RESERVED001E 0x001E RESERVED BANK0:CMCON 0x001F CMCON REGISTER BANK0:CMCON.C2OUT 7 Comparator 2 output BANK0:CMCON.C1OUT 6 Comparator 1 output BANK0:CMCON.CIS 3 Comparator Input Switch BANK0:CMCON.CM2 2 Comparator mode 2 BANK0:CMCON.CM1 1 Comparator mode 1 BANK0:CMCON.CM0 0 Comparator mode 0 ; BANK1 (0x0080:0x0100) BANK1:INDF 0x0080 INDF (not a physical register) BANK1:OPTION 0x0081 OPTION REGISTER BANK1:OPTION.RBPU 7 PORTB Pull-up Enable bit BANK1:OPTION.INTEDG 6 Interrupt Edge Select bit BANK1:OPTION.T0CS 5 TMR0 Clock Source Select bit BANK1:OPTION.T0SE 4 TMR0 Source Edge Select bit BANK1:OPTION.PSA 3 Prescaler Assignment bit BANK1:OPTION.PS2 2 Prescaler Rate Select bit 2 BANK1:OPTION.PS1 1 Prescaler Rate Select bit 1 BANK1:OPTION.PS0 0 Prescaler Rate Select bit 0 BANK1:PCL 0x0082 Program Counter's (PC) Least Significant Byte BANK1:STATUS 0x0083 STATUS REGISTER BANK1:STATUS.RP0 5 Register Bank Select bit 0 BANK1:STATUS.TO 4 Time-out bit BANK1:STATUS.PD 3 Power-down bit BANK1:STATUS.Z 2 Zero bit BANK1:STATUS.DC 1 Digit carry/borrow bit BANK1:STATUS.C 0 Carry/borrow bit BANK1:FSR 0x0084 Indirect data memory address pointer BANK1:TRISA 0x0085 PORTA Data Direction Register BANK1:TRISA.TRISA4 4 PORTA Data Direction Register bit 4 BANK1:TRISA.TRISA3 3 PORTA Data Direction Register bit 3 BANK1:TRISA.TRISA2 2 PORTA Data Direction Register bit 2 BANK1:TRISA.TRISA1 1 PORTA Data Direction Register bit 1 BANK1:TRISA.TRISA0 0 PORTA Data Direction Register bit 0 BANK1:TRISB 0x0086 PORTB Data Direction Register BANK1:TRISB.TRISB7 7 PORTB Data Direction Register bit 7 BANK1:TRISB.TRISB6 6 PORTB Data Direction Register bit 6 BANK1:TRISB.TRISB5 5 PORTB Data Direction Register bit 5 BANK1:TRISB.TRISB4 4 PORTB Data Direction Register bit 4 BANK1:TRISB.TRISB3 3 PORTB Data Direction Register bit 3 BANK1:TRISB.TRISB2 2 PORTB Data Direction Register bit 2 BANK1:TRISB.TRISB1 1 PORTB Data Direction Register bit 1 BANK1:TRISB.TRISB0 0 PORTB Data Direction Register bit 0 BANK1:RESERVED0087 0x0087 RESERVED BANK1:RESERVED0088 0x0088 RESERVED BANK1:RESERVED0089 0x0089 RESERVED BANK1:PCLATH 0x008A Write Buffer for the upper 5 bits of Program Counter BANK1:INTCON 0x008B INTCON REGISTER BANK1:INTCON.GIE 7 Global Interrupt Enable bit BANK1:INTCON.PEIE 6 Peripheral Interrupt Enable bit BANK1:INTCON.T0IE 5 TMR0 Overflow Interrupt Enable bit BANK1:INTCON.INTE 4 RB0/INT External Interrupt Enable bit BANK1:INTCON.RBIE 3 RB Port Change Interrupt Enable bit BANK1:INTCON.T0IF 2 TMR0 Overflow Interrupt Flag bit BANK1:INTCON.INTF 1 RB0/INT External Interrupt Flag bit BANK1:INTCON.RBIF 0 RB Port Change Interrupt Flag bit BANK1:PIE1 0x008C PIE1 REGISTER BANK1:PIE1.CMIE 6 Comparator Interrupt Enable bit BANK1:RESERVED008D 0x008D RESERVED BANK1:PCON 0x008E PCON REGISTER BANK1:PCON.POR 1 Power-on Reset Status bit BANK1:PCON.BOR 0 Brown-out Reset Status bit BANK1:RESERVED008F 0x008F RESERVED BANK1:RESERVED0090 0x0090 RESERVED BANK1:RESERVED0091 0x0091 RESERVED BANK1:RESERVED0092 0x0092 RESERVED BANK1:RESERVED0093 0x0093 RESERVED BANK1:RESERVED0094 0x0094 RESERVED BANK1:RESERVED0095 0x0095 RESERVED BANK1:RESERVED0096 0x0096 RESERVED BANK1:RESERVED0097 0x0097 RESERVED BANK1:RESERVED0098 0x0098 RESERVED BANK1:RESERVED0099 0x0099 RESERVED BANK1:RESERVED009A 0x009A RESERVED BANK1:RESERVED009B 0x009B RESERVED BANK1:RESERVED009C 0x009C RESERVED BANK1:RESERVED009D 0x009D RESERVED BANK1:RESERVED009E 0x009E RESERVED BANK1:VRCON 0x009F VRCON REGISTER BANK1:VRCON.VREN 7 VREF Enable BANK1:VRCON.VROE 6 VREF Output Enable BANK1:VRCON.VRR 5 VREF Range selection BANK1:VRCON.VR3 3 VREF value selection 3 BANK1:VRCON.VR2 2 VREF value selection 2 BANK1:VRCON.VR1 1 VREF value selection 1 BANK1:VRCON.VR0 0 VREF value selection 0 .16C63A ; http://www.microchip.com/download/lit/pline/picmicro/families/16c7x/30605c.pdf ; 16C63A65B_73B74B.pdf ; MEMORY MAP ; BANK_0 area DATA FSR_ 0x0000:0x0020 area DATA Gen_Purp 0x0020:0x0080 General Purpose Register area DATA MEM_Program0 0x0080:0x0800 On-chip Program Memory (Page 0) area DATA MEM_Program1 0x0800:0x1000 On-chip Program Memory (Page 1) ; BANK_1 ; area DATA FSR_ 0x0080:0x00A0 ; area DATA Gen_Purp 0x00A0:0x0100 General Purpose Register ; area DATA MEM_Program0 0x0100:0x0800 On-chip Program Memory (Page 0) ; area DATA MEM_Program1 0x0800:0x1000 On-chip Program Memory (Page 1) ; Interrupt and reset vector assignments interrupt RESET 0x0000 RESET ; INPUT/OUTPUT PORTS ; BANK0 (0x0000:0x0080) BANK0:INDF 0x0000 INDF (not a physical register) BANK0:TMR0 0x0001 Timer0 module's register BANK0:PCL 0x0002 Program Counter's (PC) Least Significant Byte BANK0:STATUS 0x0003 STATUS REGISTER BANK0:STATUS.IRP 7 Register Bank Select bit BANK0:STATUS.RP1 6 Register Bank Select bit 1 BANK0:STATUS.RP0 5 Register Bank Select bit 0 BANK0:STATUS.TO 4 Time-out bit BANK0:STATUS.PD 3 Power-down bit BANK0:STATUS.Z 2 Zero bit BANK0:STATUS.DC 1 Digit carry/borrow bit BANK0:STATUS.C 0 Carry/borrow bit BANK0:FSR 0x0004 Indirect data memory address pointer BANK0:PORTA 0x0005 PORTA REGISTER BANK0:PORTA.RA5 5 PORTA bit 5 BANK0:PORTA.RA4 4 PORTA bit 4 BANK0:PORTA.RA3 3 PORTA bit 3 BANK0:PORTA.RA2 2 PORTA bit 2 BANK0:PORTA.RA1 1 PORTA bit 1 BANK0:PORTA.RA0 0 PORTA bit 0 BANK0:PORTB 0x0006 PORTB REGISTER BANK0:PORTB.RB7 7 PORTB bit 7 BANK0:PORTB.RB6 6 PORTB bit 6 BANK0:PORTB.RB5 5 PORTB bit 5 BANK0:PORTB.RB4 4 PORTB bit 4 BANK0:PORTB.RB3 3 PORTB bit 3 BANK0:PORTB.RB2 2 PORTB bit 2 BANK0:PORTB.RB1 1 PORTB bit 1 BANK0:PORTB.RB0 0 PORTB bit 0 BANK0:PORTC 0x0007 PORTC REGISTER BANK0:PORTC.RC7 7 PORTC bit 7 BANK0:PORTC.RC6 6 PORTC bit 6 BANK0:PORTC.RC5 5 PORTC bit 5 BANK0:PORTC.RC4 4 PORTC bit 4 BANK0:PORTC.RC3 3 PORTC bit 3 BANK0:PORTC.RC2 2 PORTC bit 2 BANK0:PORTC.RC1 1 PORTC bit 1 BANK0:PORTC.RC0 0 PORTC bit 0 BANK0:RESERVED0008 0x0008 RESERVED BANK0:RESERVED0009 0x0009 RESERVED BANK0:PCLATH 0x000A Write Buffer for the upper 5 bits of the Program Counter BANK0:INTCON 0x000B INTCON REGISTER BANK0:INTCON.GIE 7 Global Interrupt Enable bit BANK0:INTCON.PEIE 6 Peripheral Interrupt Enable bit BANK0:INTCON.T0IE 5 TMR0 Overflow Interrupt Enable bit BANK0:INTCON.INTE 4 RB0/INT External Interrupt Enable bit BANK0:INTCON.RBIE 3 RB Port Change Interrupt Enable bit BANK0:INTCON.T0IF 2 TMR0 Overflow Interrupt Flag bit BANK0:INTCON.INTF 1 RB0/INT External Interrupt Flag bit BANK0:INTCON.RBIF 0 RB Port Change Interrupt Flag bit BANK0:PIR1 0x000C PIR1 REGISTER BANK0:PIR1.RCIF 5 USART Receive Interrupt Flag bit BANK0:PIR1.TXIF 4 USART Transmit Interrupt Flag bit BANK0:PIR1.SSPIF 3 Synchronous Serial Port Interrupt Flag bit BANK0:PIR1.CCP1IF 2 CCP1 Interrupt Flag bit BANK0:PIR1.TMR2IF 1 TMR2 to PR2 Match Interrupt Flag bit BANK0:PIR1.TMR1IF 0 TMR1 Overflow Interrupt Flag bit BANK0:PIR2 0x000D PIR2 REGISTER BANK0:PIR2.CCP2IF 0 CCP2 Interrupt Flag bit BANK0:TMR1L 0x000E Holding register for the Least Significant Byte of the 16-bit TMR1 register BANK0:TMR1H 0x000F Holding register for the Most Significant Byte of the 16-bit TMR1 register BANK0:T1CON 0x0010 TIMER1 CONTROL REGISTER BANK0:T1CON.T1CKPS1 5 Timer1 Input Clock Prescale Select bit 1 BANK0:T1CON.T1CKPS0 4 Timer1 Input Clock Prescale Select bit 0 BANK0:T1CON.T1OSCEN 3 Timer1 Oscillator Enable Control bit BANK0:T1CON.T1SYNC 2 Timer1 External Clock Input Synchronization Control bit BANK0:T1CON.TMR1CS 1 Timer1 Clock Source Select bit BANK0:T1CON.TMR1ON 0 Timer1 On bit BANK0:TMR2 0x0011 Timer2 module's register BANK0:T2CON 0x0012 TIMER2 CONTROL REGISTER BANK0:T2CON.TOUTPS3 6 Timer2 Output Postscale Select bit 3 BANK0:T2CON.TOUTPS2 5 Timer2 Output Postscale Select bit 2 BANK0:T2CON.TOUTPS1 4 Timer2 Output Postscale Select bit 1 BANK0:T2CON.TOUTPS0 3 Timer2 Output Postscale Select bit 0 BANK0:T2CON.TMR2ON 2 Timer2 On bit BANK0:T2CON.T2CKPS1 1 Timer2 Clock Prescale Select bit 1 BANK0:T2CON.T2CKPS0 0 Timer2 Clock Prescale Select bit 0 BANK0:SSPBUF 0x0013 Synchronous Serial Port Receive Buffer/Transmit Register BANK0:SSPCON 0x0014 SYNC SERIAL PORT CONTROL REGISTER BANK0:SSPCON.WCOL 7 Write Collision Flag bit BANK0:SSPCON.SSPOV 6 Synchronous Serial Port Overflow Flag bit BANK0:SSPCON.SSPEN 5 Synchronous Serial Port Enable bit BANK0:SSPCON.CKP 4 Clock Polarity Select bit BANK0:SSPCON.SSPM3 3 Synchronous Serial Port Mode Select bit 3 BANK0:SSPCON.SSPM2 2 Synchronous Serial Port Mode Select bit 2 BANK0:SSPCON.SSPM1 1 Synchronous Serial Port Mode Select bit 1 BANK0:SSPCON.SSPM0 0 Synchronous Serial Port Mode Select bit 0 BANK0:CCPR1L 0x0015 Capture/Compare/PWM Register1 (LSB) BANK0:CCPR1H 0x0016 Capture/Compare/PWM Register1 (MSB) BANK0:CCP1CON 0x0017 CCP1CON REGISTER BANK0:CCP1CON.CCP1X 5 PWM Least Significant bit BANK0:CCP1CON.CCP1Y 4 PWM Least Significant bit BANK0:CCP1CON.CCP1M3 3 CCP1 Mode Select bit 3 BANK0:CCP1CON.CCP1M2 2 CCP1 Mode Select bit 2 BANK0:CCP1CON.CCP1M1 1 CCP1 Mode Select bit 1 BANK0:CCP1CON.CCP1M0 0 CCP1 Mode Select bit 0 BANK0:RCSTA 0x0018 RECEIVE STATUS AND CONTROL REGISTER BANK0:RCSTA.SPEN 7 Serial Port Enable bit BANK0:RCSTA.RX9 6 9-bit Receive Enable bit BANK0:RCSTA.SREN 5 Single Receive Enable bit BANK0:RCSTA.CREN 4 Continuous Receive Enable bit BANK0:RCSTA.FERR 2 Framing Error bit BANK0:RCSTA.OERR 1 Overrun Error bit BANK0:RCSTA.RX9D 0 9th bit of Received Data BANK0:TXREG 0x0019 USART Transmit Data register BANK0:RCREG 0x001A USART Receive Data register BANK0:CCPR2L 0x001B Capture/Compare/PWM Register2 (LSB) BANK0:CCPR2H 0x001C Capture/Compare/PWM Register2 (MSB) BANK0:CCP2CON 0x001D CCP2CON REGISTER BANK0:CCP2CON.CCP2X 5 PWM Least Significant bit BANK0:CCP2CON.CCP2Y 4 PWM Least Significant bit BANK0:CCP2CON.CCP2M3 3 CCP2 Mode Select bit 3 BANK0:CCP2CON.CCP2M2 2 CCP2 Mode Select bit 2 BANK0:CCP2CON.CCP2M1 1 CCP2 Mode Select bit 1 BANK0:CCP2CON.CCP2M0 0 CCP2 Mode Select bit 0 BANK0:RESERVED001E 0x001E RESERVED BANK0:RESERVED001F 0x001F RESERVED ; BANK1 (0x0080:0x0100) BANK1:INDF 0x0080 INDF (not a physical register) BANK1:OPTION 0x0081 OPTION REGISTER BANK1:OPTION.RBPU 7 PORTB Pull-up Enable bit BANK1:OPTION.INTEDG 6 Interrupt Edge Select bit BANK1:OPTION.T0CS 5 TMR0 Clock Source Select bit BANK1:OPTION.T0SE 4 TMR0 Source Edge Select bit BANK1:OPTION.PSA 3 Prescaler Assignment bit BANK1:OPTION.PS2 2 Prescaler Rate Select bit 2 BANK1:OPTION.PS1 1 Prescaler Rate Select bit 1 BANK1:OPTION.PS0 0 Prescaler Rate Select bit 0 BANK1:PCL 0x0082 Program Counter's (PC) Least Significant Byte BANK1:STATUS 0x0083 STATUS REGISTER BANK1:STATUS.IRP 7 Register Bank Select bit BANK1:STATUS.RP1 6 Register Bank Select bit 1 BANK1:STATUS.RP0 5 Register Bank Select bit 0 BANK1:STATUS.TO 4 Time-out bit BANK1:STATUS.PD 3 Power-down bit BANK1:STATUS.Z 2 Zero bit BANK1:STATUS.DC 1 Digit carry/borrow bit BANK1:STATUS.C 0 Carry/borrow bit BANK1:FSR 0x0084 Indirect data memory address pointer BANK1:TRISA 0x0085 PORTA Data Direction Register BANK1:TRISA.TRISA5 5 PORTA Data Direction Register bit 5 BANK1:TRISA.TRISA4 4 PORTA Data Direction Register bit 4 BANK1:TRISA.TRISA3 3 PORTA Data Direction Register bit 3 BANK1:TRISA.TRISA2 2 PORTA Data Direction Register bit 2 BANK1:TRISA.TRISA1 1 PORTA Data Direction Register bit 1 BANK1:TRISA.TRISA0 0 PORTA Data Direction Register bit 0 BANK1:TRISB 0x0086 PORTB Data Direction register BANK1:TRISB.TRISB7 7 PORTB Data Direction register bit 7 BANK1:TRISB.TRISB6 6 PORTB Data Direction register bit 6 BANK1:TRISB.TRISB5 5 PORTB Data Direction register bit 5 BANK1:TRISB.TRISB4 4 PORTB Data Direction register bit 4 BANK1:TRISB.TRISB3 3 PORTB Data Direction register bit 3 BANK1:TRISB.TRISB2 2 PORTB Data Direction register bit 2 BANK1:TRISB.TRISB1 1 PORTB Data Direction register bit 1 BANK1:TRISB.TRISB0 0 PORTB Data Direction register bit 0 BANK1:TRISC 0x0087 PORTC Data Direction register BANK1:TRISC.TRISC7 7 PORTC Data Direction register bit 7 BANK1:TRISC.TRISC6 6 PORTC Data Direction register bit 6 BANK1:TRISC.TRISC5 5 PORTC Data Direction register bit 5 BANK1:TRISC.TRISC4 4 PORTC Data Direction register bit 4 BANK1:TRISC.TRISC3 3 PORTC Data Direction register bit 3 BANK1:TRISC.TRISC2 2 PORTC Data Direction register bit 2 BANK1:TRISC.TRISC1 1 PORTC Data Direction register bit 1 BANK1:TRISC.TRISC0 0 PORTC Data Direction register bit 0 BANK1:RESERVED0088 0x0088 RESERVED BANK1:RESERVED0089 0x0089 RESERVED BANK1:PCLATH 0x008A Write Buffer for the upper 5 bits of the Program Counter BANK1:INTCON 0x008B INTCON REGISTER BANK1:INTCON.GIE 7 Global Interrupt Enable bit BANK1:INTCON.PEIE 6 Peripheral Interrupt Enable bit BANK1:INTCON.T0IE 5 TMR0 Overflow Interrupt Enable bit BANK1:INTCON.INTE 4 RB0/INT External Interrupt Enable bit BANK1:INTCON.RBIE 3 RB Port Change Interrupt Enable bit BANK1:INTCON.T0IF 2 TMR0 Overflow Interrupt Flag bit BANK1:INTCON.INTF 1 RB0/INT External Interrupt Flag bit BANK1:INTCON.RBIF 0 RB Port Change Interrupt Flag bit BANK1:PIE1 0x008C PIE1 REGISTER BANK1:PIE1.RCIE 5 USART Receive Interrupt Enable bit BANK1:PIE1.TXIE 4 USART Transmit Interrupt Enable bit BANK1:PIE1.SSPIE 3 Synchronous Serial Port Interrupt Enable bit BANK1:PIE1.CCP1IE 2 CCP1 Interrupt Enable bit BANK1:PIE1.TMR2IE 1 TMR2 to PR2 Match Interrupt Enable bit BANK1:PIE1.TMR1IE 0 TMR1 Overflow Interrupt Enable bit BANK1:PIE2 0x008D PIE2 REGISTER BANK1:PIE2.CCP2IE 0 CCP2 Interrupt Enable bit BANK1:PCON 0x008E PCON REGISTER BANK1:PCON.POR 1 Power-on Reset Status bit BANK1:PCON.BOR 0 Brown-out Reset Status bit BANK1:RESERVED000F 0x008F RESERVED BANK1:RESERVED0090 0x0090 RESERVED BANK1:RESERVED0091 0x0091 RESERVED BANK1:PR2 0x0092 Timer2 Period register BANK1:SSPADD 0x0093 Synchronous Serial Port (I2C mode) Address register BANK1:SSPSTAT 0x0094 SYNC SERIAL PORT STATUS REGISTER BANK1:SSPSTAT.D_A 5 Data/Address bit (I2C mode only) BANK1:SSPSTAT.P 4 STOP bit (I2C mode only) BANK1:SSPSTAT.S 3 START bit (I2C mode only) BANK1:SSPSTAT.R_W 2 Read/Write bit information (I2C mode only) BANK1:SSPSTAT.UA 1 Update Address (10-bit I2C mode only) BANK1:SSPSTAT.BF 0 Buffer Full Status bit BANK1:RESERVED0095 0x0095 RESERVED BANK1:RESERVED0096 0x0096 RESERVED BANK1:RESERVED0097 0x0097 RESERVED BANK1:TXSTA 0x0098 TRANSMIT STATUS AND CONTROL REGISTER BANK1:TXSTA.CSRC 7 Clock Source Select bit BANK1:TXSTA.TX9 6 9-bit Transmit Enable bit BANK1:TXSTA.TXEN 5 Transmit Enable bit BANK1:TXSTA.SYNC 4 USART Mode Select bit BANK1:TXSTA.BRGH 2 High Baud Rate Select bit BANK1:TXSTA.TRMT 1 Transmit Shift Register Status bit BANK1:TXSTA.TX9D 0 9th bit of Transmit Data BANK1:SPBRG 0x0099 Baud Rate Generator register BANK1:RESERVED009A 0x009A RESERVED BANK1:RESERVED009B 0x009B RESERVED BANK1:RESERVED009C 0x009C RESERVED BANK1:RESERVED009D 0x009D RESERVED BANK1:RESERVED009E 0x009E RESERVED BANK1:RESERVED009F 0x009F RESERVED .16C65B ; http://www.microchip.com/download/lit/pline/picmicro/families/16c7x/30605c.pdf ; 16C63A65B_73B74B.pdf ; MEMORY MAP ; BANK_0 area DATA FSR_ 0x0000:0x0020 area DATA Gen_Purp 0x0020:0x0080 General Purpose Register area DATA MEM_Program0 0x0080:0x0800 On-chip Program Memory (Page 0) area DATA MEM_Program1 0x0800:0x1000 On-chip Program Memory (Page 1) ; BANK_1 ; area DATA FSR_ 0x0080:0x00A0 ; area DATA Gen_Purp 0x00A0:0x0100 General Purpose Register ; area DATA MEM_Program0 0x0100:0x0800 On-chip Program Memory (Page 0) ; area DATA MEM_Program1 0x0800:0x1000 On-chip Program Memory (Page 1) ; Interrupt and reset vector assignments interrupt RESET 0x0000 RESET ; INPUT/OUTPUT PORTS ; BANK0 (0x0000:0x0080) BANK0:INDF 0x0000 INDF (not a physical register) BANK0:TMR0 0x0001 Timer0 module's register BANK0:PCL 0x0002 Program Counter's (PC) Least Significant Byte BANK0:STATUS 0x0003 STATUS REGISTER BANK0:STATUS.IRP 7 Register Bank Select bit BANK0:STATUS.RP1 6 Register Bank Select bit 1 BANK0:STATUS.RP0 5 Register Bank Select bit 0 BANK0:STATUS.TO 4 Time-out bit BANK0:STATUS.PD 3 Power-down bit BANK0:STATUS.Z 2 Zero bit BANK0:STATUS.DC 1 Digit carry/borrow bit BANK0:STATUS.C 0 Carry/borrow bit BANK0:FSR 0x0004 Indirect data memory address pointer BANK0:PORTA 0x0005 PORTA REGISTER BANK0:PORTA.RA5 5 PORTA bit 5 BANK0:PORTA.RA4 4 PORTA bit 4 BANK0:PORTA.RA3 3 PORTA bit 3 BANK0:PORTA.RA2 2 PORTA bit 2 BANK0:PORTA.RA1 1 PORTA bit 1 BANK0:PORTA.RA0 0 PORTA bit 0 BANK0:PORTB 0x0006 PORTB REGISTER BANK0:PORTB.RB7 7 PORTB bit 7 BANK0:PORTB.RB6 6 PORTB bit 6 BANK0:PORTB.RB5 5 PORTB bit 5 BANK0:PORTB.RB4 4 PORTB bit 4 BANK0:PORTB.RB3 3 PORTB bit 3 BANK0:PORTB.RB2 2 PORTB bit 2 BANK0:PORTB.RB1 1 PORTB bit 1 BANK0:PORTB.RB0 0 PORTB bit 0 BANK0:PORTC 0x0007 PORTC REGISTER BANK0:PORTC.RC7 7 PORTC bit 7 BANK0:PORTC.RC6 6 PORTC bit 6 BANK0:PORTC.RC5 5 PORTC bit 5 BANK0:PORTC.RC4 4 PORTC bit 4 BANK0:PORTC.RC3 3 PORTC bit 3 BANK0:PORTC.RC2 2 PORTC bit 2 BANK0:PORTC.RC1 1 PORTC bit 1 BANK0:PORTC.RC0 0 PORTC bit 0 BANK0:PORTD 0x0008 PORTD REGISTER (not implemented on the PIC16C63A/73B) BANK0:PORTD.RD7 7 PORTD bit 7 BANK0:PORTD.RD6 6 PORTD bit 6 BANK0:PORTD.RD5 5 PORTD bit 5 BANK0:PORTD.RD4 4 PORTD bit 4 BANK0:PORTD.RD3 3 PORTD bit 3 BANK0:PORTD.RD2 2 PORTD bit 2 BANK0:PORTD.RD1 1 PORTD bit 1 BANK0:PORTD.RD0 0 PORTD bit 0 BANK0:PORTE 0x0009 PORTE REGISTER (not implemented on the PIC16C63A/73B) BANK0:PORTE.RE2 2 PORTE bit 2 BANK0:PORTE.RE1 1 PORTE bit 1 BANK0:PORTE.RE0 0 PORTE bit 0 BANK0:PCLATH 0x000A Write Buffer for the upper 5 bits of the Program Counter BANK0:INTCON 0x000B INTCON REGISTER BANK0:INTCON.GIE 7 Global Interrupt Enable bit BANK0:INTCON.PEIE 6 Peripheral Interrupt Enable bit BANK0:INTCON.T0IE 5 TMR0 Overflow Interrupt Enable bit BANK0:INTCON.INTE 4 RB0/INT External Interrupt Enable bit BANK0:INTCON.RBIE 3 RB Port Change Interrupt Enable bit BANK0:INTCON.T0IF 2 TMR0 Overflow Interrupt Flag bit BANK0:INTCON.INTF 1 RB0/INT External Interrupt Flag bit BANK0:INTCON.RBIF 0 RB Port Change Interrupt Flag bit BANK0:PIR1 0x000C PIR1 REGISTER BANK0:PIR1.PSPIF 7 Parallel Slave Port Read/Write Interrupt Flag bit BANK0:PIR1.RCIF 5 USART Receive Interrupt Flag bit BANK0:PIR1.TXIF 4 USART Transmit Interrupt Flag bit BANK0:PIR1.SSPIF 3 Synchronous Serial Port Interrupt Flag bit BANK0:PIR1.CCP1IF 2 CCP1 Interrupt Flag bit BANK0:PIR1.TMR2IF 1 TMR2 to PR2 Match Interrupt Flag bit BANK0:PIR1.TMR1IF 0 TMR1 Overflow Interrupt Flag bit BANK0:PIR2 0x000D PIR2 REGISTER BANK0:PIR2.CCP2IF 0 CCP2 Interrupt Flag bit BANK0:TMR1L 0x000E Holding register for the Least Significant Byte of the 16-bit TMR1 register BANK0:TMR1H 0x000F Holding register for the Most Significant Byte of the 16-bit TMR1 register BANK0:T1CON 0x0010 TIMER1 CONTROL REGISTER BANK0:T1CON.T1CKPS1 5 Timer1 Input Clock Prescale Select bit 1 BANK0:T1CON.T1CKPS0 4 Timer1 Input Clock Prescale Select bit 0 BANK0:T1CON.T1OSCEN 3 Timer1 Oscillator Enable Control bit BANK0:T1CON.T1SYNC 2 Timer1 External Clock Input Synchronization Control bit BANK0:T1CON.TMR1CS 1 Timer1 Clock Source Select bit BANK0:T1CON.TMR1ON 0 Timer1 On bit BANK0:TMR2 0x0011 Timer2 module's register BANK0:T2CON 0x0012 TIMER2 CONTROL REGISTER BANK0:T2CON.TOUTPS3 6 Timer2 Output Postscale Select bit 3 BANK0:T2CON.TOUTPS2 5 Timer2 Output Postscale Select bit 2 BANK0:T2CON.TOUTPS1 4 Timer2 Output Postscale Select bit 1 BANK0:T2CON.TOUTPS0 3 Timer2 Output Postscale Select bit 0 BANK0:T2CON.TMR2ON 2 Timer2 On bit BANK0:T2CON.T2CKPS1 1 Timer2 Clock Prescale Select bit 1 BANK0:T2CON.T2CKPS0 0 Timer2 Clock Prescale Select bit 0 BANK0:SSPBUF 0x0013 Synchronous Serial Port Receive Buffer/Transmit Register BANK0:SSPCON 0x0014 SYNC SERIAL PORT CONTROL REGISTER BANK0:SSPCON.WCOL 7 Write Collision Flag bit BANK0:SSPCON.SSPOV 6 Synchronous Serial Port Overflow Flag bit BANK0:SSPCON.SSPEN 5 Synchronous Serial Port Enable bit BANK0:SSPCON.CKP 4 Clock Polarity Select bit BANK0:SSPCON.SSPM3 3 Synchronous Serial Port Mode Select bit 3 BANK0:SSPCON.SSPM2 2 Synchronous Serial Port Mode Select bit 2 BANK0:SSPCON.SSPM1 1 Synchronous Serial Port Mode Select bit 1 BANK0:SSPCON.SSPM0 0 Synchronous Serial Port Mode Select bit 0 BANK0:CCPR1L 0x0015 Capture/Compare/PWM Register1 (LSB) BANK0:CCPR1H 0x0016 Capture/Compare/PWM Register1 (MSB) BANK0:CCP1CON 0x0017 CCP1CON REGISTER BANK0:CCP1CON.CCP1X 5 PWM Least Significant bit BANK0:CCP1CON.CCP1Y 4 PWM Least Significant bit BANK0:CCP1CON.CCP1M3 3 CCP1 Mode Select bit 3 BANK0:CCP1CON.CCP1M2 2 CCP1 Mode Select bit 2 BANK0:CCP1CON.CCP1M1 1 CCP1 Mode Select bit 1 BANK0:CCP1CON.CCP1M0 0 CCP1 Mode Select bit 0 BANK0:RCSTA 0x0018 RECEIVE STATUS AND CONTROL REGISTER BANK0:RCSTA.SPEN 7 Serial Port Enable bit BANK0:RCSTA.RX9 6 9-bit Receive Enable bit BANK0:RCSTA.SREN 5 Single Receive Enable bit BANK0:RCSTA.CREN 4 Continuous Receive Enable bit BANK0:RCSTA.FERR 2 Framing Error bit BANK0:RCSTA.OERR 1 Overrun Error bit BANK0:RCSTA.RX9D 0 9th bit of Received Data BANK0:TXREG 0x0019 USART Transmit Data register BANK0:RCREG 0x001A USART Receive Data register BANK0:CCPR2L 0x001B Capture/Compare/PWM Register2 (LSB) BANK0:CCPR2H 0x001C Capture/Compare/PWM Register2 (MSB) BANK0:CCP2CON 0x001D CCP2CON REGISTER BANK0:CCP2CON.CCP2X 5 PWM Least Significant bit BANK0:CCP2CON.CCP2Y 4 PWM Least Significant bit BANK0:CCP2CON.CCP2M3 3 CCP2 Mode Select bit 3 BANK0:CCP2CON.CCP2M2 2 CCP2 Mode Select bit 2 BANK0:CCP2CON.CCP2M1 1 CCP2 Mode Select bit 1 BANK0:CCP2CON.CCP2M0 0 CCP2 Mode Select bit 0 BANK0:RESERVED001E 0x001E RESERVED BANK0:RESERVED001F 0x001F RESERVED ; BANK1 (0x0080:0x0100) BANK1:INDF 0x0080 INDF (not a physical register) BANK1:OPTION 0x0081 OPTION REGISTER BANK1:OPTION.RBPU 7 PORTB Pull-up Enable bit BANK1:OPTION.INTEDG 6 Interrupt Edge Select bit BANK1:OPTION.T0CS 5 TMR0 Clock Source Select bit BANK1:OPTION.T0SE 4 TMR0 Source Edge Select bit BANK1:OPTION.PSA 3 Prescaler Assignment bit BANK1:OPTION.PS2 2 Prescaler Rate Select bit 2 BANK1:OPTION.PS1 1 Prescaler Rate Select bit 1 BANK1:OPTION.PS0 0 Prescaler Rate Select bit 0 BANK1:PCL 0x0082 Program Counter's (PC) Least Significant Byte BANK1:STATUS 0x0083 STATUS REGISTER BANK1:STATUS.IRP 7 Register Bank Select bit BANK1:STATUS.RP1 6 Register Bank Select bit 1 BANK1:STATUS.RP0 5 Register Bank Select bit 0 BANK1:STATUS.TO 4 Time-out bit BANK1:STATUS.PD 3 Power-down bit BANK1:STATUS.Z 2 Zero bit BANK1:STATUS.DC 1 Digit carry/borrow bit BANK1:STATUS.C 0 Carry/borrow bit BANK1:FSR 0x0084 Indirect data memory address pointer BANK1:TRISA 0x0085 PORTA Data Direction Register BANK1:TRISA.TRISA5 5 PORTA Data Direction Register bit 5 BANK1:TRISA.TRISA4 4 PORTA Data Direction Register bit 4 BANK1:TRISA.TRISA3 3 PORTA Data Direction Register bit 3 BANK1:TRISA.TRISA2 2 PORTA Data Direction Register bit 2 BANK1:TRISA.TRISA1 1 PORTA Data Direction Register bit 1 BANK1:TRISA.TRISA0 0 PORTA Data Direction Register bit 0 BANK1:TRISB 0x0086 PORTB Data Direction register BANK1:TRISB.TRISB7 7 PORTB Data Direction register bit 7 BANK1:TRISB.TRISB6 6 PORTB Data Direction register bit 6 BANK1:TRISB.TRISB5 5 PORTB Data Direction register bit 5 BANK1:TRISB.TRISB4 4 PORTB Data Direction register bit 4 BANK1:TRISB.TRISB3 3 PORTB Data Direction register bit 3 BANK1:TRISB.TRISB2 2 PORTB Data Direction register bit 2 BANK1:TRISB.TRISB1 1 PORTB Data Direction register bit 1 BANK1:TRISB.TRISB0 0 PORTB Data Direction register bit 0 BANK1:TRISC 0x0087 PORTC Data Direction register BANK1:TRISC.TRISC7 7 PORTC Data Direction register bit 7 BANK1:TRISC.TRISC6 6 PORTC Data Direction register bit 6 BANK1:TRISC.TRISC5 5 PORTC Data Direction register bit 5 BANK1:TRISC.TRISC4 4 PORTC Data Direction register bit 4 BANK1:TRISC.TRISC3 3 PORTC Data Direction register bit 3 BANK1:TRISC.TRISC2 2 PORTC Data Direction register bit 2 BANK1:TRISC.TRISC1 1 PORTC Data Direction register bit 1 BANK1:TRISC.TRISC0 0 PORTC Data Direction register bit 0 BANK1:TRISD 0x0088 PORTD Data Direction register (not implemented on the PIC16C63A/73B) BANK1:TRISD.TRISD7 7 PORTD Data Direction register bit 7 BANK1:TRISD.TRISD6 6 PORTD Data Direction register bit 6 BANK1:TRISD.TRISD5 5 PORTD Data Direction register bit 5 BANK1:TRISD.TRISD4 4 PORTD Data Direction register bit 4 BANK1:TRISD.TRISD3 3 PORTD Data Direction register bit 3 BANK1:TRISD.TRISD2 2 PORTD Data Direction register bit 2 BANK1:TRISD.TRISD1 1 PORTD Data Direction register bit 1 BANK1:TRISD.TRISD0 0 PORTD Data Direction register bit 0 BANK1:TRISE 0x0089 PORTE Data Direction register (not implemented on the PIC16C63A/73B) BANK1:TRISE.IBF 7 Input Buffer Full Status bit BANK1:TRISE.OBF 6 Output Buffer Full Status bit BANK1:TRISE.IBOV 5 Input Buffer Overflow Detect bit (in Microprocessor mode) BANK1:TRISE.PSPMODE 4 Parallel Slave Port Mode Select bit BANK1:TRISE.TRISE2 2 Direction Control bit for pin RE2/CS/AN7 BANK1:TRISE.TRISE1 1 Direction Control bit for pin RE1/WR/AN6 BANK1:TRISE.TRISE0 0 Direction Control bit for pin RE0/RD/AN5 BANK1:PCLATH 0x008A Write Buffer for the upper 5 bits of the Program Counter BANK1:INTCON 0x008B INTCON REGISTER BANK1:INTCON.GIE 7 Global Interrupt Enable bit BANK1:INTCON.PEIE 6 Peripheral Interrupt Enable bit BANK1:INTCON.T0IE 5 TMR0 Overflow Interrupt Enable bit BANK1:INTCON.INTE 4 RB0/INT External Interrupt Enable bit BANK1:INTCON.RBIE 3 RB Port Change Interrupt Enable bit BANK1:INTCON.T0IF 2 TMR0 Overflow Interrupt Flag bit BANK1:INTCON.INTF 1 RB0/INT External Interrupt Flag bit BANK1:INTCON.RBIF 0 RB Port Change Interrupt Flag bit BANK1:PIE1 0x008C PIE1 REGISTER BANK1:PIE1.PSPIE 7 Parallel Slave Port Read/Write Interrupt Enable bit BANK1:PIE1.RCIE 5 USART Receive Interrupt Enable bit BANK1:PIE1.TXIE 4 USART Transmit Interrupt Enable bit BANK1:PIE1.SSPIE 3 Synchronous Serial Port Interrupt Enable bit BANK1:PIE1.CCP1IE 2 CCP1 Interrupt Enable bit BANK1:PIE1.TMR2IE 1 TMR2 to PR2 Match Interrupt Enable bit BANK1:PIE1.TMR1IE 0 TMR1 Overflow Interrupt Enable bit BANK1:PIE2 0x008D PIE2 REGISTER BANK1:PIE2.CCP2IE 0 CCP2 Interrupt Enable bit BANK1:PCON 0x008E PCON REGISTER BANK1:PCON.POR 1 Power-on Reset Status bit BANK1:PCON.BOR 0 Brown-out Reset Status bit BANK1:RESERVED000F 0x008F RESERVED BANK1:RESERVED0090 0x0090 RESERVED BANK1:RESERVED0091 0x0091 RESERVED BANK1:PR2 0x0092 Timer2 Period register BANK1:SSPADD 0x0093 Synchronous Serial Port (I2C mode) Address register BANK1:SSPSTAT 0x0094 SYNC SERIAL PORT STATUS REGISTER BANK1:SSPSTAT.D_A 5 Data/Address bit (I2C mode only) BANK1:SSPSTAT.P 4 STOP bit (I2C mode only) BANK1:SSPSTAT.S 3 START bit (I2C mode only) BANK1:SSPSTAT.R_W 2 Read/Write bit information (I2C mode only) BANK1:SSPSTAT.UA 1 Update Address (10-bit I2C mode only) BANK1:SSPSTAT.BF 0 Buffer Full Status bit BANK1:RESERVED0095 0x0095 RESERVED BANK1:RESERVED0096 0x0096 RESERVED BANK1:RESERVED0097 0x0097 RESERVED BANK1:TXSTA 0x0098 TRANSMIT STATUS AND CONTROL REGISTER BANK1:TXSTA.CSRC 7 Clock Source Select bit BANK1:TXSTA.TX9 6 9-bit Transmit Enable bit BANK1:TXSTA.TXEN 5 Transmit Enable bit BANK1:TXSTA.SYNC 4 USART Mode Select bit BANK1:TXSTA.BRGH 2 High Baud Rate Select bit BANK1:TXSTA.TRMT 1 Transmit Shift Register Status bit BANK1:TXSTA.TX9D 0 9th bit of Transmit Data BANK1:SPBRG 0x0099 Baud Rate Generator register BANK1:RESERVED009A 0x009A RESERVED BANK1:RESERVED009B 0x009B RESERVED BANK1:RESERVED009C 0x009C RESERVED BANK1:RESERVED009D 0x009D RESERVED BANK1:RESERVED009E 0x009E RESERVED BANK1:RESERVED009F 0x009F RESERVED .16C73B ; http://www.microchip.com/download/lit/pline/picmicro/families/16c7x/30605c.pdf ; 16C63A65B_73B74B.pdf ; MEMORY MAP ; BANK_0 area DATA FSR_ 0x0000:0x0020 area DATA Gen_Purp 0x0020:0x0080 General Purpose Register area DATA MEM_Program0 0x0080:0x0800 On-chip Program Memory (Page 0) area DATA MEM_Program1 0x0800:0x1000 On-chip Program Memory (Page 1) ; BANK_1 ; area DATA FSR_ 0x0080:0x00A0 ; area DATA Gen_Purp 0x00A0:0x0100 General Purpose Register ; area DATA MEM_Program0 0x0100:0x0800 On-chip Program Memory (Page 0) ; area DATA MEM_Program1 0x0800:0x1000 On-chip Program Memory (Page 1) ; Interrupt and reset vector assignments interrupt RESET 0x0000 RESET ; INPUT/OUTPUT PORTS ; BANK0 (0x0000:0x0080) BANK0:INDF 0x0000 INDF (not a physical register) BANK0:TMR0 0x0001 Timer0 module's register BANK0:PCL 0x0002 Program Counter's (PC) Least Significant Byte BANK0:STATUS 0x0003 STATUS REGISTER BANK0:STATUS.IRP 7 Register Bank Select bit BANK0:STATUS.RP1 6 Register Bank Select bit 1 BANK0:STATUS.RP0 5 Register Bank Select bit 0 BANK0:STATUS.TO 4 Time-out bit BANK0:STATUS.PD 3 Power-down bit BANK0:STATUS.Z 2 Zero bit BANK0:STATUS.DC 1 Digit carry/borrow bit BANK0:STATUS.C 0 Carry/borrow bit BANK0:FSR 0x0004 Indirect data memory address pointer BANK0:PORTA 0x0005 PORTA REGISTER BANK0:PORTA.RA5 5 PORTA bit 5 BANK0:PORTA.RA4 4 PORTA bit 4 BANK0:PORTA.RA3 3 PORTA bit 3 BANK0:PORTA.RA2 2 PORTA bit 2 BANK0:PORTA.RA1 1 PORTA bit 1 BANK0:PORTA.RA0 0 PORTA bit 0 BANK0:PORTB 0x0006 PORTB REGISTER BANK0:PORTB.RB7 7 PORTB bit 7 BANK0:PORTB.RB6 6 PORTB bit 6 BANK0:PORTB.RB5 5 PORTB bit 5 BANK0:PORTB.RB4 4 PORTB bit 4 BANK0:PORTB.RB3 3 PORTB bit 3 BANK0:PORTB.RB2 2 PORTB bit 2 BANK0:PORTB.RB1 1 PORTB bit 1 BANK0:PORTB.RB0 0 PORTB bit 0 BANK0:PORTC 0x0007 PORTC REGISTER BANK0:PORTC.RC7 7 PORTC bit 7 BANK0:PORTC.RC6 6 PORTC bit 6 BANK0:PORTC.RC5 5 PORTC bit 5 BANK0:PORTC.RC4 4 PORTC bit 4 BANK0:PORTC.RC3 3 PORTC bit 3 BANK0:PORTC.RC2 2 PORTC bit 2 BANK0:PORTC.RC1 1 PORTC bit 1 BANK0:PORTC.RC0 0 PORTC bit 0 BANK0:RESERVED0008 0x0008 RESERVED BANK0:RESERVED0009 0x0009 RESERVED BANK0:PCLATH 0x000A Write Buffer for the upper 5 bits of the Program Counter BANK0:INTCON 0x000B INTCON REGISTER BANK0:INTCON.GIE 7 Global Interrupt Enable bit BANK0:INTCON.PEIE 6 Peripheral Interrupt Enable bit BANK0:INTCON.T0IE 5 TMR0 Overflow Interrupt Enable bit BANK0:INTCON.INTE 4 RB0/INT External Interrupt Enable bit BANK0:INTCON.RBIE 3 RB Port Change Interrupt Enable bit BANK0:INTCON.T0IF 2 TMR0 Overflow Interrupt Flag bit BANK0:INTCON.INTF 1 RB0/INT External Interrupt Flag bit BANK0:INTCON.RBIF 0 RB Port Change Interrupt Flag bit BANK0:PIR1 0x000C PIR1 REGISTER BANK0:PIR1.ADIF 6 A/D Converter Interrupt Flag bit BANK0:PIR1.RCIF 5 USART Receive Interrupt Flag bit BANK0:PIR1.TXIF 4 USART Transmit Interrupt Flag bit BANK0:PIR1.SSPIF 3 Synchronous Serial Port Interrupt Flag bit BANK0:PIR1.CCP1IF 2 CCP1 Interrupt Flag bit BANK0:PIR1.TMR2IF 1 TMR2 to PR2 Match Interrupt Flag bit BANK0:PIR1.TMR1IF 0 TMR1 Overflow Interrupt Flag bit BANK0:PIR2 0x000D PIR2 REGISTER BANK0:PIR2.CCP2IF 0 CCP2 Interrupt Flag bit BANK0:TMR1L 0x000E Holding register for the Least Significant Byte of the 16-bit TMR1 register BANK0:TMR1H 0x000F Holding register for the Most Significant Byte of the 16-bit TMR1 register BANK0:T1CON 0x0010 TIMER1 CONTROL REGISTER BANK0:T1CON.T1CKPS1 5 Timer1 Input Clock Prescale Select bit 1 BANK0:T1CON.T1CKPS0 4 Timer1 Input Clock Prescale Select bit 0 BANK0:T1CON.T1OSCEN 3 Timer1 Oscillator Enable Control bit BANK0:T1CON.T1SYNC 2 Timer1 External Clock Input Synchronization Control bit BANK0:T1CON.TMR1CS 1 Timer1 Clock Source Select bit BANK0:T1CON.TMR1ON 0 Timer1 On bit BANK0:TMR2 0x0011 Timer2 module's register BANK0:T2CON 0x0012 TIMER2 CONTROL REGISTER BANK0:T2CON.TOUTPS3 6 Timer2 Output Postscale Select bit 3 BANK0:T2CON.TOUTPS2 5 Timer2 Output Postscale Select bit 2 BANK0:T2CON.TOUTPS1 4 Timer2 Output Postscale Select bit 1 BANK0:T2CON.TOUTPS0 3 Timer2 Output Postscale Select bit 0 BANK0:T2CON.TMR2ON 2 Timer2 On bit BANK0:T2CON.T2CKPS1 1 Timer2 Clock Prescale Select bit 1 BANK0:T2CON.T2CKPS0 0 Timer2 Clock Prescale Select bit 0 BANK0:SSPBUF 0x0013 Synchronous Serial Port Receive Buffer/Transmit Register BANK0:SSPCON 0x0014 SYNC SERIAL PORT CONTROL REGISTER BANK0:SSPCON.WCOL 7 Write Collision Flag bit BANK0:SSPCON.SSPOV 6 Synchronous Serial Port Overflow Flag bit BANK0:SSPCON.SSPEN 5 Synchronous Serial Port Enable bit BANK0:SSPCON.CKP 4 Clock Polarity Select bit BANK0:SSPCON.SSPM3 3 Synchronous Serial Port Mode Select bit 3 BANK0:SSPCON.SSPM2 2 Synchronous Serial Port Mode Select bit 2 BANK0:SSPCON.SSPM1 1 Synchronous Serial Port Mode Select bit 1 BANK0:SSPCON.SSPM0 0 Synchronous Serial Port Mode Select bit 0 BANK0:CCPR1L 0x0015 Capture/Compare/PWM Register1 (LSB) BANK0:CCPR1H 0x0016 Capture/Compare/PWM Register1 (MSB) BANK0:CCP1CON 0x0017 CCP1CON REGISTER BANK0:CCP1CON.CCP1X 5 PWM Least Significant bit BANK0:CCP1CON.CCP1Y 4 PWM Least Significant bit BANK0:CCP1CON.CCP1M3 3 CCP1 Mode Select bit 3 BANK0:CCP1CON.CCP1M2 2 CCP1 Mode Select bit 2 BANK0:CCP1CON.CCP1M1 1 CCP1 Mode Select bit 1 BANK0:CCP1CON.CCP1M0 0 CCP1 Mode Select bit 0 BANK0:RCSTA 0x0018 RECEIVE STATUS AND CONTROL REGISTER BANK0:RCSTA.SPEN 7 Serial Port Enable bit BANK0:RCSTA.RX9 6 9-bit Receive Enable bit BANK0:RCSTA.SREN 5 Single Receive Enable bit BANK0:RCSTA.CREN 4 Continuous Receive Enable bit BANK0:RCSTA.FERR 2 Framing Error bit BANK0:RCSTA.OERR 1 Overrun Error bit BANK0:RCSTA.RX9D 0 9th bit of Received Data BANK0:TXREG 0x0019 USART Transmit Data register BANK0:RCREG 0x001A USART Receive Data register BANK0:CCPR2L 0x001B Capture/Compare/PWM Register2 (LSB) BANK0:CCPR2H 0x001C Capture/Compare/PWM Register2 (MSB) BANK0:CCP2CON 0x001D CCP2CON REGISTER BANK0:CCP2CON.CCP2X 5 PWM Least Significant bit BANK0:CCP2CON.CCP2Y 4 PWM Least Significant bit BANK0:CCP2CON.CCP2M3 3 CCP2 Mode Select bit 3 BANK0:CCP2CON.CCP2M2 2 CCP2 Mode Select bit 2 BANK0:CCP2CON.CCP2M1 1 CCP2 Mode Select bit 1 BANK0:CCP2CON.CCP2M0 0 CCP2 Mode Select bit 0 BANK0:ADRES 0x001E A/D Result register (not implemented on the PIC16C63A/65B) BANK0:ADCON0 0x001F ADCON0 REGISTER (not implemented on the PIC16C63A/65B) BANK0:ADCON0.ADCS1 7 A/D Conversion Clock Select bit 1 BANK0:ADCON0.ADCS0 6 A/D Conversion Clock Select bit 0 BANK0:ADCON0.CHS2 5 Analog Channel Select bit 2 BANK0:ADCON0.CHS1 4 Analog Channel Select bit 1 BANK0:ADCON0.CHS0 3 Analog Channel Select bit 0 BANK0:ADCON0.GO_DONE 2 A/D Conversion Status bit BANK0:ADCON0.ADON 0 A/D On bit ; BANK1 (0x0080:0x0100) BANK1:INDF 0x0080 INDF (not a physical register) BANK1:OPTION 0x0081 OPTION REGISTER BANK1:OPTION.RBPU 7 PORTB Pull-up Enable bit BANK1:OPTION.INTEDG 6 Interrupt Edge Select bit BANK1:OPTION.T0CS 5 TMR0 Clock Source Select bit BANK1:OPTION.T0SE 4 TMR0 Source Edge Select bit BANK1:OPTION.PSA 3 Prescaler Assignment bit BANK1:OPTION.PS2 2 Prescaler Rate Select bit 2 BANK1:OPTION.PS1 1 Prescaler Rate Select bit 1 BANK1:OPTION.PS0 0 Prescaler Rate Select bit 0 BANK1:PCL 0x0082 Program Counter's (PC) Least Significant Byte BANK1:STATUS 0x0083 STATUS REGISTER BANK1:STATUS.IRP 7 Register Bank Select bit BANK1:STATUS.RP1 6 Register Bank Select bit 1 BANK1:STATUS.RP0 5 Register Bank Select bit 0 BANK1:STATUS.TO 4 Time-out bit BANK1:STATUS.PD 3 Power-down bit BANK1:STATUS.Z 2 Zero bit BANK1:STATUS.DC 1 Digit carry/borrow bit BANK1:STATUS.C 0 Carry/borrow bit BANK1:FSR 0x0084 Indirect data memory address pointer BANK1:TRISA 0x0085 PORTA Data Direction Register BANK1:TRISA.TRISA5 5 PORTA Data Direction Register bit 5 BANK1:TRISA.TRISA4 4 PORTA Data Direction Register bit 4 BANK1:TRISA.TRISA3 3 PORTA Data Direction Register bit 3 BANK1:TRISA.TRISA2 2 PORTA Data Direction Register bit 2 BANK1:TRISA.TRISA1 1 PORTA Data Direction Register bit 1 BANK1:TRISA.TRISA0 0 PORTA Data Direction Register bit 0 BANK1:TRISB 0x0086 PORTB Data Direction register BANK1:TRISB.TRISB7 7 PORTB Data Direction register bit 7 BANK1:TRISB.TRISB6 6 PORTB Data Direction register bit 6 BANK1:TRISB.TRISB5 5 PORTB Data Direction register bit 5 BANK1:TRISB.TRISB4 4 PORTB Data Direction register bit 4 BANK1:TRISB.TRISB3 3 PORTB Data Direction register bit 3 BANK1:TRISB.TRISB2 2 PORTB Data Direction register bit 2 BANK1:TRISB.TRISB1 1 PORTB Data Direction register bit 1 BANK1:TRISB.TRISB0 0 PORTB Data Direction register bit 0 BANK1:TRISC 0x0087 PORTC Data Direction register BANK1:TRISC.TRISC7 7 PORTC Data Direction register bit 7 BANK1:TRISC.TRISC6 6 PORTC Data Direction register bit 6 BANK1:TRISC.TRISC5 5 PORTC Data Direction register bit 5 BANK1:TRISC.TRISC4 4 PORTC Data Direction register bit 4 BANK1:TRISC.TRISC3 3 PORTC Data Direction register bit 3 BANK1:TRISC.TRISC2 2 PORTC Data Direction register bit 2 BANK1:TRISC.TRISC1 1 PORTC Data Direction register bit 1 BANK1:TRISC.TRISC0 0 PORTC Data Direction register bit 0 BANK1:RESERVED0088 0x0088 RESERVED BANK1:RESERVED0089 0x0089 RESERVED BANK1:PCLATH 0x008A Write Buffer for the upper 5 bits of the Program Counter BANK1:INTCON 0x008B INTCON REGISTER BANK1:INTCON.GIE 7 Global Interrupt Enable bit BANK1:INTCON.PEIE 6 Peripheral Interrupt Enable bit BANK1:INTCON.T0IE 5 TMR0 Overflow Interrupt Enable bit BANK1:INTCON.INTE 4 RB0/INT External Interrupt Enable bit BANK1:INTCON.RBIE 3 RB Port Change Interrupt Enable bit BANK1:INTCON.T0IF 2 TMR0 Overflow Interrupt Flag bit BANK1:INTCON.INTF 1 RB0/INT External Interrupt Flag bit BANK1:INTCON.RBIF 0 RB Port Change Interrupt Flag bit BANK1:PIE1 0x008C PIE1 REGISTER BANK1:PIE1.ADIE 6 A/D Converter Interrupt Enable bit BANK1:PIE1.RCIE 5 USART Receive Interrupt Enable bit BANK1:PIE1.TXIE 4 USART Transmit Interrupt Enable bit BANK1:PIE1.SSPIE 3 Synchronous Serial Port Interrupt Enable bit BANK1:PIE1.CCP1IE 2 CCP1 Interrupt Enable bit BANK1:PIE1.TMR2IE 1 TMR2 to PR2 Match Interrupt Enable bit BANK1:PIE1.TMR1IE 0 TMR1 Overflow Interrupt Enable bit BANK1:PIE2 0x008D PIE2 REGISTER BANK1:PIE2.CCP2IE 0 CCP2 Interrupt Enable bit BANK1:PCON 0x008E PCON REGISTER BANK1:PCON.POR 1 Power-on Reset Status bit BANK1:PCON.BOR 0 Brown-out Reset Status bit BANK1:RESERVED000F 0x008F RESERVED BANK1:RESERVED0090 0x0090 RESERVED BANK1:RESERVED0091 0x0091 RESERVED BANK1:PR2 0x0092 Timer2 Period register BANK1:SSPADD 0x0093 Synchronous Serial Port (I2C mode) Address register BANK1:SSPSTAT 0x0094 SYNC SERIAL PORT STATUS REGISTER BANK1:SSPSTAT.D_A 5 Data/Address bit (I2C mode only) BANK1:SSPSTAT.P 4 STOP bit (I2C mode only) BANK1:SSPSTAT.S 3 START bit (I2C mode only) BANK1:SSPSTAT.R_W 2 Read/Write bit information (I2C mode only) BANK1:SSPSTAT.UA 1 Update Address (10-bit I2C mode only) BANK1:SSPSTAT.BF 0 Buffer Full Status bit BANK1:RESERVED0095 0x0095 RESERVED BANK1:RESERVED0096 0x0096 RESERVED BANK1:RESERVED0097 0x0097 RESERVED BANK1:TXSTA 0x0098 TRANSMIT STATUS AND CONTROL REGISTER BANK1:TXSTA.CSRC 7 Clock Source Select bit BANK1:TXSTA.TX9 6 9-bit Transmit Enable bit BANK1:TXSTA.TXEN 5 Transmit Enable bit BANK1:TXSTA.SYNC 4 USART Mode Select bit BANK1:TXSTA.BRGH 2 High Baud Rate Select bit BANK1:TXSTA.TRMT 1 Transmit Shift Register Status bit BANK1:TXSTA.TX9D 0 9th bit of Transmit Data BANK1:SPBRG 0x0099 Baud Rate Generator register BANK1:RESERVED009A 0x009A RESERVED BANK1:RESERVED009B 0x009B RESERVED BANK1:RESERVED009C 0x009C RESERVED BANK1:RESERVED009D 0x009D RESERVED BANK1:RESERVED009E 0x009E RESERVED BANK1:ADCON1 0x009F ADCON1 REGISTER (not implemented on the PIC16C63A/65B) BANK1:ADCON1.PCFG2 2 A/D Port Configuration Control bit 2 BANK1:ADCON1.PCFG1 1 A/D Port Configuration Control bit 1 BANK1:ADCON1.PCFG0 0 A/D Port Configuration Control bit 0 .16C63A ; http://www.microchip.com/download/lit/pline/picmicro/families/16c7x/30605c.pdf ; 16C63A65B_73B74B.pdf ; MEMORY MAP ; BANK_0 area DATA FSR_ 0x0000:0x0020 area DATA Gen_Purp 0x0020:0x0080 General Purpose Register area DATA MEM_Program0 0x0080:0x0800 On-chip Program Memory (Page 0) area DATA MEM_Program1 0x0800:0x1000 On-chip Program Memory (Page 1) ; BANK_1 ; area DATA FSR_ 0x0080:0x00A0 ; area DATA Gen_Purp 0x00A0:0x0100 General Purpose Register ; area DATA MEM_Program0 0x0100:0x0800 On-chip Program Memory (Page 0) ; area DATA MEM_Program1 0x0800:0x1000 On-chip Program Memory (Page 1) ; Interrupt and reset vector assignments interrupt RESET 0x0000 RESET ; INPUT/OUTPUT PORTS ; BANK0 (0x0000:0x0080) BANK0:INDF 0x0000 INDF (not a physical register) BANK0:TMR0 0x0001 Timer0 module's register BANK0:PCL 0x0002 Program Counter's (PC) Least Significant Byte BANK0:STATUS 0x0003 STATUS REGISTER BANK0:STATUS.IRP 7 Register Bank Select bit BANK0:STATUS.RP1 6 Register Bank Select bit 1 BANK0:STATUS.RP0 5 Register Bank Select bit 0 BANK0:STATUS.TO 4 Time-out bit BANK0:STATUS.PD 3 Power-down bit BANK0:STATUS.Z 2 Zero bit BANK0:STATUS.DC 1 Digit carry/borrow bit BANK0:STATUS.C 0 Carry/borrow bit BANK0:FSR 0x0004 Indirect data memory address pointer BANK0:PORTA 0x0005 PORTA REGISTER BANK0:PORTA.RA5 5 PORTA bit 5 BANK0:PORTA.RA4 4 PORTA bit 4 BANK0:PORTA.RA3 3 PORTA bit 3 BANK0:PORTA.RA2 2 PORTA bit 2 BANK0:PORTA.RA1 1 PORTA bit 1 BANK0:PORTA.RA0 0 PORTA bit 0 BANK0:PORTB 0x0006 PORTB REGISTER BANK0:PORTB.RB7 7 PORTB bit 7 BANK0:PORTB.RB6 6 PORTB bit 6 BANK0:PORTB.RB5 5 PORTB bit 5 BANK0:PORTB.RB4 4 PORTB bit 4 BANK0:PORTB.RB3 3 PORTB bit 3 BANK0:PORTB.RB2 2 PORTB bit 2 BANK0:PORTB.RB1 1 PORTB bit 1 BANK0:PORTB.RB0 0 PORTB bit 0 BANK0:PORTC 0x0007 PORTC REGISTER BANK0:PORTC.RC7 7 PORTC bit 7 BANK0:PORTC.RC6 6 PORTC bit 6 BANK0:PORTC.RC5 5 PORTC bit 5 BANK0:PORTC.RC4 4 PORTC bit 4 BANK0:PORTC.RC3 3 PORTC bit 3 BANK0:PORTC.RC2 2 PORTC bit 2 BANK0:PORTC.RC1 1 PORTC bit 1 BANK0:PORTC.RC0 0 PORTC bit 0 BANK0:PORTD 0x0008 PORTD REGISTER (not implemented on the PIC16C63A/73B) BANK0:PORTD.RD7 7 PORTD bit 7 BANK0:PORTD.RD6 6 PORTD bit 6 BANK0:PORTD.RD5 5 PORTD bit 5 BANK0:PORTD.RD4 4 PORTD bit 4 BANK0:PORTD.RD3 3 PORTD bit 3 BANK0:PORTD.RD2 2 PORTD bit 2 BANK0:PORTD.RD1 1 PORTD bit 1 BANK0:PORTD.RD0 0 PORTD bit 0 BANK0:PORTE 0x0009 PORTE REGISTER (not implemented on the PIC16C63A/73B) BANK0:PORTE.RE2 2 PORTE bit 2 BANK0:PORTE.RE1 1 PORTE bit 1 BANK0:PORTE.RE0 0 PORTE bit 0 BANK0:PCLATH 0x000A Write Buffer for the upper 5 bits of the Program Counter BANK0:INTCON 0x000B INTCON REGISTER BANK0:INTCON.GIE 7 Global Interrupt Enable bit BANK0:INTCON.PEIE 6 Peripheral Interrupt Enable bit BANK0:INTCON.T0IE 5 TMR0 Overflow Interrupt Enable bit BANK0:INTCON.INTE 4 RB0/INT External Interrupt Enable bit BANK0:INTCON.RBIE 3 RB Port Change Interrupt Enable bit BANK0:INTCON.T0IF 2 TMR0 Overflow Interrupt Flag bit BANK0:INTCON.INTF 1 RB0/INT External Interrupt Flag bit BANK0:INTCON.RBIF 0 RB Port Change Interrupt Flag bit BANK0:PIR1 0x000C PIR1 REGISTER BANK0:PIR1.PSPIF 7 (not implemented in PIC16C63A/73B) Parallel Slave Port Read/Write Interrupt Flag bit BANK0:PIR1.ADIF 6 (not implemented in PIC16C63A/65B) A/D Converter Interrupt Flag bit BANK0:PIR1.RCIF 5 USART Receive Interrupt Flag bit BANK0:PIR1.TXIF 4 USART Transmit Interrupt Flag bit BANK0:PIR1.SSPIF 3 Synchronous Serial Port Interrupt Flag bit BANK0:PIR1.CCP1IF 2 CCP1 Interrupt Flag bit BANK0:PIR1.TMR2IF 1 TMR2 to PR2 Match Interrupt Flag bit BANK0:PIR1.TMR1IF 0 TMR1 Overflow Interrupt Flag bit BANK0:PIR2 0x000D PIR2 REGISTER BANK0:PIR2.CCP2IF 0 CCP2 Interrupt Flag bit BANK0:TMR1L 0x000E Holding register for the Least Significant Byte of the 16-bit TMR1 register BANK0:TMR1H 0x000F Holding register for the Most Significant Byte of the 16-bit TMR1 register BANK0:T1CON 0x0010 TIMER1 CONTROL REGISTER BANK0:T1CON.T1CKPS1 5 Timer1 Input Clock Prescale Select bit 1 BANK0:T1CON.T1CKPS0 4 Timer1 Input Clock Prescale Select bit 0 BANK0:T1CON.T1OSCEN 3 Timer1 Oscillator Enable Control bit BANK0:T1CON.T1SYNC 2 Timer1 External Clock Input Synchronization Control bit BANK0:T1CON.TMR1CS 1 Timer1 Clock Source Select bit BANK0:T1CON.TMR1ON 0 Timer1 On bit BANK0:TMR2 0x0011 Timer2 module's register BANK0:T2CON 0x0012 TIMER2 CONTROL REGISTER BANK0:T2CON.TOUTPS3 6 Timer2 Output Postscale Select bit 3 BANK0:T2CON.TOUTPS2 5 Timer2 Output Postscale Select bit 2 BANK0:T2CON.TOUTPS1 4 Timer2 Output Postscale Select bit 1 BANK0:T2CON.TOUTPS0 3 Timer2 Output Postscale Select bit 0 BANK0:T2CON.TMR2ON 2 Timer2 On bit BANK0:T2CON.T2CKPS1 1 Timer2 Clock Prescale Select bit 1 BANK0:T2CON.T2CKPS0 0 Timer2 Clock Prescale Select bit 0 BANK0:SSPBUF 0x0013 Synchronous Serial Port Receive Buffer/Transmit Register BANK0:SSPCON 0x0014 SYNC SERIAL PORT CONTROL REGISTER BANK0:SSPCON.WCOL 7 Write Collision Flag bit BANK0:SSPCON.SSPOV 6 Synchronous Serial Port Overflow Flag bit BANK0:SSPCON.SSPEN 5 Synchronous Serial Port Enable bit BANK0:SSPCON.CKP 4 Clock Polarity Select bit BANK0:SSPCON.SSPM3 3 Synchronous Serial Port Mode Select bit 3 BANK0:SSPCON.SSPM2 2 Synchronous Serial Port Mode Select bit 2 BANK0:SSPCON.SSPM1 1 Synchronous Serial Port Mode Select bit 1 BANK0:SSPCON.SSPM0 0 Synchronous Serial Port Mode Select bit 0 BANK0:CCPR1L 0x0015 Capture/Compare/PWM Register1 (LSB) BANK0:CCPR1H 0x0016 Capture/Compare/PWM Register1 (MSB) BANK0:CCP1CON 0x0017 CCP1CON REGISTER BANK0:CCP1CON.CCP1X 5 PWM Least Significant bit BANK0:CCP1CON.CCP1Y 4 PWM Least Significant bit BANK0:CCP1CON.CCP1M3 3 CCP1 Mode Select bit 3 BANK0:CCP1CON.CCP1M2 2 CCP1 Mode Select bit 2 BANK0:CCP1CON.CCP1M1 1 CCP1 Mode Select bit 1 BANK0:CCP1CON.CCP1M0 0 CCP1 Mode Select bit 0 BANK0:RCSTA 0x0018 RECEIVE STATUS AND CONTROL REGISTER BANK0:RCSTA.SPEN 7 Serial Port Enable bit BANK0:RCSTA.RX9 6 9-bit Receive Enable bit BANK0:RCSTA.SREN 5 Single Receive Enable bit BANK0:RCSTA.CREN 4 Continuous Receive Enable bit BANK0:RCSTA.FERR 2 Framing Error bit BANK0:RCSTA.OERR 1 Overrun Error bit BANK0:RCSTA.RX9D 0 9th bit of Received Data BANK0:TXREG 0x0019 USART Transmit Data register BANK0:RCREG 0x001A USART Receive Data register BANK0:CCPR2L 0x001B Capture/Compare/PWM Register2 (LSB) BANK0:CCPR2H 0x001C Capture/Compare/PWM Register2 (MSB) BANK0:CCP2CON 0x001D CCP2CON REGISTER BANK0:CCP2CON.CCP2X 5 PWM Least Significant bit BANK0:CCP2CON.CCP2Y 4 PWM Least Significant bit BANK0:CCP2CON.CCP2M3 3 CCP2 Mode Select bit 3 BANK0:CCP2CON.CCP2M2 2 CCP2 Mode Select bit 2 BANK0:CCP2CON.CCP2M1 1 CCP2 Mode Select bit 1 BANK0:CCP2CON.CCP2M0 0 CCP2 Mode Select bit 0 BANK0:ADRES 0x001E A/D Result register (not implemented on the PIC16C63A/65B) BANK0:ADCON0 0x001F ADCON0 REGISTER (not implemented on the PIC16C63A/65B) BANK0:ADCON0.ADCS1 7 A/D Conversion Clock Select bit 1 BANK0:ADCON0.ADCS0 6 A/D Conversion Clock Select bit 0 BANK0:ADCON0.CHS2 5 Analog Channel Select bit 2 BANK0:ADCON0.CHS1 4 Analog Channel Select bit 1 BANK0:ADCON0.CHS0 3 Analog Channel Select bit 0 BANK0:ADCON0.GO_DONE 2 A/D Conversion Status bit BANK0:ADCON0.ADON 0 A/D On bit ; BANK1 (0x0080:0x0100) BANK1:INDF 0x0080 INDF (not a physical register) BANK1:OPTION 0x0081 OPTION REGISTER BANK1:OPTION.RBPU 7 PORTB Pull-up Enable bit BANK1:OPTION.INTEDG 6 Interrupt Edge Select bit BANK1:OPTION.T0CS 5 TMR0 Clock Source Select bit BANK1:OPTION.T0SE 4 TMR0 Source Edge Select bit BANK1:OPTION.PSA 3 Prescaler Assignment bit BANK1:OPTION.PS2 2 Prescaler Rate Select bit 2 BANK1:OPTION.PS1 1 Prescaler Rate Select bit 1 BANK1:OPTION.PS0 0 Prescaler Rate Select bit 0 BANK1:PCL 0x0082 Program Counter's (PC) Least Significant Byte BANK1:STATUS 0x0083 STATUS REGISTER BANK1:STATUS.IRP 7 Register Bank Select bit BANK1:STATUS.RP1 6 Register Bank Select bit 1 BANK1:STATUS.RP0 5 Register Bank Select bit 0 BANK1:STATUS.TO 4 Time-out bit BANK1:STATUS.PD 3 Power-down bit BANK1:STATUS.Z 2 Zero bit BANK1:STATUS.DC 1 Digit carry/borrow bit BANK1:STATUS.C 0 Carry/borrow bit BANK1:FSR 0x0084 Indirect data memory address pointer BANK1:TRISA 0x0085 PORTA Data Direction Register BANK1:TRISA.TRISA5 5 PORTA Data Direction Register bit 5 BANK1:TRISA.TRISA4 4 PORTA Data Direction Register bit 4 BANK1:TRISA.TRISA3 3 PORTA Data Direction Register bit 3 BANK1:TRISA.TRISA2 2 PORTA Data Direction Register bit 2 BANK1:TRISA.TRISA1 1 PORTA Data Direction Register bit 1 BANK1:TRISA.TRISA0 0 PORTA Data Direction Register bit 0 BANK1:TRISB 0x0086 PORTB Data Direction register BANK1:TRISB.TRISB7 7 PORTB Data Direction register bit 7 BANK1:TRISB.TRISB6 6 PORTB Data Direction register bit 6 BANK1:TRISB.TRISB5 5 PORTB Data Direction register bit 5 BANK1:TRISB.TRISB4 4 PORTB Data Direction register bit 4 BANK1:TRISB.TRISB3 3 PORTB Data Direction register bit 3 BANK1:TRISB.TRISB2 2 PORTB Data Direction register bit 2 BANK1:TRISB.TRISB1 1 PORTB Data Direction register bit 1 BANK1:TRISB.TRISB0 0 PORTB Data Direction register bit 0 BANK1:TRISC 0x0087 PORTC Data Direction register BANK1:TRISC.TRISC7 7 PORTC Data Direction register bit 7 BANK1:TRISC.TRISC6 6 PORTC Data Direction register bit 6 BANK1:TRISC.TRISC5 5 PORTC Data Direction register bit 5 BANK1:TRISC.TRISC4 4 PORTC Data Direction register bit 4 BANK1:TRISC.TRISC3 3 PORTC Data Direction register bit 3 BANK1:TRISC.TRISC2 2 PORTC Data Direction register bit 2 BANK1:TRISC.TRISC1 1 PORTC Data Direction register bit 1 BANK1:TRISC.TRISC0 0 PORTC Data Direction register bit 0 BANK1:TRISD 0x0088 PORTD Data Direction register (not implemented on the PIC16C63A/73B) BANK1:TRISD.TRISD7 7 PORTD Data Direction register bit 7 BANK1:TRISD.TRISD6 6 PORTD Data Direction register bit 6 BANK1:TRISD.TRISD5 5 PORTD Data Direction register bit 5 BANK1:TRISD.TRISD4 4 PORTD Data Direction register bit 4 BANK1:TRISD.TRISD3 3 PORTD Data Direction register bit 3 BANK1:TRISD.TRISD2 2 PORTD Data Direction register bit 2 BANK1:TRISD.TRISD1 1 PORTD Data Direction register bit 1 BANK1:TRISD.TRISD0 0 PORTD Data Direction register bit 0 BANK1:TRISE 0x0089 PORTE Data Direction register (not implemented on the PIC16C63A/73B) BANK1:TRISE.IBF 7 Input Buffer Full Status bit BANK1:TRISE.OBF 6 Output Buffer Full Status bit BANK1:TRISE.IBOV 5 Input Buffer Overflow Detect bit (in Microprocessor mode) BANK1:TRISE.PSPMODE 4 Parallel Slave Port Mode Select bit BANK1:TRISE.TRISE2 2 Direction Control bit for pin RE2/CS/AN7 BANK1:TRISE.TRISE1 1 Direction Control bit for pin RE1/WR/AN6 BANK1:TRISE.TRISE0 0 Direction Control bit for pin RE0/RD/AN5 BANK1:PCLATH 0x008A Write Buffer for the upper 5 bits of the Program Counter BANK1:INTCON 0x008B INTCON REGISTER BANK1:INTCON.GIE 7 Global Interrupt Enable bit BANK1:INTCON.PEIE 6 Peripheral Interrupt Enable bit BANK1:INTCON.T0IE 5 TMR0 Overflow Interrupt Enable bit BANK1:INTCON.INTE 4 RB0/INT External Interrupt Enable bit BANK1:INTCON.RBIE 3 RB Port Change Interrupt Enable bit BANK1:INTCON.T0IF 2 TMR0 Overflow Interrupt Flag bit BANK1:INTCON.INTF 1 RB0/INT External Interrupt Flag bit BANK1:INTCON.RBIF 0 RB Port Change Interrupt Flag bit BANK1:PIE1 0x008C PIE1 REGISTER BANK1:PIE1.PSPIE 7 (not implemented in PIC16C63A/73B) Parallel Slave Port Read/Write Interrupt Enable bit BANK1:PIE1.ADIE 6 (not implemented in PIC16C63A/65B) A/D Converter Interrupt Enable bit BANK1:PIE1.RCIE 5 USART Receive Interrupt Enable bit BANK1:PIE1.TXIE 4 USART Transmit Interrupt Enable bit BANK1:PIE1.SSPIE 3 Synchronous Serial Port Interrupt Enable bit BANK1:PIE1.CCP1IE 2 CCP1 Interrupt Enable bit BANK1:PIE1.TMR2IE 1 TMR2 to PR2 Match Interrupt Enable bit BANK1:PIE1.TMR1IE 0 TMR1 Overflow Interrupt Enable bit BANK1:PIE2 0x008D PIE2 REGISTER BANK1:PIE2.CCP2IE 0 CCP2 Interrupt Enable bit BANK1:PCON 0x008E PCON REGISTER BANK1:PCON.POR 1 Power-on Reset Status bit BANK1:PCON.BOR 0 Brown-out Reset Status bit BANK1:RESERVED000F 0x008F RESERVED BANK1:RESERVED0090 0x0090 RESERVED BANK1:RESERVED0091 0x0091 RESERVED BANK1:PR2 0x0092 Timer2 Period register BANK1:SSPADD 0x0093 Synchronous Serial Port (I2C mode) Address register BANK1:SSPSTAT 0x0094 SYNC SERIAL PORT STATUS REGISTER BANK1:SSPSTAT.D_A 5 Data/Address bit (I2C mode only) BANK1:SSPSTAT.P 4 STOP bit (I2C mode only) BANK1:SSPSTAT.S 3 START bit (I2C mode only) BANK1:SSPSTAT.R_W 2 Read/Write bit information (I2C mode only) BANK1:SSPSTAT.UA 1 Update Address (10-bit I2C mode only) BANK1:SSPSTAT.BF 0 Buffer Full Status bit BANK1:RESERVED0095 0x0095 RESERVED BANK1:RESERVED0096 0x0096 RESERVED BANK1:RESERVED0097 0x0097 RESERVED BANK1:TXSTA 0x0098 TRANSMIT STATUS AND CONTROL REGISTER BANK1:TXSTA.CSRC 7 Clock Source Select bit BANK1:TXSTA.TX9 6 9-bit Transmit Enable bit BANK1:TXSTA.TXEN 5 Transmit Enable bit BANK1:TXSTA.SYNC 4 USART Mode Select bit BANK1:TXSTA.BRGH 2 High Baud Rate Select bit BANK1:TXSTA.TRMT 1 Transmit Shift Register Status bit BANK1:TXSTA.TX9D 0 9th bit of Transmit Data BANK1:SPBRG 0x0099 Baud Rate Generator register BANK1:RESERVED009A 0x009A RESERVED BANK1:RESERVED009B 0x009B RESERVED BANK1:RESERVED009C 0x009C RESERVED BANK1:RESERVED009D 0x009D RESERVED BANK1:RESERVED009E 0x009E RESERVED BANK1:ADCON1 0x009F ADCON1 REGISTER (not implemented on the PIC16C63A/65B) BANK1:ADCON1.PCFG2 2 A/D Port Configuration Control bit 2 BANK1:ADCON1.PCFG1 1 A/D Port Configuration Control bit 1 BANK1:ADCON1.PCFG0 0 A/D Port Configuration Control bit 0 .16C641 ; http://www.microchip.com/download/lit/pline/picmicro/families/16c6xx/30559a.pdf ; PIC16C64X_66X.pdf ; MEMORY MAP ; BANK_0 area DATA FSR_ 0x0000:0x0020 area DATA Gen_Purp 0x0020:0x0080 General Purpose Register area DATA MEM_Program 0x0080:0x0800 On-chip Program Memory ; BANK_1 ; area DATA FSR_ 0x0080:0x00A0 ; area DATA Gen_Purp 0x00A0:0x00F0 General Purpose Register ; area DATA Gen_Purp_BANK0 0x00F0:0x0100 Mapped in Bank 0 ; area DATA MEM_Program 0x0100:0x0800 On-chip Program Memory ; Interrupt and reset vector assignments interrupt RESET 0x0000 RESET ; INPUT/OUTPUT PORTS ; BANK0 (0x0000:0x0080) BANK0:INDF 0x0000 INDF (not a physical register) BANK0:TMR0 0x0001 Timer0 module's register BANK0:PCL 0x0002 Program Counter's (PC) Least Significant Byte BANK0:STATUS 0x0003 STATUS REGISTER BANK0:STATUS.RP0 5 Register Bank Select bit 0 BANK0:STATUS.TO 4 Time-out bit BANK0:STATUS.PD 3 Power-down bit BANK0:STATUS.Z 2 Zero bit BANK0:STATUS.DC 1 Digit carry/borrow bit BANK0:STATUS.C 0 Carry/borrow bit BANK0:FSR 0x0004 Indirect data memory address pointer BANK0:PORTA 0x0005 PORTA REGISTER BANK0:PORTA.RA5 5 PORTA bit 5 BANK0:PORTA.RA4 4 PORTA bit 4 BANK0:PORTA.RA3 3 PORTA bit 3 BANK0:PORTA.RA2 2 PORTA bit 2 BANK0:PORTA.RA1 1 PORTA bit 1 BANK0:PORTA.RA0 0 PORTA bit 0 BANK0:PORTB 0x0006 PORTB REGISTER BANK0:PORTB.RB7 7 PORTB bit 7 BANK0:PORTB.RB6 6 PORTB bit 6 BANK0:PORTB.RB5 5 PORTB bit 5 BANK0:PORTB.RB4 4 PORTB bit 4 BANK0:PORTB.RB3 3 PORTB bit 3 BANK0:PORTB.RB2 2 PORTB bit 2 BANK0:PORTB.RB1 1 PORTB bit 1 BANK0:PORTB.RB0 0 PORTB bit 0 BANK0:PORTC 0x0007 PORTC REGISTER BANK0:PORTC.RC7 7 PORTC bit 7 BANK0:PORTC.RC6 6 PORTC bit 6 BANK0:PORTC.RC5 5 PORTC bit 5 BANK0:PORTC.RC4 4 PORTC bit 4 BANK0:PORTC.RC3 3 PORTC bit 3 BANK0:PORTC.RC2 2 PORTC bit 2 BANK0:PORTC.RC1 1 PORTC bit 1 BANK0:PORTC.RC0 0 PORTC bit 0 BANK0:RESERVED0008 0x0008 RESERVED BANK0:RESERVED0009 0x0009 RESERVED BANK0:PCLATH 0x000A Write buffer for upper 5 bits of program counter BANK0:INTCON 0x000B INTCON REGISTER BANK0:INTCON.GIE 7 Global Interrupt Enable bit BANK0:INTCON.PEIE 6 Peripheral Interrupt Enable bit BANK0:INTCON.T0IE 5 TMR0 Overflow Interrupt Enable bit BANK0:INTCON.INTE 4 RB0/INT External Interrupt Enable bit BANK0:INTCON.RBIE 3 RB Port Change Interrupt Enable bit BANK0:INTCON.T0IF 2 TMR0 Overflow Interrupt Flag bit BANK0:INTCON.INTF 1 RB0/INT External Interrupt Flag bit BANK0:INTCON.RBIF 0 RB Port Change Interrupt Flag bit BANK0:PIR1 0x000C PIR1 REGISTER BANK0:PIR1.CMIF 6 Comparator Interrupt Flag bit BANK0:RESERVED000D 0x000D RESERVED BANK0:RESERVED000E 0x000E RESERVED BANK0:RESERVED000F 0x000F RESERVED BANK0:RESERVED0010 0x0010 RESERVED BANK0:RESERVED0011 0x0011 RESERVED BANK0:RESERVED0012 0x0012 RESERVED BANK0:RESERVED0013 0x0013 RESERVED BANK0:RESERVED0014 0x0014 RESERVED BANK0:RESERVED0015 0x0015 RESERVED BANK0:RESERVED0016 0x0016 RESERVED BANK0:RESERVED0017 0x0017 RESERVED BANK0:RESERVED0018 0x0018 RESERVED BANK0:RESERVED0019 0x0019 RESERVED BANK0:RESERVED001A 0x001A RESERVED BANK0:RESERVED001B 0x001B RESERVED BANK0:RESERVED001C 0x001C RESERVED BANK0:RESERVED001D 0x001D RESERVED BANK0:RESERVED001E 0x001E RESERVED BANK0:CMCON 0x001F CMCON REGISTER BANK0:CMCON.C2OUT 7 Comparator 2 output BANK0:CMCON.C1OUT 6 Comparator 1 output BANK0:CMCON.CIS 3 Comparator Input Switch BANK0:CMCON.CM2 2 Comparator mode 2 BANK0:CMCON.CM1 1 Comparator mode 1 BANK0:CMCON.CM0 0 Comparator mode 0 ; BANK1 (0x0080:0x0100) BANK1:INDF 0x0080 INDF (not a physical register) BANK1:OPTION 0x0081 OPTION REGISTER BANK1:OPTION.RBPU 7 PORTB Pull-up Enable bit BANK1:OPTION.INTEDG 6 Interrupt Edge Select bit BANK1:OPTION.T0CS 5 TMR0 Clock Source Select bit BANK1:OPTION.T0SE 4 TMR0 Source Edge Select bit BANK1:OPTION.PSA 3 Prescaler Assignment bit BANK1:OPTION.PS2 2 Prescaler Rate Select bit 2 BANK1:OPTION.PS1 1 Prescaler Rate Select bit 1 BANK1:OPTION.PS0 0 Prescaler Rate Select bit 0 BANK1:PCL 0x0082 Program Counter's (PC) Least Significant Byte BANK1:STATUS 0x0083 STATUS REGISTER BANK1:STATUS.RP0 5 Register Bank Select bit 0 BANK1:STATUS.TO 4 Time-out bit BANK1:STATUS.PD 3 Power-down bit BANK1:STATUS.Z 2 Zero bit BANK1:STATUS.DC 1 Digit carry/borrow bit BANK1:STATUS.C 0 Carry/borrow bit BANK1:FSR 0x0084 Indirect data memory address pointer BANK1:TRISA 0x0085 TRISA REGISTER BANK1:TRISA.TRISA5 5 TRISA bit 5 BANK1:TRISA.TRISA4 4 TRISA bit 4 BANK1:TRISA.TRISA3 3 TRISA bit 3 BANK1:TRISA.TRISA2 2 TRISA bit 2 BANK1:TRISA.TRISA1 1 TRISA bit 1 BANK1:TRISA.TRISA0 0 TRISA bit 0 BANK1:TRISB 0x0086 TRISB REGISTER BANK1:TRISB.TRISB7 7 TRISB bit 7 BANK1:TRISB.TRISB6 6 TRISB bit 6 BANK1:TRISB.TRISB5 5 TRISB bit 5 BANK1:TRISB.TRISB4 4 TRISB bit 4 BANK1:TRISB.TRISB3 3 TRISB bit 3 BANK1:TRISB.TRISB2 2 TRISB bit 2 BANK1:TRISB.TRISB1 1 TRISB bit 1 BANK1:TRISB.TRISB0 0 TRISB bit 0 BANK1:TRISC 0x0087 TRISC REGISTER BANK1:TRISC.TRISC7 7 TRISC bit 7 BANK1:TRISC.TRISC6 6 TRISC bit 6 BANK1:TRISC.TRISC5 5 TRISC bit 5 BANK1:TRISC.TRISC4 4 TRISC bit 4 BANK1:TRISC.TRISC3 3 TRISC bit 3 BANK1:TRISC.TRISC2 2 TRISC bit 2 BANK1:TRISC.TRISC1 1 TRISC bit 1 BANK1:TRISC.TRISC0 0 TRISC bit 0 BANK1:RESERVED0088 0x0088 RESERVED BANK1:RESERVED0089 0x0089 RESERVED BANK1:PCLATH 0x008A Write buffer for upper 5 bits of program counter BANK1:INTCON 0x008B INTCON REGISTER BANK1:INTCON.GIE 7 Global Interrupt Enable bit BANK1:INTCON.PEIE 6 Peripheral Interrupt Enable bit BANK1:INTCON.T0IE 5 TMR0 Overflow Interrupt Enable bit BANK1:INTCON.INTE 4 RB0/INT External Interrupt Enable bit BANK1:INTCON.RBIE 3 RB Port Change Interrupt Enable bit BANK1:INTCON.T0IF 2 TMR0 Overflow Interrupt Flag bit BANK1:INTCON.INTF 1 RB0/INT External Interrupt Flag bit BANK1:INTCON.RBIF 0 RB Port Change Interrupt Flag bit BANK1:PIE1 0x008C PIE1 REGISTER BANK1:PIE1.CMIE 6 Comparator Interrupt Enable bit BANK1:RESERVED008D 0x008D RESERVED BANK1:PCON 0x008E PCON REGISTER BANK1:PCON.MPEEN 7 Memory Parity Error Circuitry Status bit BANK1:PCON.PER 2 Memory Parity Error Reset Status bit BANK1:PCON.POR 1 Power-on Reset Status bit BANK1:PCON.BOR 0 Brown-out Reset Status bit BANK1:RESERVED008F 0x008F RESERVED BANK1:RESERVED0090 0x0090 RESERVED BANK1:RESERVED0091 0x0091 RESERVED BANK1:RESERVED0092 0x0092 RESERVED BANK1:RESERVED0093 0x0093 RESERVED BANK1:RESERVED0094 0x0094 RESERVED BANK1:RESERVED0095 0x0095 RESERVED BANK1:RESERVED0096 0x0096 RESERVED BANK1:RESERVED0097 0x0097 RESERVED BANK1:RESERVED0098 0x0098 RESERVED BANK1:RESERVED0099 0x0099 RESERVED BANK1:RESERVED009A 0x009A RESERVED BANK1:RESERVED009B 0x009B RESERVED BANK1:RESERVED009C 0x009C RESERVED BANK1:RESERVED009D 0x009D RESERVED BANK1:RESERVED009E 0x009E RESERVED BANK1:VRCON 0x009F VRCON REGISTER BANK1:VRCON.VREN 7 VREF Enable BANK1:VRCON.VROE 6 VREF Output Enable BANK1:VRCON.VRR 5 VREF Range selection BANK1:VRCON.VR3 3 VREF value selection 3 BANK1:VRCON.VR2 2 VREF value selection 2 BANK1:VRCON.VR1 1 VREF value selection 1 BANK1:VRCON.VR0 0 VREF value selection 0 .16C642 ; http://www.microchip.com/download/lit/pline/picmicro/families/16c6xx/30559a.pdf ; PIC16C64X_66X.pdf ; MEMORY MAP ; BANK_0 area DATA FSR_ 0x0000:0x0020 area DATA Gen_Purp 0x0020:0x0080 General Purpose Register area DATA MEM_Program0 0x0080:0x0800 On-chip Program Memory (Page 0) area DATA MEM_Program1 0x0800:0x1000 On-chip Program Memory (Page 1) ; BANK_1 ; area DATA FSR_ 0x0080:0x00A0 ; area DATA Gen_Purp 0x00A0:0x00F0 General Purpose Register ; area DATA Gen_Purp_BANK0 0x00F0:0x0100 Mapped in Bank 0 ; area DATA MEM_Program0 0x0100:0x0800 On-chip Program Memory (Page 0) ; area DATA MEM_Program1 0x0800:0x1000 On-chip Program Memory (Page 1) ; Interrupt and reset vector assignments interrupt RESET 0x0000 RESET ; INPUT/OUTPUT PORTS ; BANK0 (0x0000:0x0080) BANK0:INDF 0x0000 INDF (not a physical register) BANK0:TMR0 0x0001 Timer0 module's register BANK0:PCL 0x0002 Program Counter's (PC) Least Significant Byte BANK0:STATUS 0x0003 STATUS REGISTER BANK0:STATUS.RP0 5 Register Bank Select bit 0 BANK0:STATUS.TO 4 Time-out bit BANK0:STATUS.PD 3 Power-down bit BANK0:STATUS.Z 2 Zero bit BANK0:STATUS.DC 1 Digit carry/borrow bit BANK0:STATUS.C 0 Carry/borrow bit BANK0:FSR 0x0004 Indirect data memory address pointer BANK0:PORTA 0x0005 PORTA REGISTER BANK0:PORTA.RA5 5 PORTA bit 5 BANK0:PORTA.RA4 4 PORTA bit 4 BANK0:PORTA.RA3 3 PORTA bit 3 BANK0:PORTA.RA2 2 PORTA bit 2 BANK0:PORTA.RA1 1 PORTA bit 1 BANK0:PORTA.RA0 0 PORTA bit 0 BANK0:PORTB 0x0006 PORTB REGISTER BANK0:PORTB.RB7 7 PORTB bit 7 BANK0:PORTB.RB6 6 PORTB bit 6 BANK0:PORTB.RB5 5 PORTB bit 5 BANK0:PORTB.RB4 4 PORTB bit 4 BANK0:PORTB.RB3 3 PORTB bit 3 BANK0:PORTB.RB2 2 PORTB bit 2 BANK0:PORTB.RB1 1 PORTB bit 1 BANK0:PORTB.RB0 0 PORTB bit 0 BANK0:PORTC 0x0007 PORTC REGISTER BANK0:PORTC.RC7 7 PORTC bit 7 BANK0:PORTC.RC6 6 PORTC bit 6 BANK0:PORTC.RC5 5 PORTC bit 5 BANK0:PORTC.RC4 4 PORTC bit 4 BANK0:PORTC.RC3 3 PORTC bit 3 BANK0:PORTC.RC2 2 PORTC bit 2 BANK0:PORTC.RC1 1 PORTC bit 1 BANK0:PORTC.RC0 0 PORTC bit 0 BANK0:RESERVED0008 0x0008 RESERVED BANK0:RESERVED0009 0x0009 RESERVED BANK0:PCLATH 0x000A Write buffer for upper 5 bits of program counter BANK0:INTCON 0x000B INTCON REGISTER BANK0:INTCON.GIE 7 Global Interrupt Enable bit BANK0:INTCON.PEIE 6 Peripheral Interrupt Enable bit BANK0:INTCON.T0IE 5 TMR0 Overflow Interrupt Enable bit BANK0:INTCON.INTE 4 RB0/INT External Interrupt Enable bit BANK0:INTCON.RBIE 3 RB Port Change Interrupt Enable bit BANK0:INTCON.T0IF 2 TMR0 Overflow Interrupt Flag bit BANK0:INTCON.INTF 1 RB0/INT External Interrupt Flag bit BANK0:INTCON.RBIF 0 RB Port Change Interrupt Flag bit BANK0:PIR1 0x000C PIR1 REGISTER BANK0:PIR1.CMIF 6 Comparator Interrupt Flag bit BANK0:RESERVED000D 0x000D RESERVED BANK0:RESERVED000E 0x000E RESERVED BANK0:RESERVED000F 0x000F RESERVED BANK0:RESERVED0010 0x0010 RESERVED BANK0:RESERVED0011 0x0011 RESERVED BANK0:RESERVED0012 0x0012 RESERVED BANK0:RESERVED0013 0x0013 RESERVED BANK0:RESERVED0014 0x0014 RESERVED BANK0:RESERVED0015 0x0015 RESERVED BANK0:RESERVED0016 0x0016 RESERVED BANK0:RESERVED0017 0x0017 RESERVED BANK0:RESERVED0018 0x0018 RESERVED BANK0:RESERVED0019 0x0019 RESERVED BANK0:RESERVED001A 0x001A RESERVED BANK0:RESERVED001B 0x001B RESERVED BANK0:RESERVED001C 0x001C RESERVED BANK0:RESERVED001D 0x001D RESERVED BANK0:RESERVED001E 0x001E RESERVED BANK0:CMCON 0x001F CMCON REGISTER BANK0:CMCON.C2OUT 7 Comparator 2 output BANK0:CMCON.C1OUT 6 Comparator 1 output BANK0:CMCON.CIS 3 Comparator Input Switch BANK0:CMCON.CM2 2 Comparator mode 2 BANK0:CMCON.CM1 1 Comparator mode 1 BANK0:CMCON.CM0 0 Comparator mode 0 ; BANK1 (0x0080:0x0100) BANK1:INDF 0x0080 INDF (not a physical register) BANK1:OPTION 0x0081 OPTION REGISTER BANK1:OPTION.RBPU 7 PORTB Pull-up Enable bit BANK1:OPTION.INTEDG 6 Interrupt Edge Select bit BANK1:OPTION.T0CS 5 TMR0 Clock Source Select bit BANK1:OPTION.T0SE 4 TMR0 Source Edge Select bit BANK1:OPTION.PSA 3 Prescaler Assignment bit BANK1:OPTION.PS2 2 Prescaler Rate Select bit 2 BANK1:OPTION.PS1 1 Prescaler Rate Select bit 1 BANK1:OPTION.PS0 0 Prescaler Rate Select bit 0 BANK1:PCL 0x0082 Program Counter's (PC) Least Significant Byte BANK1:STATUS 0x0083 STATUS REGISTER BANK1:STATUS.RP0 5 Register Bank Select bit 0 BANK1:STATUS.TO 4 Time-out bit BANK1:STATUS.PD 3 Power-down bit BANK1:STATUS.Z 2 Zero bit BANK1:STATUS.DC 1 Digit carry/borrow bit BANK1:STATUS.C 0 Carry/borrow bit BANK1:FSR 0x0084 Indirect data memory address pointer BANK1:TRISA 0x0085 TRISA REGISTER BANK1:TRISA.TRISA5 5 TRISA bit 5 BANK1:TRISA.TRISA4 4 TRISA bit 4 BANK1:TRISA.TRISA3 3 TRISA bit 3 BANK1:TRISA.TRISA2 2 TRISA bit 2 BANK1:TRISA.TRISA1 1 TRISA bit 1 BANK1:TRISA.TRISA0 0 TRISA bit 0 BANK1:TRISB 0x0086 TRISB REGISTER BANK1:TRISB.TRISB7 7 TRISB bit 7 BANK1:TRISB.TRISB6 6 TRISB bit 6 BANK1:TRISB.TRISB5 5 TRISB bit 5 BANK1:TRISB.TRISB4 4 TRISB bit 4 BANK1:TRISB.TRISB3 3 TRISB bit 3 BANK1:TRISB.TRISB2 2 TRISB bit 2 BANK1:TRISB.TRISB1 1 TRISB bit 1 BANK1:TRISB.TRISB0 0 TRISB bit 0 BANK1:TRISC 0x0087 TRISC REGISTER BANK1:TRISC.TRISC7 7 TRISC bit 7 BANK1:TRISC.TRISC6 6 TRISC bit 6 BANK1:TRISC.TRISC5 5 TRISC bit 5 BANK1:TRISC.TRISC4 4 TRISC bit 4 BANK1:TRISC.TRISC3 3 TRISC bit 3 BANK1:TRISC.TRISC2 2 TRISC bit 2 BANK1:TRISC.TRISC1 1 TRISC bit 1 BANK1:TRISC.TRISC0 0 TRISC bit 0 BANK1:RESERVED0088 0x0088 RESERVED BANK1:RESERVED0089 0x0089 RESERVED BANK1:PCLATH 0x008A Write buffer for upper 5 bits of program counter BANK1:INTCON 0x008B INTCON REGISTER BANK1:INTCON.GIE 7 Global Interrupt Enable bit BANK1:INTCON.PEIE 6 Peripheral Interrupt Enable bit BANK1:INTCON.T0IE 5 TMR0 Overflow Interrupt Enable bit BANK1:INTCON.INTE 4 RB0/INT External Interrupt Enable bit BANK1:INTCON.RBIE 3 RB Port Change Interrupt Enable bit BANK1:INTCON.T0IF 2 TMR0 Overflow Interrupt Flag bit BANK1:INTCON.INTF 1 RB0/INT External Interrupt Flag bit BANK1:INTCON.RBIF 0 RB Port Change Interrupt Flag bit BANK1:PIE1 0x008C PIE1 REGISTER BANK1:PIE1.CMIE 6 Comparator Interrupt Enable bit BANK1:RESERVED008D 0x008D RESERVED BANK1:PCON 0x008E PCON REGISTER BANK1:PCON.MPEEN 7 Memory Parity Error Circuitry Status bit BANK1:PCON.PER 2 Memory Parity Error Reset Status bit BANK1:PCON.POR 1 Power-on Reset Status bit BANK1:PCON.BOR 0 Brown-out Reset Status bit BANK1:RESERVED008F 0x008F RESERVED BANK1:RESERVED0090 0x0090 RESERVED BANK1:RESERVED0091 0x0091 RESERVED BANK1:RESERVED0092 0x0092 RESERVED BANK1:RESERVED0093 0x0093 RESERVED BANK1:RESERVED0094 0x0094 RESERVED BANK1:RESERVED0095 0x0095 RESERVED BANK1:RESERVED0096 0x0096 RESERVED BANK1:RESERVED0097 0x0097 RESERVED BANK1:RESERVED0098 0x0098 RESERVED BANK1:RESERVED0099 0x0099 RESERVED BANK1:RESERVED009A 0x009A RESERVED BANK1:RESERVED009B 0x009B RESERVED BANK1:RESERVED009C 0x009C RESERVED BANK1:RESERVED009D 0x009D RESERVED BANK1:RESERVED009E 0x009E RESERVED BANK1:VRCON 0x009F VRCON REGISTER BANK1:VRCON.VREN 7 VREF Enable BANK1:VRCON.VROE 6 VREF Output Enable BANK1:VRCON.VRR 5 VREF Range selection BANK1:VRCON.VR3 3 VREF value selection 3 BANK1:VRCON.VR2 2 VREF value selection 2 BANK1:VRCON.VR1 1 VREF value selection 1 BANK1:VRCON.VR0 0 VREF value selection 0 .16C661 ; http://www.microchip.com/download/lit/pline/picmicro/families/16c6xx/30559a.pdf ; PIC16C64X_66X.pdf ; MEMORY MAP ; BANK_0 area DATA FSR_ 0x0000:0x0020 area DATA Gen_Purp 0x0020:0x0080 General Purpose Register area DATA MEM_Program 0x0080:0x0800 On-chip Program Memory ; BANK_1 ; area DATA FSR_ 0x0080:0x00A0 ; area DATA Gen_Purp 0x00A0:0x00F0 General Purpose Register ; area DATA Gen_Purp_BANK0 0x00F0:0x0100 Mapped in Bank 0 ; area DATA MEM_Program 0x0100:0x0800 On-chip Program Memory ; Interrupt and reset vector assignments interrupt RESET 0x0000 RESET ; INPUT/OUTPUT PORTS ; BANK0 (0x0000:0x0080) BANK0:INDF 0x0000 INDF (not a physical register) BANK0:TMR0 0x0001 Timer0 module's register BANK0:PCL 0x0002 Program Counter's (PC) Least Significant Byte BANK0:STATUS 0x0003 STATUS REGISTER BANK0:STATUS.RP0 5 Register Bank Select bit 0 BANK0:STATUS.TO 4 Time-out bit BANK0:STATUS.PD 3 Power-down bit BANK0:STATUS.Z 2 Zero bit BANK0:STATUS.DC 1 Digit carry/borrow bit BANK0:STATUS.C 0 Carry/borrow bit BANK0:FSR 0x0004 Indirect data memory address pointer BANK0:PORTA 0x0005 PORTA REGISTER BANK0:PORTA.RA5 5 PORTA bit 5 BANK0:PORTA.RA4 4 PORTA bit 4 BANK0:PORTA.RA3 3 PORTA bit 3 BANK0:PORTA.RA2 2 PORTA bit 2 BANK0:PORTA.RA1 1 PORTA bit 1 BANK0:PORTA.RA0 0 PORTA bit 0 BANK0:PORTB 0x0006 PORTB REGISTER BANK0:PORTB.RB7 7 PORTB bit 7 BANK0:PORTB.RB6 6 PORTB bit 6 BANK0:PORTB.RB5 5 PORTB bit 5 BANK0:PORTB.RB4 4 PORTB bit 4 BANK0:PORTB.RB3 3 PORTB bit 3 BANK0:PORTB.RB2 2 PORTB bit 2 BANK0:PORTB.RB1 1 PORTB bit 1 BANK0:PORTB.RB0 0 PORTB bit 0 BANK0:PORTC 0x0007 PORTC REGISTER BANK0:PORTC.RC7 7 PORTC bit 7 BANK0:PORTC.RC6 6 PORTC bit 6 BANK0:PORTC.RC5 5 PORTC bit 5 BANK0:PORTC.RC4 4 PORTC bit 4 BANK0:PORTC.RC3 3 PORTC bit 3 BANK0:PORTC.RC2 2 PORTC bit 2 BANK0:PORTC.RC1 1 PORTC bit 1 BANK0:PORTC.RC0 0 PORTC bit 0 BANK0:PORTD 0x0008 PORTD REGISTER BANK0:PORTD.RD7 7 PORTD bit 7 BANK0:PORTD.RD6 6 PORTD bit 6 BANK0:PORTD.RD5 5 PORTD bit 5 BANK0:PORTD.RD4 4 PORTD bit 4 BANK0:PORTD.RD3 3 PORTD bit 3 BANK0:PORTD.RD2 2 PORTD bit 2 BANK0:PORTD.RD1 1 PORTD bit 1 BANK0:PORTD.RD0 0 PORTD bit 0 BANK0:PORTE 0x0009 PORTE REGISTER BANK0:PORTE.RE2 2 PORTE bit 2 BANK0:PORTE.RE1 1 PORTE bit 1 BANK0:PORTE.RE0 0 PORTE bit 0 BANK0:PCLATH 0x000A Write buffer for upper 5 bits of program counter BANK0:INTCON 0x000B INTCON REGISTER BANK0:INTCON.GIE 7 Global Interrupt Enable bit BANK0:INTCON.PEIE 6 Peripheral Interrupt Enable bit BANK0:INTCON.T0IE 5 TMR0 Overflow Interrupt Enable bit BANK0:INTCON.INTE 4 RB0/INT External Interrupt Enable bit BANK0:INTCON.RBIE 3 RB Port Change Interrupt Enable bit BANK0:INTCON.T0IF 2 TMR0 Overflow Interrupt Flag bit BANK0:INTCON.INTF 1 RB0/INT External Interrupt Flag bit BANK0:INTCON.RBIF 0 RB Port Change Interrupt Flag bit BANK0:PIR1 0x000C PIR1 REGISTER BANK0:PIR1.PSPIF 7 Parallel Slave Port Interrupt Flag bit BANK0:PIR1.CMIF 6 Comparator Interrupt Flag bit BANK0:RESERVED000D 0x000D RESERVED BANK0:RESERVED000E 0x000E RESERVED BANK0:RESERVED000F 0x000F RESERVED BANK0:RESERVED0010 0x0010 RESERVED BANK0:RESERVED0011 0x0011 RESERVED BANK0:RESERVED0012 0x0012 RESERVED BANK0:RESERVED0013 0x0013 RESERVED BANK0:RESERVED0014 0x0014 RESERVED BANK0:RESERVED0015 0x0015 RESERVED BANK0:RESERVED0016 0x0016 RESERVED BANK0:RESERVED0017 0x0017 RESERVED BANK0:RESERVED0018 0x0018 RESERVED BANK0:RESERVED0019 0x0019 RESERVED BANK0:RESERVED001A 0x001A RESERVED BANK0:RESERVED001B 0x001B RESERVED BANK0:RESERVED001C 0x001C RESERVED BANK0:RESERVED001D 0x001D RESERVED BANK0:RESERVED001E 0x001E RESERVED BANK0:CMCON 0x001F CMCON REGISTER BANK0:CMCON.C2OUT 7 Comparator 2 output BANK0:CMCON.C1OUT 6 Comparator 1 output BANK0:CMCON.CIS 3 Comparator Input Switch BANK0:CMCON.CM2 2 Comparator mode 2 BANK0:CMCON.CM1 1 Comparator mode 1 BANK0:CMCON.CM0 0 Comparator mode 0 ; BANK1 (0x0080:0x0100) BANK1:INDF 0x0080 INDF (not a physical register) BANK1:OPTION 0x0081 OPTION REGISTER BANK1:OPTION.RBPU 7 PORTB Pull-up Enable bit BANK1:OPTION.INTEDG 6 Interrupt Edge Select bit BANK1:OPTION.T0CS 5 TMR0 Clock Source Select bit BANK1:OPTION.T0SE 4 TMR0 Source Edge Select bit BANK1:OPTION.PSA 3 Prescaler Assignment bit BANK1:OPTION.PS2 2 Prescaler Rate Select bit 2 BANK1:OPTION.PS1 1 Prescaler Rate Select bit 1 BANK1:OPTION.PS0 0 Prescaler Rate Select bit 0 BANK1:PCL 0x0082 Program Counter's (PC) Least Significant Byte BANK1:STATUS 0x0083 STATUS REGISTER BANK1:STATUS.RP0 5 Register Bank Select bit 0 BANK1:STATUS.TO 4 Time-out bit BANK1:STATUS.PD 3 Power-down bit BANK1:STATUS.Z 2 Zero bit BANK1:STATUS.DC 1 Digit carry/borrow bit BANK1:STATUS.C 0 Carry/borrow bit BANK1:FSR 0x0084 Indirect data memory address pointer BANK1:TRISA 0x0085 TRISA REGISTER BANK1:TRISA.TRISA5 5 TRISA bit 5 BANK1:TRISA.TRISA4 4 TRISA bit 4 BANK1:TRISA.TRISA3 3 TRISA bit 3 BANK1:TRISA.TRISA2 2 TRISA bit 2 BANK1:TRISA.TRISA1 1 TRISA bit 1 BANK1:TRISA.TRISA0 0 TRISA bit 0 BANK1:TRISB 0x0086 TRISB REGISTER BANK1:TRISB.TRISB7 7 TRISB bit 7 BANK1:TRISB.TRISB6 6 TRISB bit 6 BANK1:TRISB.TRISB5 5 TRISB bit 5 BANK1:TRISB.TRISB4 4 TRISB bit 4 BANK1:TRISB.TRISB3 3 TRISB bit 3 BANK1:TRISB.TRISB2 2 TRISB bit 2 BANK1:TRISB.TRISB1 1 TRISB bit 1 BANK1:TRISB.TRISB0 0 TRISB bit 0 BANK1:TRISC 0x0087 TRISC REGISTER BANK1:TRISC.TRISC7 7 TRISC bit 7 BANK1:TRISC.TRISC6 6 TRISC bit 6 BANK1:TRISC.TRISC5 5 TRISC bit 5 BANK1:TRISC.TRISC4 4 TRISC bit 4 BANK1:TRISC.TRISC3 3 TRISC bit 3 BANK1:TRISC.TRISC2 2 TRISC bit 2 BANK1:TRISC.TRISC1 1 TRISC bit 1 BANK1:TRISC.TRISC0 0 TRISC bit 0 BANK1:TRISD 0x0088 TRISD REGISTER BANK1:TRISD.TRISD7 7 TRISD bit 7 BANK1:TRISD.TRISD6 6 TRISD bit 6 BANK1:TRISD.TRISD5 5 TRISD bit 5 BANK1:TRISD.TRISD4 4 TRISD bit 4 BANK1:TRISD.TRISD3 3 TRISD bit 3 BANK1:TRISD.TRISD2 2 TRISD bit 2 BANK1:TRISD.TRISD1 1 TRISD bit 1 BANK1:TRISD.TRISD0 0 TRISD bit 0 BANK1:TRISE 0x0089 TRISE REGISTER BANK1:TRISE.IBF 7 Input Buffer Full Status bit BANK1:TRISE.OBF 6 Output Buffer Full Status bit BANK1:TRISE.IBOV 5 Input Buffer Overflow Detect bit BANK1:TRISE.PSPMODE 4 Parallel Slave Port Mode Select bit BANK1:TRISE.TRISE2 2 Direction control bit for pin RE2/CS BANK1:TRISE.TRISE1 1 Direction control bit for pin RE1/WR BANK1:TRISE.TRISE0 0 Direction control bit for pin RE0/RD BANK1:PCLATH 0x008A Write buffer for upper 5 bits of program counter BANK1:INTCON 0x008B INTCON REGISTER BANK1:INTCON.GIE 7 Global Interrupt Enable bit BANK1:INTCON.PEIE 6 Peripheral Interrupt Enable bit BANK1:INTCON.T0IE 5 TMR0 Overflow Interrupt Enable bit BANK1:INTCON.INTE 4 RB0/INT External Interrupt Enable bit BANK1:INTCON.RBIE 3 RB Port Change Interrupt Enable bit BANK1:INTCON.T0IF 2 TMR0 Overflow Interrupt Flag bit BANK1:INTCON.INTF 1 RB0/INT External Interrupt Flag bit BANK1:INTCON.RBIF 0 RB Port Change Interrupt Flag bit BANK1:PIE1 0x008C PIE1 REGISTER BANK1:PIE1.PSPIE 7 Parallel Slave Port Read/Write Interrupt Enable bit BANK1:PIE1.CMIE 6 Comparator Interrupt Enable bit BANK1:RESERVED008D 0x008D RESERVED BANK1:PCON 0x008E PCON REGISTER BANK1:PCON.MPEEN 7 Memory Parity Error Circuitry Status bit BANK1:PCON.PER 2 Memory Parity Error Reset Status bit BANK1:PCON.POR 1 Power-on Reset Status bit BANK1:PCON.BOR 0 Brown-out Reset Status bit BANK1:RESERVED008F 0x008F RESERVED BANK1:RESERVED0090 0x0090 RESERVED BANK1:RESERVED0091 0x0091 RESERVED BANK1:RESERVED0092 0x0092 RESERVED BANK1:RESERVED0093 0x0093 RESERVED BANK1:RESERVED0094 0x0094 RESERVED BANK1:RESERVED0095 0x0095 RESERVED BANK1:RESERVED0096 0x0096 RESERVED BANK1:RESERVED0097 0x0097 RESERVED BANK1:RESERVED0098 0x0098 RESERVED BANK1:RESERVED0099 0x0099 RESERVED BANK1:RESERVED009A 0x009A RESERVED BANK1:RESERVED009B 0x009B RESERVED BANK1:RESERVED009C 0x009C RESERVED BANK1:RESERVED009D 0x009D RESERVED BANK1:RESERVED009E 0x009E RESERVED BANK1:VRCON 0x009F VRCON REGISTER BANK1:VRCON.VREN 7 VREF Enable BANK1:VRCON.VROE 6 VREF Output Enable BANK1:VRCON.VRR 5 VREF Range selection BANK1:VRCON.VR3 3 VREF value selection 3 BANK1:VRCON.VR2 2 VREF value selection 2 BANK1:VRCON.VR1 1 VREF value selection 1 BANK1:VRCON.VR0 0 VREF value selection 0 .16C662 ; http://www.microchip.com/download/lit/pline/picmicro/families/16c6xx/30559a.pdf ; PIC16C64X_66X.pdf ; MEMORY MAP ; BANK_0 area DATA FSR_ 0x0000:0x0020 area DATA Gen_Purp 0x0020:0x0080 General Purpose Register area DATA MEM_Program0 0x0080:0x0800 On-chip Program Memory (Page 0) area DATA MEM_Program1 0x0800:0x1000 On-chip Program Memory (Page 1) ; BANK_1 ; area DATA FSR_ 0x0080:0x00A0 ; area DATA Gen_Purp 0x00A0:0x00F0 General Purpose Register ; area DATA Gen_Purp_BANK0 0x00F0:0x0100 Mapped in Bank 0 ; area DATA MEM_Program0 0x0100:0x0800 On-chip Program Memory (Page 0) ; area DATA MEM_Program1 0x0800:0x1000 On-chip Program Memory (Page 1) ; Interrupt and reset vector assignments interrupt RESET 0x0000 RESET ; INPUT/OUTPUT PORTS ; BANK0 (0x0000:0x0080) BANK0:INDF 0x0000 INDF (not a physical register) BANK0:TMR0 0x0001 Timer0 module's register BANK0:PCL 0x0002 Program Counter's (PC) Least Significant Byte BANK0:STATUS 0x0003 STATUS REGISTER BANK0:STATUS.RP0 5 Register Bank Select bit 0 BANK0:STATUS.TO 4 Time-out bit BANK0:STATUS.PD 3 Power-down bit BANK0:STATUS.Z 2 Zero bit BANK0:STATUS.DC 1 Digit carry/borrow bit BANK0:STATUS.C 0 Carry/borrow bit BANK0:FSR 0x0004 Indirect data memory address pointer BANK0:PORTA 0x0005 PORTA REGISTER BANK0:PORTA.RA5 5 PORTA bit 5 BANK0:PORTA.RA4 4 PORTA bit 4 BANK0:PORTA.RA3 3 PORTA bit 3 BANK0:PORTA.RA2 2 PORTA bit 2 BANK0:PORTA.RA1 1 PORTA bit 1 BANK0:PORTA.RA0 0 PORTA bit 0 BANK0:PORTB 0x0006 PORTB REGISTER BANK0:PORTB.RB7 7 PORTB bit 7 BANK0:PORTB.RB6 6 PORTB bit 6 BANK0:PORTB.RB5 5 PORTB bit 5 BANK0:PORTB.RB4 4 PORTB bit 4 BANK0:PORTB.RB3 3 PORTB bit 3 BANK0:PORTB.RB2 2 PORTB bit 2 BANK0:PORTB.RB1 1 PORTB bit 1 BANK0:PORTB.RB0 0 PORTB bit 0 BANK0:PORTC 0x0007 PORTC REGISTER BANK0:PORTC.RC7 7 PORTC bit 7 BANK0:PORTC.RC6 6 PORTC bit 6 BANK0:PORTC.RC5 5 PORTC bit 5 BANK0:PORTC.RC4 4 PORTC bit 4 BANK0:PORTC.RC3 3 PORTC bit 3 BANK0:PORTC.RC2 2 PORTC bit 2 BANK0:PORTC.RC1 1 PORTC bit 1 BANK0:PORTC.RC0 0 PORTC bit 0 BANK0:PORTD 0x0008 PORTD REGISTER BANK0:PORTD.RD7 7 PORTD bit 7 BANK0:PORTD.RD6 6 PORTD bit 6 BANK0:PORTD.RD5 5 PORTD bit 5 BANK0:PORTD.RD4 4 PORTD bit 4 BANK0:PORTD.RD3 3 PORTD bit 3 BANK0:PORTD.RD2 2 PORTD bit 2 BANK0:PORTD.RD1 1 PORTD bit 1 BANK0:PORTD.RD0 0 PORTD bit 0 BANK0:PORTE 0x0009 PORTE REGISTER BANK0:PORTE.RE2 2 PORTE bit 2 BANK0:PORTE.RE1 1 PORTE bit 1 BANK0:PORTE.RE0 0 PORTE bit 0 BANK0:PCLATH 0x000A Write buffer for upper 5 bits of program counter BANK0:INTCON 0x000B INTCON REGISTER BANK0:INTCON.GIE 7 Global Interrupt Enable bit BANK0:INTCON.PEIE 6 Peripheral Interrupt Enable bit BANK0:INTCON.T0IE 5 TMR0 Overflow Interrupt Enable bit BANK0:INTCON.INTE 4 RB0/INT External Interrupt Enable bit BANK0:INTCON.RBIE 3 RB Port Change Interrupt Enable bit BANK0:INTCON.T0IF 2 TMR0 Overflow Interrupt Flag bit BANK0:INTCON.INTF 1 RB0/INT External Interrupt Flag bit BANK0:INTCON.RBIF 0 RB Port Change Interrupt Flag bit BANK0:PIR1 0x000C PIR1 REGISTER BANK0:PIR1.PSPIF 7 Parallel Slave Port Interrupt Flag bit BANK0:PIR1.CMIF 6 Comparator Interrupt Flag bit BANK0:RESERVED000D 0x000D RESERVED BANK0:RESERVED000E 0x000E RESERVED BANK0:RESERVED000F 0x000F RESERVED BANK0:RESERVED0010 0x0010 RESERVED BANK0:RESERVED0011 0x0011 RESERVED BANK0:RESERVED0012 0x0012 RESERVED BANK0:RESERVED0013 0x0013 RESERVED BANK0:RESERVED0014 0x0014 RESERVED BANK0:RESERVED0015 0x0015 RESERVED BANK0:RESERVED0016 0x0016 RESERVED BANK0:RESERVED0017 0x0017 RESERVED BANK0:RESERVED0018 0x0018 RESERVED BANK0:RESERVED0019 0x0019 RESERVED BANK0:RESERVED001A 0x001A RESERVED BANK0:RESERVED001B 0x001B RESERVED BANK0:RESERVED001C 0x001C RESERVED BANK0:RESERVED001D 0x001D RESERVED BANK0:RESERVED001E 0x001E RESERVED BANK0:CMCON 0x001F CMCON REGISTER BANK0:CMCON.C2OUT 7 Comparator 2 output BANK0:CMCON.C1OUT 6 Comparator 1 output BANK0:CMCON.CIS 3 Comparator Input Switch BANK0:CMCON.CM2 2 Comparator mode 2 BANK0:CMCON.CM1 1 Comparator mode 1 BANK0:CMCON.CM0 0 Comparator mode 0 ; BANK1 (0x0080:0x0100) BANK1:INDF 0x0080 INDF (not a physical register) BANK1:OPTION 0x0081 OPTION REGISTER BANK1:OPTION.RBPU 7 PORTB Pull-up Enable bit BANK1:OPTION.INTEDG 6 Interrupt Edge Select bit BANK1:OPTION.T0CS 5 TMR0 Clock Source Select bit BANK1:OPTION.T0SE 4 TMR0 Source Edge Select bit BANK1:OPTION.PSA 3 Prescaler Assignment bit BANK1:OPTION.PS2 2 Prescaler Rate Select bit 2 BANK1:OPTION.PS1 1 Prescaler Rate Select bit 1 BANK1:OPTION.PS0 0 Prescaler Rate Select bit 0 BANK1:PCL 0x0082 Program Counter's (PC) Least Significant Byte BANK1:STATUS 0x0083 STATUS REGISTER BANK1:STATUS.RP0 5 Register Bank Select bit 0 BANK1:STATUS.TO 4 Time-out bit BANK1:STATUS.PD 3 Power-down bit BANK1:STATUS.Z 2 Zero bit BANK1:STATUS.DC 1 Digit carry/borrow bit BANK1:STATUS.C 0 Carry/borrow bit BANK1:FSR 0x0084 Indirect data memory address pointer BANK1:TRISA 0x0085 TRISA REGISTER BANK1:TRISA.TRISA5 5 TRISA bit 5 BANK1:TRISA.TRISA4 4 TRISA bit 4 BANK1:TRISA.TRISA3 3 TRISA bit 3 BANK1:TRISA.TRISA2 2 TRISA bit 2 BANK1:TRISA.TRISA1 1 TRISA bit 1 BANK1:TRISA.TRISA0 0 TRISA bit 0 BANK1:TRISB 0x0086 TRISB REGISTER BANK1:TRISB.TRISB7 7 TRISB bit 7 BANK1:TRISB.TRISB6 6 TRISB bit 6 BANK1:TRISB.TRISB5 5 TRISB bit 5 BANK1:TRISB.TRISB4 4 TRISB bit 4 BANK1:TRISB.TRISB3 3 TRISB bit 3 BANK1:TRISB.TRISB2 2 TRISB bit 2 BANK1:TRISB.TRISB1 1 TRISB bit 1 BANK1:TRISB.TRISB0 0 TRISB bit 0 BANK1:TRISC 0x0087 TRISC REGISTER BANK1:TRISC.TRISC7 7 TRISC bit 7 BANK1:TRISC.TRISC6 6 TRISC bit 6 BANK1:TRISC.TRISC5 5 TRISC bit 5 BANK1:TRISC.TRISC4 4 TRISC bit 4 BANK1:TRISC.TRISC3 3 TRISC bit 3 BANK1:TRISC.TRISC2 2 TRISC bit 2 BANK1:TRISC.TRISC1 1 TRISC bit 1 BANK1:TRISC.TRISC0 0 TRISC bit 0 BANK1:TRISD 0x0088 TRISD REGISTER BANK1:TRISD.TRISD7 7 TRISD bit 7 BANK1:TRISD.TRISD6 6 TRISD bit 6 BANK1:TRISD.TRISD5 5 TRISD bit 5 BANK1:TRISD.TRISD4 4 TRISD bit 4 BANK1:TRISD.TRISD3 3 TRISD bit 3 BANK1:TRISD.TRISD2 2 TRISD bit 2 BANK1:TRISD.TRISD1 1 TRISD bit 1 BANK1:TRISD.TRISD0 0 TRISD bit 0 BANK1:TRISE 0x0089 TRISE REGISTER BANK1:TRISE.IBF 7 Input Buffer Full Status bit BANK1:TRISE.OBF 6 Output Buffer Full Status bit BANK1:TRISE.IBOV 5 Input Buffer Overflow Detect bit BANK1:TRISE.PSPMODE 4 Parallel Slave Port Mode Select bit BANK1:TRISE.TRISE2 2 Direction control bit for pin RE2/CS BANK1:TRISE.TRISE1 1 Direction control bit for pin RE1/WR BANK1:TRISE.TRISE0 0 Direction control bit for pin RE0/RD BANK1:PCLATH 0x008A Write buffer for upper 5 bits of program counter BANK1:INTCON 0x008B INTCON REGISTER BANK1:INTCON.GIE 7 Global Interrupt Enable bit BANK1:INTCON.PEIE 6 Peripheral Interrupt Enable bit BANK1:INTCON.T0IE 5 TMR0 Overflow Interrupt Enable bit BANK1:INTCON.INTE 4 RB0/INT External Interrupt Enable bit BANK1:INTCON.RBIE 3 RB Port Change Interrupt Enable bit BANK1:INTCON.T0IF 2 TMR0 Overflow Interrupt Flag bit BANK1:INTCON.INTF 1 RB0/INT External Interrupt Flag bit BANK1:INTCON.RBIF 0 RB Port Change Interrupt Flag bit BANK1:PIE1 0x008C PIE1 REGISTER BANK1:PIE1.PSPIE 7 Parallel Slave Port Read/Write Interrupt Enable bit BANK1:PIE1.CMIE 6 Comparator Interrupt Enable bit BANK1:RESERVED008D 0x008D RESERVED BANK1:PCON 0x008E PCON REGISTER BANK1:PCON.MPEEN 7 Memory Parity Error Circuitry Status bit BANK1:PCON.PER 2 Memory Parity Error Reset Status bit BANK1:PCON.POR 1 Power-on Reset Status bit BANK1:PCON.BOR 0 Brown-out Reset Status bit BANK1:RESERVED008F 0x008F RESERVED BANK1:RESERVED0090 0x0090 RESERVED BANK1:RESERVED0091 0x0091 RESERVED BANK1:RESERVED0092 0x0092 RESERVED BANK1:RESERVED0093 0x0093 RESERVED BANK1:RESERVED0094 0x0094 RESERVED BANK1:RESERVED0095 0x0095 RESERVED BANK1:RESERVED0096 0x0096 RESERVED BANK1:RESERVED0097 0x0097 RESERVED BANK1:RESERVED0098 0x0098 RESERVED BANK1:RESERVED0099 0x0099 RESERVED BANK1:RESERVED009A 0x009A RESERVED BANK1:RESERVED009B 0x009B RESERVED BANK1:RESERVED009C 0x009C RESERVED BANK1:RESERVED009D 0x009D RESERVED BANK1:RESERVED009E 0x009E RESERVED BANK1:VRCON 0x009F VRCON REGISTER BANK1:VRCON.VREN 7 VREF Enable BANK1:VRCON.VROE 6 VREF Output Enable BANK1:VRCON.VRR 5 VREF Range selection BANK1:VRCON.VR3 3 VREF value selection 3 BANK1:VRCON.VR2 2 VREF value selection 2 BANK1:VRCON.VR1 1 VREF value selection 1 BANK1:VRCON.VR0 0 VREF value selection 0 .16C61 ; http://www.microchip.com/download/lit/pline/picmicro/families/16c6x/30234d.pdf ; PIC16C6x.pdf ; MEMORY MAP ; BANK_0 area DATA FSR_ 0x0000:0x000C area DATA Gen_Purp 0x000C:0x0030 General Purpose Register area BSS RESERVED 0x0030:0x0080 area DATA MEM_Program 0x0080:0x0400 On-chip Program Memory ; BANK_1 ; area DATA FSR_ 0x0080:0x008C ; area DATA Gen_Purp_BANK0 0x008C:0x00B0 Mapped in Bank 0 ; area BSS RESERVED 0x00B0:0x0100 ; area DATA MEM_Program 0x0100:0x0400 On-chip Program Memory ; Interrupt and reset vector assignments interrupt RESET 0x0000 RESET ; INPUT/OUTPUT PORTS ; BANK0 (0x0000:0x0080) BANK0:INDF 0x0000 INDF (not a physical register) BANK0:TMR0 0x0001 Timer0 module's register BANK0:PCL 0x0002 Program Counter's (PC) Least Significant Byte BANK0:STATUS 0x0003 STATUS REGISTER BANK0:STATUS.RP0 5 Register Bank Select bit 0 BANK0:STATUS.TO 4 Time-out bit BANK0:STATUS.PD 3 Power-down bit BANK0:STATUS.Z 2 Zero bit BANK0:STATUS.DC 1 Digit carry/borrow bit BANK0:STATUS.C 0 Carry/borrow bit BANK0:FSR 0x0004 Indirect data memory address pointer BANK0:PORTA 0x0005 PORTA register BANK0:PORTA.RA4 4 PORTA bit 4 BANK0:PORTA.RA3 3 PORTA bit 3 BANK0:PORTA.RA2 2 PORTA bit 2 BANK0:PORTA.RA1 1 PORTA bit 1 BANK0:PORTA.RA0 0 PORTA bit 0 BANK0:PORTB 0x0006 PORTB register BANK0:PORTB.RB7 7 PORTB bit 7 BANK0:PORTB.RB6 6 PORTB bit 6 BANK0:PORTB.RB5 5 PORTB bit 5 BANK0:PORTB.RB4 4 PORTB bit 4 BANK0:PORTB.RB3 3 PORTB bit 3 BANK0:PORTB.RB2 2 PORTB bit 2 BANK0:PORTB.RB1 1 PORTB bit 1 BANK0:PORTB.RB0 0 PORTB bit 0 BANK0:RESERVED0007 0x0007 RESERVED BANK0:RESERVED0008 0x0008 RESERVED BANK0:RESERVED0009 0x0009 RESERVED BANK0:PCLATH 0x000A Write Buffer for the upper 5 bits of the Program Counter BANK0:INTCON 0x000B INTCON REGISTER BANK0:INTCON.GIE 7 Global Interrupt Enable bit BANK0:INTCON.T0IE 5 TMR0 Overflow Interrupt Enable bit BANK0:INTCON.INTE 4 RB0/INT External Interrupt Enable bit BANK0:INTCON.RBIE 3 RB Port Change Interrupt Enable bit BANK0:INTCON.T0IF 2 TMR0 Overflow Interrupt Flag bit BANK0:INTCON.INTF 1 RB0/INT External Interrupt Flag bit BANK0:INTCON.RBIF 0 RB Port Change Interrupt Flag bit ; BANK1 (0x0080:0x0100) BANK1:INDF 0x0080 INDF (not a physical register) BANK1:OPTION 0x0081 OPTION REGISTER BANK1:OPTION.RBPU 7 PORTB Pull-up Enable bit BANK1:OPTION.INTEDG 6 Interrupt Edge Select bit BANK1:OPTION.T0CS 5 TMR0 Clock Source Select bit BANK1:OPTION.T0SE 4 TMR0 Source Edge Select bit BANK1:OPTION.PSA 3 Prescaler Assignment bit BANK1:OPTION.PS2 2 Prescaler Rate Select bit 2 BANK1:OPTION.PS1 1 Prescaler Rate Select bit 1 BANK1:OPTION.PS0 0 Prescaler Rate Select bit 0 BANK1:PCL 0x0082 Program Counter's (PC) Least Significant Byte BANK1:STATUS 0x0083 STATUS REGISTER BANK1:STATUS.RP0 5 Register Bank Select bit 0 BANK1:STATUS.TO 4 Time-out bit BANK1:STATUS.PD 3 Power-down bit BANK1:STATUS.Z 2 Zero bit BANK1:STATUS.DC 1 Digit carry/borrow bit BANK1:STATUS.C 0 Carry/borrow bit BANK1:FSR 0x0084 Indirect data memory address pointer BANK1:TRISA 0x0085 PORTA Data Direction Register BANK1:TRISA.TRISA4 4 PORTA Data Direction Register bit 4 BANK1:TRISA.TRISA3 3 PORTA Data Direction Register bit 3 BANK1:TRISA.TRISA2 2 PORTA Data Direction Register bit 2 BANK1:TRISA.TRISA1 1 PORTA Data Direction Register bit 1 BANK1:TRISA.TRISA0 0 PORTA Data Direction Register bit 0 BANK1:TRISB 0x0086 PORTB Data Direction Register BANK1:TRISB.TRISB7 7 PORTB Data Direction Register bit 7 BANK1:TRISB.TRISB6 6 PORTB Data Direction Register bit 6 BANK1:TRISB.TRISB5 5 PORTB Data Direction Register bit 5 BANK1:TRISB.TRISB4 4 PORTB Data Direction Register bit 4 BANK1:TRISB.TRISB3 3 PORTB Data Direction Register bit 3 BANK1:TRISB.TRISB2 2 PORTB Data Direction Register bit 2 BANK1:TRISB.TRISB1 1 PORTB Data Direction Register bit 1 BANK1:TRISB.TRISB0 0 PORTB Data Direction Register bit 0 BANK1:RESERVED0087 0x0087 RESERVED BANK1:RESERVED0088 0x0088 RESERVED BANK1:RESERVED0089 0x0089 RESERVED BANK1:PCLATH 0x008A Write Buffer for the upper 5 bits of the Program Counter BANK1:INTCON 0x008B INTCON REGISTER BANK1:INTCON.GIE 7 Global Interrupt Enable bit BANK1:INTCON.T0IE 5 TMR0 Overflow Interrupt Enable bit BANK1:INTCON.INTE 4 RB0/INT External Interrupt Enable bit BANK1:INTCON.RBIE 3 RB Port Change Interrupt Enable bit BANK1:INTCON.T0IF 2 TMR0 Overflow Interrupt Flag bit BANK1:INTCON.INTF 1 RB0/INT External Interrupt Flag bit BANK1:INTCON.RBIF 0 RB Port Change Interrupt Flag bit .16C62 ; http://www.microchip.com/download/lit/pline/picmicro/families/16c6x/30234d.pdf ; PIC16C6x.pdf ; MEMORY MAP ; BANK_0 area DATA FSR_ 0x0000:0x0020 area DATA Gen_Purp 0x0020:0x0080 General Purpose Register area DATA MEM_Program 0x0080:0x0800 On-chip Program Memory ; BANK_1 area DATA FSR_ 0x0080:0x00A0 area DATA Gen_Purp 0x00A0:0x00C0 General Purpose Register area BSS RESERVED 0x00C0:0x0100 area DATA MEM_Program 0x0100:0x0800 On-chip Program Memory ; Interrupt and reset vector assignments interrupt RESET 0x0000 RESET ; INPUT/OUTPUT PORTS ; BANK0 (0x0000:0x0080) BANK0:INDF 0x0000 INDF (not a physical register) BANK0:TMR0 0x0001 Timer0 module's register BANK0:PCL 0x0002 Program Counter's (PC) Least Significant Byte BANK0:STATUS 0x0003 STATUS REGISTER BANK0:STATUS.RP0 5 Register Bank Select bit 0 BANK0:STATUS.TO 4 Time-out bit BANK0:STATUS.PD 3 Power-down bit BANK0:STATUS.Z 2 Zero bit BANK0:STATUS.DC 1 Digit carry/borrow bit BANK0:STATUS.C 0 Carry/borrow bit BANK0:FSR 0x0004 Indirect data memory address pointer BANK0:PORTA 0x0005 PORTA register BANK0:PORTA.RA5 5 PORTA bit 5 BANK0:PORTA.RA4 4 PORTA bit 4 BANK0:PORTA.RA3 3 PORTA bit 3 BANK0:PORTA.RA2 2 PORTA bit 2 BANK0:PORTA.RA1 1 PORTA bit 1 BANK0:PORTA.RA0 0 PORTA bit 0 BANK0:PORTB 0x0006 PORTB register BANK0:PORTB.RB7 7 PORTB bit 7 BANK0:PORTB.RB6 6 PORTB bit 6 BANK0:PORTB.RB5 5 PORTB bit 5 BANK0:PORTB.RB4 4 PORTB bit 4 BANK0:PORTB.RB3 3 PORTB bit 3 BANK0:PORTB.RB2 2 PORTB bit 2 BANK0:PORTB.RB1 1 PORTB bit 1 BANK0:PORTB.RB0 0 PORTB bit 0 BANK0:PORTC 0x0007 PORTC register BANK0:PORTC.RC7 7 PORTC bit 7 BANK0:PORTC.RC6 6 PORTC bit 6 BANK0:PORTC.RC5 5 PORTC bit 5 BANK0:PORTC.RC4 4 PORTC bit 4 BANK0:PORTC.RC3 3 PORTC bit 3 BANK0:PORTC.RC2 2 PORTC bit 2 BANK0:PORTC.RC1 1 PORTC bit 1 BANK0:PORTC.RC0 0 PORTC bit 0 BANK0:RESERVED0008 0x0008 RESERVED BANK0:RESERVED0009 0x0009 RESERVED BANK0:PCLATH 0x000A Write Buffer for the upper 5 bits of the Program Counter BANK0:INTCON 0x000B INTCON REGISTER BANK0:INTCON.GIE 7 Global Interrupt Enable bit BANK0:INTCON.PEIE 6 Peripheral Interrupt Enable bit BANK0:INTCON.T0IE 5 TMR0 Overflow Interrupt Enable bit BANK0:INTCON.INTE 4 RB0/INT External Interrupt Enable bit BANK0:INTCON.RBIE 3 RB Port Change Interrupt Enable bit BANK0:INTCON.T0IF 2 TMR0 Overflow Interrupt Flag bit BANK0:INTCON.INTF 1 RB0/INT External Interrupt Flag bit BANK0:INTCON.RBIF 0 RB Port Change Interrupt Flag bit BANK0:PIR1 0x000C PIR1 REGISTER BANK0:PIR1.SSPIF 3 Synchronous Serial Port Interrupt Flag bit BANK0:PIR1.CCP1IF 2 CCP1 Interrupt Flag bit BANK0:PIR1.TMR2IF 1 TMR2 to PR2 Match Interrupt Flag bit BANK0:PIR1.TMR1IF 0 TMR1 Overflow Interrupt Flag bit BANK0:RESERVED000D 0x000D RESERVED BANK0:TMR1L 0x000E Holding register for the Least Significant Byte of the 16-bit TMR1 register BANK0:TMR1H 0x000F Holding register for the Most Significant Byte of the 16-bit TMR1 register BANK0:T1CON 0x0010 TIMER1 CONTROL REGISTER BANK0:T1CON.T1CKPS1 5 Timer1 Input Clock Prescale Select bit 1 BANK0:T1CON.T1CKPS0 4 Timer1 Input Clock Prescale Select bit 0 BANK0:T1CON.T1OSCEN 3 Timer1 Oscillator Enable Control bit BANK0:T1CON.T1SYNC 2 Timer1 External Clock Input Synchronization Control bit BANK0:T1CON.TMR1CS 1 Timer1 Clock Source Select bit BANK0:T1CON.TMR1ON 0 Timer1 On bit BANK0:TMR2 0x0011 Timer2 module's register BANK0:T2CON 0x0012 TIMER2 CONTROL REGISTER BANK0:T2CON.TOUTPS3 6 Timer2 Output Postscale Select bit 3 BANK0:T2CON.TOUTPS2 5 Timer2 Output Postscale Select bit 2 BANK0:T2CON.TOUTPS1 4 Timer2 Output Postscale Select bit 1 BANK0:T2CON.TOUTPS0 3 Timer2 Output Postscale Select bit 0 BANK0:T2CON.TMR2ON 2 Timer2 On bit BANK0:T2CON.T2CKPS1 1 Timer2 Clock Prescale Select bit 1 BANK0:T2CON.T2CKPS0 0 Timer2 Clock Prescale Select bit 0 BANK0:SSPBUF 0x0013 Synchronous Serial Port Receive Buffer/Transmit Register BANK0:SSPCON 0x0014 SYNC SERIAL PORT CONTROL REGISTER BANK0:SSPCON.WCOL 7 Write Collision Detect bit BANK0:SSPCON.SSPOV 6 Receive Overflow Indicator bit BANK0:SSPCON.SSPEN 5 Synchronous Serial Port Enable bit BANK0:SSPCON.CKP 4 Clock Polarity Select bit BANK0:SSPCON.SSPM3 3 Synchronous Serial Port Mode Select bit 3 BANK0:SSPCON.SSPM2 2 Synchronous Serial Port Mode Select bit 2 BANK0:SSPCON.SSPM1 1 Synchronous Serial Port Mode Select bit 1 BANK0:SSPCON.SSPM0 0 Synchronous Serial Port Mode Select bit 0 BANK0:CCPR1L 0x0015 Capture/Compare/PWM1 (LSB) BANK0:CCPR1H 0x0016 Capture/Compare/PWM1 (MSB) BANK0:CCP1CON 0x0017 CCP1CON REGISTER BANK0:CCP1CON.CCP1X 5 PWM Least Significant bit BANK0:CCP1CON.CCP1Y 4 PWM Least Significant bit BANK0:CCP1CON.CCP1M3 3 CCP1 Mode Select bit 3 BANK0:CCP1CON.CCP1M2 2 CCP1 Mode Select bit 2 BANK0:CCP1CON.CCP1M1 1 CCP1 Mode Select bit 1 BANK0:CCP1CON.CCP1M0 0 CCP1 Mode Select bit 0 BANK0:RESERVED0018 0x0018 RESERVED BANK0:RESERVED0019 0x0019 RESERVED BANK0:RESERVED001A 0x001A RESERVED BANK0:RESERVED001B 0x001B RESERVED BANK0:RESERVED001C 0x001C RESERVED BANK0:RESERVED001D 0x001D RESERVED BANK0:RESERVED001E 0x001E RESERVED BANK0:RESERVED001F 0x001F RESERVED ; BANK1 (0x0080:0x0100) BANK1:INDF 0x0080 INDF (not a physical register) BANK1:OPTION 0x0081 OPTION REGISTER BANK1:OPTION.RBPU 7 PORTB Pull-up Enable bit BANK1:OPTION.INTEDG 6 Interrupt Edge Select bit BANK1:OPTION.T0CS 5 TMR0 Clock Source Select bit BANK1:OPTION.T0SE 4 TMR0 Source Edge Select bit BANK1:OPTION.PSA 3 Prescaler Assignment bit BANK1:OPTION.PS2 2 Prescaler Rate Select bit 2 BANK1:OPTION.PS1 1 Prescaler Rate Select bit 1 BANK1:OPTION.PS0 0 Prescaler Rate Select bit 0 BANK1:PCL 0x0082 Program Counter's (PC) Least Significant Byte BANK1:STATUS 0x0083 STATUS REGISTER BANK1:STATUS.RP0 5 Register Bank Select bit 0 BANK1:STATUS.TO 4 Time-out bit BANK1:STATUS.PD 3 Power-down bit BANK1:STATUS.Z 2 Zero bit BANK1:STATUS.DC 1 Digit carry/borrow bit BANK1:STATUS.C 0 Carry/borrow bit BANK1:FSR 0x0084 Indirect data memory address pointer BANK1:TRISA 0x0085 PORTA Data Direction Register BANK1:TRISA.TRISA5 5 PORTA Data Direction Register bit 5 BANK1:TRISA.TRISA4 4 PORTA Data Direction Register bit 4 BANK1:TRISA.TRISA3 3 PORTA Data Direction Register bit 3 BANK1:TRISA.TRISA2 2 PORTA Data Direction Register bit 2 BANK1:TRISA.TRISA1 1 PORTA Data Direction Register bit 1 BANK1:TRISA.TRISA0 0 PORTA Data Direction Register bit 0 BANK1:TRISB 0x0086 PORTB Data Direction Register BANK1:TRISB.TRISB7 7 PORTB Data Direction Register bit 7 BANK1:TRISB.TRISB6 6 PORTB Data Direction Register bit 6 BANK1:TRISB.TRISB5 5 PORTB Data Direction Register bit 5 BANK1:TRISB.TRISB4 4 PORTB Data Direction Register bit 4 BANK1:TRISB.TRISB3 3 PORTB Data Direction Register bit 3 BANK1:TRISB.TRISB2 2 PORTB Data Direction Register bit 2 BANK1:TRISB.TRISB1 1 PORTB Data Direction Register bit 1 BANK1:TRISB.TRISB0 0 PORTB Data Direction Register bit 0 BANK1:TRISC 0x0087 PORTC Data Direction Register BANK1:TRISC.TRISC7 7 PORTC Data Direction Register bit 7 BANK1:TRISC.TRISC6 6 PORTC Data Direction Register bit 6 BANK1:TRISC.TRISC5 5 PORTC Data Direction Register bit 5 BANK1:TRISC.TRISC4 4 PORTC Data Direction Register bit 4 BANK1:TRISC.TRISC3 3 PORTC Data Direction Register bit 3 BANK1:TRISC.TRISC2 2 PORTC Data Direction Register bit 2 BANK1:TRISC.TRISC1 1 PORTC Data Direction Register bit 1 BANK1:TRISC.TRISC0 0 PORTC Data Direction Register bit 0 BANK1:RESERVED0088 0x0088 RESERVED BANK1:RESERVED0089 0x0089 RESERVED BANK1:PCLATH 0x008A Write Buffer for the upper 5 bits of the Program Counter BANK1:INTCON 0x008B INTCON REGISTER BANK1:INTCON.GIE 7 Global Interrupt Enable bit BANK1:INTCON.PEIE 6 Peripheral Interrupt Enable bit BANK1:INTCON.T0IE 5 TMR0 Overflow Interrupt Enable bit BANK1:INTCON.INTE 4 RB0/INT External Interrupt Enable bit BANK1:INTCON.RBIE 3 RB Port Change Interrupt Enable bit BANK1:INTCON.T0IF 2 TMR0 Overflow Interrupt Flag bit BANK1:INTCON.INTF 1 RB0/INT External Interrupt Flag bit BANK1:INTCON.RBIF 0 RB Port Change Interrupt Flag bit BANK1:PIE1 0x008C PIE1 REGISTER BANK1:PIE1.SSPIE 3 Synchronous Serial Port Interrupt Enable bit BANK1:PIE1.CCP1IE 2 CCP1 Interrupt Enable bit BANK1:PIE1.TMR2IE 1 TMR2 to PR2 Match Interrupt Enable bit BANK1:PIE1.TMR1IE 0 TMR1 Overflow Interrupt Enable bit BANK1:RESERVED008D 0x008D RESERVED BANK1:PCON 0x008E PCON REGISTER BANK1:PCON.POR 1 Power-on Reset Status bit BANK1:RESERVED008F 0x008F RESERVED BANK1:RESERVED0090 0x0090 RESERVED BANK1:RESERVED0091 0x0091 RESERVED BANK1:PR2 0x0092 Timer2 Period Register BANK1:SSPADD 0x0093 Synchronous Serial Port (I2C mode) Address Register BANK1:SSPSTAT 0x0094 SYNC SERIAL PORT STATUS REGISTER BANK1:SSPSTAT.D_A 5 Data/Address bit (I2C mode only) BANK1:SSPSTAT.P 4 Stop bit (I2C mode only) BANK1:SSPSTAT.S 3 Start bit (I2C mode only) BANK1:SSPSTAT.R_W 2 Read/Write bit information (I2C mode only) BANK1:SSPSTAT.UA 1 Update Address (I2C mode only) BANK1:SSPSTAT.BF 0 Buffer Full Status bit BANK1:RESERVED0095 0x0095 RESERVED BANK1:RESERVED0096 0x0096 RESERVED BANK1:RESERVED0097 0x0097 RESERVED BANK1:RESERVED0098 0x0098 RESERVED BANK1:RESERVED0099 0x0099 RESERVED BANK1:RESERVED009A 0x009A RESERVED BANK1:RESERVED009B 0x009B RESERVED BANK1:RESERVED009C 0x009C RESERVED BANK1:RESERVED009D 0x009D RESERVED BANK1:RESERVED009E 0x009E RESERVED BANK1:RESERVED009F 0x009F RESERVED .16C62A ; http://www.microchip.com/download/lit/pline/picmicro/families/16c6x/30234d.pdf ; PIC16C6x.pdf ; MEMORY MAP ; BANK_0 area DATA FSR_ 0x0000:0x0020 area DATA Gen_Purp 0x0020:0x0080 General Purpose Register area DATA MEM_Program 0x0080:0x0800 On-chip Program Memory ; BANK_1 area DATA FSR_ 0x0080:0x00A0 area DATA Gen_Purp 0x00A0:0x00C0 General Purpose Register area BSS RESERVED 0x00C0:0x0100 area DATA MEM_Program 0x0100:0x0800 On-chip Program Memory ; Interrupt and reset vector assignments interrupt RESET 0x0000 RESET ; INPUT/OUTPUT PORTS ; BANK0 (0x0000:0x0080) BANK0:INDF 0x0000 INDF (not a physical register) BANK0:TMR0 0x0001 Timer0 module's register BANK0:PCL 0x0002 Program Counter's (PC) Least Significant Byte BANK0:STATUS 0x0003 STATUS REGISTER BANK0:STATUS.RP0 5 Register Bank Select bit 0 BANK0:STATUS.TO 4 Time-out bit BANK0:STATUS.PD 3 Power-down bit BANK0:STATUS.Z 2 Zero bit BANK0:STATUS.DC 1 Digit carry/borrow bit BANK0:STATUS.C 0 Carry/borrow bit BANK0:FSR 0x0004 Indirect data memory address pointer BANK0:PORTA 0x0005 PORTA register BANK0:PORTA.RA5 5 PORTA bit 5 BANK0:PORTA.RA4 4 PORTA bit 4 BANK0:PORTA.RA3 3 PORTA bit 3 BANK0:PORTA.RA2 2 PORTA bit 2 BANK0:PORTA.RA1 1 PORTA bit 1 BANK0:PORTA.RA0 0 PORTA bit 0 BANK0:PORTB 0x0006 PORTB register BANK0:PORTB.RB7 7 PORTB bit 7 BANK0:PORTB.RB6 6 PORTB bit 6 BANK0:PORTB.RB5 5 PORTB bit 5 BANK0:PORTB.RB4 4 PORTB bit 4 BANK0:PORTB.RB3 3 PORTB bit 3 BANK0:PORTB.RB2 2 PORTB bit 2 BANK0:PORTB.RB1 1 PORTB bit 1 BANK0:PORTB.RB0 0 PORTB bit 0 BANK0:PORTC 0x0007 PORTC register BANK0:PORTC.RC7 7 PORTC bit 7 BANK0:PORTC.RC6 6 PORTC bit 6 BANK0:PORTC.RC5 5 PORTC bit 5 BANK0:PORTC.RC4 4 PORTC bit 4 BANK0:PORTC.RC3 3 PORTC bit 3 BANK0:PORTC.RC2 2 PORTC bit 2 BANK0:PORTC.RC1 1 PORTC bit 1 BANK0:PORTC.RC0 0 PORTC bit 0 BANK0:RESERVED0008 0x0008 RESERVED BANK0:RESERVED0009 0x0009 RESERVED BANK0:PCLATH 0x000A Write Buffer for the upper 5 bits of the Program Counter BANK0:INTCON 0x000B INTCON REGISTER BANK0:INTCON.GIE 7 Global Interrupt Enable bit BANK0:INTCON.PEIE 6 Peripheral Interrupt Enable bit BANK0:INTCON.T0IE 5 TMR0 Overflow Interrupt Enable bit BANK0:INTCON.INTE 4 RB0/INT External Interrupt Enable bit BANK0:INTCON.RBIE 3 RB Port Change Interrupt Enable bit BANK0:INTCON.T0IF 2 TMR0 Overflow Interrupt Flag bit BANK0:INTCON.INTF 1 RB0/INT External Interrupt Flag bit BANK0:INTCON.RBIF 0 RB Port Change Interrupt Flag bit BANK0:PIR1 0x000C PIR1 REGISTER BANK0:PIR1.SSPIF 3 Synchronous Serial Port Interrupt Flag bit BANK0:PIR1.CCP1IF 2 CCP1 Interrupt Flag bit BANK0:PIR1.TMR2IF 1 TMR2 to PR2 Match Interrupt Flag bit BANK0:PIR1.TMR1IF 0 TMR1 Overflow Interrupt Flag bit BANK0:RESERVED000D 0x000D RESERVED BANK0:TMR1L 0x000E Holding register for the Least Significant Byte of the 16-bit TMR1 register BANK0:TMR1H 0x000F Holding register for the Most Significant Byte of the 16-bit TMR1 register BANK0:T1CON 0x0010 TIMER1 CONTROL REGISTER BANK0:T1CON.T1CKPS1 5 Timer1 Input Clock Prescale Select bit 1 BANK0:T1CON.T1CKPS0 4 Timer1 Input Clock Prescale Select bit 0 BANK0:T1CON.T1OSCEN 3 Timer1 Oscillator Enable Control bit BANK0:T1CON.T1SYNC 2 Timer1 External Clock Input Synchronization Control bit BANK0:T1CON.TMR1CS 1 Timer1 Clock Source Select bit BANK0:T1CON.TMR1ON 0 Timer1 On bit BANK0:TMR2 0x0011 Timer2 module's register BANK0:T2CON 0x0012 TIMER2 CONTROL REGISTER BANK0:T2CON.TOUTPS3 6 Timer2 Output Postscale Select bit 3 BANK0:T2CON.TOUTPS2 5 Timer2 Output Postscale Select bit 2 BANK0:T2CON.TOUTPS1 4 Timer2 Output Postscale Select bit 1 BANK0:T2CON.TOUTPS0 3 Timer2 Output Postscale Select bit 0 BANK0:T2CON.TMR2ON 2 Timer2 On bit BANK0:T2CON.T2CKPS1 1 Timer2 Clock Prescale Select bit 1 BANK0:T2CON.T2CKPS0 0 Timer2 Clock Prescale Select bit 0 BANK0:SSPBUF 0x0013 Synchronous Serial Port Receive Buffer/Transmit Register BANK0:SSPCON 0x0014 SYNC SERIAL PORT CONTROL REGISTER BANK0:SSPCON.WCOL 7 Write Collision Detect bit BANK0:SSPCON.SSPOV 6 Receive Overflow Indicator bit BANK0:SSPCON.SSPEN 5 Synchronous Serial Port Enable bit BANK0:SSPCON.CKP 4 Clock Polarity Select bit BANK0:SSPCON.SSPM3 3 Synchronous Serial Port Mode Select bit 3 BANK0:SSPCON.SSPM2 2 Synchronous Serial Port Mode Select bit 2 BANK0:SSPCON.SSPM1 1 Synchronous Serial Port Mode Select bit 1 BANK0:SSPCON.SSPM0 0 Synchronous Serial Port Mode Select bit 0 BANK0:CCPR1L 0x0015 Capture/Compare/PWM1 (LSB) BANK0:CCPR1H 0x0016 Capture/Compare/PWM1 (MSB) BANK0:CCP1CON 0x0017 CCP1CON REGISTER BANK0:CCP1CON.CCP1X 5 PWM Least Significant bit BANK0:CCP1CON.CCP1Y 4 PWM Least Significant bit BANK0:CCP1CON.CCP1M3 3 CCP1 Mode Select bit 3 BANK0:CCP1CON.CCP1M2 2 CCP1 Mode Select bit 2 BANK0:CCP1CON.CCP1M1 1 CCP1 Mode Select bit 1 BANK0:CCP1CON.CCP1M0 0 CCP1 Mode Select bit 0 BANK0:RESERVED0018 0x0018 RESERVED BANK0:RESERVED0019 0x0019 RESERVED BANK0:RESERVED001A 0x001A RESERVED BANK0:RESERVED001B 0x001B RESERVED BANK0:RESERVED001C 0x001C RESERVED BANK0:RESERVED001D 0x001D RESERVED BANK0:RESERVED001E 0x001E RESERVED BANK0:RESERVED001F 0x001F RESERVED ; BANK1 (0x0080:0x0100) BANK1:INDF 0x0080 INDF (not a physical register) BANK1:OPTION 0x0081 OPTION REGISTER BANK1:OPTION.RBPU 7 PORTB Pull-up Enable bit BANK1:OPTION.INTEDG 6 Interrupt Edge Select bit BANK1:OPTION.T0CS 5 TMR0 Clock Source Select bit BANK1:OPTION.T0SE 4 TMR0 Source Edge Select bit BANK1:OPTION.PSA 3 Prescaler Assignment bit BANK1:OPTION.PS2 2 Prescaler Rate Select bit 2 BANK1:OPTION.PS1 1 Prescaler Rate Select bit 1 BANK1:OPTION.PS0 0 Prescaler Rate Select bit 0 BANK1:PCL 0x0082 Program Counter's (PC) Least Significant Byte BANK1:STATUS 0x0083 STATUS REGISTER BANK1:STATUS.RP0 5 Register Bank Select bit 0 BANK1:STATUS.TO 4 Time-out bit BANK1:STATUS.PD 3 Power-down bit BANK1:STATUS.Z 2 Zero bit BANK1:STATUS.DC 1 Digit carry/borrow bit BANK1:STATUS.C 0 Carry/borrow bit BANK1:FSR 0x0084 Indirect data memory address pointer BANK1:TRISA 0x0085 PORTA Data Direction Register BANK1:TRISA.TRISA5 5 PORTA Data Direction Register bit 5 BANK1:TRISA.TRISA4 4 PORTA Data Direction Register bit 4 BANK1:TRISA.TRISA3 3 PORTA Data Direction Register bit 3 BANK1:TRISA.TRISA2 2 PORTA Data Direction Register bit 2 BANK1:TRISA.TRISA1 1 PORTA Data Direction Register bit 1 BANK1:TRISA.TRISA0 0 PORTA Data Direction Register bit 0 BANK1:TRISB 0x0086 PORTB Data Direction Register BANK1:TRISB.TRISB7 7 PORTB Data Direction Register bit 7 BANK1:TRISB.TRISB6 6 PORTB Data Direction Register bit 6 BANK1:TRISB.TRISB5 5 PORTB Data Direction Register bit 5 BANK1:TRISB.TRISB4 4 PORTB Data Direction Register bit 4 BANK1:TRISB.TRISB3 3 PORTB Data Direction Register bit 3 BANK1:TRISB.TRISB2 2 PORTB Data Direction Register bit 2 BANK1:TRISB.TRISB1 1 PORTB Data Direction Register bit 1 BANK1:TRISB.TRISB0 0 PORTB Data Direction Register bit 0 BANK1:TRISC 0x0087 PORTC Data Direction Register BANK1:TRISC.TRISC7 7 PORTC Data Direction Register bit 7 BANK1:TRISC.TRISC6 6 PORTC Data Direction Register bit 6 BANK1:TRISC.TRISC5 5 PORTC Data Direction Register bit 5 BANK1:TRISC.TRISC4 4 PORTC Data Direction Register bit 4 BANK1:TRISC.TRISC3 3 PORTC Data Direction Register bit 3 BANK1:TRISC.TRISC2 2 PORTC Data Direction Register bit 2 BANK1:TRISC.TRISC1 1 PORTC Data Direction Register bit 1 BANK1:TRISC.TRISC0 0 PORTC Data Direction Register bit 0 BANK1:RESERVED0088 0x0088 RESERVED BANK1:RESERVED0089 0x0089 RESERVED BANK1:PCLATH 0x008A Write Buffer for the upper 5 bits of the Program Counter BANK1:INTCON 0x008B INTCON REGISTER BANK1:INTCON.GIE 7 Global Interrupt Enable bit BANK1:INTCON.PEIE 6 Peripheral Interrupt Enable bit BANK1:INTCON.T0IE 5 TMR0 Overflow Interrupt Enable bit BANK1:INTCON.INTE 4 RB0/INT External Interrupt Enable bit BANK1:INTCON.RBIE 3 RB Port Change Interrupt Enable bit BANK1:INTCON.T0IF 2 TMR0 Overflow Interrupt Flag bit BANK1:INTCON.INTF 1 RB0/INT External Interrupt Flag bit BANK1:INTCON.RBIF 0 RB Port Change Interrupt Flag bit BANK1:PIE1 0x008C PIE1 REGISTER BANK1:PIE1.SSPIE 3 Synchronous Serial Port Interrupt Enable bit BANK1:PIE1.CCP1IE 2 CCP1 Interrupt Enable bit BANK1:PIE1.TMR2IE 1 TMR2 to PR2 Match Interrupt Enable bit BANK1:PIE1.TMR1IE 0 TMR1 Overflow Interrupt Enable bit BANK1:RESERVED008D 0x008D RESERVED BANK1:PCON 0x008E PCON REGISTER BANK1:PCON.POR 1 Power-on Reset Status bit BANK1:PCON.BOR 0 Brown-out Reset Status bit BANK1:RESERVED008F 0x008F RESERVED BANK1:RESERVED0090 0x0090 RESERVED BANK1:RESERVED0091 0x0091 RESERVED BANK1:PR2 0x0092 Timer2 Period Register BANK1:SSPADD 0x0093 Synchronous Serial Port (I2C mode) Address Register BANK1:SSPSTAT 0x0094 SYNC SERIAL PORT STATUS REGISTER BANK1:SSPSTAT.D_A 5 Data/Address bit (I2C mode only) BANK1:SSPSTAT.P 4 Stop bit (I2C mode only) BANK1:SSPSTAT.S 3 Start bit (I2C mode only) BANK1:SSPSTAT.R_W 2 Read/Write bit information (I2C mode only) BANK1:SSPSTAT.UA 1 Update Address (I2C mode only) BANK1:SSPSTAT.BF 0 Buffer Full Status bit BANK1:RESERVED0095 0x0095 RESERVED BANK1:RESERVED0096 0x0096 RESERVED BANK1:RESERVED0097 0x0097 RESERVED BANK1:RESERVED0098 0x0098 RESERVED BANK1:RESERVED0099 0x0099 RESERVED BANK1:RESERVED009A 0x009A RESERVED BANK1:RESERVED009B 0x009B RESERVED BANK1:RESERVED009C 0x009C RESERVED BANK1:RESERVED009D 0x009D RESERVED BANK1:RESERVED009E 0x009E RESERVED BANK1:RESERVED009F 0x009F RESERVED .16C63 ; http://www.microchip.com/download/lit/pline/picmicro/families/16c6x/30234d.pdf ; PIC16C6x.pdf ; MEMORY MAP ; BANK_0 area DATA FSR_ 0x0000:0x0020 area DATA Gen_Purp 0x0020:0x0080 General Purpose Register area DATA MEM_Program0 0x0080:0x0800 On-chip Program Memory (Page 0) area DATA MEM_Program1 0x0800:0x1000 On-chip Program Memory (Page 1) ; BANK_1 area DATA FSR_ 0x0080:0x00A0 area DATA Gen_Purp 0x00A0:0x0100 General Purpose Register area DATA MEM_Program0 0x0100:0x0800 On-chip Program Memory (Page 0) area DATA MEM_Program1 0x0800:0x1000 On-chip Program Memory (Page 1) ; Interrupt and reset vector assignments interrupt RESET 0x0000 RESET ; INPUT/OUTPUT PORTS ; BANK0 (0x0000:0x0080) BANK0:INDF 0x0000 INDF (not a physical register) BANK0:TMR0 0x0001 Timer0 module's register BANK0:PCL 0x0002 Program Counter's (PC) Least Significant Byte BANK0:STATUS 0x0003 STATUS REGISTER BANK0:STATUS.RP0 5 Register Bank Select bit 0 BANK0:STATUS.TO 4 Time-out bit BANK0:STATUS.PD 3 Power-down bit BANK0:STATUS.Z 2 Zero bit BANK0:STATUS.DC 1 Digit carry/borrow bit BANK0:STATUS.C 0 Carry/borrow bit BANK0:FSR 0x0004 Indirect data memory address pointer BANK0:PORTA 0x0005 PORTA register BANK0:PORTA.RA5 5 PORTA bit 5 BANK0:PORTA.RA4 4 PORTA bit 4 BANK0:PORTA.RA3 3 PORTA bit 3 BANK0:PORTA.RA2 2 PORTA bit 2 BANK0:PORTA.RA1 1 PORTA bit 1 BANK0:PORTA.RA0 0 PORTA bit 0 BANK0:PORTB 0x0006 PORTB register BANK0:PORTB.RB7 7 PORTB bit 7 BANK0:PORTB.RB6 6 PORTB bit 6 BANK0:PORTB.RB5 5 PORTB bit 5 BANK0:PORTB.RB4 4 PORTB bit 4 BANK0:PORTB.RB3 3 PORTB bit 3 BANK0:PORTB.RB2 2 PORTB bit 2 BANK0:PORTB.RB1 1 PORTB bit 1 BANK0:PORTB.RB0 0 PORTB bit 0 BANK0:PORTC 0x0007 PORTC register BANK0:PORTC.RC7 7 PORTC bit 7 BANK0:PORTC.RC6 6 PORTC bit 6 BANK0:PORTC.RC5 5 PORTC bit 5 BANK0:PORTC.RC4 4 PORTC bit 4 BANK0:PORTC.RC3 3 PORTC bit 3 BANK0:PORTC.RC2 2 PORTC bit 2 BANK0:PORTC.RC1 1 PORTC bit 1 BANK0:PORTC.RC0 0 PORTC bit 0 BANK0:RESERVED0008 0x0008 RESERVED BANK0:RESERVED0009 0x0009 RESERVED BANK0:PCLATH 0x000A Write Buffer for the upper 5 bits of the Program Counter BANK0:INTCON 0x000B INTCON REGISTER BANK0:INTCON.GIE 7 Global Interrupt Enable bit BANK0:INTCON.PEIE 6 Peripheral Interrupt Enable bit BANK0:INTCON.T0IE 5 TMR0 Overflow Interrupt Enable bit BANK0:INTCON.INTE 4 RB0/INT External Interrupt Enable bit BANK0:INTCON.RBIE 3 RB Port Change Interrupt Enable bit BANK0:INTCON.T0IF 2 TMR0 Overflow Interrupt Flag bit BANK0:INTCON.INTF 1 RB0/INT External Interrupt Flag bit BANK0:INTCON.RBIF 0 RB Port Change Interrupt Flag bit BANK0:PIR1 0x000C PIR1 REGISTER BANK0:PIR1.RCIF 5 USART Receive Interrupt Flag bit BANK0:PIR1.TXIF 4 USART Transmit Interrupt Flag bit BANK0:PIR1.SSPIF 3 Synchronous Serial Port Interrupt Flag bit BANK0:PIR1.CCP1IF 2 CCP1 Interrupt Flag bit BANK0:PIR1.TMR2IF 1 TMR2 to PR2 Match Interrupt Flag bit BANK0:PIR1.TMR1IF 0 TMR1 Overflow Interrupt Flag bit BANK0:PIR2 0x000D PIR2 REGISTER BANK0:PIR2.CCP2IF 0 CCP2 Interrupt Flag bit BANK0:TMR1L 0x000E Holding register for the Least Significant Byte of the 16-bit TMR1 register BANK0:TMR1H 0x000F Holding register for the Most Significant Byte of the 16-bit TMR1 register BANK0:T1CON 0x0010 TIMER1 CONTROL REGISTER BANK0:T1CON.T1CKPS1 5 Timer1 Input Clock Prescale Select bit 1 BANK0:T1CON.T1CKPS0 4 Timer1 Input Clock Prescale Select bit 0 BANK0:T1CON.T1OSCEN 3 Timer1 Oscillator Enable Control bit BANK0:T1CON.T1SYNC 2 Timer1 External Clock Input Synchronization Control bit BANK0:T1CON.TMR1CS 1 Timer1 Clock Source Select bit BANK0:T1CON.TMR1ON 0 Timer1 On bit BANK0:TMR2 0x0011 Timer2 module's register BANK0:T2CON 0x0012 TIMER2 CONTROL REGISTER BANK0:T2CON.TOUTPS3 6 Timer2 Output Postscale Select bit 3 BANK0:T2CON.TOUTPS2 5 Timer2 Output Postscale Select bit 2 BANK0:T2CON.TOUTPS1 4 Timer2 Output Postscale Select bit 1 BANK0:T2CON.TOUTPS0 3 Timer2 Output Postscale Select bit 0 BANK0:T2CON.TMR2ON 2 Timer2 On bit BANK0:T2CON.T2CKPS1 1 Timer2 Clock Prescale Select bit 1 BANK0:T2CON.T2CKPS0 0 Timer2 Clock Prescale Select bit 0 BANK0:SSPBUF 0x0013 Synchronous Serial Port Receive Buffer/Transmit Register BANK0:SSPCON 0x0014 SYNC SERIAL PORT CONTROL REGISTER BANK0:SSPCON.WCOL 7 Write Collision Detect bit BANK0:SSPCON.SSPOV 6 Receive Overflow Indicator bit BANK0:SSPCON.SSPEN 5 Synchronous Serial Port Enable bit BANK0:SSPCON.CKP 4 Clock Polarity Select bit BANK0:SSPCON.SSPM3 3 Synchronous Serial Port Mode Select bit 3 BANK0:SSPCON.SSPM2 2 Synchronous Serial Port Mode Select bit 2 BANK0:SSPCON.SSPM1 1 Synchronous Serial Port Mode Select bit 1 BANK0:SSPCON.SSPM0 0 Synchronous Serial Port Mode Select bit 0 BANK0:CCPR1L 0x0015 Capture/Compare/PWM1 (LSB) BANK0:CCPR1H 0x0016 Capture/Compare/PWM1 (MSB) BANK0:CCP1CON 0x0017 CCP1CON REGISTER BANK0:CCP1CON.CCP1X 5 PWM Least Significant bit BANK0:CCP1CON.CCP1Y 4 PWM Least Significant bit BANK0:CCP1CON.CCP1M3 3 CCP1 Mode Select bit 3 BANK0:CCP1CON.CCP1M2 2 CCP1 Mode Select bit 2 BANK0:CCP1CON.CCP1M1 1 CCP1 Mode Select bit 1 BANK0:CCP1CON.CCP1M0 0 CCP1 Mode Select bit 0 BANK0:RCSTA 0x0018 RECEIVE STATUS AND CONTROL REGISTER BANK0:RCSTA.SPEN 7 Serial Port Enable bit BANK0:RCSTA.RX9 6 9-bit Receive Enable bit BANK0:RCSTA.SREN 5 Single Receive Enable bit BANK0:RCSTA.CREN 4 Continuous Receive Enable bit BANK0:RCSTA.FERR 2 Framing Error bit BANK0:RCSTA.OERR 1 Overrun Error bit BANK0:RCSTA.RX9D 0 9th bit of received data BANK0:TXREG 0x0019 USART Transmit Data Register BANK0:RCREG 0x001A USART Receive Data Register BANK0:CCPR2L 0x001B Capture/Compare/PWM2 (LSB) BANK0:CCPR2H 0x001C Capture/Compare/PWM2 (MSB) BANK0:CCP2CON 0x001D CCP2CON REGISTER BANK0:CCP2CON.CCP2X 5 PWM Least Significant bit BANK0:CCP2CON.CCP2Y 4 PWM Least Significant bit BANK0:CCP2CON.CCP2M3 3 CCP2 Mode Select bit 3 BANK0:CCP2CON.CCP2M2 2 CCP2 Mode Select bit 2 BANK0:CCP2CON.CCP2M1 1 CCP2 Mode Select bit 1 BANK0:CCP2CON.CCP2M0 0 CCP2 Mode Select bit 0 BANK0:RESERVED001E 0x001E RESERVED BANK0:RESERVED001F 0x001F RESERVED ; BANK1 (0x0080:0x0100) BANK1:INDF 0x0080 INDF (not a physical register) BANK1:OPTION 0x0081 OPTION REGISTER BANK1:OPTION.RBPU 7 PORTB Pull-up Enable bit BANK1:OPTION.INTEDG 6 Interrupt Edge Select bit BANK1:OPTION.T0CS 5 TMR0 Clock Source Select bit BANK1:OPTION.T0SE 4 TMR0 Source Edge Select bit BANK1:OPTION.PSA 3 Prescaler Assignment bit BANK1:OPTION.PS2 2 Prescaler Rate Select bit 2 BANK1:OPTION.PS1 1 Prescaler Rate Select bit 1 BANK1:OPTION.PS0 0 Prescaler Rate Select bit 0 BANK1:PCL 0x0082 Program Counter's (PC) Least Significant Byte BANK1:STATUS 0x0083 STATUS REGISTER BANK1:STATUS.RP0 5 Register Bank Select bit 0 BANK1:STATUS.TO 4 Time-out bit BANK1:STATUS.PD 3 Power-down bit BANK1:STATUS.Z 2 Zero bit BANK1:STATUS.DC 1 Digit carry/borrow bit BANK1:STATUS.C 0 Carry/borrow bit BANK1:FSR 0x0084 Indirect data memory address pointer BANK1:TRISA 0x0085 PORTA Data Direction Register BANK1:TRISA.TRISA5 5 PORTA Data Direction Register bit 5 BANK1:TRISA.TRISA4 4 PORTA Data Direction Register bit 4 BANK1:TRISA.TRISA3 3 PORTA Data Direction Register bit 3 BANK1:TRISA.TRISA2 2 PORTA Data Direction Register bit 2 BANK1:TRISA.TRISA1 1 PORTA Data Direction Register bit 1 BANK1:TRISA.TRISA0 0 PORTA Data Direction Register bit 0 BANK1:TRISB 0x0086 PORTB Data Direction Register BANK1:TRISB.TRISB7 7 PORTB Data Direction Register bit 7 BANK1:TRISB.TRISB6 6 PORTB Data Direction Register bit 6 BANK1:TRISB.TRISB5 5 PORTB Data Direction Register bit 5 BANK1:TRISB.TRISB4 4 PORTB Data Direction Register bit 4 BANK1:TRISB.TRISB3 3 PORTB Data Direction Register bit 3 BANK1:TRISB.TRISB2 2 PORTB Data Direction Register bit 2 BANK1:TRISB.TRISB1 1 PORTB Data Direction Register bit 1 BANK1:TRISB.TRISB0 0 PORTB Data Direction Register bit 0 BANK1:TRISC 0x0087 PORTC Data Direction Register BANK1:TRISC.TRISC7 7 PORTC Data Direction Register bit 7 BANK1:TRISC.TRISC6 6 PORTC Data Direction Register bit 6 BANK1:TRISC.TRISC5 5 PORTC Data Direction Register bit 5 BANK1:TRISC.TRISC4 4 PORTC Data Direction Register bit 4 BANK1:TRISC.TRISC3 3 PORTC Data Direction Register bit 3 BANK1:TRISC.TRISC2 2 PORTC Data Direction Register bit 2 BANK1:TRISC.TRISC1 1 PORTC Data Direction Register bit 1 BANK1:TRISC.TRISC0 0 PORTC Data Direction Register bit 0 BANK1:RESERVED0088 0x0088 RESERVED BANK1:RESERVED0089 0x0089 RESERVED BANK1:PCLATH 0x008A Write Buffer for the upper 5 bits of the Program Counter BANK1:INTCON 0x008B INTCON REGISTER BANK1:INTCON.GIE 7 Global Interrupt Enable bit BANK1:INTCON.PEIE 6 Peripheral Interrupt Enable bit BANK1:INTCON.T0IE 5 TMR0 Overflow Interrupt Enable bit BANK1:INTCON.INTE 4 RB0/INT External Interrupt Enable bit BANK1:INTCON.RBIE 3 RB Port Change Interrupt Enable bit BANK1:INTCON.T0IF 2 TMR0 Overflow Interrupt Flag bit BANK1:INTCON.INTF 1 RB0/INT External Interrupt Flag bit BANK1:INTCON.RBIF 0 RB Port Change Interrupt Flag bit BANK1:PIE1 0x008C PIE1 REGISTER BANK1:PIE1.RCIE 5 USART Receive Interrupt Enable bit BANK1:PIE1.TXIE 4 USART Transmit Interrupt Enable bit BANK1:PIE1.SSPIE 3 Synchronous Serial Port Interrupt Enable bit BANK1:PIE1.CCP1IE 2 CCP1 Interrupt Enable bit BANK1:PIE1.TMR2IE 1 TMR2 to PR2 Match Interrupt Enable bit BANK1:PIE1.TMR1IE 0 TMR1 Overflow Interrupt Enable bit BANK1:PIE2 0x008D PIE2 REGISTER BANK1:PIE2.CCP2IE 0 CCP2 Interrupt Enable bit BANK1:PCON 0x008E PCON REGISTER BANK1:PCON.POR 1 Power-on Reset Status bit BANK1:PCON.BOR 0 Brown-out Reset Status bit BANK1:RESERVED008F 0x008F RESERVED BANK1:RESERVED0090 0x0090 RESERVED BANK1:RESERVED0091 0x0091 RESERVED BANK1:PR2 0x0092 Timer2 Period Register BANK1:SSPADD 0x0093 Synchronous Serial Port (I2C mode) Address Register BANK1:SSPSTAT 0x0094 SYNC SERIAL PORT STATUS REGISTER BANK1:SSPSTAT.D_A 5 Data/Address bit (I2C mode only) BANK1:SSPSTAT.P 4 Stop bit (I2C mode only) BANK1:SSPSTAT.S 3 Start bit (I2C mode only) BANK1:SSPSTAT.R_W 2 Read/Write bit information (I2C mode only) BANK1:SSPSTAT.UA 1 Update Address (I2C mode only) BANK1:SSPSTAT.BF 0 Buffer Full Status bit BANK1:RESERVED0095 0x0095 RESERVED BANK1:RESERVED0096 0x0096 RESERVED BANK1:RESERVED0097 0x0097 RESERVED BANK1:TXSTA 0x0098 TRANSMIT STATUS AND CONTROL REGISTER BANK1:TXSTA.CSRC 7 Clock Source Select bit BANK1:TXSTA.TX9 6 9-bit Transmit Enable bit BANK1:TXSTA.TXEN 5 Transmit Enable bit BANK1:TXSTA.SYNC 4 USART Mode Select bit BANK1:TXSTA.BRGH 2 High Baud Rate Select bit BANK1:TXSTA.TRMT 1 Transmit Shift Register Status bit BANK1:TXSTA.TX9D 0 9th bit of transmit data BANK1:SPBRG 0x0099 Baud Rate Generator Register BANK1:RESERVED009A 0x009A RESERVED BANK1:RESERVED009B 0x009B RESERVED BANK1:RESERVED009C 0x009C RESERVED BANK1:RESERVED009D 0x009D RESERVED BANK1:RESERVED009E 0x009E RESERVED BANK1:RESERVED009F 0x009F RESERVED .16C64 ; http://www.microchip.com/download/lit/pline/picmicro/families/16c6x/30234d.pdf ; PIC16C6x.pdf ; MEMORY MAP ; BANK_0 area DATA FSR_ 0x0000:0x0020 area DATA Gen_Purp 0x0020:0x0080 General Purpose Register area DATA MEM_Program 0x0080:0x0800 On-chip Program Memory ; BANK_1 area DATA FSR_ 0x0080:0x00A0 area DATA Gen_Purp 0x00A0:0x00C0 General Purpose Register area BSS RESERVED 0x00C0:0x0100 area DATA MEM_Program 0x0100:0x0800 On-chip Program Memory ; Interrupt and reset vector assignments interrupt RESET 0x0000 RESET ; INPUT/OUTPUT PORTS ; BANK0 (0x0000:0x0080) BANK0:INDF 0x0000 INDF (not a physical register) BANK0:TMR0 0x0001 Timer0 module's register BANK0:PCL 0x0002 Program Counter's (PC) Least Significant Byte BANK0:STATUS 0x0003 STATUS REGISTER BANK0:STATUS.RP0 5 Register Bank Select bit 0 BANK0:STATUS.TO 4 Time-out bit BANK0:STATUS.PD 3 Power-down bit BANK0:STATUS.Z 2 Zero bit BANK0:STATUS.DC 1 Digit carry/borrow bit BANK0:STATUS.C 0 Carry/borrow bit BANK0:FSR 0x0004 Indirect data memory address pointer BANK0:PORTA 0x0005 PORTA register BANK0:PORTA.RA5 5 PORTA bit 5 BANK0:PORTA.RA4 4 PORTA bit 4 BANK0:PORTA.RA3 3 PORTA bit 3 BANK0:PORTA.RA2 2 PORTA bit 2 BANK0:PORTA.RA1 1 PORTA bit 1 BANK0:PORTA.RA0 0 PORTA bit 0 BANK0:PORTB 0x0006 PORTB register BANK0:PORTB.RB7 7 PORTB bit 7 BANK0:PORTB.RB6 6 PORTB bit 6 BANK0:PORTB.RB5 5 PORTB bit 5 BANK0:PORTB.RB4 4 PORTB bit 4 BANK0:PORTB.RB3 3 PORTB bit 3 BANK0:PORTB.RB2 2 PORTB bit 2 BANK0:PORTB.RB1 1 PORTB bit 1 BANK0:PORTB.RB0 0 PORTB bit 0 BANK0:PORTC 0x0007 PORTC register BANK0:PORTC.RC7 7 PORTC bit 7 BANK0:PORTC.RC6 6 PORTC bit 6 BANK0:PORTC.RC5 5 PORTC bit 5 BANK0:PORTC.RC4 4 PORTC bit 4 BANK0:PORTC.RC3 3 PORTC bit 3 BANK0:PORTC.RC2 2 PORTC bit 2 BANK0:PORTC.RC1 1 PORTC bit 1 BANK0:PORTC.RC0 0 PORTC bit 0 BANK0:PORTD 0x0008 PORTD register BANK0:PORTD.RD7 7 PORTD bit 7 BANK0:PORTD.RD6 6 PORTD bit 6 BANK0:PORTD.RD5 5 PORTD bit 5 BANK0:PORTD.RD4 4 PORTD bit 4 BANK0:PORTD.RD3 3 PORTD bit 3 BANK0:PORTD.RD2 2 PORTD bit 2 BANK0:PORTD.RD1 1 PORTD bit 1 BANK0:PORTD.RD0 0 PORTD bit 0 BANK0:PORTE 0x0009 PORTE register BANK0:PORTE.RE2 2 PORTE bit 2 BANK0:PORTE.RE1 1 PORTE bit 1 BANK0:PORTE.RE0 0 PORTE bit 0 BANK0:PCLATH 0x000A Write Buffer for the upper 5 bits of the Program Counter BANK0:INTCON 0x000B INTCON REGISTER BANK0:INTCON.GIE 7 Global Interrupt Enable bit BANK0:INTCON.PEIE 6 Peripheral Interrupt Enable bit BANK0:INTCON.T0IE 5 TMR0 Overflow Interrupt Enable bit BANK0:INTCON.INTE 4 RB0/INT External Interrupt Enable bit BANK0:INTCON.RBIE 3 RB Port Change Interrupt Enable bit BANK0:INTCON.T0IF 2 TMR0 Overflow Interrupt Flag bit BANK0:INTCON.INTF 1 RB0/INT External Interrupt Flag bit BANK0:INTCON.RBIF 0 RB Port Change Interrupt Flag bit BANK0:PIR1 0x000C PIR1 REGISTER BANK0:PIR1.PSPIF 7 Parallel Slave Port Interrupt Flag bit BANK0:PIR1.SSPIF 3 Synchronous Serial Port Interrupt Flag bit BANK0:PIR1.CCP1IF 2 CCP1 Interrupt Flag bit BANK0:PIR1.TMR2IF 1 TMR2 to PR2 Match Interrupt Flag bit BANK0:PIR1.TMR1IF 0 TMR1 Overflow Interrupt Flag bit BANK0:RESERVED000D 0x000D RESERVED BANK0:TMR1L 0x000E Holding register for the Least Significant Byte of the 16-bit TMR1 register BANK0:TMR1H 0x000F Holding register for the Most Significant Byte of the 16-bit TMR1 register BANK0:T1CON 0x0010 TIMER1 CONTROL REGISTER BANK0:T1CON.T1CKPS1 5 Timer1 Input Clock Prescale Select bit 1 BANK0:T1CON.T1CKPS0 4 Timer1 Input Clock Prescale Select bit 0 BANK0:T1CON.T1OSCEN 3 Timer1 Oscillator Enable Control bit BANK0:T1CON.T1SYNC 2 Timer1 External Clock Input Synchronization Control bit BANK0:T1CON.TMR1CS 1 Timer1 Clock Source Select bit BANK0:T1CON.TMR1ON 0 Timer1 On bit BANK0:TMR2 0x0011 Timer2 module's register BANK0:T2CON 0x0012 TIMER2 CONTROL REGISTER BANK0:T2CON.TOUTPS3 6 Timer2 Output Postscale Select bit 3 BANK0:T2CON.TOUTPS2 5 Timer2 Output Postscale Select bit 2 BANK0:T2CON.TOUTPS1 4 Timer2 Output Postscale Select bit 1 BANK0:T2CON.TOUTPS0 3 Timer2 Output Postscale Select bit 0 BANK0:T2CON.TMR2ON 2 Timer2 On bit BANK0:T2CON.T2CKPS1 1 Timer2 Clock Prescale Select bit 1 BANK0:T2CON.T2CKPS0 0 Timer2 Clock Prescale Select bit 0 BANK0:SSPBUF 0x0013 Synchronous Serial Port Receive Buffer/Transmit Register BANK0:SSPCON 0x0014 SYNC SERIAL PORT CONTROL REGISTER BANK0:SSPCON.WCOL 7 Write Collision Detect bit BANK0:SSPCON.SSPOV 6 Receive Overflow Indicator bit BANK0:SSPCON.SSPEN 5 Synchronous Serial Port Enable bit BANK0:SSPCON.CKP 4 Clock Polarity Select bit BANK0:SSPCON.SSPM3 3 Synchronous Serial Port Mode Select bit 3 BANK0:SSPCON.SSPM2 2 Synchronous Serial Port Mode Select bit 2 BANK0:SSPCON.SSPM1 1 Synchronous Serial Port Mode Select bit 1 BANK0:SSPCON.SSPM0 0 Synchronous Serial Port Mode Select bit 0 BANK0:CCPR1L 0x0015 Capture/Compare/PWM1 (LSB) BANK0:CCPR1H 0x0016 Capture/Compare/PWM1 (MSB) BANK0:CCP1CON 0x0017 CCP1CON REGISTER BANK0:CCP1CON.CCP1X 5 PWM Least Significant bit BANK0:CCP1CON.CCP1Y 4 PWM Least Significant bit BANK0:CCP1CON.CCP1M3 3 CCP1 Mode Select bit 3 BANK0:CCP1CON.CCP1M2 2 CCP1 Mode Select bit 2 BANK0:CCP1CON.CCP1M1 1 CCP1 Mode Select bit 1 BANK0:CCP1CON.CCP1M0 0 CCP1 Mode Select bit 0 ; BANK1 (0x0080:0x0100) BANK1:INDF 0x0080 INDF (not a physical register) BANK1:OPTION 0x0081 OPTION REGISTER BANK1:OPTION.RBPU 7 PORTB Pull-up Enable bit BANK1:OPTION.INTEDG 6 Interrupt Edge Select bit BANK1:OPTION.T0CS 5 TMR0 Clock Source Select bit BANK1:OPTION.T0SE 4 TMR0 Source Edge Select bit BANK1:OPTION.PSA 3 Prescaler Assignment bit BANK1:OPTION.PS2 2 Prescaler Rate Select bit 2 BANK1:OPTION.PS1 1 Prescaler Rate Select bit 1 BANK1:OPTION.PS0 0 Prescaler Rate Select bit 0 BANK1:PCL 0x0082 Program Counter's (PC) Least Significant Byte BANK1:STATUS 0x0083 STATUS REGISTER BANK1:STATUS.RP0 5 Register Bank Select bit 0 BANK1:STATUS.TO 4 Time-out bit BANK1:STATUS.PD 3 Power-down bit BANK1:STATUS.Z 2 Zero bit BANK1:STATUS.DC 1 Digit carry/borrow bit BANK1:STATUS.C 0 Carry/borrow bit BANK1:FSR 0x0084 Indirect data memory address pointer BANK1:TRISA 0x0085 PORTA Data Direction Register BANK1:TRISA.TRISA5 5 PORTA Data Direction Register bit 5 BANK1:TRISA.TRISA4 4 PORTA Data Direction Register bit 4 BANK1:TRISA.TRISA3 3 PORTA Data Direction Register bit 3 BANK1:TRISA.TRISA2 2 PORTA Data Direction Register bit 2 BANK1:TRISA.TRISA1 1 PORTA Data Direction Register bit 1 BANK1:TRISA.TRISA0 0 PORTA Data Direction Register bit 0 BANK1:TRISB 0x0086 PORTB Data Direction Register BANK1:TRISB.TRISB7 7 PORTB Data Direction Register bit 7 BANK1:TRISB.TRISB6 6 PORTB Data Direction Register bit 6 BANK1:TRISB.TRISB5 5 PORTB Data Direction Register bit 5 BANK1:TRISB.TRISB4 4 PORTB Data Direction Register bit 4 BANK1:TRISB.TRISB3 3 PORTB Data Direction Register bit 3 BANK1:TRISB.TRISB2 2 PORTB Data Direction Register bit 2 BANK1:TRISB.TRISB1 1 PORTB Data Direction Register bit 1 BANK1:TRISB.TRISB0 0 PORTB Data Direction Register bit 0 BANK1:TRISC 0x0087 PORTC Data Direction Register BANK1:TRISC.TRISC7 7 PORTC Data Direction Register bit 7 BANK1:TRISC.TRISC6 6 PORTC Data Direction Register bit 6 BANK1:TRISC.TRISC5 5 PORTC Data Direction Register bit 5 BANK1:TRISC.TRISC4 4 PORTC Data Direction Register bit 4 BANK1:TRISC.TRISC3 3 PORTC Data Direction Register bit 3 BANK1:TRISC.TRISC2 2 PORTC Data Direction Register bit 2 BANK1:TRISC.TRISC1 1 PORTC Data Direction Register bit 1 BANK1:TRISC.TRISC0 0 PORTC Data Direction Register bit 0 BANK1:TRISD 0x0088 PORTD Data Direction Register BANK1:TRISD.TRISD7 7 PORTD Data Direction Register bit 7 BANK1:TRISD.TRISD6 6 PORTD Data Direction Register bit 6 BANK1:TRISD.TRISD5 5 PORTD Data Direction Register bit 5 BANK1:TRISD.TRISD4 4 PORTD Data Direction Register bit 4 BANK1:TRISD.TRISD3 3 PORTD Data Direction Register bit 3 BANK1:TRISD.TRISD2 2 PORTD Data Direction Register bit 2 BANK1:TRISD.TRISD1 1 PORTD Data Direction Register bit 1 BANK1:TRISD.TRISD0 0 PORTD Data Direction Register bit 0 BANK1:TRISE 0x0089 PORTE Data Direction Register BANK1:TRISE.IBF 7 Input Buffer Full Status bit BANK1:TRISE.OBF 6 Output Buffer Full Status bit BANK1:TRISE.IBOV 5 Input Buffer Overflow Detect bit BANK1:TRISE.PSPMODE 4 Parallel Slave Port Mode Select bit BANK1:TRISE.TRISE2 2 Direction Control bit for pin RE2/CS BANK1:TRISE.TRISE1 1 Direction Control bit for pin RE1/WR BANK1:TRISE.TRISE0 0 Direction Control bit for pin RE0/RD BANK1:PCLATH 0x008A Write Buffer for the upper 5 bits of the Program Counter BANK1:INTCON 0x008B INTCON REGISTER BANK1:INTCON.GIE 7 Global Interrupt Enable bit BANK1:INTCON.PEIE 6 Peripheral Interrupt Enable bit BANK1:INTCON.T0IE 5 TMR0 Overflow Interrupt Enable bit BANK1:INTCON.INTE 4 RB0/INT External Interrupt Enable bit BANK1:INTCON.RBIE 3 RB Port Change Interrupt Enable bit BANK1:INTCON.T0IF 2 TMR0 Overflow Interrupt Flag bit BANK1:INTCON.INTF 1 RB0/INT External Interrupt Flag bit BANK1:INTCON.RBIF 0 RB Port Change Interrupt Flag bit BANK1:PIE1 0x008C PIE1 REGISTER BANK1:PIE1.SSPIE 3 Synchronous Serial Port Interrupt Enable bit BANK1:PIE1.CCP1IE 2 CCP1 Interrupt Enable bit BANK1:PIE1.TMR2IE 1 TMR2 to PR2 Match Interrupt Enable bit BANK1:PIE1.TMR1IE 0 TMR1 Overflow Interrupt Enable bit BANK1:RESERVED008D 0x008D RESERVED BANK1:PCON 0x008E PCON REGISTER BANK1:PCON.POR 1 Power-on Reset Status bit BANK1:RESERVED008F 0x008F RESERVED BANK1:RESERVED0090 0x0090 RESERVED BANK1:RESERVED0091 0x0091 RESERVED BANK1:PR2 0x0092 Timer2 Period Register BANK1:SSPADD 0x0093 Synchronous Serial Port (I2C mode) Address Register BANK1:SSPSTAT 0x0094 SYNC SERIAL PORT STATUS REGISTER BANK1:SSPSTAT.D_A 5 Data/Address bit (I2C mode only) BANK1:SSPSTAT.P 4 Stop bit (I2C mode only) BANK1:SSPSTAT.S 3 Start bit (I2C mode only) BANK1:SSPSTAT.R_W 2 Read/Write bit information (I2C mode only) BANK1:SSPSTAT.UA 1 Update Address (I2C mode only) BANK1:SSPSTAT.BF 0 Buffer Full Status bit BANK1:RESERVED0095 0x0095 RESERVED BANK1:RESERVED0096 0x0096 RESERVED BANK1:RESERVED0097 0x0097 RESERVED BANK1:RESERVED0098 0x0098 RESERVED BANK1:RESERVED0099 0x0099 RESERVED BANK1:RESERVED009A 0x009A RESERVED BANK1:RESERVED009B 0x009B RESERVED BANK1:RESERVED009C 0x009C RESERVED BANK1:RESERVED009D 0x009D RESERVED BANK1:RESERVED009E 0x009E RESERVED BANK1:RESERVED009F 0x009F RESERVED .16C64A ; http://www.microchip.com/download/lit/pline/picmicro/families/16c6x/30234d.pdf ; PIC16C6x.pdf ; MEMORY MAP ; BANK_0 area DATA FSR_ 0x0000:0x0020 area DATA Gen_Purp 0x0020:0x0080 General Purpose Register area DATA MEM_Program 0x0080:0x0800 On-chip Program Memory ; BANK_1 area DATA FSR_ 0x0080:0x00A0 area DATA Gen_Purp 0x00A0:0x00C0 General Purpose Register area BSS RESERVED 0x00C0:0x0100 area DATA MEM_Program 0x0100:0x0800 On-chip Program Memory ; Interrupt and reset vector assignments interrupt RESET 0x0000 RESET ; INPUT/OUTPUT PORTS ; BANK0 (0x0000:0x0080) BANK0:INDF 0x0000 INDF (not a physical register) BANK0:TMR0 0x0001 Timer0 module's register BANK0:PCL 0x0002 Program Counter's (PC) Least Significant Byte BANK0:STATUS 0x0003 STATUS REGISTER BANK0:STATUS.RP0 5 Register Bank Select bit 0 BANK0:STATUS.TO 4 Time-out bit BANK0:STATUS.PD 3 Power-down bit BANK0:STATUS.Z 2 Zero bit BANK0:STATUS.DC 1 Digit carry/borrow bit BANK0:STATUS.C 0 Carry/borrow bit BANK0:FSR 0x0004 Indirect data memory address pointer BANK0:PORTA 0x0005 PORTA register BANK0:PORTA.RA5 5 PORTA bit 5 BANK0:PORTA.RA4 4 PORTA bit 4 BANK0:PORTA.RA3 3 PORTA bit 3 BANK0:PORTA.RA2 2 PORTA bit 2 BANK0:PORTA.RA1 1 PORTA bit 1 BANK0:PORTA.RA0 0 PORTA bit 0 BANK0:PORTB 0x0006 PORTB register BANK0:PORTB.RB7 7 PORTB bit 7 BANK0:PORTB.RB6 6 PORTB bit 6 BANK0:PORTB.RB5 5 PORTB bit 5 BANK0:PORTB.RB4 4 PORTB bit 4 BANK0:PORTB.RB3 3 PORTB bit 3 BANK0:PORTB.RB2 2 PORTB bit 2 BANK0:PORTB.RB1 1 PORTB bit 1 BANK0:PORTB.RB0 0 PORTB bit 0 BANK0:PORTC 0x0007 PORTC register BANK0:PORTC.RC7 7 PORTC bit 7 BANK0:PORTC.RC6 6 PORTC bit 6 BANK0:PORTC.RC5 5 PORTC bit 5 BANK0:PORTC.RC4 4 PORTC bit 4 BANK0:PORTC.RC3 3 PORTC bit 3 BANK0:PORTC.RC2 2 PORTC bit 2 BANK0:PORTC.RC1 1 PORTC bit 1 BANK0:PORTC.RC0 0 PORTC bit 0 BANK0:PORTD 0x0008 PORTD register BANK0:PORTD.RD7 7 PORTD bit 7 BANK0:PORTD.RD6 6 PORTD bit 6 BANK0:PORTD.RD5 5 PORTD bit 5 BANK0:PORTD.RD4 4 PORTD bit 4 BANK0:PORTD.RD3 3 PORTD bit 3 BANK0:PORTD.RD2 2 PORTD bit 2 BANK0:PORTD.RD1 1 PORTD bit 1 BANK0:PORTD.RD0 0 PORTD bit 0 BANK0:PORTE 0x0009 PORTE register BANK0:PORTE.RE2 2 PORTE bit 2 BANK0:PORTE.RE1 1 PORTE bit 1 BANK0:PORTE.RE0 0 PORTE bit 0 BANK0:PCLATH 0x000A Write Buffer for the upper 5 bits of the Program Counter BANK0:INTCON 0x000B INTCON REGISTER BANK0:INTCON.GIE 7 Global Interrupt Enable bit BANK0:INTCON.PEIE 6 Peripheral Interrupt Enable bit BANK0:INTCON.T0IE 5 TMR0 Overflow Interrupt Enable bit BANK0:INTCON.INTE 4 RB0/INT External Interrupt Enable bit BANK0:INTCON.RBIE 3 RB Port Change Interrupt Enable bit BANK0:INTCON.T0IF 2 TMR0 Overflow Interrupt Flag bit BANK0:INTCON.INTF 1 RB0/INT External Interrupt Flag bit BANK0:INTCON.RBIF 0 RB Port Change Interrupt Flag bit BANK0:PIR1 0x000C PIR1 REGISTER BANK0:PIR1.PSPIF 7 Parallel Slave Port Interrupt Flag bit BANK0:PIR1.SSPIF 3 Synchronous Serial Port Interrupt Flag bit BANK0:PIR1.CCP1IF 2 CCP1 Interrupt Flag bit BANK0:PIR1.TMR2IF 1 TMR2 to PR2 Match Interrupt Flag bit BANK0:PIR1.TMR1IF 0 TMR1 Overflow Interrupt Flag bit BANK0:RESERVED000D 0x000D RESERVED BANK0:TMR1L 0x000E Holding register for the Least Significant Byte of the 16-bit TMR1 register BANK0:TMR1H 0x000F Holding register for the Most Significant Byte of the 16-bit TMR1 register BANK0:T1CON 0x0010 TIMER1 CONTROL REGISTER BANK0:T1CON.T1CKPS1 5 Timer1 Input Clock Prescale Select bit 1 BANK0:T1CON.T1CKPS0 4 Timer1 Input Clock Prescale Select bit 0 BANK0:T1CON.T1OSCEN 3 Timer1 Oscillator Enable Control bit BANK0:T1CON.T1SYNC 2 Timer1 External Clock Input Synchronization Control bit BANK0:T1CON.TMR1CS 1 Timer1 Clock Source Select bit BANK0:T1CON.TMR1ON 0 Timer1 On bit BANK0:TMR2 0x0011 Timer2 module's register BANK0:T2CON 0x0012 TIMER2 CONTROL REGISTER BANK0:T2CON.TOUTPS3 6 Timer2 Output Postscale Select bit 3 BANK0:T2CON.TOUTPS2 5 Timer2 Output Postscale Select bit 2 BANK0:T2CON.TOUTPS1 4 Timer2 Output Postscale Select bit 1 BANK0:T2CON.TOUTPS0 3 Timer2 Output Postscale Select bit 0 BANK0:T2CON.TMR2ON 2 Timer2 On bit BANK0:T2CON.T2CKPS1 1 Timer2 Clock Prescale Select bit 1 BANK0:T2CON.T2CKPS0 0 Timer2 Clock Prescale Select bit 0 BANK0:SSPBUF 0x0013 Synchronous Serial Port Receive Buffer/Transmit Register BANK0:SSPCON 0x0014 SYNC SERIAL PORT CONTROL REGISTER BANK0:SSPCON.WCOL 7 Write Collision Detect bit BANK0:SSPCON.SSPOV 6 Receive Overflow Indicator bit BANK0:SSPCON.SSPEN 5 Synchronous Serial Port Enable bit BANK0:SSPCON.CKP 4 Clock Polarity Select bit BANK0:SSPCON.SSPM3 3 Synchronous Serial Port Mode Select bit 3 BANK0:SSPCON.SSPM2 2 Synchronous Serial Port Mode Select bit 2 BANK0:SSPCON.SSPM1 1 Synchronous Serial Port Mode Select bit 1 BANK0:SSPCON.SSPM0 0 Synchronous Serial Port Mode Select bit 0 BANK0:CCPR1L 0x0015 Capture/Compare/PWM1 (LSB) BANK0:CCPR1H 0x0016 Capture/Compare/PWM1 (MSB) BANK0:CCP1CON 0x0017 CCP1CON REGISTER BANK0:CCP1CON.CCP1X 5 PWM Least Significant bit BANK0:CCP1CON.CCP1Y 4 PWM Least Significant bit BANK0:CCP1CON.CCP1M3 3 CCP1 Mode Select bit 3 BANK0:CCP1CON.CCP1M2 2 CCP1 Mode Select bit 2 BANK0:CCP1CON.CCP1M1 1 CCP1 Mode Select bit 1 BANK0:CCP1CON.CCP1M0 0 CCP1 Mode Select bit 0 ; BANK1 (0x0080:0x0100) BANK1:INDF 0x0080 INDF (not a physical register) BANK1:OPTION 0x0081 OPTION REGISTER BANK1:OPTION.RBPU 7 PORTB Pull-up Enable bit BANK1:OPTION.INTEDG 6 Interrupt Edge Select bit BANK1:OPTION.T0CS 5 TMR0 Clock Source Select bit BANK1:OPTION.T0SE 4 TMR0 Source Edge Select bit BANK1:OPTION.PSA 3 Prescaler Assignment bit BANK1:OPTION.PS2 2 Prescaler Rate Select bit 2 BANK1:OPTION.PS1 1 Prescaler Rate Select bit 1 BANK1:OPTION.PS0 0 Prescaler Rate Select bit 0 BANK1:PCL 0x0082 Program Counter's (PC) Least Significant Byte BANK1:STATUS 0x0083 STATUS REGISTER BANK1:STATUS.RP0 5 Register Bank Select bit 0 BANK1:STATUS.TO 4 Time-out bit BANK1:STATUS.PD 3 Power-down bit BANK1:STATUS.Z 2 Zero bit BANK1:STATUS.DC 1 Digit carry/borrow bit BANK1:STATUS.C 0 Carry/borrow bit BANK1:FSR 0x0084 Indirect data memory address pointer BANK1:TRISA 0x0085 PORTA Data Direction Register BANK1:TRISA.TRISA5 5 PORTA Data Direction Register bit 5 BANK1:TRISA.TRISA4 4 PORTA Data Direction Register bit 4 BANK1:TRISA.TRISA3 3 PORTA Data Direction Register bit 3 BANK1:TRISA.TRISA2 2 PORTA Data Direction Register bit 2 BANK1:TRISA.TRISA1 1 PORTA Data Direction Register bit 1 BANK1:TRISA.TRISA0 0 PORTA Data Direction Register bit 0 BANK1:TRISB 0x0086 PORTB Data Direction Register BANK1:TRISB.TRISB7 7 PORTB Data Direction Register bit 7 BANK1:TRISB.TRISB6 6 PORTB Data Direction Register bit 6 BANK1:TRISB.TRISB5 5 PORTB Data Direction Register bit 5 BANK1:TRISB.TRISB4 4 PORTB Data Direction Register bit 4 BANK1:TRISB.TRISB3 3 PORTB Data Direction Register bit 3 BANK1:TRISB.TRISB2 2 PORTB Data Direction Register bit 2 BANK1:TRISB.TRISB1 1 PORTB Data Direction Register bit 1 BANK1:TRISB.TRISB0 0 PORTB Data Direction Register bit 0 BANK1:TRISC 0x0087 PORTC Data Direction Register BANK1:TRISC.TRISC7 7 PORTC Data Direction Register bit 7 BANK1:TRISC.TRISC6 6 PORTC Data Direction Register bit 6 BANK1:TRISC.TRISC5 5 PORTC Data Direction Register bit 5 BANK1:TRISC.TRISC4 4 PORTC Data Direction Register bit 4 BANK1:TRISC.TRISC3 3 PORTC Data Direction Register bit 3 BANK1:TRISC.TRISC2 2 PORTC Data Direction Register bit 2 BANK1:TRISC.TRISC1 1 PORTC Data Direction Register bit 1 BANK1:TRISC.TRISC0 0 PORTC Data Direction Register bit 0 BANK1:TRISD 0x0088 PORTD Data Direction Register BANK1:TRISD.TRISD7 7 PORTD Data Direction Register bit 7 BANK1:TRISD.TRISD6 6 PORTD Data Direction Register bit 6 BANK1:TRISD.TRISD5 5 PORTD Data Direction Register bit 5 BANK1:TRISD.TRISD4 4 PORTD Data Direction Register bit 4 BANK1:TRISD.TRISD3 3 PORTD Data Direction Register bit 3 BANK1:TRISD.TRISD2 2 PORTD Data Direction Register bit 2 BANK1:TRISD.TRISD1 1 PORTD Data Direction Register bit 1 BANK1:TRISD.TRISD0 0 PORTD Data Direction Register bit 0 BANK1:TRISE 0x0089 PORTE Data Direction Register BANK1:TRISE.IBF 7 Input Buffer Full Status bit BANK1:TRISE.OBF 6 Output Buffer Full Status bit BANK1:TRISE.IBOV 5 Input Buffer Overflow Detect bit BANK1:TRISE.PSPMODE 4 Parallel Slave Port Mode Select bit BANK1:TRISE.TRISE2 2 Direction Control bit for pin RE2/CS BANK1:TRISE.TRISE1 1 Direction Control bit for pin RE1/WR BANK1:TRISE.TRISE0 0 Direction Control bit for pin RE0/RD BANK1:PCLATH 0x008A Write Buffer for the upper 5 bits of the Program Counter BANK1:INTCON 0x008B INTCON REGISTER BANK1:INTCON.GIE 7 Global Interrupt Enable bit BANK1:INTCON.PEIE 6 Peripheral Interrupt Enable bit BANK1:INTCON.T0IE 5 TMR0 Overflow Interrupt Enable bit BANK1:INTCON.INTE 4 RB0/INT External Interrupt Enable bit BANK1:INTCON.RBIE 3 RB Port Change Interrupt Enable bit BANK1:INTCON.T0IF 2 TMR0 Overflow Interrupt Flag bit BANK1:INTCON.INTF 1 RB0/INT External Interrupt Flag bit BANK1:INTCON.RBIF 0 RB Port Change Interrupt Flag bit BANK1:PIE1 0x008C PIE1 REGISTER BANK1:PIE1.SSPIE 3 Synchronous Serial Port Interrupt Enable bit BANK1:PIE1.CCP1IE 2 CCP1 Interrupt Enable bit BANK1:PIE1.TMR2IE 1 TMR2 to PR2 Match Interrupt Enable bit BANK1:PIE1.TMR1IE 0 TMR1 Overflow Interrupt Enable bit BANK1:RESERVED008D 0x008D RESERVED BANK1:PCON 0x008E PCON REGISTER BANK1:PCON.POR 1 Power-on Reset Status bit BANK1:PCON.BOR 0 Brown-out Reset Status bit BANK1:RESERVED008F 0x008F RESERVED BANK1:RESERVED0090 0x0090 RESERVED BANK1:RESERVED0091 0x0091 RESERVED BANK1:PR2 0x0092 Timer2 Period Register BANK1:SSPADD 0x0093 Synchronous Serial Port (I2C mode) Address Register BANK1:SSPSTAT 0x0094 SYNC SERIAL PORT STATUS REGISTER BANK1:SSPSTAT.D_A 5 Data/Address bit (I2C mode only) BANK1:SSPSTAT.P 4 Stop bit (I2C mode only) BANK1:SSPSTAT.S 3 Start bit (I2C mode only) BANK1:SSPSTAT.R_W 2 Read/Write bit information (I2C mode only) BANK1:SSPSTAT.UA 1 Update Address (I2C mode only) BANK1:SSPSTAT.BF 0 Buffer Full Status bit BANK1:RESERVED0095 0x0095 RESERVED BANK1:RESERVED0096 0x0096 RESERVED BANK1:RESERVED0097 0x0097 RESERVED BANK1:RESERVED0098 0x0098 RESERVED BANK1:RESERVED0099 0x0099 RESERVED BANK1:RESERVED009A 0x009A RESERVED BANK1:RESERVED009B 0x009B RESERVED BANK1:RESERVED009C 0x009C RESERVED BANK1:RESERVED009D 0x009D RESERVED BANK1:RESERVED009E 0x009E RESERVED BANK1:RESERVED009F 0x009F RESERVED .16C65 ; http://www.microchip.com/download/lit/pline/picmicro/families/16c6x/30234d.pdf ; PIC16C6x.pdf ; MEMORY MAP ; BANK_0 area DATA FSR_ 0x0000:0x0020 area DATA Gen_Purp 0x0020:0x0080 General Purpose Register area DATA MEM_Program0 0x0080:0x0800 On-chip Program Memory (Page 0) area DATA MEM_Program1 0x0800:0x1000 On-chip Program Memory (Page 1) ; BANK_1 area DATA FSR_ 0x0080:0x00A0 area DATA Gen_Purp 0x00A0:0x0100 General Purpose Register area DATA MEM_Program0 0x0100:0x0800 On-chip Program Memory (Page 0) area DATA MEM_Program1 0x0800:0x1000 On-chip Program Memory (Page 1) ; Interrupt and reset vector assignments interrupt RESET 0x0000 RESET ; INPUT/OUTPUT PORTS ; BANK0 (0x0000:0x0080) BANK0:INDF 0x0000 INDF (not a physical register) BANK0:TMR0 0x0001 Timer0 module's register BANK0:PCL 0x0002 Program Counter's (PC) Least Significant Byte BANK0:STATUS 0x0003 STATUS REGISTER BANK0:STATUS.RP0 5 Register Bank Select bit 0 BANK0:STATUS.TO 4 Time-out bit BANK0:STATUS.PD 3 Power-down bit BANK0:STATUS.Z 2 Zero bit BANK0:STATUS.DC 1 Digit carry/borrow bit BANK0:STATUS.C 0 Carry/borrow bit BANK0:FSR 0x0004 Indirect data memory address pointer BANK0:PORTA 0x0005 PORTA register BANK0:PORTA.RA5 5 PORTA bit 5 BANK0:PORTA.RA4 4 PORTA bit 4 BANK0:PORTA.RA3 3 PORTA bit 3 BANK0:PORTA.RA2 2 PORTA bit 2 BANK0:PORTA.RA1 1 PORTA bit 1 BANK0:PORTA.RA0 0 PORTA bit 0 BANK0:PORTB 0x0006 PORTB register BANK0:PORTB.RB7 7 PORTB bit 7 BANK0:PORTB.RB6 6 PORTB bit 6 BANK0:PORTB.RB5 5 PORTB bit 5 BANK0:PORTB.RB4 4 PORTB bit 4 BANK0:PORTB.RB3 3 PORTB bit 3 BANK0:PORTB.RB2 2 PORTB bit 2 BANK0:PORTB.RB1 1 PORTB bit 1 BANK0:PORTB.RB0 0 PORTB bit 0 BANK0:PORTC 0x0007 PORTC register BANK0:PORTC.RC7 7 PORTC bit 7 BANK0:PORTC.RC6 6 PORTC bit 6 BANK0:PORTC.RC5 5 PORTC bit 5 BANK0:PORTC.RC4 4 PORTC bit 4 BANK0:PORTC.RC3 3 PORTC bit 3 BANK0:PORTC.RC2 2 PORTC bit 2 BANK0:PORTC.RC1 1 PORTC bit 1 BANK0:PORTC.RC0 0 PORTC bit 0 BANK0:PORTD 0x0008 PORTD register BANK0:PORTD.RD7 7 PORTD bit 7 BANK0:PORTD.RD6 6 PORTD bit 6 BANK0:PORTD.RD5 5 PORTD bit 5 BANK0:PORTD.RD4 4 PORTD bit 4 BANK0:PORTD.RD3 3 PORTD bit 3 BANK0:PORTD.RD2 2 PORTD bit 2 BANK0:PORTD.RD1 1 PORTD bit 1 BANK0:PORTD.RD0 0 PORTD bit 0 BANK0:PORTE 0x0009 PORTE register BANK0:PORTE.RE2 2 PORTE bit 2 BANK0:PORTE.RE1 1 PORTE bit 1 BANK0:PORTE.RE0 0 PORTE bit 0 BANK0:PCLATH 0x000A Write Buffer for the upper 5 bits of the Program Counter BANK0:INTCON 0x000B INTCON REGISTER BANK0:INTCON.GIE 7 Global Interrupt Enable bit BANK0:INTCON.PEIE 6 Peripheral Interrupt Enable bit BANK0:INTCON.T0IE 5 TMR0 Overflow Interrupt Enable bit BANK0:INTCON.INTE 4 RB0/INT External Interrupt Enable bit BANK0:INTCON.RBIE 3 RB Port Change Interrupt Enable bit BANK0:INTCON.T0IF 2 TMR0 Overflow Interrupt Flag bit BANK0:INTCON.INTF 1 RB0/INT External Interrupt Flag bit BANK0:INTCON.RBIF 0 RB Port Change Interrupt Flag bit BANK0:PIR1 0x000C PIR1 REGISTER BANK0:PIR1.PSPIF 7 Parallel Slave Port Interrupt Flag bit BANK0:PIR1.RCIF 5 USART Receive Interrupt Flag bit BANK0:PIR1.TXIF 4 USART Transmit Interrupt Flag bit BANK0:PIR1.SSPIF 3 Synchronous Serial Port Interrupt Flag bit BANK0:PIR1.CCP1IF 2 CCP1 Interrupt Flag bit BANK0:PIR1.TMR2IF 1 TMR2 to PR2 Match Interrupt Flag bit BANK0:PIR1.TMR1IF 0 TMR1 Overflow Interrupt Flag bit BANK0:PIR2 0x000D PIR2 REGISTER BANK0:PIR2.CCP2IF 0 CCP2 Interrupt Flag bit BANK0:TMR1L 0x000E Holding register for the Least Significant Byte of the 16-bit TMR1 register BANK0:TMR1H 0x000F Holding register for the Most Significant Byte of the 16-bit TMR1 register BANK0:T1CON 0x0010 TIMER1 CONTROL REGISTER BANK0:T1CON.T1CKPS1 5 Timer1 Input Clock Prescale Select bit 1 BANK0:T1CON.T1CKPS0 4 Timer1 Input Clock Prescale Select bit 0 BANK0:T1CON.T1OSCEN 3 Timer1 Oscillator Enable Control bit BANK0:T1CON.T1SYNC 2 Timer1 External Clock Input Synchronization Control bit BANK0:T1CON.TMR1CS 1 Timer1 Clock Source Select bit BANK0:T1CON.TMR1ON 0 Timer1 On bit BANK0:TMR2 0x0011 Timer2 module's register BANK0:T2CON 0x0012 TIMER2 CONTROL REGISTER BANK0:T2CON.TOUTPS3 6 Timer2 Output Postscale Select bit 3 BANK0:T2CON.TOUTPS2 5 Timer2 Output Postscale Select bit 2 BANK0:T2CON.TOUTPS1 4 Timer2 Output Postscale Select bit 1 BANK0:T2CON.TOUTPS0 3 Timer2 Output Postscale Select bit 0 BANK0:T2CON.TMR2ON 2 Timer2 On bit BANK0:T2CON.T2CKPS1 1 Timer2 Clock Prescale Select bit 1 BANK0:T2CON.T2CKPS0 0 Timer2 Clock Prescale Select bit 0 BANK0:SSPBUF 0x0013 Synchronous Serial Port Receive Buffer/Transmit Register BANK0:SSPCON 0x0014 SYNC SERIAL PORT CONTROL REGISTER BANK0:SSPCON.WCOL 7 Write Collision Detect bit BANK0:SSPCON.SSPOV 6 Receive Overflow Indicator bit BANK0:SSPCON.SSPEN 5 Synchronous Serial Port Enable bit BANK0:SSPCON.CKP 4 Clock Polarity Select bit BANK0:SSPCON.SSPM3 3 Synchronous Serial Port Mode Select bit 3 BANK0:SSPCON.SSPM2 2 Synchronous Serial Port Mode Select bit 2 BANK0:SSPCON.SSPM1 1 Synchronous Serial Port Mode Select bit 1 BANK0:SSPCON.SSPM0 0 Synchronous Serial Port Mode Select bit 0 BANK0:CCPR1L 0x0015 Capture/Compare/PWM1 (LSB) BANK0:CCPR1H 0x0016 Capture/Compare/PWM1 (MSB) BANK0:CCP1CON 0x0017 CCP1CON REGISTER BANK0:CCP1CON.CCP1X 5 PWM Least Significant bit BANK0:CCP1CON.CCP1Y 4 PWM Least Significant bit BANK0:CCP1CON.CCP1M3 3 CCP1 Mode Select bit 3 BANK0:CCP1CON.CCP1M2 2 CCP1 Mode Select bit 2 BANK0:CCP1CON.CCP1M1 1 CCP1 Mode Select bit 1 BANK0:CCP1CON.CCP1M0 0 CCP1 Mode Select bit 0 BANK0:RCSTA 0x0018 RECEIVE STATUS AND CONTROL REGISTER BANK0:RCSTA.SPEN 7 Serial Port Enable bit BANK0:RCSTA.RX9 6 9-bit Receive Enable bit BANK0:RCSTA.SREN 5 Single Receive Enable bit BANK0:RCSTA.CREN 4 Continuous Receive Enable bit BANK0:RCSTA.FERR 2 Framing Error bit BANK0:RCSTA.OERR 1 Overrun Error bit BANK0:RCSTA.RX9D 0 9th bit of received data BANK0:TXREG 0x0019 USART Transmit Data Register BANK0:RCREG 0x001A USART Receive Data Register BANK0:CCPR2L 0x001B Capture/Compare/PWM2 (LSB) BANK0:CCPR2H 0x001C Capture/Compare/PWM2 (MSB) BANK0:CCP2CON 0x001D CCP2CON REGISTER BANK0:CCP2CON.CCP2X 5 PWM Least Significant bit BANK0:CCP2CON.CCP2Y 4 PWM Least Significant bit BANK0:CCP2CON.CCP2M3 3 CCP2 Mode Select bit 3 BANK0:CCP2CON.CCP2M2 2 CCP2 Mode Select bit 2 BANK0:CCP2CON.CCP2M1 1 CCP2 Mode Select bit 1 BANK0:CCP2CON.CCP2M0 0 CCP2 Mode Select bit 0 BANK0:RESERVED001E 0x001E RESERVED BANK0:RESERVED001F 0x001F RESERVED ; BANK1 (0x0080:0x0100) BANK1:INDF 0x0080 INDF (not a physical register) BANK1:OPTION 0x0081 OPTION REGISTER BANK1:OPTION.RBPU 7 PORTB Pull-up Enable bit BANK1:OPTION.INTEDG 6 Interrupt Edge Select bit BANK1:OPTION.T0CS 5 TMR0 Clock Source Select bit BANK1:OPTION.T0SE 4 TMR0 Source Edge Select bit BANK1:OPTION.PSA 3 Prescaler Assignment bit BANK1:OPTION.PS2 2 Prescaler Rate Select bit 2 BANK1:OPTION.PS1 1 Prescaler Rate Select bit 1 BANK1:OPTION.PS0 0 Prescaler Rate Select bit 0 BANK1:PCL 0x0082 Program Counter's (PC) Least Significant Byte BANK1:STATUS 0x0083 STATUS REGISTER BANK1:STATUS.RP0 5 Register Bank Select bit 0 BANK1:STATUS.TO 4 Time-out bit BANK1:STATUS.PD 3 Power-down bit BANK1:STATUS.Z 2 Zero bit BANK1:STATUS.DC 1 Digit carry/borrow bit BANK1:STATUS.C 0 Carry/borrow bit BANK1:FSR 0x0084 Indirect data memory address pointer BANK1:TRISA 0x0085 PORTA Data Direction Register BANK1:TRISA.TRISA5 5 PORTA Data Direction Register bit 5 BANK1:TRISA.TRISA4 4 PORTA Data Direction Register bit 4 BANK1:TRISA.TRISA3 3 PORTA Data Direction Register bit 3 BANK1:TRISA.TRISA2 2 PORTA Data Direction Register bit 2 BANK1:TRISA.TRISA1 1 PORTA Data Direction Register bit 1 BANK1:TRISA.TRISA0 0 PORTA Data Direction Register bit 0 BANK1:TRISB 0x0086 PORTB Data Direction Register BANK1:TRISB.TRISB7 7 PORTB Data Direction Register bit 7 BANK1:TRISB.TRISB6 6 PORTB Data Direction Register bit 6 BANK1:TRISB.TRISB5 5 PORTB Data Direction Register bit 5 BANK1:TRISB.TRISB4 4 PORTB Data Direction Register bit 4 BANK1:TRISB.TRISB3 3 PORTB Data Direction Register bit 3 BANK1:TRISB.TRISB2 2 PORTB Data Direction Register bit 2 BANK1:TRISB.TRISB1 1 PORTB Data Direction Register bit 1 BANK1:TRISB.TRISB0 0 PORTB Data Direction Register bit 0 BANK1:TRISC 0x0087 PORTC Data Direction Register BANK1:TRISC.TRISC7 7 PORTC Data Direction Register bit 7 BANK1:TRISC.TRISC6 6 PORTC Data Direction Register bit 6 BANK1:TRISC.TRISC5 5 PORTC Data Direction Register bit 5 BANK1:TRISC.TRISC4 4 PORTC Data Direction Register bit 4 BANK1:TRISC.TRISC3 3 PORTC Data Direction Register bit 3 BANK1:TRISC.TRISC2 2 PORTC Data Direction Register bit 2 BANK1:TRISC.TRISC1 1 PORTC Data Direction Register bit 1 BANK1:TRISC.TRISC0 0 PORTC Data Direction Register bit 0 BANK1:TRISD 0x0088 PORTD Data Direction Register BANK1:TRISD.TRISD7 7 PORTD Data Direction Register bit 7 BANK1:TRISD.TRISD6 6 PORTD Data Direction Register bit 6 BANK1:TRISD.TRISD5 5 PORTD Data Direction Register bit 5 BANK1:TRISD.TRISD4 4 PORTD Data Direction Register bit 4 BANK1:TRISD.TRISD3 3 PORTD Data Direction Register bit 3 BANK1:TRISD.TRISD2 2 PORTD Data Direction Register bit 2 BANK1:TRISD.TRISD1 1 PORTD Data Direction Register bit 1 BANK1:TRISD.TRISD0 0 PORTD Data Direction Register bit 0 BANK1:TRISE 0x0089 PORTE Data Direction Bits BANK1:TRISE.IBF 7 Input Buffer Full Status bit BANK1:TRISE.OBF 6 Output Buffer Full Status bit BANK1:TRISE.IBOV 5 Input Buffer Overflow Detect bit BANK1:TRISE.PSPMODE 4 Parallel Slave Port Mode Select bit BANK1:TRISE.TRISE2 2 Direction Control bit for pin RE2/CS BANK1:TRISE.TRISE1 1 Direction Control bit for pin RE1/WR BANK1:TRISE.TRISE0 0 Direction Control bit for pin RE0/RD BANK1:PCLATH 0x008A Write Buffer for the upper 5 bits of the Program Counter BANK1:INTCON 0x008B INTCON REGISTER BANK1:INTCON.GIE 7 Global Interrupt Enable bit BANK1:INTCON.PEIE 6 Peripheral Interrupt Enable bit BANK1:INTCON.T0IE 5 TMR0 Overflow Interrupt Enable bit BANK1:INTCON.INTE 4 RB0/INT External Interrupt Enable bit BANK1:INTCON.RBIE 3 RB Port Change Interrupt Enable bit BANK1:INTCON.T0IF 2 TMR0 Overflow Interrupt Flag bit BANK1:INTCON.INTF 1 RB0/INT External Interrupt Flag bit BANK1:INTCON.RBIF 0 RB Port Change Interrupt Flag bit BANK1:PIE1 0x008C PIE1 REGISTER BANK1:PIE1.PSPIE 7 Parallel Slave Port Read/Write Interrupt Enable bit BANK1:PIE1.RCIE 5 USART Receive Interrupt Enable bit BANK1:PIE1.TXIE 4 USART Transmit Interrupt Enable bit BANK1:PIE1.SSPIE 3 Synchronous Serial Port Interrupt Enable bit BANK1:PIE1.CCP1IE 2 CCP1 Interrupt Enable bit BANK1:PIE1.TMR2IE 1 TMR2 to PR2 Match Interrupt Enable bit BANK1:PIE1.TMR1IE 0 TMR1 Overflow Interrupt Enable bit BANK1:PIE2 0x008D PIE2 REGISTER BANK1:PIE2.CCP2IE 0 CCP2 Interrupt Enable bit BANK1:PCON 0x008E PCON REGISTER BANK1:PCON.POR 1 Power-on Reset Status bit BANK1:RESERVED008F 0x008F RESERVED BANK1:RESERVED0090 0x0090 RESERVED BANK1:RESERVED0091 0x0091 RESERVED BANK1:PR2 0x0092 Timer2 Period Register BANK1:SSPADD 0x0093 Synchronous Serial Port (I2C mode) Address Register BANK1:SSPSTAT 0x0094 SYNC SERIAL PORT STATUS REGISTER BANK1:SSPSTAT.D_A 5 Data/Address bit (I2C mode only) BANK1:SSPSTAT.P 4 Stop bit (I2C mode only) BANK1:SSPSTAT.S 3 Start bit (I2C mode only) BANK1:SSPSTAT.R_W 2 Read/Write bit information (I2C mode only) BANK1:SSPSTAT.UA 1 Update Address (I2C mode only) BANK1:SSPSTAT.BF 0 Buffer Full Status bit BANK1:RESERVED0095 0x0095 RESERVED BANK1:RESERVED0096 0x0096 RESERVED BANK1:RESERVED0097 0x0097 RESERVED BANK1:TXSTA 0x0098 TRANSMIT STATUS AND CONTROL REGISTER BANK1:TXSTA.CSRC 7 Clock Source Select bit BANK1:TXSTA.TX9 6 9-bit Transmit Enable bit BANK1:TXSTA.TXEN 5 Transmit Enable bit BANK1:TXSTA.SYNC 4 USART Mode Select bit BANK1:TXSTA.BRGH 2 High Baud Rate Select bit BANK1:TXSTA.TRMT 1 Transmit Shift Register Status bit BANK1:TXSTA.TX9D 0 9th bit of transmit data BANK1:SPBRG 0x0099 Baud Rate Generator Register BANK1:RESERVED009A 0x009A RESERVED BANK1:RESERVED009B 0x009B RESERVED BANK1:RESERVED009C 0x009C RESERVED BANK1:RESERVED009D 0x009D RESERVED BANK1:RESERVED009E 0x009E RESERVED BANK1:RESERVED009F 0x009F RESERVED .16C65A ; http://www.microchip.com/download/lit/pline/picmicro/families/16c6x/30234d.pdf ; PIC16C6x.pdf ; MEMORY MAP ; BANK_0 area DATA FSR_ 0x0000:0x0020 area DATA Gen_Purp 0x0020:0x0080 General Purpose Register area DATA MEM_Program0 0x0080:0x0800 On-chip Program Memory (Page 0) area DATA MEM_Program1 0x0800:0x1000 On-chip Program Memory (Page 1) ; BANK_1 area DATA FSR_ 0x0080:0x00A0 area DATA Gen_Purp 0x00A0:0x0100 General Purpose Register area DATA MEM_Program0 0x0100:0x0800 On-chip Program Memory (Page 0) area DATA MEM_Program1 0x0800:0x1000 On-chip Program Memory (Page 1) ; Interrupt and reset vector assignments interrupt RESET 0x0000 RESET ; INPUT/OUTPUT PORTS ; BANK0 (0x0000:0x0080) BANK0:INDF 0x0000 INDF (not a physical register) BANK0:TMR0 0x0001 Timer0 module's register BANK0:PCL 0x0002 Program Counter's (PC) Least Significant Byte BANK0:STATUS 0x0003 STATUS REGISTER BANK0:STATUS.RP0 5 Register Bank Select bit 0 BANK0:STATUS.TO 4 Time-out bit BANK0:STATUS.PD 3 Power-down bit BANK0:STATUS.Z 2 Zero bit BANK0:STATUS.DC 1 Digit carry/borrow bit BANK0:STATUS.C 0 Carry/borrow bit BANK0:FSR 0x0004 Indirect data memory address pointer BANK0:PORTA 0x0005 PORTA register BANK0:PORTA.RA5 5 PORTA bit 5 BANK0:PORTA.RA4 4 PORTA bit 4 BANK0:PORTA.RA3 3 PORTA bit 3 BANK0:PORTA.RA2 2 PORTA bit 2 BANK0:PORTA.RA1 1 PORTA bit 1 BANK0:PORTA.RA0 0 PORTA bit 0 BANK0:PORTB 0x0006 PORTB register BANK0:PORTB.RB7 7 PORTB bit 7 BANK0:PORTB.RB6 6 PORTB bit 6 BANK0:PORTB.RB5 5 PORTB bit 5 BANK0:PORTB.RB4 4 PORTB bit 4 BANK0:PORTB.RB3 3 PORTB bit 3 BANK0:PORTB.RB2 2 PORTB bit 2 BANK0:PORTB.RB1 1 PORTB bit 1 BANK0:PORTB.RB0 0 PORTB bit 0 BANK0:PORTC 0x0007 PORTC register BANK0:PORTC.RC7 7 PORTC bit 7 BANK0:PORTC.RC6 6 PORTC bit 6 BANK0:PORTC.RC5 5 PORTC bit 5 BANK0:PORTC.RC4 4 PORTC bit 4 BANK0:PORTC.RC3 3 PORTC bit 3 BANK0:PORTC.RC2 2 PORTC bit 2 BANK0:PORTC.RC1 1 PORTC bit 1 BANK0:PORTC.RC0 0 PORTC bit 0 BANK0:PORTD 0x0008 PORTD register BANK0:PORTD.RD7 7 PORTD bit 7 BANK0:PORTD.RD6 6 PORTD bit 6 BANK0:PORTD.RD5 5 PORTD bit 5 BANK0:PORTD.RD4 4 PORTD bit 4 BANK0:PORTD.RD3 3 PORTD bit 3 BANK0:PORTD.RD2 2 PORTD bit 2 BANK0:PORTD.RD1 1 PORTD bit 1 BANK0:PORTD.RD0 0 PORTD bit 0 BANK0:PORTE 0x0009 PORTE register BANK0:PORTE.RE2 2 PORTE bit 2 BANK0:PORTE.RE1 1 PORTE bit 1 BANK0:PORTE.RE0 0 PORTE bit 0 BANK0:PCLATH 0x000A Write Buffer for the upper 5 bits of the Program Counter BANK0:INTCON 0x000B INTCON REGISTER BANK0:INTCON.GIE 7 Global Interrupt Enable bit BANK0:INTCON.PEIE 6 Peripheral Interrupt Enable bit BANK0:INTCON.T0IE 5 TMR0 Overflow Interrupt Enable bit BANK0:INTCON.INTE 4 RB0/INT External Interrupt Enable bit BANK0:INTCON.RBIE 3 RB Port Change Interrupt Enable bit BANK0:INTCON.T0IF 2 TMR0 Overflow Interrupt Flag bit BANK0:INTCON.INTF 1 RB0/INT External Interrupt Flag bit BANK0:INTCON.RBIF 0 RB Port Change Interrupt Flag bit BANK0:PIR1 0x000C PIR1 REGISTER BANK0:PIR1.PSPIF 7 Parallel Slave Port Interrupt Flag bit BANK0:PIR1.RCIF 5 USART Receive Interrupt Flag bit BANK0:PIR1.TXIF 4 USART Transmit Interrupt Flag bit BANK0:PIR1.SSPIF 3 Synchronous Serial Port Interrupt Flag bit BANK0:PIR1.CCP1IF 2 CCP1 Interrupt Flag bit BANK0:PIR1.TMR2IF 1 TMR2 to PR2 Match Interrupt Flag bit BANK0:PIR1.TMR1IF 0 TMR1 Overflow Interrupt Flag bit BANK0:PIR2 0x000D PIR2 REGISTER BANK0:PIR2.CCP2IF 0 CCP2 Interrupt Flag bit BANK0:TMR1L 0x000E Holding register for the Least Significant Byte of the 16-bit TMR1 register BANK0:TMR1H 0x000F Holding register for the Most Significant Byte of the 16-bit TMR1 register BANK0:T1CON 0x0010 TIMER1 CONTROL REGISTER BANK0:T1CON.T1CKPS1 5 Timer1 Input Clock Prescale Select bit 1 BANK0:T1CON.T1CKPS0 4 Timer1 Input Clock Prescale Select bit 0 BANK0:T1CON.T1OSCEN 3 Timer1 Oscillator Enable Control bit BANK0:T1CON.T1SYNC 2 Timer1 External Clock Input Synchronization Control bit BANK0:T1CON.TMR1CS 1 Timer1 Clock Source Select bit BANK0:T1CON.TMR1ON 0 Timer1 On bit BANK0:TMR2 0x0011 Timer2 module's register BANK0:T2CON 0x0012 TIMER2 CONTROL REGISTER BANK0:T2CON.TOUTPS3 6 Timer2 Output Postscale Select bit 3 BANK0:T2CON.TOUTPS2 5 Timer2 Output Postscale Select bit 2 BANK0:T2CON.TOUTPS1 4 Timer2 Output Postscale Select bit 1 BANK0:T2CON.TOUTPS0 3 Timer2 Output Postscale Select bit 0 BANK0:T2CON.TMR2ON 2 Timer2 On bit BANK0:T2CON.T2CKPS1 1 Timer2 Clock Prescale Select bit 1 BANK0:T2CON.T2CKPS0 0 Timer2 Clock Prescale Select bit 0 BANK0:SSPBUF 0x0013 Synchronous Serial Port Receive Buffer/Transmit Register BANK0:SSPCON 0x0014 SYNC SERIAL PORT CONTROL REGISTER BANK0:SSPCON.WCOL 7 Write Collision Detect bit BANK0:SSPCON.SSPOV 6 Receive Overflow Indicator bit BANK0:SSPCON.SSPEN 5 Synchronous Serial Port Enable bit BANK0:SSPCON.CKP 4 Clock Polarity Select bit BANK0:SSPCON.SSPM3 3 Synchronous Serial Port Mode Select bit 3 BANK0:SSPCON.SSPM2 2 Synchronous Serial Port Mode Select bit 2 BANK0:SSPCON.SSPM1 1 Synchronous Serial Port Mode Select bit 1 BANK0:SSPCON.SSPM0 0 Synchronous Serial Port Mode Select bit 0 BANK0:CCPR1L 0x0015 Capture/Compare/PWM1 (LSB) BANK0:CCPR1H 0x0016 Capture/Compare/PWM1 (MSB) BANK0:CCP1CON 0x0017 CCP1CON REGISTER BANK0:CCP1CON.CCP1X 5 PWM Least Significant bit BANK0:CCP1CON.CCP1Y 4 PWM Least Significant bit BANK0:CCP1CON.CCP1M3 3 CCP1 Mode Select bit 3 BANK0:CCP1CON.CCP1M2 2 CCP1 Mode Select bit 2 BANK0:CCP1CON.CCP1M1 1 CCP1 Mode Select bit 1 BANK0:CCP1CON.CCP1M0 0 CCP1 Mode Select bit 0 BANK0:RCSTA 0x0018 RECEIVE STATUS AND CONTROL REGISTER BANK0:RCSTA.SPEN 7 Serial Port Enable bit BANK0:RCSTA.RX9 6 9-bit Receive Enable bit BANK0:RCSTA.SREN 5 Single Receive Enable bit BANK0:RCSTA.CREN 4 Continuous Receive Enable bit BANK0:RCSTA.FERR 2 Framing Error bit BANK0:RCSTA.OERR 1 Overrun Error bit BANK0:RCSTA.RX9D 0 9th bit of received data BANK0:TXREG 0x0019 USART Transmit Data Register BANK0:RCREG 0x001A USART Receive Data Register BANK0:CCPR2L 0x001B Capture/Compare/PWM2 (LSB) BANK0:CCPR2H 0x001C Capture/Compare/PWM2 (MSB) BANK0:CCP2CON 0x001D CCP2CON REGISTER BANK0:CCP2CON.CCP2X 5 PWM Least Significant bit BANK0:CCP2CON.CCP2Y 4 PWM Least Significant bit BANK0:CCP2CON.CCP2M3 3 CCP2 Mode Select bit 3 BANK0:CCP2CON.CCP2M2 2 CCP2 Mode Select bit 2 BANK0:CCP2CON.CCP2M1 1 CCP2 Mode Select bit 1 BANK0:CCP2CON.CCP2M0 0 CCP2 Mode Select bit 0 BANK0:RESERVED001E 0x001E RESERVED BANK0:RESERVED001F 0x001F RESERVED ; BANK1 (0x0080:0x0100) BANK1:INDF 0x0080 INDF (not a physical register) BANK1:OPTION 0x0081 OPTION REGISTER BANK1:OPTION.RBPU 7 PORTB Pull-up Enable bit BANK1:OPTION.INTEDG 6 Interrupt Edge Select bit BANK1:OPTION.T0CS 5 TMR0 Clock Source Select bit BANK1:OPTION.T0SE 4 TMR0 Source Edge Select bit BANK1:OPTION.PSA 3 Prescaler Assignment bit BANK1:OPTION.PS2 2 Prescaler Rate Select bit 2 BANK1:OPTION.PS1 1 Prescaler Rate Select bit 1 BANK1:OPTION.PS0 0 Prescaler Rate Select bit 0 BANK1:PCL 0x0082 Program Counter's (PC) Least Significant Byte BANK1:STATUS 0x0083 STATUS REGISTER BANK1:STATUS.RP0 5 Register Bank Select bit 0 BANK1:STATUS.TO 4 Time-out bit BANK1:STATUS.PD 3 Power-down bit BANK1:STATUS.Z 2 Zero bit BANK1:STATUS.DC 1 Digit carry/borrow bit BANK1:STATUS.C 0 Carry/borrow bit BANK1:FSR 0x0084 Indirect data memory address pointer BANK1:TRISA 0x0085 PORTA Data Direction Register BANK1:TRISA.TRISA5 5 PORTA Data Direction Register bit 5 BANK1:TRISA.TRISA4 4 PORTA Data Direction Register bit 4 BANK1:TRISA.TRISA3 3 PORTA Data Direction Register bit 3 BANK1:TRISA.TRISA2 2 PORTA Data Direction Register bit 2 BANK1:TRISA.TRISA1 1 PORTA Data Direction Register bit 1 BANK1:TRISA.TRISA0 0 PORTA Data Direction Register bit 0 BANK1:TRISB 0x0086 PORTB Data Direction Register BANK1:TRISB.TRISB7 7 PORTB Data Direction Register bit 7 BANK1:TRISB.TRISB6 6 PORTB Data Direction Register bit 6 BANK1:TRISB.TRISB5 5 PORTB Data Direction Register bit 5 BANK1:TRISB.TRISB4 4 PORTB Data Direction Register bit 4 BANK1:TRISB.TRISB3 3 PORTB Data Direction Register bit 3 BANK1:TRISB.TRISB2 2 PORTB Data Direction Register bit 2 BANK1:TRISB.TRISB1 1 PORTB Data Direction Register bit 1 BANK1:TRISB.TRISB0 0 PORTB Data Direction Register bit 0 BANK1:TRISC 0x0087 PORTC Data Direction Register BANK1:TRISC.TRISC7 7 PORTC Data Direction Register bit 7 BANK1:TRISC.TRISC6 6 PORTC Data Direction Register bit 6 BANK1:TRISC.TRISC5 5 PORTC Data Direction Register bit 5 BANK1:TRISC.TRISC4 4 PORTC Data Direction Register bit 4 BANK1:TRISC.TRISC3 3 PORTC Data Direction Register bit 3 BANK1:TRISC.TRISC2 2 PORTC Data Direction Register bit 2 BANK1:TRISC.TRISC1 1 PORTC Data Direction Register bit 1 BANK1:TRISC.TRISC0 0 PORTC Data Direction Register bit 0 BANK1:TRISD 0x0088 PORTD Data Direction Register BANK1:TRISD.TRISD7 7 PORTD Data Direction Register bit 7 BANK1:TRISD.TRISD6 6 PORTD Data Direction Register bit 6 BANK1:TRISD.TRISD5 5 PORTD Data Direction Register bit 5 BANK1:TRISD.TRISD4 4 PORTD Data Direction Register bit 4 BANK1:TRISD.TRISD3 3 PORTD Data Direction Register bit 3 BANK1:TRISD.TRISD2 2 PORTD Data Direction Register bit 2 BANK1:TRISD.TRISD1 1 PORTD Data Direction Register bit 1 BANK1:TRISD.TRISD0 0 PORTD Data Direction Register bit 0 BANK1:TRISE 0x0089 PORTE Data Direction Bits BANK1:TRISE.IBF 7 Input Buffer Full Status bit BANK1:TRISE.OBF 6 Output Buffer Full Status bit BANK1:TRISE.IBOV 5 Input Buffer Overflow Detect bit BANK1:TRISE.PSPMODE 4 Parallel Slave Port Mode Select bit BANK1:TRISE.TRISE2 2 Direction Control bit for pin RE2/CS BANK1:TRISE.TRISE1 1 Direction Control bit for pin RE1/WR BANK1:TRISE.TRISE0 0 Direction Control bit for pin RE0/RD BANK1:PCLATH 0x008A Write Buffer for the upper 5 bits of the Program Counter BANK1:INTCON 0x008B INTCON REGISTER BANK1:INTCON.GIE 7 Global Interrupt Enable bit BANK1:INTCON.PEIE 6 Peripheral Interrupt Enable bit BANK1:INTCON.T0IE 5 TMR0 Overflow Interrupt Enable bit BANK1:INTCON.INTE 4 RB0/INT External Interrupt Enable bit BANK1:INTCON.RBIE 3 RB Port Change Interrupt Enable bit BANK1:INTCON.T0IF 2 TMR0 Overflow Interrupt Flag bit BANK1:INTCON.INTF 1 RB0/INT External Interrupt Flag bit BANK1:INTCON.RBIF 0 RB Port Change Interrupt Flag bit BANK1:PIE1 0x008C PIE1 REGISTER BANK1:PIE1.PSPIE 7 Parallel Slave Port Read/Write Interrupt Enable bit BANK1:PIE1.RCIE 5 USART Receive Interrupt Enable bit BANK1:PIE1.TXIE 4 USART Transmit Interrupt Enable bit BANK1:PIE1.SSPIE 3 Synchronous Serial Port Interrupt Enable bit BANK1:PIE1.CCP1IE 2 CCP1 Interrupt Enable bit BANK1:PIE1.TMR2IE 1 TMR2 to PR2 Match Interrupt Enable bit BANK1:PIE1.TMR1IE 0 TMR1 Overflow Interrupt Enable bit BANK1:PIE2 0x008D PIE2 REGISTER BANK1:PIE2.CCP2IE 0 CCP2 Interrupt Enable bit BANK1:PCON 0x008E PCON REGISTER BANK1:PCON.POR 1 Power-on Reset Status bit BANK1:PCON.BOR 0 Brown-out Reset Status bit BANK1:RESERVED008F 0x008F RESERVED BANK1:RESERVED0090 0x0090 RESERVED BANK1:RESERVED0091 0x0091 RESERVED BANK1:PR2 0x0092 Timer2 Period Register BANK1:SSPADD 0x0093 Synchronous Serial Port (I2C mode) Address Register BANK1:SSPSTAT 0x0094 SYNC SERIAL PORT STATUS REGISTER BANK1:SSPSTAT.D_A 5 Data/Address bit (I2C mode only) BANK1:SSPSTAT.P 4 Stop bit (I2C mode only) BANK1:SSPSTAT.S 3 Start bit (I2C mode only) BANK1:SSPSTAT.R_W 2 Read/Write bit information (I2C mode only) BANK1:SSPSTAT.UA 1 Update Address (I2C mode only) BANK1:SSPSTAT.BF 0 Buffer Full Status bit BANK1:RESERVED0095 0x0095 RESERVED BANK1:RESERVED0096 0x0096 RESERVED BANK1:RESERVED0097 0x0097 RESERVED BANK1:TXSTA 0x0098 TRANSMIT STATUS AND CONTROL REGISTER BANK1:TXSTA.CSRC 7 Clock Source Select bit BANK1:TXSTA.TX9 6 9-bit Transmit Enable bit BANK1:TXSTA.TXEN 5 Transmit Enable bit BANK1:TXSTA.SYNC 4 USART Mode Select bit BANK1:TXSTA.BRGH 2 High Baud Rate Select bit BANK1:TXSTA.TRMT 1 Transmit Shift Register Status bit BANK1:TXSTA.TX9D 0 9th bit of transmit data BANK1:SPBRG 0x0099 Baud Rate Generator Register BANK1:RESERVED009A 0x009A RESERVED BANK1:RESERVED009B 0x009B RESERVED BANK1:RESERVED009C 0x009C RESERVED BANK1:RESERVED009D 0x009D RESERVED BANK1:RESERVED009E 0x009E RESERVED BANK1:RESERVED009F 0x009F RESERVED .16C66 ; http://www.microchip.com/download/lit/pline/picmicro/families/16c6x/30234d.pdf ; PIC16C6x.pdf ; MEMORY MAP ; BANK_0 area DATA FSR_ 0x0000:0x0020 area DATA Gen_Purp 0x0020:0x0080 General Purpose Register area DATA MEM_Program0 0x0080:0x0800 On-chip Program Memory (Page 0) area DATA MEM_Program1 0x0800:0x1000 On-chip Program Memory (Page 1) area DATA MEM_Program2 0x1000:0x1800 On-chip Program Memory (Page 2) area DATA MEM_Program3 0x1800:0x2000 On-chip Program Memory (Page 3) ; BANK_1 ; area DATA FSR_ 0x0080:0x00A0 ; area DATA Gen_Purp 0x00A0:0x00F0 General Purpose Register ; area DATA Gen_Purp_BANK0 0x00F0:0x0100 accesses 70h-7Fh in Bank 0 ; area DATA MEM_Program0 0x0100:0x0800 On-chip Program Memory (Page 0) ; area DATA MEM_Program1 0x0800:0x1000 On-chip Program Memory (Page 1) ; area DATA MEM_Program2 0x1000:0x1800 On-chip Program Memory (Page 2) ; area DATA MEM_Program3 0x1800:0x2000 On-chip Program Memory (Page 3) ; BANK_2 ; area DATA FSR_ 0x0100:0x0110 ; area DATA Gen_Purp0 0x0110:0x0120 General Purpose Register 16 Bytes ; area DATA Gen_Purp1 0x0120:0x0170 General Purpose Register 80 Bytes ; area DATA Gen_Purp_BANK0 0x0170:0x0180 accesses 70h-7Fh in Bank 0 ; area DATA MEM_Program0 0x0180:0x0800 On-chip Program Memory (Page 0) ; area DATA MEM_Program1 0x0800:0x1000 On-chip Program Memory (Page 1) ; area DATA MEM_Program2 0x1000:0x1800 On-chip Program Memory (Page 2) ; area DATA MEM_Program3 0x1800:0x2000 On-chip Program Memory (Page 3) ; BANK_3 ; area DATA FSR_ 0x0180:0x0190 ; area DATA Gen_Purp0 0x0190:0x01A0 General Purpose Register 16 Bytes ; area DATA Gen_Purp1 0x01A0:0x01F0 General Purpose Register 80 Bytes ; area DATA Gen_Purp_BANK0 0x01F0:0x0200 accesses 70h-7Fh in Bank 0 ; area DATA MEM_Program0 0x0200:0x0800 On-chip Program Memory (Page 0) ; area DATA MEM_Program1 0x0800:0x1000 On-chip Program Memory (Page 1) ; area DATA MEM_Program2 0x1000:0x1800 On-chip Program Memory (Page 2) ; area DATA MEM_Program3 0x1800:0x2000 On-chip Program Memory (Page 3) ; Interrupt and reset vector assignments interrupt RESET 0x0000 RESET ; INPUT/OUTPUT PORTS ; BANK0 (0x0000:0x0080) BANK0:INDF 0x0000 INDF (not a physical register) BANK0:TMR0 0x0001 Timer0 module's register BANK0:PCL 0x0002 Program Counter's (PC) Least Significant Byte BANK0:STATUS 0x0003 STATUS REGISTER BANK0:STATUS.IRP 7 RegIster Bank Select bit BANK0:STATUS.RP1 6 Register Bank Select bit 1 BANK0:STATUS.RP0 5 Register Bank Select bit 0 BANK0:STATUS.TO 4 Time-out bit BANK0:STATUS.PD 3 Power-down bit BANK0:STATUS.Z 2 Zero bit BANK0:STATUS.DC 1 Digit carry/borrow bit BANK0:STATUS.C 0 Carry/borrow bit BANK0:FSR 0x0004 Indirect data memory address pointer BANK0:PORTA 0x0005 PORTA register BANK0:PORTA.RA5 5 PORTA bit 5 BANK0:PORTA.RA4 4 PORTA bit 4 BANK0:PORTA.RA3 3 PORTA bit 3 BANK0:PORTA.RA2 2 PORTA bit 2 BANK0:PORTA.RA1 1 PORTA bit 1 BANK0:PORTA.RA0 0 PORTA bit 0 BANK0:PORTB 0x0006 PORTB register BANK0:PORTB.RB7 7 PORTB bit 7 BANK0:PORTB.RB6 6 PORTB bit 6 BANK0:PORTB.RB5 5 PORTB bit 5 BANK0:PORTB.RB4 4 PORTB bit 4 BANK0:PORTB.RB3 3 PORTB bit 3 BANK0:PORTB.RB2 2 PORTB bit 2 BANK0:PORTB.RB1 1 PORTB bit 1 BANK0:PORTB.RB0 0 PORTB bit 0 BANK0:PORTC 0x0007 PORTC register BANK0:PORTC.RC7 7 PORTC bit 7 BANK0:PORTC.RC6 6 PORTC bit 6 BANK0:PORTC.RC5 5 PORTC bit 5 BANK0:PORTC.RC4 4 PORTC bit 4 BANK0:PORTC.RC3 3 PORTC bit 3 BANK0:PORTC.RC2 2 PORTC bit 2 BANK0:PORTC.RC1 1 PORTC bit 1 BANK0:PORTC.RC0 0 PORTC bit 0 BANK0:RESERVED0008 0x0008 RESERVED BANK0:RESERVED0009 0x0009 RESERVED BANK0:PCLATH 0x000A Write Buffer for the upper 5 bits of the Program Counter BANK0:INTCON 0x000B INTCON REGISTER BANK0:INTCON.GIE 7 Global Interrupt Enable bit BANK0:INTCON.PEIE 6 Peripheral Interrupt Enable bit BANK0:INTCON.T0IE 5 TMR0 Overflow Interrupt Enable bit BANK0:INTCON.INTE 4 RB0/INT External Interrupt Enable bit BANK0:INTCON.RBIE 3 RB Port Change Interrupt Enable bit BANK0:INTCON.T0IF 2 TMR0 Overflow Interrupt Flag bit BANK0:INTCON.INTF 1 RB0/INT External Interrupt Flag bit BANK0:INTCON.RBIF 0 RB Port Change Interrupt Flag bit BANK0:PIR1 0x000C PIR1 REGISTER BANK0:PIR1.RCIF 5 USART Receive Interrupt Flag bit BANK0:PIR1.TXIF 4 USART Transmit Interrupt Flag bit BANK0:PIR1.SSPIF 3 Synchronous Serial Port Interrupt Flag bit BANK0:PIR1.CCP1IF 2 CCP1 Interrupt Flag bit BANK0:PIR1.TMR2IF 1 TMR2 to PR2 Match Interrupt Flag bit BANK0:PIR1.TMR1IF 0 TMR1 Overflow Interrupt Flag bit BANK0:PIR2 0x000D PIR2 REGISTER BANK0:PIR2.CCP2IF 0 CCP2 Interrupt Flag bit BANK0:TMR1L 0x000E Holding register for the Least Significant Byte of the 16-bit TMR1 register BANK0:TMR1H 0x000F Holding register for the Most Significant Byte of the 16-bit TMR1 register BANK0:T1CON 0x0010 TIMER1 CONTROL REGISTER BANK0:T1CON.T1CKPS1 5 Timer1 Input Clock Prescale Select bit 1 BANK0:T1CON.T1CKPS0 4 Timer1 Input Clock Prescale Select bit 0 BANK0:T1CON.T1OSCEN 3 Timer1 Oscillator Enable Control bit BANK0:T1CON.T1SYNC 2 Timer1 External Clock Input Synchronization Control bit BANK0:T1CON.TMR1CS 1 Timer1 Clock Source Select bit BANK0:T1CON.TMR1ON 0 Timer1 On bit BANK0:TMR2 0x0011 Timer2 module's register BANK0:T2CON 0x0012 TIMER2 CONTROL REGISTER BANK0:T2CON.TOUTPS3 6 Timer2 Output Postscale Select bit 3 BANK0:T2CON.TOUTPS2 5 Timer2 Output Postscale Select bit 2 BANK0:T2CON.TOUTPS1 4 Timer2 Output Postscale Select bit 1 BANK0:T2CON.TOUTPS0 3 Timer2 Output Postscale Select bit 0 BANK0:T2CON.TMR2ON 2 Timer2 On bit BANK0:T2CON.T2CKPS1 1 Timer2 Clock Prescale Select bit 1 BANK0:T2CON.T2CKPS0 0 Timer2 Clock Prescale Select bit 0 BANK0:SSPBUF 0x0013 Synchronous Serial Port Receive Buffer/Transmit Register BANK0:SSPCON 0x0014 SYNC SERIAL PORT CONTROL REGISTER BANK0:SSPCON.WCOL 7 Write Collision Detect bit BANK0:SSPCON.SSPOV 6 Receive Overflow Indicator bit BANK0:SSPCON.SSPEN 5 Synchronous Serial Port Enable bit BANK0:SSPCON.CKP 4 Clock Polarity Select bit BANK0:SSPCON.SSPM3 3 Synchronous Serial Port Mode Select bit 3 BANK0:SSPCON.SSPM2 2 Synchronous Serial Port Mode Select bit 2 BANK0:SSPCON.SSPM1 1 Synchronous Serial Port Mode Select bit 1 BANK0:SSPCON.SSPM0 0 Synchronous Serial Port Mode Select bit 0 BANK0:CCPR1L 0x0015 Capture/Compare/PWM1 (LSB) BANK0:CCPR1H 0x0016 Capture/Compare/PWM1 (MSB) BANK0:CCP1CON 0x0017 CCP1CON REGISTER BANK0:CCP1CON.CCP1X 5 PWM Least Significant bit BANK0:CCP1CON.CCP1Y 4 PWM Least Significant bit BANK0:CCP1CON.CCP1M3 3 CCP1 Mode Select bit 3 BANK0:CCP1CON.CCP1M2 2 CCP1 Mode Select bit 2 BANK0:CCP1CON.CCP1M1 1 CCP1 Mode Select bit 1 BANK0:CCP1CON.CCP1M0 0 CCP1 Mode Select bit 0 BANK0:RCSTA 0x0018 RECEIVE STATUS AND CONTROL REGISTER BANK0:RCSTA.SPEN 7 Serial Port Enable bit BANK0:RCSTA.RX9 6 9-bit Receive Enable bit BANK0:RCSTA.SREN 5 Single Receive Enable bit BANK0:RCSTA.CREN 4 Continuous Receive Enable bit BANK0:RCSTA.FERR 2 Framing Error bit BANK0:RCSTA.OERR 1 Overrun Error bit BANK0:RCSTA.RX9D 0 9th bit of received data BANK0:TXREG 0x0019 USART Transmit Data Register BANK0:RCREG 0x001A USART Receive Data Register BANK0:CCPR2L 0x001B Capture/Compare/PWM2 (LSB) BANK0:CCPR2H 0x001C Capture/Compare/PWM2 (MSB) BANK0:CCP2CON 0x001D CCP2CON REGISTER BANK0:CCP2CON.CCP2X 5 PWM Least Significant bit BANK0:CCP2CON.CCP2Y 4 PWM Least Significant bit BANK0:CCP2CON.CCP2M3 3 CCP2 Mode Select bit 3 BANK0:CCP2CON.CCP2M2 2 CCP2 Mode Select bit 2 BANK0:CCP2CON.CCP2M1 1 CCP2 Mode Select bit 1 BANK0:CCP2CON.CCP2M0 0 CCP2 Mode Select bit 0 BANK0:RESERVED001E 0x001E RESERVED BANK0:RESERVED001F 0x001F RESERVED ; BANK1 (0x0080:0x0100) BANK1:INDF 0x0080 INDF (not a physical register) BANK1:OPTION 0x0081 OPTION REGISTER BANK1:OPTION.RBPU 7 PORTB Pull-up Enable bit BANK1:OPTION.INTEDG 6 Interrupt Edge Select bit BANK1:OPTION.T0CS 5 TMR0 Clock Source Select bit BANK1:OPTION.T0SE 4 TMR0 Source Edge Select bit BANK1:OPTION.PSA 3 Prescaler Assignment bit BANK1:OPTION.PS2 2 Prescaler Rate Select bit 2 BANK1:OPTION.PS1 1 Prescaler Rate Select bit 1 BANK1:OPTION.PS0 0 Prescaler Rate Select bit 0 BANK1:PCL 0x0082 Program Counter's (PC) Least Significant Byte BANK1:STATUS 0x0083 STATUS REGISTER BANK1:STATUS.IRP 7 RegIster Bank Select bit BANK1:STATUS.RP1 6 Register Bank Select bit 1 BANK1:STATUS.RP0 5 Register Bank Select bit 0 BANK1:STATUS.TO 4 Time-out bit BANK1:STATUS.PD 3 Power-down bit BANK1:STATUS.Z 2 Zero bit BANK1:STATUS.DC 1 Digit carry/borrow bit BANK1:STATUS.C 0 Carry/borrow bit BANK1:FSR 0x0084 Indirect data memory address pointer BANK1:TRISA 0x0085 PORTA Data Direction Register BANK1:TRISA.TRISA5 5 PORTA Data Direction Register bit 5 BANK1:TRISA.TRISA4 4 PORTA Data Direction Register bit 4 BANK1:TRISA.TRISA3 3 PORTA Data Direction Register bit 3 BANK1:TRISA.TRISA2 2 PORTA Data Direction Register bit 2 BANK1:TRISA.TRISA1 1 PORTA Data Direction Register bit 1 BANK1:TRISA.TRISA0 0 PORTA Data Direction Register bit 0 BANK1:TRISB 0x0086 PORTB Data Direction Register BANK1:TRISB.TRISB7 7 PORTB Data Direction Register bit 7 BANK1:TRISB.TRISB6 6 PORTB Data Direction Register bit 6 BANK1:TRISB.TRISB5 5 PORTB Data Direction Register bit 5 BANK1:TRISB.TRISB4 4 PORTB Data Direction Register bit 4 BANK1:TRISB.TRISB3 3 PORTB Data Direction Register bit 3 BANK1:TRISB.TRISB2 2 PORTB Data Direction Register bit 2 BANK1:TRISB.TRISB1 1 PORTB Data Direction Register bit 1 BANK1:TRISB.TRISB0 0 PORTB Data Direction Register bit 0 BANK1:TRISC 0x0087 PORTC Data Direction Register BANK1:TRISC.TRISC7 7 PORTC Data Direction Register bit 7 BANK1:TRISC.TRISC6 6 PORTC Data Direction Register bit 6 BANK1:TRISC.TRISC5 5 PORTC Data Direction Register bit 5 BANK1:TRISC.TRISC4 4 PORTC Data Direction Register bit 4 BANK1:TRISC.TRISC3 3 PORTC Data Direction Register bit 3 BANK1:TRISC.TRISC2 2 PORTC Data Direction Register bit 2 BANK1:TRISC.TRISC1 1 PORTC Data Direction Register bit 1 BANK1:TRISC.TRISC0 0 PORTC Data Direction Register bit 0 BANK1:RESERVED0088 0x0088 RESERVED BANK1:RESERVED0089 0x0089 RESERVED BANK1:PCLATH 0x008A Write Buffer for the upper 5 bits of the Program Counter BANK1:INTCON 0x008B INTCON REGISTER BANK1:INTCON.GIE 7 Global Interrupt Enable bit BANK1:INTCON.PEIE 6 Peripheral Interrupt Enable bit BANK1:INTCON.T0IE 5 TMR0 Overflow Interrupt Enable bit BANK1:INTCON.INTE 4 RB0/INT External Interrupt Enable bit BANK1:INTCON.RBIE 3 RB Port Change Interrupt Enable bit BANK1:INTCON.T0IF 2 TMR0 Overflow Interrupt Flag bit BANK1:INTCON.INTF 1 RB0/INT External Interrupt Flag bit BANK1:INTCON.RBIF 0 RB Port Change Interrupt Flag bit BANK1:PIE1 0x008C PIE1 REGISTER BANK1:PIE1.RCIE 5 USART Receive Interrupt Enable bit BANK1:PIE1.TXIE 4 USART Transmit Interrupt Enable bit BANK1:PIE1.SSPIE 3 Synchronous Serial Port Interrupt Enable bit BANK1:PIE1.CCP1IE 2 CCP1 Interrupt Enable bit BANK1:PIE1.TMR2IE 1 TMR2 to PR2 Match Interrupt Enable bit BANK1:PIE1.TMR1IE 0 TMR1 Overflow Interrupt Enable bit BANK1:PIE2 0x008D PIE2 REGISTER BANK1:PIE2.CCP2IE 0 CCP2 Interrupt Enable bit BANK1:PCON 0x008E PCON REGISTER BANK1:PCON.POR 1 Power-on Reset Status bit BANK1:PCON.BOR 0 Brown-out Reset Status bit BANK1:RESERVED008F 0x008F RESERVED BANK1:RESERVED0090 0x0090 RESERVED BANK1:RESERVED0091 0x0091 RESERVED BANK1:PR2 0x0092 Timer2 Period Register BANK1:SSPADD 0x0093 Synchronous Serial Port (I2C mode) Address Register BANK1:SSPSTAT 0x0094 SYNC SERIAL PORT STATUS REGISTER BANK1:SSPSTAT.SMP 7 SPI data input sample phase BANK1:SSPSTAT.CKE 6 SPI Clock Edge Select BANK1:SSPSTAT.D_A 5 Data/Address bit (I2C mode only) BANK1:SSPSTAT.P 4 Stop bit (I2C mode only) BANK1:SSPSTAT.S 3 Start bit (I2C mode only) BANK1:SSPSTAT.R_W 2 Read/Write bit information (I2C mode only) BANK1:SSPSTAT.UA 1 Update Address (I2C mode only) BANK1:SSPSTAT.BF 0 Buffer Full Status bit BANK1:RESERVED0095 0x0095 RESERVED BANK1:RESERVED0096 0x0096 RESERVED BANK1:RESERVED0097 0x0097 RESERVED BANK1:TXSTA 0x0098 TRANSMIT STATUS AND CONTROL REGISTER BANK1:TXSTA.CSRC 7 Clock Source Select bit BANK1:TXSTA.TX9 6 9-bit Transmit Enable bit BANK1:TXSTA.TXEN 5 Transmit Enable bit BANK1:TXSTA.SYNC 4 USART Mode Select bit BANK1:TXSTA.BRGH 2 High Baud Rate Select bit BANK1:TXSTA.TRMT 1 Transmit Shift Register Status bit BANK1:TXSTA.TX9D 0 9th bit of transmit data BANK1:SPBRG 0x0099 Baud Rate Generator Register BANK1:RESERVED009A 0x009A RESERVED BANK1:RESERVED009B 0x009B RESERVED BANK1:RESERVED009C 0x009C RESERVED BANK1:RESERVED009D 0x009D RESERVED BANK1:RESERVED009E 0x009E RESERVED BANK1:RESERVED009F 0x009F RESERVED ; BANK2 (0x0100:0x0180) BANK2:INDF 0x0100 INDF (not a physical register) BANK2:TMR0 0x0101 Timer0 module's register BANK2:PCL 0x0102 Program Counter's (PC) Least Significant Byte BANK2:STATUS 0x0103 STATUS REGISTER BANK2:STATUS.IRP 7 RegIster Bank Select bit BANK2:STATUS.RP1 6 Register Bank Select bit 1 BANK2:STATUS.RP0 5 Register Bank Select bit 0 BANK2:STATUS.TO 4 Time-out bit BANK2:STATUS.PD 3 Power-down bit BANK2:STATUS.Z 2 Zero bit BANK2:STATUS.DC 1 Digit carry/borrow bit BANK2:STATUS.C 0 Carry/borrow bit BANK2:FSR 0x0104 Indirect data memory address pointer BANK2:RESERVED0105 0x0105 RESERVED BANK2:PORTB 0x0106 PORTB register BANK2:PORTB.RB7 7 PORTB bit 7 BANK2:PORTB.RB6 6 PORTB bit 6 BANK2:PORTB.RB5 5 PORTB bit 5 BANK2:PORTB.RB4 4 PORTB bit 4 BANK2:PORTB.RB3 3 PORTB bit 3 BANK2:PORTB.RB2 2 PORTB bit 2 BANK2:PORTB.RB1 1 PORTB bit 1 BANK2:PORTB.RB0 0 PORTB bit 0 BANK2:RESERVED0107 0x0107 RESERVED BANK2:RESERVED0108 0x0108 RESERVED BANK2:RESERVED0109 0x0109 RESERVED BANK2:PCLATH 0x010A Write Buffer for the upper 5 bits of the Program Counter BANK2:INTCON 0x010B INTCON REGISTER BANK2:INTCON.GIE 7 Global Interrupt Enable bit BANK2:INTCON.PEIE 6 Peripheral Interrupt Enable bit BANK2:INTCON.T0IE 5 TMR0 Overflow Interrupt Enable bit BANK2:INTCON.INTE 4 RB0/INT External Interrupt Enable bit BANK2:INTCON.RBIE 3 RB Port Change Interrupt Enable bit BANK2:INTCON.T0IF 2 TMR0 Overflow Interrupt Flag bit BANK2:INTCON.INTF 1 RB0/INT External Interrupt Flag bit BANK2:INTCON.RBIF 0 RB Port Change Interrupt Flag bit BANK2:RESERVED010C 0x010C RESERVED BANK2:RESERVED010D 0x010D RESERVED BANK2:RESERVED010E 0x010E RESERVED BANK2:RESERVED010F 0x010F RESERVED ; BANK3 (0x0180:0x0200) BANK3:INDF 0x0180 INDF (not a physical register) BANK3:OPTION 0x0181 OPTION REGISTER BANK3:OPTION.RBPU 7 PORTB Pull-up Enable bit BANK3:OPTION.INTEDG 6 Interrupt Edge Select bit BANK3:OPTION.T0CS 5 TMR0 Clock Source Select bit BANK3:OPTION.T0SE 4 TMR0 Source Edge Select bit BANK3:OPTION.PSA 3 Prescaler Assignment bit BANK3:OPTION.PS2 2 Prescaler Rate Select bit 2 BANK3:OPTION.PS1 1 Prescaler Rate Select bit 1 BANK3:OPTION.PS0 0 Prescaler Rate Select bit 0 BANK3:PCL 0x0182 Program Counter's (PC) Least Significant Byte BANK3:STATUS 0x0183 STATUS REGISTER BANK3:STATUS.IRP 7 RegIster Bank Select bit BANK3:STATUS.RP1 6 Register Bank Select bit 1 BANK3:STATUS.RP0 5 Register Bank Select bit 0 BANK3:STATUS.TO 4 Time-out bit BANK3:STATUS.PD 3 Power-down bit BANK3:STATUS.Z 2 Zero bit BANK3:STATUS.DC 1 Digit carry/borrow bit BANK3:STATUS.C 0 Carry/borrow bit BANK3:FSR 0x0184 Indirect data memory address pointer BANK3:RESERVED0185 0x0185 RESERVED BANK3:TRISB 0x0186 PORTB Data Direction Register BANK3:TRISB.TRISB7 7 PORTB Data Direction Register bit 7 BANK3:TRISB.TRISB6 6 PORTB Data Direction Register bit 6 BANK3:TRISB.TRISB5 5 PORTB Data Direction Register bit 5 BANK3:TRISB.TRISB4 4 PORTB Data Direction Register bit 4 BANK3:TRISB.TRISB3 3 PORTB Data Direction Register bit 3 BANK3:TRISB.TRISB2 2 PORTB Data Direction Register bit 2 BANK3:TRISB.TRISB1 1 PORTB Data Direction Register bit 1 BANK3:TRISB.TRISB0 0 PORTB Data Direction Register bit 0 BANK3:RESERVED0187 0x0187 RESERVED BANK3:RESERVED0188 0x0188 RESERVED BANK3:RESERVED0189 0x0189 RESERVED BANK3:PCLATH 0x018A Write Buffer for the upper 5 bits of the Program Counter BANK3:INTCON 0x018B INTCON REGISTER BANK3:INTCON.GIE 7 Global Interrupt Enable bit BANK3:INTCON.PEIE 6 Peripheral Interrupt Enable bit BANK3:INTCON.T0IE 5 TMR0 Overflow Interrupt Enable bit BANK3:INTCON.INTE 4 RB0/INT External Interrupt Enable bit BANK3:INTCON.RBIE 3 RB Port Change Interrupt Enable bit BANK3:INTCON.T0IF 2 TMR0 Overflow Interrupt Flag bit BANK3:INTCON.INTF 1 RB0/INT External Interrupt Flag bit BANK3:INTCON.RBIF 0 RB Port Change Interrupt Flag bit BANK3:RESERVED018C 0x018C RESERVED BANK3:RESERVED018D 0x018D RESERVED BANK3:RESERVED018E 0x018E RESERVED BANK3:RESERVED018F 0x018F RESERVED .16C67 ; http://www.microchip.com/download/lit/pline/picmicro/families/16c6x/30234d.pdf ; PIC16C6x.pdf ; MEMORY MAP ; BANK_0 area DATA FSR_ 0x0000:0x0020 area DATA Gen_Purp 0x0020:0x0080 General Purpose Register area DATA MEM_Program0 0x0080:0x0800 On-chip Program Memory (Page 0) area DATA MEM_Program1 0x0800:0x1000 On-chip Program Memory (Page 1) area DATA MEM_Program2 0x1000:0x1800 On-chip Program Memory (Page 2) area DATA MEM_Program3 0x1800:0x2000 On-chip Program Memory (Page 3) ; BANK_1 ; area DATA FSR_ 0x0080:0x00A0 ; area DATA Gen_Purp 0x00A0:0x00F0 General Purpose Register ; area DATA Gen_Purp_BANK0 0x00F0:0x0100 accesses 70h-7Fh in Bank 0 ; area DATA MEM_Program0 0x0100:0x0800 On-chip Program Memory (Page 0) ; area DATA MEM_Program1 0x0800:0x1000 On-chip Program Memory (Page 1) ; area DATA MEM_Program2 0x1000:0x1800 On-chip Program Memory (Page 2) ; area DATA MEM_Program3 0x1800:0x2000 On-chip Program Memory (Page 3) ; BANK_2 ; area DATA FSR_ 0x0100:0x0110 ; area DATA Gen_Purp0 0x0110:0x0120 General Purpose Register 16 Bytes ; area DATA Gen_Purp1 0x0120:0x0170 General Purpose Register 80 Bytes ; area DATA Gen_Purp_BANK0 0x0170:0x0180 accesses 70h-7Fh in Bank 0 ; area DATA MEM_Program0 0x0180:0x0800 On-chip Program Memory (Page 0) ; area DATA MEM_Program1 0x0800:0x1000 On-chip Program Memory (Page 1) ; area DATA MEM_Program2 0x1000:0x1800 On-chip Program Memory (Page 2) ; area DATA MEM_Program3 0x1800:0x2000 On-chip Program Memory (Page 3) ; BANK_3 ; area DATA FSR_ 0x0180:0x0190 ; area DATA Gen_Purp0 0x0190:0x01A0 General Purpose Register 16 Bytes ; area DATA Gen_Purp1 0x01A0:0x01F0 General Purpose Register 80 Bytes ; area DATA Gen_Purp_BANK0 0x01F0:0x0200 accesses 70h-7Fh in Bank 0 ; area DATA MEM_Program0 0x0200:0x0800 On-chip Program Memory (Page 0) ; area DATA MEM_Program1 0x0800:0x1000 On-chip Program Memory (Page 1) ; area DATA MEM_Program2 0x1000:0x1800 On-chip Program Memory (Page 2) ; area DATA MEM_Program3 0x1800:0x2000 On-chip Program Memory (Page 3) ; Interrupt and reset vector assignments interrupt RESET 0x0000 RESET ; INPUT/OUTPUT PORTS ; BANK0 (0x0000:0x0080) BANK0:INDF 0x0000 INDF (not a physical register) BANK0:TMR0 0x0001 Timer0 module's register BANK0:PCL 0x0002 Program Counter's (PC) Least Significant Byte BANK0:STATUS 0x0003 STATUS REGISTER BANK0:STATUS.IRP 7 RegIster Bank Select bit BANK0:STATUS.RP1 6 Register Bank Select bit 1 BANK0:STATUS.RP0 5 Register Bank Select bit 0 BANK0:STATUS.TO 4 Time-out bit BANK0:STATUS.PD 3 Power-down bit BANK0:STATUS.Z 2 Zero bit BANK0:STATUS.DC 1 Digit carry/borrow bit BANK0:STATUS.C 0 Carry/borrow bit BANK0:FSR 0x0004 Indirect data memory address pointer BANK0:PORTA 0x0005 PORTA register BANK0:PORTA.RA5 5 PORTA bit 5 BANK0:PORTA.RA4 4 PORTA bit 4 BANK0:PORTA.RA3 3 PORTA bit 3 BANK0:PORTA.RA2 2 PORTA bit 2 BANK0:PORTA.RA1 1 PORTA bit 1 BANK0:PORTA.RA0 0 PORTA bit 0 BANK0:PORTB 0x0006 PORTB register BANK0:PORTB.RB7 7 PORTB bit 7 BANK0:PORTB.RB6 6 PORTB bit 6 BANK0:PORTB.RB5 5 PORTB bit 5 BANK0:PORTB.RB4 4 PORTB bit 4 BANK0:PORTB.RB3 3 PORTB bit 3 BANK0:PORTB.RB2 2 PORTB bit 2 BANK0:PORTB.RB1 1 PORTB bit 1 BANK0:PORTB.RB0 0 PORTB bit 0 BANK0:PORTC 0x0007 PORTC register BANK0:PORTC.RC7 7 PORTC bit 7 BANK0:PORTC.RC6 6 PORTC bit 6 BANK0:PORTC.RC5 5 PORTC bit 5 BANK0:PORTC.RC4 4 PORTC bit 4 BANK0:PORTC.RC3 3 PORTC bit 3 BANK0:PORTC.RC2 2 PORTC bit 2 BANK0:PORTC.RC1 1 PORTC bit 1 BANK0:PORTC.RC0 0 PORTC bit 0 BANK0:PORTD 0x0008 PORTD register BANK0:PORTD.RD7 7 PORTD bit 7 BANK0:PORTD.RD6 6 PORTD bit 6 BANK0:PORTD.RD5 5 PORTD bit 5 BANK0:PORTD.RD4 4 PORTD bit 4 BANK0:PORTD.RD3 3 PORTD bit 3 BANK0:PORTD.RD2 2 PORTD bit 2 BANK0:PORTD.RD1 1 PORTD bit 1 BANK0:PORTD.RD0 0 PORTD bit 0 BANK0:PORTE 0x0009 PORTE register BANK0:PORTE.RE2 2 PORTE bit 2 BANK0:PORTE.RE1 1 PORTE bit 1 BANK0:PORTE.RE0 0 PORTE bit 0 BANK0:PCLATH 0x000A Write Buffer for the upper 5 bits of the Program Counter BANK0:INTCON 0x000B INTCON REGISTER BANK0:INTCON.GIE 7 Global Interrupt Enable bit BANK0:INTCON.PEIE 6 Peripheral Interrupt Enable bit BANK0:INTCON.T0IE 5 TMR0 Overflow Interrupt Enable bit BANK0:INTCON.INTE 4 RB0/INT External Interrupt Enable bit BANK0:INTCON.RBIE 3 RB Port Change Interrupt Enable bit BANK0:INTCON.T0IF 2 TMR0 Overflow Interrupt Flag bit BANK0:INTCON.INTF 1 RB0/INT External Interrupt Flag bit BANK0:INTCON.RBIF 0 RB Port Change Interrupt Flag bit BANK0:PIR1 0x000C PIR1 REGISTER BANK0:PIR1.PSPIF 7 Parallel Slave Port Interrupt Flag bit BANK0:PIR1.RCIF 5 USART Receive Interrupt Flag bit BANK0:PIR1.TXIF 4 USART Transmit Interrupt Flag bit BANK0:PIR1.SSPIF 3 Synchronous Serial Port Interrupt Flag bit BANK0:PIR1.CCP1IF 2 CCP1 Interrupt Flag bit BANK0:PIR1.TMR2IF 1 TMR2 to PR2 Match Interrupt Flag bit BANK0:PIR1.TMR1IF 0 TMR1 Overflow Interrupt Flag bit BANK0:PIR2 0x000D PIR2 REGISTER BANK0:PIR2.CCP2IF 0 CCP2 Interrupt Flag bit BANK0:TMR1L 0x000E Holding register for the Least Significant Byte of the 16-bit TMR1 register BANK0:TMR1H 0x000F Holding register for the Most Significant Byte of the 16-bit TMR1 register BANK0:T1CON 0x0010 TIMER1 CONTROL REGISTER BANK0:T1CON.T1CKPS1 5 Timer1 Input Clock Prescale Select bit 1 BANK0:T1CON.T1CKPS0 4 Timer1 Input Clock Prescale Select bit 0 BANK0:T1CON.T1OSCEN 3 Timer1 Oscillator Enable Control bit BANK0:T1CON.T1SYNC 2 Timer1 External Clock Input Synchronization Control bit BANK0:T1CON.TMR1CS 1 Timer1 Clock Source Select bit BANK0:T1CON.TMR1ON 0 Timer1 On bit BANK0:TMR2 0x0011 Timer2 module's register BANK0:T2CON 0x0012 TIMER2 CONTROL REGISTER BANK0:T2CON.TOUTPS3 6 Timer2 Output Postscale Select bit 3 BANK0:T2CON.TOUTPS2 5 Timer2 Output Postscale Select bit 2 BANK0:T2CON.TOUTPS1 4 Timer2 Output Postscale Select bit 1 BANK0:T2CON.TOUTPS0 3 Timer2 Output Postscale Select bit 0 BANK0:T2CON.TMR2ON 2 Timer2 On bit BANK0:T2CON.T2CKPS1 1 Timer2 Clock Prescale Select bit 1 BANK0:T2CON.T2CKPS0 0 Timer2 Clock Prescale Select bit 0 BANK0:SSPBUF 0x0013 Synchronous Serial Port Receive Buffer/Transmit Register BANK0:SSPCON 0x0014 SYNC SERIAL PORT CONTROL REGISTER BANK0:SSPCON.WCOL 7 Write Collision Detect bit BANK0:SSPCON.SSPOV 6 Receive Overflow Indicator bit BANK0:SSPCON.SSPEN 5 Synchronous Serial Port Enable bit BANK0:SSPCON.CKP 4 Clock Polarity Select bit BANK0:SSPCON.SSPM3 3 Synchronous Serial Port Mode Select bit 3 BANK0:SSPCON.SSPM2 2 Synchronous Serial Port Mode Select bit 2 BANK0:SSPCON.SSPM1 1 Synchronous Serial Port Mode Select bit 1 BANK0:SSPCON.SSPM0 0 Synchronous Serial Port Mode Select bit 0 BANK0:CCPR1L 0x0015 Capture/Compare/PWM1 (LSB) BANK0:CCPR1H 0x0016 Capture/Compare/PWM1 (MSB) BANK0:CCP1CON 0x0017 CCP1CON REGISTER BANK0:CCP1CON.CCP1X 5 PWM Least Significant bit BANK0:CCP1CON.CCP1Y 4 PWM Least Significant bit BANK0:CCP1CON.CCP1M3 3 CCP1 Mode Select bit 3 BANK0:CCP1CON.CCP1M2 2 CCP1 Mode Select bit 2 BANK0:CCP1CON.CCP1M1 1 CCP1 Mode Select bit 1 BANK0:CCP1CON.CCP1M0 0 CCP1 Mode Select bit 0 BANK0:RCSTA 0x0018 RECEIVE STATUS AND CONTROL REGISTER BANK0:RCSTA.SPEN 7 Serial Port Enable bit BANK0:RCSTA.RX9 6 9-bit Receive Enable bit BANK0:RCSTA.SREN 5 Single Receive Enable bit BANK0:RCSTA.CREN 4 Continuous Receive Enable bit BANK0:RCSTA.FERR 2 Framing Error bit BANK0:RCSTA.OERR 1 Overrun Error bit BANK0:RCSTA.RX9D 0 9th bit of received data BANK0:TXREG 0x0019 USART Transmit Data Register BANK0:RCREG 0x001A USART Receive Data Register BANK0:CCPR2L 0x001B Capture/Compare/PWM2 (LSB) BANK0:CCPR2H 0x001C Capture/Compare/PWM2 (MSB) BANK0:CCP2CON 0x001D CCP2CON REGISTER BANK0:CCP2CON.CCP2X 5 PWM Least Significant bit BANK0:CCP2CON.CCP2Y 4 PWM Least Significant bit BANK0:CCP2CON.CCP2M3 3 CCP2 Mode Select bit 3 BANK0:CCP2CON.CCP2M2 2 CCP2 Mode Select bit 2 BANK0:CCP2CON.CCP2M1 1 CCP2 Mode Select bit 1 BANK0:CCP2CON.CCP2M0 0 CCP2 Mode Select bit 0 BANK0:RESERVED001E 0x001E RESERVED BANK0:RESERVED001F 0x001F RESERVED ; BANK1 (0x0080:0x0100) BANK1:INDF 0x0080 INDF (not a physical register) BANK1:OPTION 0x0081 OPTION REGISTER BANK1:OPTION.RBPU 7 PORTB Pull-up Enable bit BANK1:OPTION.INTEDG 6 Interrupt Edge Select bit BANK1:OPTION.T0CS 5 TMR0 Clock Source Select bit BANK1:OPTION.T0SE 4 TMR0 Source Edge Select bit BANK1:OPTION.PSA 3 Prescaler Assignment bit BANK1:OPTION.PS2 2 Prescaler Rate Select bit 2 BANK1:OPTION.PS1 1 Prescaler Rate Select bit 1 BANK1:OPTION.PS0 0 Prescaler Rate Select bit 0 BANK1:PCL 0x0082 Program Counter's (PC) Least Significant Byte BANK1:STATUS 0x0083 STATUS REGISTER BANK1:STATUS.IRP 7 RegIster Bank Select bit BANK1:STATUS.RP1 6 Register Bank Select bit 1 BANK1:STATUS.RP0 5 Register Bank Select bit 0 BANK1:STATUS.TO 4 Time-out bit BANK1:STATUS.PD 3 Power-down bit BANK1:STATUS.Z 2 Zero bit BANK1:STATUS.DC 1 Digit carry/borrow bit BANK1:STATUS.C 0 Carry/borrow bit BANK1:FSR 0x0084 Indirect data memory address pointer BANK1:TRISA 0x0085 PORTA Data Direction Register BANK1:TRISA.TRISA5 5 PORTA Data Direction Register bit 5 BANK1:TRISA.TRISA4 4 PORTA Data Direction Register bit 4 BANK1:TRISA.TRISA3 3 PORTA Data Direction Register bit 3 BANK1:TRISA.TRISA2 2 PORTA Data Direction Register bit 2 BANK1:TRISA.TRISA1 1 PORTA Data Direction Register bit 1 BANK1:TRISA.TRISA0 0 PORTA Data Direction Register bit 0 BANK1:TRISB 0x0086 PORTB Data Direction Register BANK1:TRISB.TRISB7 7 PORTB Data Direction Register bit 7 BANK1:TRISB.TRISB6 6 PORTB Data Direction Register bit 6 BANK1:TRISB.TRISB5 5 PORTB Data Direction Register bit 5 BANK1:TRISB.TRISB4 4 PORTB Data Direction Register bit 4 BANK1:TRISB.TRISB3 3 PORTB Data Direction Register bit 3 BANK1:TRISB.TRISB2 2 PORTB Data Direction Register bit 2 BANK1:TRISB.TRISB1 1 PORTB Data Direction Register bit 1 BANK1:TRISB.TRISB0 0 PORTB Data Direction Register bit 0 BANK1:TRISC 0x0087 PORTC Data Direction Register BANK1:TRISC.TRISC7 7 PORTC Data Direction Register bit 7 BANK1:TRISC.TRISC6 6 PORTC Data Direction Register bit 6 BANK1:TRISC.TRISC5 5 PORTC Data Direction Register bit 5 BANK1:TRISC.TRISC4 4 PORTC Data Direction Register bit 4 BANK1:TRISC.TRISC3 3 PORTC Data Direction Register bit 3 BANK1:TRISC.TRISC2 2 PORTC Data Direction Register bit 2 BANK1:TRISC.TRISC1 1 PORTC Data Direction Register bit 1 BANK1:TRISC.TRISC0 0 PORTC Data Direction Register bit 0 BANK1:TRISD 0x0088 PORTD Data Direction Register BANK1:TRISD.TRISD7 7 PORTD Data Direction Register bit 7 BANK1:TRISD.TRISD6 6 PORTD Data Direction Register bit 6 BANK1:TRISD.TRISD5 5 PORTD Data Direction Register bit 5 BANK1:TRISD.TRISD4 4 PORTD Data Direction Register bit 4 BANK1:TRISD.TRISD3 3 PORTD Data Direction Register bit 3 BANK1:TRISD.TRISD2 2 PORTD Data Direction Register bit 2 BANK1:TRISD.TRISD1 1 PORTD Data Direction Register bit 1 BANK1:TRISD.TRISD0 0 PORTD Data Direction Register bit 0 BANK1:TRISE 0x0089 PORTE Data Direction Bits BANK1:TRISE.IBF 7 Input Buffer Full Status bit BANK1:TRISE.OBF 6 Output Buffer Full Status bit BANK1:TRISE.IBOV 5 Input Buffer Overflow Detect bit BANK1:TRISE.PSPMODE 4 Parallel Slave Port Mode Select bit BANK1:TRISE.TRISE2 2 Direction Control bit for pin RE2/CS BANK1:TRISE.TRISE1 1 Direction Control bit for pin RE1/WR BANK1:TRISE.TRISE0 0 Direction Control bit for pin RE0/RD BANK1:PCLATH 0x008A Write Buffer for the upper 5 bits of the Program Counter BANK1:INTCON 0x008B INTCON REGISTER BANK1:INTCON.GIE 7 Global Interrupt Enable bit BANK1:INTCON.PEIE 6 Peripheral Interrupt Enable bit BANK1:INTCON.T0IE 5 TMR0 Overflow Interrupt Enable bit BANK1:INTCON.INTE 4 RB0/INT External Interrupt Enable bit BANK1:INTCON.RBIE 3 RB Port Change Interrupt Enable bit BANK1:INTCON.T0IF 2 TMR0 Overflow Interrupt Flag bit BANK1:INTCON.INTF 1 RB0/INT External Interrupt Flag bit BANK1:INTCON.RBIF 0 RB Port Change Interrupt Flag bit BANK1:PIE1 0x008C PIE1 REGISTER BANK1:PIE1.PSPIE 7 Parallel Slave Port Read/Write Interrupt Enable bit BANK1:PIE1.RCIE 5 USART Receive Interrupt Enable bit BANK1:PIE1.TXIE 4 USART Transmit Interrupt Enable bit BANK1:PIE1.SSPIE 3 Synchronous Serial Port Interrupt Enable bit BANK1:PIE1.CCP1IE 2 CCP1 Interrupt Enable bit BANK1:PIE1.TMR2IE 1 TMR2 to PR2 Match Interrupt Enable bit BANK1:PIE1.TMR1IE 0 TMR1 Overflow Interrupt Enable bit BANK1:PIE2 0x008D PIE2 REGISTER BANK1:PIE2.CCP2IE 0 CCP2 Interrupt Enable bit BANK1:PCON 0x008E PCON REGISTER BANK1:PCON.POR 1 Power-on Reset Status bit BANK1:PCON.BOR 0 Brown-out Reset Status bit BANK1:RESERVED008F 0x008F RESERVED BANK1:RESERVED0090 0x0090 RESERVED BANK1:RESERVED0091 0x0091 RESERVED BANK1:PR2 0x0092 Timer2 Period Register BANK1:SSPADD 0x0093 Synchronous Serial Port (I2C mode) Address Register BANK1:SSPSTAT 0x0094 SYNC SERIAL PORT STATUS REGISTER BANK1:SSPSTAT.SMP 7 SPI data input sample phase BANK1:SSPSTAT.CKE 6 SPI Clock Edge Select BANK1:SSPSTAT.D_A 5 Data/Address bit (I2C mode only) BANK1:SSPSTAT.P 4 Stop bit (I2C mode only) BANK1:SSPSTAT.S 3 Start bit (I2C mode only) BANK1:SSPSTAT.R_W 2 Read/Write bit information (I2C mode only) BANK1:SSPSTAT.UA 1 Update Address (I2C mode only) BANK1:SSPSTAT.BF 0 Buffer Full Status bit BANK1:RESERVED0095 0x0095 RESERVED BANK1:RESERVED0096 0x0096 RESERVED BANK1:RESERVED0097 0x0097 RESERVED BANK1:TXSTA 0x0098 TRANSMIT STATUS AND CONTROL REGISTER BANK1:TXSTA.CSRC 7 Clock Source Select bit BANK1:TXSTA.TX9 6 9-bit Transmit Enable bit BANK1:TXSTA.TXEN 5 Transmit Enable bit BANK1:TXSTA.SYNC 4 USART Mode Select bit BANK1:TXSTA.BRGH 2 High Baud Rate Select bit BANK1:TXSTA.TRMT 1 Transmit Shift Register Status bit BANK1:TXSTA.TX9D 0 9th bit of transmit data BANK1:SPBRG 0x0099 Baud Rate Generator Register BANK1:RESERVED009A 0x009A RESERVED BANK1:RESERVED009B 0x009B RESERVED BANK1:RESERVED009C 0x009C RESERVED BANK1:RESERVED009D 0x009D RESERVED BANK1:RESERVED009E 0x009E RESERVED BANK1:RESERVED009F 0x009F RESERVED ; BANK2 (0x0100:0x0180) BANK2:INDF 0x0100 INDF (not a physical register) BANK2:TMR0 0x0101 Timer0 module's register BANK2:PCL 0x0102 Program Counter's (PC) Least Significant Byte BANK2:STATUS 0x0103 STATUS REGISTER BANK2:STATUS.IRP 7 RegIster Bank Select bit BANK2:STATUS.RP1 6 Register Bank Select bit 1 BANK2:STATUS.RP0 5 Register Bank Select bit 0 BANK2:STATUS.TO 4 Time-out bit BANK2:STATUS.PD 3 Power-down bit BANK2:STATUS.Z 2 Zero bit BANK2:STATUS.DC 1 Digit carry/borrow bit BANK2:STATUS.C 0 Carry/borrow bit BANK2:FSR 0x0104 Indirect data memory address pointer BANK2:RESERVED0105 0x0105 RESERVED BANK2:PORTB 0x0106 PORTB register BANK2:PORTB.RB7 7 PORTB bit 7 BANK2:PORTB.RB6 6 PORTB bit 6 BANK2:PORTB.RB5 5 PORTB bit 5 BANK2:PORTB.RB4 4 PORTB bit 4 BANK2:PORTB.RB3 3 PORTB bit 3 BANK2:PORTB.RB2 2 PORTB bit 2 BANK2:PORTB.RB1 1 PORTB bit 1 BANK2:PORTB.RB0 0 PORTB bit 0 BANK2:RESERVED0107 0x0107 RESERVED BANK2:RESERVED0108 0x0108 RESERVED BANK2:RESERVED0109 0x0109 RESERVED BANK2:PCLATH 0x010A Write Buffer for the upper 5 bits of the Program Counter BANK2:INTCON 0x010B INTCON REGISTER BANK2:INTCON.GIE 7 Global Interrupt Enable bit BANK2:INTCON.PEIE 6 Peripheral Interrupt Enable bit BANK2:INTCON.T0IE 5 TMR0 Overflow Interrupt Enable bit BANK2:INTCON.INTE 4 RB0/INT External Interrupt Enable bit BANK2:INTCON.RBIE 3 RB Port Change Interrupt Enable bit BANK2:INTCON.T0IF 2 TMR0 Overflow Interrupt Flag bit BANK2:INTCON.INTF 1 RB0/INT External Interrupt Flag bit BANK2:INTCON.RBIF 0 RB Port Change Interrupt Flag bit BANK2:RESERVED010C 0x010C RESERVED BANK2:RESERVED010D 0x010D RESERVED BANK2:RESERVED010E 0x010E RESERVED BANK2:RESERVED010F 0x010F RESERVED ; BANK3 (0x0180:0x0200) BANK3:INDF 0x0180 INDF (not a physical register) BANK3:OPTION 0x0181 OPTION REGISTER BANK3:OPTION.RBPU 7 PORTB Pull-up Enable bit BANK3:OPTION.INTEDG 6 Interrupt Edge Select bit BANK3:OPTION.T0CS 5 TMR0 Clock Source Select bit BANK3:OPTION.T0SE 4 TMR0 Source Edge Select bit BANK3:OPTION.PSA 3 Prescaler Assignment bit BANK3:OPTION.PS2 2 Prescaler Rate Select bit 2 BANK3:OPTION.PS1 1 Prescaler Rate Select bit 1 BANK3:OPTION.PS0 0 Prescaler Rate Select bit 0 BANK3:PCL 0x0182 Program Counter's (PC) Least Significant Byte BANK3:STATUS 0x0183 STATUS REGISTER BANK3:STATUS.IRP 7 RegIster Bank Select bit BANK3:STATUS.RP1 6 Register Bank Select bit 1 BANK3:STATUS.RP0 5 Register Bank Select bit 0 BANK3:STATUS.TO 4 Time-out bit BANK3:STATUS.PD 3 Power-down bit BANK3:STATUS.Z 2 Zero bit BANK3:STATUS.DC 1 Digit carry/borrow bit BANK3:STATUS.C 0 Carry/borrow bit BANK3:FSR 0x0184 Indirect data memory address pointer BANK3:RESERVED0185 0x0185 RESERVED BANK3:TRISB 0x0186 PORTB Data Direction Register BANK3:TRISB.TRISB7 7 PORTB Data Direction Register bit 7 BANK3:TRISB.TRISB6 6 PORTB Data Direction Register bit 6 BANK3:TRISB.TRISB5 5 PORTB Data Direction Register bit 5 BANK3:TRISB.TRISB4 4 PORTB Data Direction Register bit 4 BANK3:TRISB.TRISB3 3 PORTB Data Direction Register bit 3 BANK3:TRISB.TRISB2 2 PORTB Data Direction Register bit 2 BANK3:TRISB.TRISB1 1 PORTB Data Direction Register bit 1 BANK3:TRISB.TRISB0 0 PORTB Data Direction Register bit 0 BANK3:RESERVED0187 0x0187 RESERVED BANK3:RESERVED0188 0x0188 RESERVED BANK3:RESERVED0189 0x0189 RESERVED BANK3:PCLATH 0x018A Write Buffer for the upper 5 bits of the Program Counter BANK3:INTCON 0x018B INTCON REGISTER BANK3:INTCON.GIE 7 Global Interrupt Enable bit BANK3:INTCON.PEIE 6 Peripheral Interrupt Enable bit BANK3:INTCON.T0IE 5 TMR0 Overflow Interrupt Enable bit BANK3:INTCON.INTE 4 RB0/INT External Interrupt Enable bit BANK3:INTCON.RBIE 3 RB Port Change Interrupt Enable bit BANK3:INTCON.T0IF 2 TMR0 Overflow Interrupt Flag bit BANK3:INTCON.INTF 1 RB0/INT External Interrupt Flag bit BANK3:INTCON.RBIF 0 RB Port Change Interrupt Flag bit BANK3:RESERVED018C 0x018C RESERVED BANK3:RESERVED018D 0x018D RESERVED BANK3:RESERVED018E 0x018E RESERVED BANK3:RESERVED018F 0x018F RESERVED .16CR62 ; http://www.microchip.com/download/lit/pline/picmicro/families/16c6x/30234d.pdf ; PIC16C6x.pdf ; MEMORY MAP ; BANK_0 area DATA FSR_ 0x0000:0x0020 area DATA Gen_Purp 0x0020:0x0080 General Purpose Register area DATA MEM_Program 0x0080:0x0800 On-chip Program Memory ; BANK_1 area DATA FSR_ 0x0080:0x00A0 area DATA Gen_Purp 0x00A0:0x00C0 General Purpose Register area BSS RESERVED 0x00C0:0x0100 area DATA MEM_Program 0x0100:0x0800 On-chip Program Memory ; Interrupt and reset vector assignments interrupt RESET 0x0000 RESET ; INPUT/OUTPUT PORTS ; BANK0 (0x0000:0x0080) BANK0:INDF 0x0000 INDF (not a physical register) BANK0:TMR0 0x0001 Timer0 module's register BANK0:PCL 0x0002 Program Counter's (PC) Least Significant Byte BANK0:STATUS 0x0003 STATUS REGISTER BANK0:STATUS.RP0 5 Register Bank Select bit 0 BANK0:STATUS.TO 4 Time-out bit BANK0:STATUS.PD 3 Power-down bit BANK0:STATUS.Z 2 Zero bit BANK0:STATUS.DC 1 Digit carry/borrow bit BANK0:STATUS.C 0 Carry/borrow bit BANK0:FSR 0x0004 Indirect data memory address pointer BANK0:PORTA 0x0005 PORTA register BANK0:PORTA.RA5 5 PORTA bit 5 BANK0:PORTA.RA4 4 PORTA bit 4 BANK0:PORTA.RA3 3 PORTA bit 3 BANK0:PORTA.RA2 2 PORTA bit 2 BANK0:PORTA.RA1 1 PORTA bit 1 BANK0:PORTA.RA0 0 PORTA bit 0 BANK0:PORTB 0x0006 PORTB register BANK0:PORTB.RB7 7 PORTB bit 7 BANK0:PORTB.RB6 6 PORTB bit 6 BANK0:PORTB.RB5 5 PORTB bit 5 BANK0:PORTB.RB4 4 PORTB bit 4 BANK0:PORTB.RB3 3 PORTB bit 3 BANK0:PORTB.RB2 2 PORTB bit 2 BANK0:PORTB.RB1 1 PORTB bit 1 BANK0:PORTB.RB0 0 PORTB bit 0 BANK0:PORTC 0x0007 PORTC register BANK0:PORTC.RC7 7 PORTC bit 7 BANK0:PORTC.RC6 6 PORTC bit 6 BANK0:PORTC.RC5 5 PORTC bit 5 BANK0:PORTC.RC4 4 PORTC bit 4 BANK0:PORTC.RC3 3 PORTC bit 3 BANK0:PORTC.RC2 2 PORTC bit 2 BANK0:PORTC.RC1 1 PORTC bit 1 BANK0:PORTC.RC0 0 PORTC bit 0 BANK0:RESERVED0008 0x0008 RESERVED BANK0:RESERVED0009 0x0009 RESERVED BANK0:PCLATH 0x000A Write Buffer for the upper 5 bits of the Program Counter BANK0:INTCON 0x000B INTCON REGISTER BANK0:INTCON.GIE 7 Global Interrupt Enable bit BANK0:INTCON.PEIE 6 Peripheral Interrupt Enable bit BANK0:INTCON.T0IE 5 TMR0 Overflow Interrupt Enable bit BANK0:INTCON.INTE 4 RB0/INT External Interrupt Enable bit BANK0:INTCON.RBIE 3 RB Port Change Interrupt Enable bit BANK0:INTCON.T0IF 2 TMR0 Overflow Interrupt Flag bit BANK0:INTCON.INTF 1 RB0/INT External Interrupt Flag bit BANK0:INTCON.RBIF 0 RB Port Change Interrupt Flag bit BANK0:PIR1 0x000C PIR1 REGISTER BANK0:PIR1.SSPIF 3 Synchronous Serial Port Interrupt Flag bit BANK0:PIR1.CCP1IF 2 CCP1 Interrupt Flag bit BANK0:PIR1.TMR2IF 1 TMR2 to PR2 Match Interrupt Flag bit BANK0:PIR1.TMR1IF 0 TMR1 Overflow Interrupt Flag bit BANK0:RESERVED000D 0x000D RESERVED BANK0:TMR1L 0x000E Holding register for the Least Significant Byte of the 16-bit TMR1 register BANK0:TMR1H 0x000F Holding register for the Most Significant Byte of the 16-bit TMR1 register BANK0:T1CON 0x0010 TIMER1 CONTROL REGISTER BANK0:T1CON.T1CKPS1 5 Timer1 Input Clock Prescale Select bit 1 BANK0:T1CON.T1CKPS0 4 Timer1 Input Clock Prescale Select bit 0 BANK0:T1CON.T1OSCEN 3 Timer1 Oscillator Enable Control bit BANK0:T1CON.T1SYNC 2 Timer1 External Clock Input Synchronization Control bit BANK0:T1CON.TMR1CS 1 Timer1 Clock Source Select bit BANK0:T1CON.TMR1ON 0 Timer1 On bit BANK0:TMR2 0x0011 Timer2 module's register BANK0:T2CON 0x0012 TIMER2 CONTROL REGISTER BANK0:T2CON.TOUTPS3 6 Timer2 Output Postscale Select bit 3 BANK0:T2CON.TOUTPS2 5 Timer2 Output Postscale Select bit 2 BANK0:T2CON.TOUTPS1 4 Timer2 Output Postscale Select bit 1 BANK0:T2CON.TOUTPS0 3 Timer2 Output Postscale Select bit 0 BANK0:T2CON.TMR2ON 2 Timer2 On bit BANK0:T2CON.T2CKPS1 1 Timer2 Clock Prescale Select bit 1 BANK0:T2CON.T2CKPS0 0 Timer2 Clock Prescale Select bit 0 BANK0:SSPBUF 0x0013 Synchronous Serial Port Receive Buffer/Transmit Register BANK0:SSPCON 0x0014 SYNC SERIAL PORT CONTROL REGISTER BANK0:SSPCON.WCOL 7 Write Collision Detect bit BANK0:SSPCON.SSPOV 6 Receive Overflow Indicator bit BANK0:SSPCON.SSPEN 5 Synchronous Serial Port Enable bit BANK0:SSPCON.CKP 4 Clock Polarity Select bit BANK0:SSPCON.SSPM3 3 Synchronous Serial Port Mode Select bit 3 BANK0:SSPCON.SSPM2 2 Synchronous Serial Port Mode Select bit 2 BANK0:SSPCON.SSPM1 1 Synchronous Serial Port Mode Select bit 1 BANK0:SSPCON.SSPM0 0 Synchronous Serial Port Mode Select bit 0 BANK0:CCPR1L 0x0015 Capture/Compare/PWM1 (LSB) BANK0:CCPR1H 0x0016 Capture/Compare/PWM1 (MSB) BANK0:CCP1CON 0x0017 CCP1CON REGISTER BANK0:CCP1CON.CCP1X 5 PWM Least Significant bit BANK0:CCP1CON.CCP1Y 4 PWM Least Significant bit BANK0:CCP1CON.CCP1M3 3 CCP1 Mode Select bit 3 BANK0:CCP1CON.CCP1M2 2 CCP1 Mode Select bit 2 BANK0:CCP1CON.CCP1M1 1 CCP1 Mode Select bit 1 BANK0:CCP1CON.CCP1M0 0 CCP1 Mode Select bit 0 BANK0:RESERVED0018 0x0018 RESERVED BANK0:RESERVED0019 0x0019 RESERVED BANK0:RESERVED001A 0x001A RESERVED BANK0:RESERVED001B 0x001B RESERVED BANK0:RESERVED001C 0x001C RESERVED BANK0:RESERVED001D 0x001D RESERVED BANK0:RESERVED001E 0x001E RESERVED BANK0:RESERVED001F 0x001F RESERVED ; BANK1 (0x0080:0x0100) BANK1:INDF 0x0080 INDF (not a physical register) BANK1:OPTION 0x0081 OPTION REGISTER BANK1:OPTION.RBPU 7 PORTB Pull-up Enable bit BANK1:OPTION.INTEDG 6 Interrupt Edge Select bit BANK1:OPTION.T0CS 5 TMR0 Clock Source Select bit BANK1:OPTION.T0SE 4 TMR0 Source Edge Select bit BANK1:OPTION.PSA 3 Prescaler Assignment bit BANK1:OPTION.PS2 2 Prescaler Rate Select bit 2 BANK1:OPTION.PS1 1 Prescaler Rate Select bit 1 BANK1:OPTION.PS0 0 Prescaler Rate Select bit 0 BANK1:PCL 0x0082 Program Counter's (PC) Least Significant Byte BANK1:STATUS 0x0083 STATUS REGISTER BANK1:STATUS.RP0 5 Register Bank Select bit 0 BANK1:STATUS.TO 4 Time-out bit BANK1:STATUS.PD 3 Power-down bit BANK1:STATUS.Z 2 Zero bit BANK1:STATUS.DC 1 Digit carry/borrow bit BANK1:STATUS.C 0 Carry/borrow bit BANK1:FSR 0x0084 Indirect data memory address pointer BANK1:TRISA 0x0085 PORTA Data Direction Register BANK1:TRISA.TRISA5 5 PORTA Data Direction Register bit 5 BANK1:TRISA.TRISA4 4 PORTA Data Direction Register bit 4 BANK1:TRISA.TRISA3 3 PORTA Data Direction Register bit 3 BANK1:TRISA.TRISA2 2 PORTA Data Direction Register bit 2 BANK1:TRISA.TRISA1 1 PORTA Data Direction Register bit 1 BANK1:TRISA.TRISA0 0 PORTA Data Direction Register bit 0 BANK1:TRISB 0x0086 PORTB Data Direction Register BANK1:TRISB.TRISB7 7 PORTB Data Direction Register bit 7 BANK1:TRISB.TRISB6 6 PORTB Data Direction Register bit 6 BANK1:TRISB.TRISB5 5 PORTB Data Direction Register bit 5 BANK1:TRISB.TRISB4 4 PORTB Data Direction Register bit 4 BANK1:TRISB.TRISB3 3 PORTB Data Direction Register bit 3 BANK1:TRISB.TRISB2 2 PORTB Data Direction Register bit 2 BANK1:TRISB.TRISB1 1 PORTB Data Direction Register bit 1 BANK1:TRISB.TRISB0 0 PORTB Data Direction Register bit 0 BANK1:TRISC 0x0087 PORTC Data Direction Register BANK1:TRISC.TRISC7 7 PORTC Data Direction Register bit 7 BANK1:TRISC.TRISC6 6 PORTC Data Direction Register bit 6 BANK1:TRISC.TRISC5 5 PORTC Data Direction Register bit 5 BANK1:TRISC.TRISC4 4 PORTC Data Direction Register bit 4 BANK1:TRISC.TRISC3 3 PORTC Data Direction Register bit 3 BANK1:TRISC.TRISC2 2 PORTC Data Direction Register bit 2 BANK1:TRISC.TRISC1 1 PORTC Data Direction Register bit 1 BANK1:TRISC.TRISC0 0 PORTC Data Direction Register bit 0 BANK1:RESERVED0088 0x0088 RESERVED BANK1:RESERVED0089 0x0089 RESERVED BANK1:PCLATH 0x008A Write Buffer for the upper 5 bits of the Program Counter BANK1:INTCON 0x008B INTCON REGISTER BANK1:INTCON.GIE 7 Global Interrupt Enable bit BANK1:INTCON.PEIE 6 Peripheral Interrupt Enable bit BANK1:INTCON.T0IE 5 TMR0 Overflow Interrupt Enable bit BANK1:INTCON.INTE 4 RB0/INT External Interrupt Enable bit BANK1:INTCON.RBIE 3 RB Port Change Interrupt Enable bit BANK1:INTCON.T0IF 2 TMR0 Overflow Interrupt Flag bit BANK1:INTCON.INTF 1 RB0/INT External Interrupt Flag bit BANK1:INTCON.RBIF 0 RB Port Change Interrupt Flag bit BANK1:PIE1 0x008C PIE1 REGISTER BANK1:PIE1.SSPIE 3 Synchronous Serial Port Interrupt Enable bit BANK1:PIE1.CCP1IE 2 CCP1 Interrupt Enable bit BANK1:PIE1.TMR2IE 1 TMR2 to PR2 Match Interrupt Enable bit BANK1:PIE1.TMR1IE 0 TMR1 Overflow Interrupt Enable bit BANK1:RESERVED008D 0x008D RESERVED BANK1:PCON 0x008E PCON REGISTER BANK1:PCON.POR 1 Power-on Reset Status bit BANK1:PCON.BOR 0 Brown-out Reset Status bit BANK1:RESERVED008F 0x008F RESERVED BANK1:RESERVED0090 0x0090 RESERVED BANK1:RESERVED0091 0x0091 RESERVED BANK1:PR2 0x0092 Timer2 Period Register BANK1:SSPADD 0x0093 Synchronous Serial Port (I2C mode) Address Register BANK1:SSPSTAT 0x0094 SYNC SERIAL PORT STATUS REGISTER BANK1:SSPSTAT.D_A 5 Data/Address bit (I2C mode only) BANK1:SSPSTAT.P 4 Stop bit (I2C mode only) BANK1:SSPSTAT.S 3 Start bit (I2C mode only) BANK1:SSPSTAT.R_W 2 Read/Write bit information (I2C mode only) BANK1:SSPSTAT.UA 1 Update Address (I2C mode only) BANK1:SSPSTAT.BF 0 Buffer Full Status bit BANK1:RESERVED0095 0x0095 RESERVED BANK1:RESERVED0096 0x0096 RESERVED BANK1:RESERVED0097 0x0097 RESERVED BANK1:RESERVED0098 0x0098 RESERVED BANK1:RESERVED0099 0x0099 RESERVED BANK1:RESERVED009A 0x009A RESERVED BANK1:RESERVED009B 0x009B RESERVED BANK1:RESERVED009C 0x009C RESERVED BANK1:RESERVED009D 0x009D RESERVED BANK1:RESERVED009E 0x009E RESERVED BANK1:RESERVED009F 0x009F RESERVED .16CR63 ; http://www.microchip.com/download/lit/pline/picmicro/families/16c6x/30234d.pdf ; PIC16C6x.pdf ; MEMORY MAP ; BANK_0 area DATA FSR_ 0x0000:0x0020 area DATA Gen_Purp 0x0020:0x0080 General Purpose Register area DATA MEM_Program0 0x0080:0x0800 On-chip Program Memory (Page 0) area DATA MEM_Program1 0x0800:0x1000 On-chip Program Memory (Page 1) ; BANK_1 area DATA FSR_ 0x0080:0x00A0 area DATA Gen_Purp 0x00A0:0x0100 General Purpose Register area DATA MEM_Program0 0x0100:0x0800 On-chip Program Memory (Page 0) area DATA MEM_Program1 0x0800:0x1000 On-chip Program Memory (Page 1) ; Interrupt and reset vector assignments interrupt RESET 0x0000 RESET ; INPUT/OUTPUT PORTS ; BANK0 (0x0000:0x0080) BANK0:INDF 0x0000 INDF (not a physical register) BANK0:TMR0 0x0001 Timer0 module's register BANK0:PCL 0x0002 Program Counter's (PC) Least Significant Byte BANK0:STATUS 0x0003 STATUS REGISTER BANK0:STATUS.RP0 5 Register Bank Select bit 0 BANK0:STATUS.TO 4 Time-out bit BANK0:STATUS.PD 3 Power-down bit BANK0:STATUS.Z 2 Zero bit BANK0:STATUS.DC 1 Digit carry/borrow bit BANK0:STATUS.C 0 Carry/borrow bit BANK0:FSR 0x0004 Indirect data memory address pointer BANK0:PORTA 0x0005 PORTA register BANK0:PORTA.RA5 5 PORTA bit 5 BANK0:PORTA.RA4 4 PORTA bit 4 BANK0:PORTA.RA3 3 PORTA bit 3 BANK0:PORTA.RA2 2 PORTA bit 2 BANK0:PORTA.RA1 1 PORTA bit 1 BANK0:PORTA.RA0 0 PORTA bit 0 BANK0:PORTB 0x0006 PORTB register BANK0:PORTB.RB7 7 PORTB bit 7 BANK0:PORTB.RB6 6 PORTB bit 6 BANK0:PORTB.RB5 5 PORTB bit 5 BANK0:PORTB.RB4 4 PORTB bit 4 BANK0:PORTB.RB3 3 PORTB bit 3 BANK0:PORTB.RB2 2 PORTB bit 2 BANK0:PORTB.RB1 1 PORTB bit 1 BANK0:PORTB.RB0 0 PORTB bit 0 BANK0:PORTC 0x0007 PORTC register BANK0:PORTC.RC7 7 PORTC bit 7 BANK0:PORTC.RC6 6 PORTC bit 6 BANK0:PORTC.RC5 5 PORTC bit 5 BANK0:PORTC.RC4 4 PORTC bit 4 BANK0:PORTC.RC3 3 PORTC bit 3 BANK0:PORTC.RC2 2 PORTC bit 2 BANK0:PORTC.RC1 1 PORTC bit 1 BANK0:PORTC.RC0 0 PORTC bit 0 BANK0:RESERVED0008 0x0008 RESERVED BANK0:RESERVED0009 0x0009 RESERVED BANK0:PCLATH 0x000A Write Buffer for the upper 5 bits of the Program Counter BANK0:INTCON 0x000B INTCON REGISTER BANK0:INTCON.GIE 7 Global Interrupt Enable bit BANK0:INTCON.PEIE 6 Peripheral Interrupt Enable bit BANK0:INTCON.T0IE 5 TMR0 Overflow Interrupt Enable bit BANK0:INTCON.INTE 4 RB0/INT External Interrupt Enable bit BANK0:INTCON.RBIE 3 RB Port Change Interrupt Enable bit BANK0:INTCON.T0IF 2 TMR0 Overflow Interrupt Flag bit BANK0:INTCON.INTF 1 RB0/INT External Interrupt Flag bit BANK0:INTCON.RBIF 0 RB Port Change Interrupt Flag bit BANK0:PIR1 0x000C PIR1 REGISTER BANK0:PIR1.RCIF 5 USART Receive Interrupt Flag bit BANK0:PIR1.TXIF 4 USART Transmit Interrupt Flag bit BANK0:PIR1.SSPIF 3 Synchronous Serial Port Interrupt Flag bit BANK0:PIR1.CCP1IF 2 CCP1 Interrupt Flag bit BANK0:PIR1.TMR2IF 1 TMR2 to PR2 Match Interrupt Flag bit BANK0:PIR1.TMR1IF 0 TMR1 Overflow Interrupt Flag bit BANK0:PIR2 0x000D PIR2 REGISTER BANK0:PIR2.CCP2IF 0 CCP2 Interrupt Flag bit BANK0:TMR1L 0x000E Holding register for the Least Significant Byte of the 16-bit TMR1 register BANK0:TMR1H 0x000F Holding register for the Most Significant Byte of the 16-bit TMR1 register BANK0:T1CON 0x0010 TIMER1 CONTROL REGISTER BANK0:T1CON.T1CKPS1 5 Timer1 Input Clock Prescale Select bit 1 BANK0:T1CON.T1CKPS0 4 Timer1 Input Clock Prescale Select bit 0 BANK0:T1CON.T1OSCEN 3 Timer1 Oscillator Enable Control bit BANK0:T1CON.T1SYNC 2 Timer1 External Clock Input Synchronization Control bit BANK0:T1CON.TMR1CS 1 Timer1 Clock Source Select bit BANK0:T1CON.TMR1ON 0 Timer1 On bit BANK0:TMR2 0x0011 Timer2 module's register BANK0:T2CON 0x0012 TIMER2 CONTROL REGISTER BANK0:T2CON.TOUTPS3 6 Timer2 Output Postscale Select bit 3 BANK0:T2CON.TOUTPS2 5 Timer2 Output Postscale Select bit 2 BANK0:T2CON.TOUTPS1 4 Timer2 Output Postscale Select bit 1 BANK0:T2CON.TOUTPS0 3 Timer2 Output Postscale Select bit 0 BANK0:T2CON.TMR2ON 2 Timer2 On bit BANK0:T2CON.T2CKPS1 1 Timer2 Clock Prescale Select bit 1 BANK0:T2CON.T2CKPS0 0 Timer2 Clock Prescale Select bit 0 BANK0:SSPBUF 0x0013 Synchronous Serial Port Receive Buffer/Transmit Register BANK0:SSPCON 0x0014 SYNC SERIAL PORT CONTROL REGISTER BANK0:SSPCON.WCOL 7 Write Collision Detect bit BANK0:SSPCON.SSPOV 6 Receive Overflow Indicator bit BANK0:SSPCON.SSPEN 5 Synchronous Serial Port Enable bit BANK0:SSPCON.CKP 4 Clock Polarity Select bit BANK0:SSPCON.SSPM3 3 Synchronous Serial Port Mode Select bit 3 BANK0:SSPCON.SSPM2 2 Synchronous Serial Port Mode Select bit 2 BANK0:SSPCON.SSPM1 1 Synchronous Serial Port Mode Select bit 1 BANK0:SSPCON.SSPM0 0 Synchronous Serial Port Mode Select bit 0 BANK0:CCPR1L 0x0015 Capture/Compare/PWM1 (LSB) BANK0:CCPR1H 0x0016 Capture/Compare/PWM1 (MSB) BANK0:CCP1CON 0x0017 CCP1CON REGISTER BANK0:CCP1CON.CCP1X 5 PWM Least Significant bit BANK0:CCP1CON.CCP1Y 4 PWM Least Significant bit BANK0:CCP1CON.CCP1M3 3 CCP1 Mode Select bit 3 BANK0:CCP1CON.CCP1M2 2 CCP1 Mode Select bit 2 BANK0:CCP1CON.CCP1M1 1 CCP1 Mode Select bit 1 BANK0:CCP1CON.CCP1M0 0 CCP1 Mode Select bit 0 BANK0:RCSTA 0x0018 RECEIVE STATUS AND CONTROL REGISTER BANK0:RCSTA.SPEN 7 Serial Port Enable bit BANK0:RCSTA.RX9 6 9-bit Receive Enable bit BANK0:RCSTA.SREN 5 Single Receive Enable bit BANK0:RCSTA.CREN 4 Continuous Receive Enable bit BANK0:RCSTA.FERR 2 Framing Error bit BANK0:RCSTA.OERR 1 Overrun Error bit BANK0:RCSTA.RX9D 0 9th bit of received data BANK0:TXREG 0x0019 USART Transmit Data Register BANK0:RCREG 0x001A USART Receive Data Register BANK0:CCPR2L 0x001B Capture/Compare/PWM2 (LSB) BANK0:CCPR2H 0x001C Capture/Compare/PWM2 (MSB) BANK0:CCP2CON 0x001D CCP2CON REGISTER BANK0:CCP2CON.CCP2X 5 PWM Least Significant bit BANK0:CCP2CON.CCP2Y 4 PWM Least Significant bit BANK0:CCP2CON.CCP2M3 3 CCP2 Mode Select bit 3 BANK0:CCP2CON.CCP2M2 2 CCP2 Mode Select bit 2 BANK0:CCP2CON.CCP2M1 1 CCP2 Mode Select bit 1 BANK0:CCP2CON.CCP2M0 0 CCP2 Mode Select bit 0 BANK0:RESERVED001E 0x001E RESERVED BANK0:RESERVED001F 0x001F RESERVED ; BANK1 (0x0080:0x0100) BANK1:INDF 0x0080 INDF (not a physical register) BANK1:OPTION 0x0081 OPTION REGISTER BANK1:OPTION.RBPU 7 PORTB Pull-up Enable bit BANK1:OPTION.INTEDG 6 Interrupt Edge Select bit BANK1:OPTION.T0CS 5 TMR0 Clock Source Select bit BANK1:OPTION.T0SE 4 TMR0 Source Edge Select bit BANK1:OPTION.PSA 3 Prescaler Assignment bit BANK1:OPTION.PS2 2 Prescaler Rate Select bit 2 BANK1:OPTION.PS1 1 Prescaler Rate Select bit 1 BANK1:OPTION.PS0 0 Prescaler Rate Select bit 0 BANK1:PCL 0x0082 Program Counter's (PC) Least Significant Byte BANK1:STATUS 0x0083 STATUS REGISTER BANK1:STATUS.RP0 5 Register Bank Select bit 0 BANK1:STATUS.TO 4 Time-out bit BANK1:STATUS.PD 3 Power-down bit BANK1:STATUS.Z 2 Zero bit BANK1:STATUS.DC 1 Digit carry/borrow bit BANK1:STATUS.C 0 Carry/borrow bit BANK1:FSR 0x0084 Indirect data memory address pointer BANK1:TRISA 0x0085 PORTA Data Direction Register BANK1:TRISA.TRISA5 5 PORTA Data Direction Register bit 5 BANK1:TRISA.TRISA4 4 PORTA Data Direction Register bit 4 BANK1:TRISA.TRISA3 3 PORTA Data Direction Register bit 3 BANK1:TRISA.TRISA2 2 PORTA Data Direction Register bit 2 BANK1:TRISA.TRISA1 1 PORTA Data Direction Register bit 1 BANK1:TRISA.TRISA0 0 PORTA Data Direction Register bit 0 BANK1:TRISB 0x0086 PORTB Data Direction Register BANK1:TRISB.TRISB7 7 PORTB Data Direction Register bit 7 BANK1:TRISB.TRISB6 6 PORTB Data Direction Register bit 6 BANK1:TRISB.TRISB5 5 PORTB Data Direction Register bit 5 BANK1:TRISB.TRISB4 4 PORTB Data Direction Register bit 4 BANK1:TRISB.TRISB3 3 PORTB Data Direction Register bit 3 BANK1:TRISB.TRISB2 2 PORTB Data Direction Register bit 2 BANK1:TRISB.TRISB1 1 PORTB Data Direction Register bit 1 BANK1:TRISB.TRISB0 0 PORTB Data Direction Register bit 0 BANK1:TRISC 0x0087 PORTC Data Direction Register BANK1:TRISC.TRISC7 7 PORTC Data Direction Register bit 7 BANK1:TRISC.TRISC6 6 PORTC Data Direction Register bit 6 BANK1:TRISC.TRISC5 5 PORTC Data Direction Register bit 5 BANK1:TRISC.TRISC4 4 PORTC Data Direction Register bit 4 BANK1:TRISC.TRISC3 3 PORTC Data Direction Register bit 3 BANK1:TRISC.TRISC2 2 PORTC Data Direction Register bit 2 BANK1:TRISC.TRISC1 1 PORTC Data Direction Register bit 1 BANK1:TRISC.TRISC0 0 PORTC Data Direction Register bit 0 BANK1:RESERVED0088 0x0088 RESERVED BANK1:RESERVED0089 0x0089 RESERVED BANK1:PCLATH 0x008A Write Buffer for the upper 5 bits of the Program Counter BANK1:INTCON 0x008B INTCON REGISTER BANK1:INTCON.GIE 7 Global Interrupt Enable bit BANK1:INTCON.PEIE 6 Peripheral Interrupt Enable bit BANK1:INTCON.T0IE 5 TMR0 Overflow Interrupt Enable bit BANK1:INTCON.INTE 4 RB0/INT External Interrupt Enable bit BANK1:INTCON.RBIE 3 RB Port Change Interrupt Enable bit BANK1:INTCON.T0IF 2 TMR0 Overflow Interrupt Flag bit BANK1:INTCON.INTF 1 RB0/INT External Interrupt Flag bit BANK1:INTCON.RBIF 0 RB Port Change Interrupt Flag bit BANK1:PIE1 0x008C PIE1 REGISTER BANK1:PIE1.RCIE 5 USART Receive Interrupt Enable bit BANK1:PIE1.TXIE 4 USART Transmit Interrupt Enable bit BANK1:PIE1.SSPIE 3 Synchronous Serial Port Interrupt Enable bit BANK1:PIE1.CCP1IE 2 CCP1 Interrupt Enable bit BANK1:PIE1.TMR2IE 1 TMR2 to PR2 Match Interrupt Enable bit BANK1:PIE1.TMR1IE 0 TMR1 Overflow Interrupt Enable bit BANK1:PIE2 0x008D PIE2 REGISTER BANK1:PIE2.CCP2IE 0 CCP2 Interrupt Enable bit BANK1:PCON 0x008E PCON REGISTER BANK1:PCON.POR 1 Power-on Reset Status bit BANK1:PCON.BOR 0 Brown-out Reset Status bit BANK1:RESERVED008F 0x008F RESERVED BANK1:RESERVED0090 0x0090 RESERVED BANK1:RESERVED0091 0x0091 RESERVED BANK1:PR2 0x0092 Timer2 Period Register BANK1:SSPADD 0x0093 Synchronous Serial Port (I2C mode) Address Register BANK1:SSPSTAT 0x0094 SYNC SERIAL PORT STATUS REGISTER BANK1:SSPSTAT.D_A 5 Data/Address bit (I2C mode only) BANK1:SSPSTAT.P 4 Stop bit (I2C mode only) BANK1:SSPSTAT.S 3 Start bit (I2C mode only) BANK1:SSPSTAT.R_W 2 Read/Write bit information (I2C mode only) BANK1:SSPSTAT.UA 1 Update Address (I2C mode only) BANK1:SSPSTAT.BF 0 Buffer Full Status bit BANK1:RESERVED0095 0x0095 RESERVED BANK1:RESERVED0096 0x0096 RESERVED BANK1:RESERVED0097 0x0097 RESERVED BANK1:TXSTA 0x0098 TRANSMIT STATUS AND CONTROL REGISTER BANK1:TXSTA.CSRC 7 Clock Source Select bit BANK1:TXSTA.TX9 6 9-bit Transmit Enable bit BANK1:TXSTA.TXEN 5 Transmit Enable bit BANK1:TXSTA.SYNC 4 USART Mode Select bit BANK1:TXSTA.BRGH 2 High Baud Rate Select bit BANK1:TXSTA.TRMT 1 Transmit Shift Register Status bit BANK1:TXSTA.TX9D 0 9th bit of transmit data BANK1:SPBRG 0x0099 Baud Rate Generator Register BANK1:RESERVED009A 0x009A RESERVED BANK1:RESERVED009B 0x009B RESERVED BANK1:RESERVED009C 0x009C RESERVED BANK1:RESERVED009D 0x009D RESERVED BANK1:RESERVED009E 0x009E RESERVED BANK1:RESERVED009F 0x009F RESERVED .16CR64 ; http://www.microchip.com/download/lit/pline/picmicro/families/16c6x/30234d.pdf ; PIC16C6x.pdf ; MEMORY MAP ; BANK_0 area DATA FSR_ 0x0000:0x0020 area DATA Gen_Purp 0x0020:0x0080 General Purpose Register area DATA MEM_Program 0x0080:0x0800 On-chip Program Memory ; BANK_1 area DATA FSR_ 0x0080:0x00A0 area DATA Gen_Purp 0x00A0:0x00C0 General Purpose Register area BSS RESERVED 0x00C0:0x0100 area DATA MEM_Program 0x0100:0x0800 On-chip Program Memory ; Interrupt and reset vector assignments interrupt RESET 0x0000 RESET ; INPUT/OUTPUT PORTS ; BANK0 (0x0000:0x0080) BANK0:INDF 0x0000 INDF (not a physical register) BANK0:TMR0 0x0001 Timer0 module's register BANK0:PCL 0x0002 Program Counter's (PC) Least Significant Byte BANK0:STATUS 0x0003 STATUS REGISTER BANK0:STATUS.RP0 5 Register Bank Select bit 0 BANK0:STATUS.TO 4 Time-out bit BANK0:STATUS.PD 3 Power-down bit BANK0:STATUS.Z 2 Zero bit BANK0:STATUS.DC 1 Digit carry/borrow bit BANK0:STATUS.C 0 Carry/borrow bit BANK0:FSR 0x0004 Indirect data memory address pointer BANK0:PORTA 0x0005 PORTA register BANK0:PORTA.RA5 5 PORTA bit 5 BANK0:PORTA.RA4 4 PORTA bit 4 BANK0:PORTA.RA3 3 PORTA bit 3 BANK0:PORTA.RA2 2 PORTA bit 2 BANK0:PORTA.RA1 1 PORTA bit 1 BANK0:PORTA.RA0 0 PORTA bit 0 BANK0:PORTB 0x0006 PORTB register BANK0:PORTB.RB7 7 PORTB bit 7 BANK0:PORTB.RB6 6 PORTB bit 6 BANK0:PORTB.RB5 5 PORTB bit 5 BANK0:PORTB.RB4 4 PORTB bit 4 BANK0:PORTB.RB3 3 PORTB bit 3 BANK0:PORTB.RB2 2 PORTB bit 2 BANK0:PORTB.RB1 1 PORTB bit 1 BANK0:PORTB.RB0 0 PORTB bit 0 BANK0:PORTC 0x0007 PORTC register BANK0:PORTC.RC7 7 PORTC bit 7 BANK0:PORTC.RC6 6 PORTC bit 6 BANK0:PORTC.RC5 5 PORTC bit 5 BANK0:PORTC.RC4 4 PORTC bit 4 BANK0:PORTC.RC3 3 PORTC bit 3 BANK0:PORTC.RC2 2 PORTC bit 2 BANK0:PORTC.RC1 1 PORTC bit 1 BANK0:PORTC.RC0 0 PORTC bit 0 BANK0:PORTD 0x0008 PORTD register BANK0:PORTD.RD7 7 PORTD bit 7 BANK0:PORTD.RD6 6 PORTD bit 6 BANK0:PORTD.RD5 5 PORTD bit 5 BANK0:PORTD.RD4 4 PORTD bit 4 BANK0:PORTD.RD3 3 PORTD bit 3 BANK0:PORTD.RD2 2 PORTD bit 2 BANK0:PORTD.RD1 1 PORTD bit 1 BANK0:PORTD.RD0 0 PORTD bit 0 BANK0:PORTE 0x0009 PORTE register BANK0:PORTE.RE2 2 PORTE bit 2 BANK0:PORTE.RE1 1 PORTE bit 1 BANK0:PORTE.RE0 0 PORTE bit 0 BANK0:PCLATH 0x000A Write Buffer for the upper 5 bits of the Program Counter BANK0:INTCON 0x000B INTCON REGISTER BANK0:INTCON.GIE 7 Global Interrupt Enable bit BANK0:INTCON.PEIE 6 Peripheral Interrupt Enable bit BANK0:INTCON.T0IE 5 TMR0 Overflow Interrupt Enable bit BANK0:INTCON.INTE 4 RB0/INT External Interrupt Enable bit BANK0:INTCON.RBIE 3 RB Port Change Interrupt Enable bit BANK0:INTCON.T0IF 2 TMR0 Overflow Interrupt Flag bit BANK0:INTCON.INTF 1 RB0/INT External Interrupt Flag bit BANK0:INTCON.RBIF 0 RB Port Change Interrupt Flag bit BANK0:PIR1 0x000C PIR1 REGISTER BANK0:PIR1.PSPIF 7 Parallel Slave Port Interrupt Flag bit BANK0:PIR1.SSPIF 3 Synchronous Serial Port Interrupt Flag bit BANK0:PIR1.CCP1IF 2 CCP1 Interrupt Flag bit BANK0:PIR1.TMR2IF 1 TMR2 to PR2 Match Interrupt Flag bit BANK0:PIR1.TMR1IF 0 TMR1 Overflow Interrupt Flag bit BANK0:RESERVED000D 0x000D RESERVED BANK0:TMR1L 0x000E Holding register for the Least Significant Byte of the 16-bit TMR1 register BANK0:TMR1H 0x000F Holding register for the Most Significant Byte of the 16-bit TMR1 register BANK0:T1CON 0x0010 TIMER1 CONTROL REGISTER BANK0:T1CON.T1CKPS1 5 Timer1 Input Clock Prescale Select bit 1 BANK0:T1CON.T1CKPS0 4 Timer1 Input Clock Prescale Select bit 0 BANK0:T1CON.T1OSCEN 3 Timer1 Oscillator Enable Control bit BANK0:T1CON.T1SYNC 2 Timer1 External Clock Input Synchronization Control bit BANK0:T1CON.TMR1CS 1 Timer1 Clock Source Select bit BANK0:T1CON.TMR1ON 0 Timer1 On bit BANK0:TMR2 0x0011 Timer2 module's register BANK0:T2CON 0x0012 TIMER2 CONTROL REGISTER BANK0:T2CON.TOUTPS3 6 Timer2 Output Postscale Select bit 3 BANK0:T2CON.TOUTPS2 5 Timer2 Output Postscale Select bit 2 BANK0:T2CON.TOUTPS1 4 Timer2 Output Postscale Select bit 1 BANK0:T2CON.TOUTPS0 3 Timer2 Output Postscale Select bit 0 BANK0:T2CON.TMR2ON 2 Timer2 On bit BANK0:T2CON.T2CKPS1 1 Timer2 Clock Prescale Select bit 1 BANK0:T2CON.T2CKPS0 0 Timer2 Clock Prescale Select bit 0 BANK0:SSPBUF 0x0013 Synchronous Serial Port Receive Buffer/Transmit Register BANK0:SSPCON 0x0014 SYNC SERIAL PORT CONTROL REGISTER BANK0:SSPCON.WCOL 7 Write Collision Detect bit BANK0:SSPCON.SSPOV 6 Receive Overflow Indicator bit BANK0:SSPCON.SSPEN 5 Synchronous Serial Port Enable bit BANK0:SSPCON.CKP 4 Clock Polarity Select bit BANK0:SSPCON.SSPM3 3 Synchronous Serial Port Mode Select bit 3 BANK0:SSPCON.SSPM2 2 Synchronous Serial Port Mode Select bit 2 BANK0:SSPCON.SSPM1 1 Synchronous Serial Port Mode Select bit 1 BANK0:SSPCON.SSPM0 0 Synchronous Serial Port Mode Select bit 0 BANK0:CCPR1L 0x0015 Capture/Compare/PWM1 (LSB) BANK0:CCPR1H 0x0016 Capture/Compare/PWM1 (MSB) BANK0:CCP1CON 0x0017 CCP1CON REGISTER BANK0:CCP1CON.CCP1X 5 PWM Least Significant bit BANK0:CCP1CON.CCP1Y 4 PWM Least Significant bit BANK0:CCP1CON.CCP1M3 3 CCP1 Mode Select bit 3 BANK0:CCP1CON.CCP1M2 2 CCP1 Mode Select bit 2 BANK0:CCP1CON.CCP1M1 1 CCP1 Mode Select bit 1 BANK0:CCP1CON.CCP1M0 0 CCP1 Mode Select bit 0 ; BANK1 (0x0080:0x0100) BANK1:INDF 0x0080 INDF (not a physical register) BANK1:OPTION 0x0081 OPTION REGISTER BANK1:OPTION.RBPU 7 PORTB Pull-up Enable bit BANK1:OPTION.INTEDG 6 Interrupt Edge Select bit BANK1:OPTION.T0CS 5 TMR0 Clock Source Select bit BANK1:OPTION.T0SE 4 TMR0 Source Edge Select bit BANK1:OPTION.PSA 3 Prescaler Assignment bit BANK1:OPTION.PS2 2 Prescaler Rate Select bit 2 BANK1:OPTION.PS1 1 Prescaler Rate Select bit 1 BANK1:OPTION.PS0 0 Prescaler Rate Select bit 0 BANK1:PCL 0x0082 Program Counter's (PC) Least Significant Byte BANK1:STATUS 0x0083 STATUS REGISTER BANK1:STATUS.RP0 5 Register Bank Select bit 0 BANK1:STATUS.TO 4 Time-out bit BANK1:STATUS.PD 3 Power-down bit BANK1:STATUS.Z 2 Zero bit BANK1:STATUS.DC 1 Digit carry/borrow bit BANK1:STATUS.C 0 Carry/borrow bit BANK1:FSR 0x0084 Indirect data memory address pointer BANK1:TRISA 0x0085 PORTA Data Direction Register BANK1:TRISA.TRISA5 5 PORTA Data Direction Register bit 5 BANK1:TRISA.TRISA4 4 PORTA Data Direction Register bit 4 BANK1:TRISA.TRISA3 3 PORTA Data Direction Register bit 3 BANK1:TRISA.TRISA2 2 PORTA Data Direction Register bit 2 BANK1:TRISA.TRISA1 1 PORTA Data Direction Register bit 1 BANK1:TRISA.TRISA0 0 PORTA Data Direction Register bit 0 BANK1:TRISB 0x0086 PORTB Data Direction Register BANK1:TRISB.TRISB7 7 PORTB Data Direction Register bit 7 BANK1:TRISB.TRISB6 6 PORTB Data Direction Register bit 6 BANK1:TRISB.TRISB5 5 PORTB Data Direction Register bit 5 BANK1:TRISB.TRISB4 4 PORTB Data Direction Register bit 4 BANK1:TRISB.TRISB3 3 PORTB Data Direction Register bit 3 BANK1:TRISB.TRISB2 2 PORTB Data Direction Register bit 2 BANK1:TRISB.TRISB1 1 PORTB Data Direction Register bit 1 BANK1:TRISB.TRISB0 0 PORTB Data Direction Register bit 0 BANK1:TRISC 0x0087 PORTC Data Direction Register BANK1:TRISC.TRISC7 7 PORTC Data Direction Register bit 7 BANK1:TRISC.TRISC6 6 PORTC Data Direction Register bit 6 BANK1:TRISC.TRISC5 5 PORTC Data Direction Register bit 5 BANK1:TRISC.TRISC4 4 PORTC Data Direction Register bit 4 BANK1:TRISC.TRISC3 3 PORTC Data Direction Register bit 3 BANK1:TRISC.TRISC2 2 PORTC Data Direction Register bit 2 BANK1:TRISC.TRISC1 1 PORTC Data Direction Register bit 1 BANK1:TRISC.TRISC0 0 PORTC Data Direction Register bit 0 BANK1:TRISD 0x0088 PORTD Data Direction Register BANK1:TRISD.TRISD7 7 PORTD Data Direction Register bit 7 BANK1:TRISD.TRISD6 6 PORTD Data Direction Register bit 6 BANK1:TRISD.TRISD5 5 PORTD Data Direction Register bit 5 BANK1:TRISD.TRISD4 4 PORTD Data Direction Register bit 4 BANK1:TRISD.TRISD3 3 PORTD Data Direction Register bit 3 BANK1:TRISD.TRISD2 2 PORTD Data Direction Register bit 2 BANK1:TRISD.TRISD1 1 PORTD Data Direction Register bit 1 BANK1:TRISD.TRISD0 0 PORTD Data Direction Register bit 0 BANK1:TRISE 0x0089 PORTE Data Direction Register BANK1:TRISE.IBF 7 Input Buffer Full Status bit BANK1:TRISE.OBF 6 Output Buffer Full Status bit BANK1:TRISE.IBOV 5 Input Buffer Overflow Detect bit BANK1:TRISE.PSPMODE 4 Parallel Slave Port Mode Select bit BANK1:TRISE.TRISE2 2 Direction Control bit for pin RE2/CS BANK1:TRISE.TRISE1 1 Direction Control bit for pin RE1/WR BANK1:TRISE.TRISE0 0 Direction Control bit for pin RE0/RD BANK1:PCLATH 0x008A Write Buffer for the upper 5 bits of the Program Counter BANK1:INTCON 0x008B INTCON REGISTER BANK1:INTCON.GIE 7 Global Interrupt Enable bit BANK1:INTCON.PEIE 6 Peripheral Interrupt Enable bit BANK1:INTCON.T0IE 5 TMR0 Overflow Interrupt Enable bit BANK1:INTCON.INTE 4 RB0/INT External Interrupt Enable bit BANK1:INTCON.RBIE 3 RB Port Change Interrupt Enable bit BANK1:INTCON.T0IF 2 TMR0 Overflow Interrupt Flag bit BANK1:INTCON.INTF 1 RB0/INT External Interrupt Flag bit BANK1:INTCON.RBIF 0 RB Port Change Interrupt Flag bit BANK1:PIE1 0x008C PIE1 REGISTER BANK1:PIE1.SSPIE 3 Synchronous Serial Port Interrupt Enable bit BANK1:PIE1.CCP1IE 2 CCP1 Interrupt Enable bit BANK1:PIE1.TMR2IE 1 TMR2 to PR2 Match Interrupt Enable bit BANK1:PIE1.TMR1IE 0 TMR1 Overflow Interrupt Enable bit BANK1:RESERVED008D 0x008D RESERVED BANK1:PCON 0x008E PCON REGISTER BANK1:PCON.POR 1 Power-on Reset Status bit BANK1:RESERVED008F 0x008F RESERVED BANK1:RESERVED0090 0x0090 RESERVED BANK1:RESERVED0091 0x0091 RESERVED BANK1:PR2 0x0092 Timer2 Period Register BANK1:SSPADD 0x0093 Synchronous Serial Port (I2C mode) Address Register BANK1:SSPSTAT 0x0094 SYNC SERIAL PORT STATUS REGISTER BANK1:SSPSTAT.D_A 5 Data/Address bit (I2C mode only) BANK1:SSPSTAT.P 4 Stop bit (I2C mode only) BANK1:SSPSTAT.S 3 Start bit (I2C mode only) BANK1:SSPSTAT.R_W 2 Read/Write bit information (I2C mode only) BANK1:SSPSTAT.UA 1 Update Address (I2C mode only) BANK1:SSPSTAT.BF 0 Buffer Full Status bit BANK1:RESERVED0095 0x0095 RESERVED BANK1:RESERVED0096 0x0096 RESERVED BANK1:RESERVED0097 0x0097 RESERVED BANK1:RESERVED0098 0x0098 RESERVED BANK1:RESERVED0099 0x0099 RESERVED BANK1:RESERVED009A 0x009A RESERVED BANK1:RESERVED009B 0x009B RESERVED BANK1:RESERVED009C 0x009C RESERVED BANK1:RESERVED009D 0x009D RESERVED BANK1:RESERVED009E 0x009E RESERVED BANK1:RESERVED009F 0x009F RESERVED .16CR65 ; http://www.microchip.com/download/lit/pline/picmicro/families/16c6x/30234d.pdf ; PIC16C6x.pdf ; MEMORY MAP ; BANK_0 area DATA FSR_ 0x0000:0x0020 area DATA Gen_Purp 0x0020:0x0080 General Purpose Register area DATA MEM_Program0 0x0080:0x0800 On-chip Program Memory (Page 0) area DATA MEM_Program1 0x0800:0x1000 On-chip Program Memory (Page 1) ; BANK_1 area DATA FSR_ 0x0080:0x00A0 area DATA Gen_Purp 0x00A0:0x0100 General Purpose Register area DATA MEM_Program0 0x0100:0x0800 On-chip Program Memory (Page 0) area DATA MEM_Program1 0x0800:0x1000 On-chip Program Memory (Page 1) ; Interrupt and reset vector assignments interrupt RESET 0x0000 RESET ; INPUT/OUTPUT PORTS ; BANK0 (0x0000:0x0080) BANK0:INDF 0x0000 INDF (not a physical register) BANK0:TMR0 0x0001 Timer0 module's register BANK0:PCL 0x0002 Program Counter's (PC) Least Significant Byte BANK0:STATUS 0x0003 STATUS REGISTER BANK0:STATUS.RP0 5 Register Bank Select bit 0 BANK0:STATUS.TO 4 Time-out bit BANK0:STATUS.PD 3 Power-down bit BANK0:STATUS.Z 2 Zero bit BANK0:STATUS.DC 1 Digit carry/borrow bit BANK0:STATUS.C 0 Carry/borrow bit BANK0:FSR 0x0004 Indirect data memory address pointer BANK0:PORTA 0x0005 PORTA register BANK0:PORTA.RA5 5 PORTA bit 5 BANK0:PORTA.RA4 4 PORTA bit 4 BANK0:PORTA.RA3 3 PORTA bit 3 BANK0:PORTA.RA2 2 PORTA bit 2 BANK0:PORTA.RA1 1 PORTA bit 1 BANK0:PORTA.RA0 0 PORTA bit 0 BANK0:PORTB 0x0006 PORTB register BANK0:PORTB.RB7 7 PORTB bit 7 BANK0:PORTB.RB6 6 PORTB bit 6 BANK0:PORTB.RB5 5 PORTB bit 5 BANK0:PORTB.RB4 4 PORTB bit 4 BANK0:PORTB.RB3 3 PORTB bit 3 BANK0:PORTB.RB2 2 PORTB bit 2 BANK0:PORTB.RB1 1 PORTB bit 1 BANK0:PORTB.RB0 0 PORTB bit 0 BANK0:PORTC 0x0007 PORTC register BANK0:PORTC.RC7 7 PORTC bit 7 BANK0:PORTC.RC6 6 PORTC bit 6 BANK0:PORTC.RC5 5 PORTC bit 5 BANK0:PORTC.RC4 4 PORTC bit 4 BANK0:PORTC.RC3 3 PORTC bit 3 BANK0:PORTC.RC2 2 PORTC bit 2 BANK0:PORTC.RC1 1 PORTC bit 1 BANK0:PORTC.RC0 0 PORTC bit 0 BANK0:PORTD 0x0008 PORTD register BANK0:PORTD.RD7 7 PORTD bit 7 BANK0:PORTD.RD6 6 PORTD bit 6 BANK0:PORTD.RD5 5 PORTD bit 5 BANK0:PORTD.RD4 4 PORTD bit 4 BANK0:PORTD.RD3 3 PORTD bit 3 BANK0:PORTD.RD2 2 PORTD bit 2 BANK0:PORTD.RD1 1 PORTD bit 1 BANK0:PORTD.RD0 0 PORTD bit 0 BANK0:PORTE 0x0009 PORTE register BANK0:PORTE.RE2 2 PORTE bit 2 BANK0:PORTE.RE1 1 PORTE bit 1 BANK0:PORTE.RE0 0 PORTE bit 0 BANK0:PCLATH 0x000A Write Buffer for the upper 5 bits of the Program Counter BANK0:INTCON 0x000B INTCON REGISTER BANK0:INTCON.GIE 7 Global Interrupt Enable bit BANK0:INTCON.PEIE 6 Peripheral Interrupt Enable bit BANK0:INTCON.T0IE 5 TMR0 Overflow Interrupt Enable bit BANK0:INTCON.INTE 4 RB0/INT External Interrupt Enable bit BANK0:INTCON.RBIE 3 RB Port Change Interrupt Enable bit BANK0:INTCON.T0IF 2 TMR0 Overflow Interrupt Flag bit BANK0:INTCON.INTF 1 RB0/INT External Interrupt Flag bit BANK0:INTCON.RBIF 0 RB Port Change Interrupt Flag bit BANK0:PIR1 0x000C PIR1 REGISTER BANK0:PIR1.PSPIF 7 Parallel Slave Port Interrupt Flag bit BANK0:PIR1.RCIF 5 USART Receive Interrupt Flag bit BANK0:PIR1.TXIF 4 USART Transmit Interrupt Flag bit BANK0:PIR1.SSPIF 3 Synchronous Serial Port Interrupt Flag bit BANK0:PIR1.CCP1IF 2 CCP1 Interrupt Flag bit BANK0:PIR1.TMR2IF 1 TMR2 to PR2 Match Interrupt Flag bit BANK0:PIR1.TMR1IF 0 TMR1 Overflow Interrupt Flag bit BANK0:PIR2 0x000D PIR2 REGISTER BANK0:PIR2.CCP2IF 0 CCP2 Interrupt Flag bit BANK0:TMR1L 0x000E Holding register for the Least Significant Byte of the 16-bit TMR1 register BANK0:TMR1H 0x000F Holding register for the Most Significant Byte of the 16-bit TMR1 register BANK0:T1CON 0x0010 TIMER1 CONTROL REGISTER BANK0:T1CON.T1CKPS1 5 Timer1 Input Clock Prescale Select bit 1 BANK0:T1CON.T1CKPS0 4 Timer1 Input Clock Prescale Select bit 0 BANK0:T1CON.T1OSCEN 3 Timer1 Oscillator Enable Control bit BANK0:T1CON.T1SYNC 2 Timer1 External Clock Input Synchronization Control bit BANK0:T1CON.TMR1CS 1 Timer1 Clock Source Select bit BANK0:T1CON.TMR1ON 0 Timer1 On bit BANK0:TMR2 0x0011 Timer2 module's register BANK0:T2CON 0x0012 TIMER2 CONTROL REGISTER BANK0:T2CON.TOUTPS3 6 Timer2 Output Postscale Select bit 3 BANK0:T2CON.TOUTPS2 5 Timer2 Output Postscale Select bit 2 BANK0:T2CON.TOUTPS1 4 Timer2 Output Postscale Select bit 1 BANK0:T2CON.TOUTPS0 3 Timer2 Output Postscale Select bit 0 BANK0:T2CON.TMR2ON 2 Timer2 On bit BANK0:T2CON.T2CKPS1 1 Timer2 Clock Prescale Select bit 1 BANK0:T2CON.T2CKPS0 0 Timer2 Clock Prescale Select bit 0 BANK0:SSPBUF 0x0013 Synchronous Serial Port Receive Buffer/Transmit Register BANK0:SSPCON 0x0014 SYNC SERIAL PORT CONTROL REGISTER BANK0:SSPCON.WCOL 7 Write Collision Detect bit BANK0:SSPCON.SSPOV 6 Receive Overflow Indicator bit BANK0:SSPCON.SSPEN 5 Synchronous Serial Port Enable bit BANK0:SSPCON.CKP 4 Clock Polarity Select bit BANK0:SSPCON.SSPM3 3 Synchronous Serial Port Mode Select bit 3 BANK0:SSPCON.SSPM2 2 Synchronous Serial Port Mode Select bit 2 BANK0:SSPCON.SSPM1 1 Synchronous Serial Port Mode Select bit 1 BANK0:SSPCON.SSPM0 0 Synchronous Serial Port Mode Select bit 0 BANK0:CCPR1L 0x0015 Capture/Compare/PWM1 (LSB) BANK0:CCPR1H 0x0016 Capture/Compare/PWM1 (MSB) BANK0:CCP1CON 0x0017 CCP1CON REGISTER BANK0:CCP1CON.CCP1X 5 PWM Least Significant bit BANK0:CCP1CON.CCP1Y 4 PWM Least Significant bit BANK0:CCP1CON.CCP1M3 3 CCP1 Mode Select bit 3 BANK0:CCP1CON.CCP1M2 2 CCP1 Mode Select bit 2 BANK0:CCP1CON.CCP1M1 1 CCP1 Mode Select bit 1 BANK0:CCP1CON.CCP1M0 0 CCP1 Mode Select bit 0 BANK0:RCSTA 0x0018 RECEIVE STATUS AND CONTROL REGISTER BANK0:RCSTA.SPEN 7 Serial Port Enable bit BANK0:RCSTA.RX9 6 9-bit Receive Enable bit BANK0:RCSTA.SREN 5 Single Receive Enable bit BANK0:RCSTA.CREN 4 Continuous Receive Enable bit BANK0:RCSTA.FERR 2 Framing Error bit BANK0:RCSTA.OERR 1 Overrun Error bit BANK0:RCSTA.RX9D 0 9th bit of received data BANK0:TXREG 0x0019 USART Transmit Data Register BANK0:RCREG 0x001A USART Receive Data Register BANK0:CCPR2L 0x001B Capture/Compare/PWM2 (LSB) BANK0:CCPR2H 0x001C Capture/Compare/PWM2 (MSB) BANK0:CCP2CON 0x001D CCP2CON REGISTER BANK0:CCP2CON.CCP2X 5 PWM Least Significant bit BANK0:CCP2CON.CCP2Y 4 PWM Least Significant bit BANK0:CCP2CON.CCP2M3 3 CCP2 Mode Select bit 3 BANK0:CCP2CON.CCP2M2 2 CCP2 Mode Select bit 2 BANK0:CCP2CON.CCP2M1 1 CCP2 Mode Select bit 1 BANK0:CCP2CON.CCP2M0 0 CCP2 Mode Select bit 0 BANK0:RESERVED001E 0x001E RESERVED BANK0:RESERVED001F 0x001F RESERVED ; BANK1 (0x0080:0x0100) BANK1:INDF 0x0080 INDF (not a physical register) BANK1:OPTION 0x0081 OPTION REGISTER BANK1:OPTION.RBPU 7 PORTB Pull-up Enable bit BANK1:OPTION.INTEDG 6 Interrupt Edge Select bit BANK1:OPTION.T0CS 5 TMR0 Clock Source Select bit BANK1:OPTION.T0SE 4 TMR0 Source Edge Select bit BANK1:OPTION.PSA 3 Prescaler Assignment bit BANK1:OPTION.PS2 2 Prescaler Rate Select bit 2 BANK1:OPTION.PS1 1 Prescaler Rate Select bit 1 BANK1:OPTION.PS0 0 Prescaler Rate Select bit 0 BANK1:PCL 0x0082 Program Counter's (PC) Least Significant Byte BANK1:STATUS 0x0083 STATUS REGISTER BANK1:STATUS.RP0 5 Register Bank Select bit 0 BANK1:STATUS.TO 4 Time-out bit BANK1:STATUS.PD 3 Power-down bit BANK1:STATUS.Z 2 Zero bit BANK1:STATUS.DC 1 Digit carry/borrow bit BANK1:STATUS.C 0 Carry/borrow bit BANK1:FSR 0x0084 Indirect data memory address pointer BANK1:TRISA 0x0085 PORTA Data Direction Register BANK1:TRISA.TRISA5 5 PORTA Data Direction Register bit 5 BANK1:TRISA.TRISA4 4 PORTA Data Direction Register bit 4 BANK1:TRISA.TRISA3 3 PORTA Data Direction Register bit 3 BANK1:TRISA.TRISA2 2 PORTA Data Direction Register bit 2 BANK1:TRISA.TRISA1 1 PORTA Data Direction Register bit 1 BANK1:TRISA.TRISA0 0 PORTA Data Direction Register bit 0 BANK1:TRISB 0x0086 PORTB Data Direction Register BANK1:TRISB.TRISB7 7 PORTB Data Direction Register bit 7 BANK1:TRISB.TRISB6 6 PORTB Data Direction Register bit 6 BANK1:TRISB.TRISB5 5 PORTB Data Direction Register bit 5 BANK1:TRISB.TRISB4 4 PORTB Data Direction Register bit 4 BANK1:TRISB.TRISB3 3 PORTB Data Direction Register bit 3 BANK1:TRISB.TRISB2 2 PORTB Data Direction Register bit 2 BANK1:TRISB.TRISB1 1 PORTB Data Direction Register bit 1 BANK1:TRISB.TRISB0 0 PORTB Data Direction Register bit 0 BANK1:TRISC 0x0087 PORTC Data Direction Register BANK1:TRISC.TRISC7 7 PORTC Data Direction Register bit 7 BANK1:TRISC.TRISC6 6 PORTC Data Direction Register bit 6 BANK1:TRISC.TRISC5 5 PORTC Data Direction Register bit 5 BANK1:TRISC.TRISC4 4 PORTC Data Direction Register bit 4 BANK1:TRISC.TRISC3 3 PORTC Data Direction Register bit 3 BANK1:TRISC.TRISC2 2 PORTC Data Direction Register bit 2 BANK1:TRISC.TRISC1 1 PORTC Data Direction Register bit 1 BANK1:TRISC.TRISC0 0 PORTC Data Direction Register bit 0 BANK1:TRISD 0x0088 PORTD Data Direction Register BANK1:TRISD.TRISD7 7 PORTD Data Direction Register bit 7 BANK1:TRISD.TRISD6 6 PORTD Data Direction Register bit 6 BANK1:TRISD.TRISD5 5 PORTD Data Direction Register bit 5 BANK1:TRISD.TRISD4 4 PORTD Data Direction Register bit 4 BANK1:TRISD.TRISD3 3 PORTD Data Direction Register bit 3 BANK1:TRISD.TRISD2 2 PORTD Data Direction Register bit 2 BANK1:TRISD.TRISD1 1 PORTD Data Direction Register bit 1 BANK1:TRISD.TRISD0 0 PORTD Data Direction Register bit 0 BANK1:TRISE 0x0089 PORTE Data Direction Bits BANK1:TRISE.IBF 7 Input Buffer Full Status bit BANK1:TRISE.OBF 6 Output Buffer Full Status bit BANK1:TRISE.IBOV 5 Input Buffer Overflow Detect bit BANK1:TRISE.PSPMODE 4 Parallel Slave Port Mode Select bit BANK1:TRISE.TRISE2 2 Direction Control bit for pin RE2/CS BANK1:TRISE.TRISE1 1 Direction Control bit for pin RE1/WR BANK1:TRISE.TRISE0 0 Direction Control bit for pin RE0/RD BANK1:PCLATH 0x008A Write Buffer for the upper 5 bits of the Program Counter BANK1:INTCON 0x008B INTCON REGISTER BANK1:INTCON.GIE 7 Global Interrupt Enable bit BANK1:INTCON.PEIE 6 Peripheral Interrupt Enable bit BANK1:INTCON.T0IE 5 TMR0 Overflow Interrupt Enable bit BANK1:INTCON.INTE 4 RB0/INT External Interrupt Enable bit BANK1:INTCON.RBIE 3 RB Port Change Interrupt Enable bit BANK1:INTCON.T0IF 2 TMR0 Overflow Interrupt Flag bit BANK1:INTCON.INTF 1 RB0/INT External Interrupt Flag bit BANK1:INTCON.RBIF 0 RB Port Change Interrupt Flag bit BANK1:PIE1 0x008C PIE1 REGISTER BANK1:PIE1.PSPIE 7 Parallel Slave Port Read/Write Interrupt Enable bit BANK1:PIE1.RCIE 5 USART Receive Interrupt Enable bit BANK1:PIE1.TXIE 4 USART Transmit Interrupt Enable bit BANK1:PIE1.SSPIE 3 Synchronous Serial Port Interrupt Enable bit BANK1:PIE1.CCP1IE 2 CCP1 Interrupt Enable bit BANK1:PIE1.TMR2IE 1 TMR2 to PR2 Match Interrupt Enable bit BANK1:PIE1.TMR1IE 0 TMR1 Overflow Interrupt Enable bit BANK1:PIE2 0x008D PIE2 REGISTER BANK1:PIE2.CCP2IE 0 CCP2 Interrupt Enable bit BANK1:PCON 0x008E PCON REGISTER BANK1:PCON.POR 1 Power-on Reset Status bit BANK1:PCON.BOR 0 Brown-out Reset Status bit BANK1:RESERVED008F 0x008F RESERVED BANK1:RESERVED0090 0x0090 RESERVED BANK1:RESERVED0091 0x0091 RESERVED BANK1:PR2 0x0092 Timer2 Period Register BANK1:SSPADD 0x0093 Synchronous Serial Port (I2C mode) Address Register BANK1:SSPSTAT 0x0094 SYNC SERIAL PORT STATUS REGISTER BANK1:SSPSTAT.D_A 5 Data/Address bit (I2C mode only) BANK1:SSPSTAT.P 4 Stop bit (I2C mode only) BANK1:SSPSTAT.S 3 Start bit (I2C mode only) BANK1:SSPSTAT.R_W 2 Read/Write bit information (I2C mode only) BANK1:SSPSTAT.UA 1 Update Address (I2C mode only) BANK1:SSPSTAT.BF 0 Buffer Full Status bit BANK1:RESERVED0095 0x0095 RESERVED BANK1:RESERVED0096 0x0096 RESERVED BANK1:RESERVED0097 0x0097 RESERVED BANK1:TXSTA 0x0098 TRANSMIT STATUS AND CONTROL REGISTER BANK1:TXSTA.CSRC 7 Clock Source Select bit BANK1:TXSTA.TX9 6 9-bit Transmit Enable bit BANK1:TXSTA.TXEN 5 Transmit Enable bit BANK1:TXSTA.SYNC 4 USART Mode Select bit BANK1:TXSTA.BRGH 2 High Baud Rate Select bit BANK1:TXSTA.TRMT 1 Transmit Shift Register Status bit BANK1:TXSTA.TX9D 0 9th bit of transmit data BANK1:SPBRG 0x0099 Baud Rate Generator Register BANK1:RESERVED009A 0x009A RESERVED BANK1:RESERVED009B 0x009B RESERVED BANK1:RESERVED009C 0x009C RESERVED BANK1:RESERVED009D 0x009D RESERVED BANK1:RESERVED009E 0x009E RESERVED BANK1:RESERVED009F 0x009F RESERVED .16C712 ; http://www.microchip.com/download/lit/pline/picmicro/families/16c71x/41106a.pdf ; PIC16C712_6.pdf ; MEMORY MAP ; BANK_0 area DATA FSR_ 0x0000:0x0020 area DATA Gen_Purp 0x0020:0x0080 General Purpose Register area DATA MEM_Program 0x0080:0x0400 On-chip Program Memory ; BANK_1 ; area DATA FSR_ 0x0080:0x00A0 ; area DATA Gen_Purp 0x00A0:0x00C0 General Purpose Register ; area BSS RESERVED 0x00C0:0x0100 ; area DATA MEM_Program 0x0100:0x0400 On-chip Program Memory ; Interrupt and reset vector assignments interrupt RESET 0x0000 RESET ; INPUT/OUTPUT PORTS ; BANK0 (0x0000:0x0080) BANK0:INDF 0x0000 INDF (not a physical register) BANK0:TMR0 0x0001 Timer0 module's register BANK0:PCL 0x0002 Program Counter's (PC) Least Significant Byte BANK0:STATUS 0x0003 STATUS REGISTER BANK0:STATUS.RP0 5 Register Bank Select bit 0 BANK0:STATUS.TO 4 Time-out bit BANK0:STATUS.PD 3 Power-down bit BANK0:STATUS.Z 2 Zero bit BANK0:STATUS.DC 1 Digit carry/borrow bit BANK0:STATUS.C 0 Carry/borrow bit BANK0:FSR 0x0004 Indirect data memory address pointer BANK0:PORTA 0x0005 PORTA REGISTER BANK0:PORTA.RA4 4 PORTA bit 4 BANK0:PORTA.RA3 3 PORTA bit 3 BANK0:PORTA.RA2 2 PORTA bit 2 BANK0:PORTA.RA1 1 PORTA bit 1 BANK0:PORTA.RA0 0 PORTA bit 0 BANK0:PORTB 0x0006 PORTB REGISTER BANK0:PORTB.RB7 7 PORTB bit 7 BANK0:PORTB.RB6 6 PORTB bit 6 BANK0:PORTB.RB5 5 PORTB bit 5 BANK0:PORTB.RB4 4 PORTB bit 4 BANK0:PORTB.RB3 3 PORTB bit 3 BANK0:PORTB.RB2 2 PORTB bit 2 BANK0:PORTB.RB1 1 PORTB bit 1 BANK0:PORTB.RB0 0 PORTB bit 0 BANK0:DATACCP 0x0007 DATACCP REGISTER BANK0:DATACCP.DCCP 2 BANK0:DATACCP.DT1CK 0 BANK0:RESERVED0008 0x0008 RESERVED BANK0:RESERVED0009 0x0009 RESERVED BANK0:PCLATH 0x000A Write Buffer for the upper 5 bits of the Program Counter BANK0:INTCON 0x000B INTCON REGISTER BANK0:INTCON.GIE 7 Global Interrupt Enable bit BANK0:INTCON.PEIE 6 Peripheral Interrupt Enable bit BANK0:INTCON.T0IE 5 TMR0 Overflow Interrupt Enable bit BANK0:INTCON.INTE 4 RB0/INT External Interrupt Enable bit BANK0:INTCON.RBIE 3 RB Port Change Interrupt Enable bit BANK0:INTCON.T0IF 2 TMR0 Overflow Interrupt Flag bit BANK0:INTCON.INTF 1 RB0/INT External Interrupt Flag bit BANK0:INTCON.RBIF 0 RB Port Change Interrupt Flag bit BANK0:PIR1 0x000C PIR1 REGISTER BANK0:PIR1.ADIF 6 A/D Converter Interrupt Flag bit BANK0:PIR1.CCP1IF 2 CCP1 Interrupt Flag bit BANK0:PIR1.TMR2IF 1 TMR2 to PR2 Match Interrupt Flag bit BANK0:PIR1.TMR1IF 0 TMR1 Overflow Interrupt Flag bit BANK0:RESERVED000D 0x000D RESERVED BANK0:TMR1L 0x000E Holding register for the Least Significant Byte of the 16-bit TMR1 register BANK0:TRM1H 0x000F Holding register for the Most Significant Byte of the 16-bit TMR1 register BANK0:T1CON 0x0010 TIMER1 CONTROL REGISTER BANK0:T1CON.T1CKPS1 5 Timer1 Input Clock Prescale Select bit 1 BANK0:T1CON.T1CKPS0 4 Timer1 Input Clock Prescale Select bit 0 BANK0:T1CON.T1OSCEN 3 Timer1 Oscillator Enable Control bit BANK0:T1CON.T1SYNC 2 Timer1 External Clock Input Synchronization Control bit BANK0:T1CON.TMR1CS 1 Timer1 Clock Source Select bit BANK0:T1CON.TMR1ON 0 Timer1 On bit BANK0:TRM2 0x0011 Timer2 module's register BANK0:T2CON 0x0012 TIMER2 CONTROL REGISTER BANK0:T2CON.TOUTPS3 6 Timer2 Output Postscale Select bit 3 BANK0:T2CON.TOUTPS2 5 Timer2 Output Postscale Select bit 2 BANK0:T2CON.TOUTPS1 4 Timer2 Output Postscale Select bit 1 BANK0:T2CON.TOUTPS0 3 Timer2 Output Postscale Select bit 0 BANK0:T2CON.TMR2ON 2 Timer2 On bit BANK0:T2CON.T2CKPS1 1 Timer2 Clock Prescale Select bit 1 BANK0:T2CON.T2CKPS0 0 Timer2 Clock Prescale Select bit 0 BANK0:RESERVED0013 0x0013 RESERVED BANK0:RESERVED0014 0x0014 RESERVED BANK0:CCPR1L 0x0015 Capture/Compare/PWM Register1 (LSB) BANK0:CCPR1H 0x0016 Capture/Compare/PWM Register1 (MSB) BANK0:CCP1CON 0x0017 CCP1CON REGISTER BANK0:CCP1CON.DC1B1 5 PWM Least Significant bit 1 BANK0:CCP1CON.DC1B0 4 PWM Least Significant bit 0 BANK0:CCP1CON.CCP1M3 3 CCP1 Mode Select bit 3 BANK0:CCP1CON.CCP1M2 2 CCP1 Mode Select bit 2 BANK0:CCP1CON.CCP1M1 1 CCP1 Mode Select bit 1 BANK0:CCP1CON.CCP1M0 0 CCP1 Mode Select bit 0 BANK0:RESERVED0018 0x0018 RESERVED BANK0:RESERVED0019 0x0019 RESERVED BANK0:RESERVED001A 0x001A RESERVED BANK0:RESERVED001B 0x001B RESERVED BANK0:RESERVED001C 0x001C RESERVED BANK0:RESERVED001D 0x001D RESERVED BANK0:ADRES 0x001E A/D Result Register BANK0:ADCON0 0x001F ADCON0 REGISTER BANK0:ADCON0.ADCS1 7 A/D Conversion Clock Select bit 1 BANK0:ADCON0.ADCS0 6 A/D Conversion Clock Select bit 0 BANK0:ADCON0.CHS2 5 Analog Channel Select bit 2 BANK0:ADCON0.CHS1 4 Analog Channel Select bit 1 BANK0:ADCON0.CHS0 3 Analog Channel Select bit 0 BANK0:ADCON0.GO_DONE 2 A/D Conversion Status bit BANK0:ADCON0.ADON 0 A/D On bit ; BANK1 (0x0080:0x0100) BANK1:INDF 0x0080 INDF (not a physical register) BANK1:OPTION 0x0081 OPTION REGISTER BANK1:OPTION.RBPU 7 PORTB Pull-up Enable bit BANK1:OPTION.INTEDG 6 Interrupt Edge Select bit BANK1:OPTION.T0CS 5 TMR0 Clock Source Select bit BANK1:OPTION.T0SE 4 TMR0 Source Edge Select bit BANK1:OPTION.PSA 3 Prescaler Assignment bit BANK1:OPTION.PS2 2 Prescaler Rate Select bit 2 BANK1:OPTION.PS1 1 Prescaler Rate Select bit 1 BANK1:OPTION.PS0 0 Prescaler Rate Select bit 0 BANK1:PCL 0x0082 Program Counter's (PC) Least Significant Byte BANK1:STATUS 0x0083 STATUS REGISTER BANK1:STATUS.RP0 5 Register Bank Select bit 0 BANK1:STATUS.TO 4 Time-out bit BANK1:STATUS.PD 3 Power-down bit BANK1:STATUS.Z 2 Zero bit BANK1:STATUS.DC 1 Digit carry/borrow bit BANK1:STATUS.C 0 Carry/borrow bit BANK1:FSR 0x0084 Indirect data memory address pointer BANK1:TRISA 0x0085 PORTA Data Direction Register BANK1:TRISA.TRISA4 4 PORTA Data Direction Register bit 4 BANK1:TRISA.TRISA3 3 PORTA Data Direction Register bit 3 BANK1:TRISA.TRISA2 2 PORTA Data Direction Register bit 2 BANK1:TRISA.TRISA1 1 PORTA Data Direction Register bit 1 BANK1:TRISA.TRISA0 0 PORTA Data Direction Register bit 0 BANK1:TRISB 0x0086 PORTB Data Direction Register BANK1:TRISB.TRISB7 7 PORTB Data Direction Register bit 7 BANK1:TRISB.TRISB6 6 PORTB Data Direction Register bit 6 BANK1:TRISB.TRISB5 5 PORTB Data Direction Register bit 5 BANK1:TRISB.TRISB4 4 PORTB Data Direction Register bit 4 BANK1:TRISB.TRISB3 3 PORTB Data Direction Register bit 3 BANK1:TRISB.TRISB2 2 PORTB Data Direction Register bit 2 BANK1:TRISB.TRISB1 1 PORTB Data Direction Register bit 1 BANK1:TRISB.TRISB0 0 PORTB Data Direction Register bit 0 BANK1:TRISCCP 0x0087 TRISCCP Register BANK1:TRISCCP.TCCP 2 Tri state control bit for CCP BANK1:TRISCCP.TT1CK 0 Tri state control bit for T1CKI pin BANK1:RESERVED0088 0x0088 RESERVED BANK1:RESERVED0089 0x0089 RESERVED BANK1:PCLATH 0x008A Write Buffer for the upper 5 bits of the Program Counter BANK1:INTCON 0x008B INTCON REGISTER BANK1:INTCON.GIE 7 Global Interrupt Enable bit BANK1:INTCON.PEIE 6 Peripheral Interrupt Enable bit BANK1:INTCON.T0IE 5 TMR0 Overflow Interrupt Enable bit BANK1:INTCON.INTE 4 RB0/INT External Interrupt Enable bit BANK1:INTCON.RBIE 3 RB Port Change Interrupt Enable bit BANK1:INTCON.T0IF 2 TMR0 Overflow Interrupt Flag bit BANK1:INTCON.INTF 1 RB0/INT External Interrupt Flag bit BANK1:INTCON.RBIF 0 RB Port Change Interrupt Flag bit BANK1:PIE1 0x008C PIE1 REGISTER BANK1:PIE1.ADIE 6 A/D Converter Interrupt Enable bit BANK1:PIE1.CCP1IE 2 CCP1 Interrupt Enable bit BANK1:PIE1.TMR2IE 1 TMR2 to PR2 Match Interrupt Enable bit BANK1:PIE1.TMR1IE 0 TMR1 Overflow Interrupt Enable bit BANK1:RESERVED008D 0x008D RESERVED BANK1:PCON 0x008E PCON REGISTER BANK1:PCON.POR 1 Power-on Reset Status bit BANK1:PCON.BOR 0 Brown-out Reset Status bit BANK1:RESERVED008F 0x008F RESERVED BANK1:RESERVED0090 0x0090 RESERVED BANK1:RESERVED0091 0x0091 RESERVED BANK1:PR2 0x0092 Timer2 Period Register BANK1:RESERVED0092 0x0092 RESERVED BANK1:RESERVED0093 0x0093 RESERVED BANK1:RESERVED0094 0x0094 RESERVED BANK1:RESERVED0095 0x0095 RESERVED BANK1:RESERVED0096 0x0096 RESERVED BANK1:RESERVED0097 0x0097 RESERVED BANK1:RESERVED0098 0x0098 RESERVED BANK1:RESERVED0099 0x0099 RESERVED BANK1:RESERVED009A 0x009A RESERVED BANK1:RESERVED009B 0x009B RESERVED BANK1:RESERVED009C 0x009C RESERVED BANK1:RESERVED009D 0x009D RESERVED BANK1:RESERVED009E 0x009E RESERVED BANK1:ADCON1 0x009F ADCON1 REGISTER BANK1:ADCON1.PCFG2 2 A/D Port Configuration Control bit 2 BANK1:ADCON1.PCFG1 1 A/D Port Configuration Control bit 1 BANK1:ADCON1.PCFG0 0 A/D Port Configuration Control bit 0 .16C716 ; http://www.microchip.com/download/lit/pline/picmicro/families/16c71x/41106a.pdf ; PIC16C712_6.pdf ; MEMORY MAP ; BANK_0 area DATA FSR_ 0x0000:0x0020 area DATA Gen_Purp 0x0020:0x0080 General Purpose Register area DATA MEM_Program 0x0080:0x0800 On-chip Program Memory ; BANK_1 ; area DATA FSR_ 0x0080:0x00A0 ; area DATA Gen_Purp 0x00A0:0x00C0 General Purpose Register ; area BSS RESERVED 0x00C0:0x0100 ; area DATA MEM_Program 0x0100:0x0800 On-chip Program Memory ; Interrupt and reset vector assignments interrupt RESET 0x0000 RESET ; INPUT/OUTPUT PORTS ; BANK0 (0x0000:0x0080) BANK0:INDF 0x0000 INDF (not a physical register) BANK0:TMR0 0x0001 Timer0 module's register BANK0:PCL 0x0002 Program Counter's (PC) Least Significant Byte BANK0:STATUS 0x0003 STATUS REGISTER BANK0:STATUS.RP0 5 Register Bank Select bit 0 BANK0:STATUS.TO 4 Time-out bit BANK0:STATUS.PD 3 Power-down bit BANK0:STATUS.Z 2 Zero bit BANK0:STATUS.DC 1 Digit carry/borrow bit BANK0:STATUS.C 0 Carry/borrow bit BANK0:FSR 0x0004 Indirect data memory address pointer BANK0:PORTA 0x0005 PORTA REGISTER BANK0:PORTA.RA4 4 PORTA bit 4 BANK0:PORTA.RA3 3 PORTA bit 3 BANK0:PORTA.RA2 2 PORTA bit 2 BANK0:PORTA.RA1 1 PORTA bit 1 BANK0:PORTA.RA0 0 PORTA bit 0 BANK0:PORTB 0x0006 PORTB REGISTER BANK0:PORTB.RB7 7 PORTB bit 7 BANK0:PORTB.RB6 6 PORTB bit 6 BANK0:PORTB.RB5 5 PORTB bit 5 BANK0:PORTB.RB4 4 PORTB bit 4 BANK0:PORTB.RB3 3 PORTB bit 3 BANK0:PORTB.RB2 2 PORTB bit 2 BANK0:PORTB.RB1 1 PORTB bit 1 BANK0:PORTB.RB0 0 PORTB bit 0 BANK0:DATACCP 0x0007 DATACCP REGISTER BANK0:DATACCP.DCCP 2 BANK0:DATACCP.DT1CK 0 BANK0:RESERVED0008 0x0008 RESERVED BANK0:RESERVED0009 0x0009 RESERVED BANK0:PCLATH 0x000A Write Buffer for the upper 5 bits of the Program Counter BANK0:INTCON 0x000B INTCON REGISTER BANK0:INTCON.GIE 7 Global Interrupt Enable bit BANK0:INTCON.PEIE 6 Peripheral Interrupt Enable bit BANK0:INTCON.T0IE 5 TMR0 Overflow Interrupt Enable bit BANK0:INTCON.INTE 4 RB0/INT External Interrupt Enable bit BANK0:INTCON.RBIE 3 RB Port Change Interrupt Enable bit BANK0:INTCON.T0IF 2 TMR0 Overflow Interrupt Flag bit BANK0:INTCON.INTF 1 RB0/INT External Interrupt Flag bit BANK0:INTCON.RBIF 0 RB Port Change Interrupt Flag bit BANK0:PIR1 0x000C PIR1 REGISTER BANK0:PIR1.ADIF 6 A/D Converter Interrupt Flag bit BANK0:PIR1.CCP1IF 2 CCP1 Interrupt Flag bit BANK0:PIR1.TMR2IF 1 TMR2 to PR2 Match Interrupt Flag bit BANK0:PIR1.TMR1IF 0 TMR1 Overflow Interrupt Flag bit BANK0:RESERVED000D 0x000D RESERVED BANK0:TMR1L 0x000E Holding register for the Least Significant Byte of the 16-bit TMR1 register BANK0:TRM1H 0x000F Holding register for the Most Significant Byte of the 16-bit TMR1 register BANK0:T1CON 0x0010 TIMER1 CONTROL REGISTER BANK0:T1CON.T1CKPS1 5 Timer1 Input Clock Prescale Select bit 1 BANK0:T1CON.T1CKPS0 4 Timer1 Input Clock Prescale Select bit 0 BANK0:T1CON.T1OSCEN 3 Timer1 Oscillator Enable Control bit BANK0:T1CON.T1SYNC 2 Timer1 External Clock Input Synchronization Control bit BANK0:T1CON.TMR1CS 1 Timer1 Clock Source Select bit BANK0:T1CON.TMR1ON 0 Timer1 On bit BANK0:TRM2 0x0011 Timer2 module's register BANK0:T2CON 0x0012 TIMER2 CONTROL REGISTER BANK0:T2CON.TOUTPS3 6 Timer2 Output Postscale Select bit 3 BANK0:T2CON.TOUTPS2 5 Timer2 Output Postscale Select bit 2 BANK0:T2CON.TOUTPS1 4 Timer2 Output Postscale Select bit 1 BANK0:T2CON.TOUTPS0 3 Timer2 Output Postscale Select bit 0 BANK0:T2CON.TMR2ON 2 Timer2 On bit BANK0:T2CON.T2CKPS1 1 Timer2 Clock Prescale Select bit 1 BANK0:T2CON.T2CKPS0 0 Timer2 Clock Prescale Select bit 0 BANK0:RESERVED0013 0x0013 RESERVED BANK0:RESERVED0014 0x0014 RESERVED BANK0:CCPR1L 0x0015 Capture/Compare/PWM Register1 (LSB) BANK0:CCPR1H 0x0016 Capture/Compare/PWM Register1 (MSB) BANK0:CCP1CON 0x0017 CCP1CON REGISTER BANK0:CCP1CON.DC1B1 5 PWM Least Significant bit 1 BANK0:CCP1CON.DC1B0 4 PWM Least Significant bit 0 BANK0:CCP1CON.CCP1M3 3 CCP1 Mode Select bit 3 BANK0:CCP1CON.CCP1M2 2 CCP1 Mode Select bit 2 BANK0:CCP1CON.CCP1M1 1 CCP1 Mode Select bit 1 BANK0:CCP1CON.CCP1M0 0 CCP1 Mode Select bit 0 BANK0:RESERVED0018 0x0018 RESERVED BANK0:RESERVED0019 0x0019 RESERVED BANK0:RESERVED001A 0x001A RESERVED BANK0:RESERVED001B 0x001B RESERVED BANK0:RESERVED001C 0x001C RESERVED BANK0:RESERVED001D 0x001D RESERVED BANK0:ADRES 0x001E A/D Result Register BANK0:ADCON0 0x001F ADCON0 REGISTER BANK0:ADCON0.ADCS1 7 A/D Conversion Clock Select bit 1 BANK0:ADCON0.ADCS0 6 A/D Conversion Clock Select bit 0 BANK0:ADCON0.CHS2 5 Analog Channel Select bit 2 BANK0:ADCON0.CHS1 4 Analog Channel Select bit 1 BANK0:ADCON0.CHS0 3 Analog Channel Select bit 0 BANK0:ADCON0.GO_DONE 2 A/D Conversion Status bit BANK0:ADCON0.ADON 0 A/D On bit ; BANK1 (0x0080:0x0100) BANK1:INDF 0x0080 INDF (not a physical register) BANK1:OPTION 0x0081 OPTION REGISTER BANK1:OPTION.RBPU 7 PORTB Pull-up Enable bit BANK1:OPTION.INTEDG 6 Interrupt Edge Select bit BANK1:OPTION.T0CS 5 TMR0 Clock Source Select bit BANK1:OPTION.T0SE 4 TMR0 Source Edge Select bit BANK1:OPTION.PSA 3 Prescaler Assignment bit BANK1:OPTION.PS2 2 Prescaler Rate Select bit 2 BANK1:OPTION.PS1 1 Prescaler Rate Select bit 1 BANK1:OPTION.PS0 0 Prescaler Rate Select bit 0 BANK1:PCL 0x0082 Program Counter's (PC) Least Significant Byte BANK1:STATUS 0x0083 STATUS REGISTER BANK1:STATUS.RP0 5 Register Bank Select bit 0 BANK1:STATUS.TO 4 Time-out bit BANK1:STATUS.PD 3 Power-down bit BANK1:STATUS.Z 2 Zero bit BANK1:STATUS.DC 1 Digit carry/borrow bit BANK1:STATUS.C 0 Carry/borrow bit BANK1:FSR 0x0084 Indirect data memory address pointer BANK1:TRISA 0x0085 PORTA Data Direction Register BANK1:TRISA.TRISA4 4 PORTA Data Direction Register bit 4 BANK1:TRISA.TRISA3 3 PORTA Data Direction Register bit 3 BANK1:TRISA.TRISA2 2 PORTA Data Direction Register bit 2 BANK1:TRISA.TRISA1 1 PORTA Data Direction Register bit 1 BANK1:TRISA.TRISA0 0 PORTA Data Direction Register bit 0 BANK1:TRISB 0x0086 PORTB Data Direction Register BANK1:TRISB.TRISB7 7 PORTB Data Direction Register bit 7 BANK1:TRISB.TRISB6 6 PORTB Data Direction Register bit 6 BANK1:TRISB.TRISB5 5 PORTB Data Direction Register bit 5 BANK1:TRISB.TRISB4 4 PORTB Data Direction Register bit 4 BANK1:TRISB.TRISB3 3 PORTB Data Direction Register bit 3 BANK1:TRISB.TRISB2 2 PORTB Data Direction Register bit 2 BANK1:TRISB.TRISB1 1 PORTB Data Direction Register bit 1 BANK1:TRISB.TRISB0 0 PORTB Data Direction Register bit 0 BANK1:TRISCCP 0x0087 TRISCCP Register BANK1:TRISCCP.TCCP 2 Tri state control bit for CCP BANK1:TRISCCP.TT1CK 0 Tri state control bit for T1CKI pin BANK1:RESERVED0088 0x0088 RESERVED BANK1:RESERVED0089 0x0089 RESERVED BANK1:PCLATH 0x008A Write Buffer for the upper 5 bits of the Program Counter BANK1:INTCON 0x008B INTCON REGISTER BANK1:INTCON.GIE 7 Global Interrupt Enable bit BANK1:INTCON.PEIE 6 Peripheral Interrupt Enable bit BANK1:INTCON.T0IE 5 TMR0 Overflow Interrupt Enable bit BANK1:INTCON.INTE 4 RB0/INT External Interrupt Enable bit BANK1:INTCON.RBIE 3 RB Port Change Interrupt Enable bit BANK1:INTCON.T0IF 2 TMR0 Overflow Interrupt Flag bit BANK1:INTCON.INTF 1 RB0/INT External Interrupt Flag bit BANK1:INTCON.RBIF 0 RB Port Change Interrupt Flag bit BANK1:PIE1 0x008C PIE1 REGISTER BANK1:PIE1.ADIE 6 A/D Converter Interrupt Enable bit BANK1:PIE1.CCP1IE 2 CCP1 Interrupt Enable bit BANK1:PIE1.TMR2IE 1 TMR2 to PR2 Match Interrupt Enable bit BANK1:PIE1.TMR1IE 0 TMR1 Overflow Interrupt Enable bit BANK1:RESERVED008D 0x008D RESERVED BANK1:PCON 0x008E PCON REGISTER BANK1:PCON.POR 1 Power-on Reset Status bit BANK1:PCON.BOR 0 Brown-out Reset Status bit BANK1:RESERVED008F 0x008F RESERVED BANK1:RESERVED0090 0x0090 RESERVED BANK1:RESERVED0091 0x0091 RESERVED BANK1:PR2 0x0092 Timer2 Period Register BANK1:RESERVED0092 0x0092 RESERVED BANK1:RESERVED0093 0x0093 RESERVED BANK1:RESERVED0094 0x0094 RESERVED BANK1:RESERVED0095 0x0095 RESERVED BANK1:RESERVED0096 0x0096 RESERVED BANK1:RESERVED0097 0x0097 RESERVED BANK1:RESERVED0098 0x0098 RESERVED BANK1:RESERVED0099 0x0099 RESERVED BANK1:RESERVED009A 0x009A RESERVED BANK1:RESERVED009B 0x009B RESERVED BANK1:RESERVED009C 0x009C RESERVED BANK1:RESERVED009D 0x009D RESERVED BANK1:RESERVED009E 0x009E RESERVED BANK1:ADCON1 0x009F ADCON1 REGISTER BANK1:ADCON1.PCFG2 2 A/D Port Configuration Control bit 2 BANK1:ADCON1.PCFG1 1 A/D Port Configuration Control bit 1 BANK1:ADCON1.PCFG0 0 A/D Port Configuration Control bit 0 .16C717 ; http://www.microchip.com/download/lit/pline/picmicro/families/16c71x/41120b.pdf ; PIC16C717_70_71.pdf ; MEMORY MAP ; BANK_0 area DATA FSR_ 0x0000:0x0020 area DATA Gen_Purp 0x0020:0x0080 General Purpose Register area DATA MEM_Program 0x0080:0x0800 On-chip Program Memory ; BANK_1 ; area DATA FSR_ 0x0080:0x00A0 ; area DATA Gen_Purp 0x00A0:0x00F0 General Purpose Register ; area DATA Gen_Purp_BANK0 0x00F0:0x0100 accesses 70h-7Fh ; area DATA MEM_Program 0x0100:0x0800 On-chip Program Memory ; BANK_2 ; area DATA FSR_ 0x0100:0x0120 ; area DATA Gen_Purp 0x0120:0x0170 General Purpose Register ; area DATA Gen_Purp_BANK0 0x0170:0x0180 accesses 70h-7Fh ; area DATA MEM_Program 0x0180:0x0800 On-chip Program Memory ; BANK_3 ; area DATA FSR_ 0x0180:0x01A0 ; area BSS RESERVED 0x01A0:0x01F0 ; area DATA Gen_Purp_BANK0 0x01F0:0x0200 accesses 70h-7Fh ; area DATA MEM_Program 0x0200:0x0800 On-chip Program Memory ; Interrupt and reset vector assignments interrupt RESET 0x0000 RESET ; INPUT/OUTPUT PORTS ; BANK0 (0x0000:0x0080) BANK0:INDF 0x0000 INDF (not a physical register) BANK0:TMR0 0x0001 Timer0 module's register BANK0:PCL 0x0002 Program Counter's (PC) Least Significant Byte BANK0:STATUS 0x0003 STATUS REGISTER BANK0:STATUS.IRP 7 Register Bank Select bit BANK0:STATUS.RP1 6 Register Bank Select bit 1 BANK0:STATUS.RP0 5 Register Bank Select bit 0 BANK0:STATUS.TO 4 Time-out bit BANK0:STATUS.PD 3 Power-down bit BANK0:STATUS.Z 2 Zero bit BANK0:STATUS.DC 1 Digit carry/borrow bit BANK0:STATUS.C 0 Carry/borrow bit BANK0:FSR 0x0004 Indirect data memory address pointer BANK0:PORTA 0x0005 PORTA REGISTER BANK0:PORTA.RA7 7 PORTA bit 7 BANK0:PORTA.RA6 6 PORTA bit 6 BANK0:PORTA.RA5 5 PORTA bit 5 BANK0:PORTA.RA4 4 PORTA bit 4 BANK0:PORTA.RA3 3 PORTA bit 3 BANK0:PORTA.RA2 2 PORTA bit 2 BANK0:PORTA.RA1 1 PORTA bit 1 BANK0:PORTA.RA0 0 PORTA bit 0 BANK0:PORTB 0x0006 PORTB REGISTER BANK0:PORTB.RB7 7 PORTB bit 7 BANK0:PORTB.RB6 6 PORTB bit 6 BANK0:PORTB.RB5 5 PORTB bit 5 BANK0:PORTB.RB4 4 PORTB bit 4 BANK0:PORTB.RB3 3 PORTB bit 3 BANK0:PORTB.RB2 2 PORTB bit 2 BANK0:PORTB.RB1 1 PORTB bit 1 BANK0:PORTB.RB0 0 PORTB bit 0 BANK0:RESERVED0007 0x0007 RESERVED BANK0:RESERVED0008 0x0008 RESERVED BANK0:RESERVED0009 0x0009 RESERVED BANK0:PCLATH 0x000A Write Buffer for the upper 5 bits of the Program Counter BANK0:INTCON 0x000B INTERRUPT CONTROL REGISTER BANK0:INTCON.GIE 7 Global Interrupt Enable bit BANK0:INTCON.PEIE 6 Peripheral Interrupt Enable bit BANK0:INTCON.T0IE 5 TMR0 Overflow Interrupt Enable bit BANK0:INTCON.INTE 4 RB0/INT External Interrupt Enable bit BANK0:INTCON.RBIE 3 RB Port Change Interrupt Enable bit BANK0:INTCON.T0IF 2 TMR0 Overflow Interrupt Flag bit BANK0:INTCON.INTF 1 RB0/INT External Interrupt Flag bit BANK0:INTCON.RBIF 0 RB Port Change Interrupt Flag bit BANK0:PIR1 0x000C PERIPHERAL INTERRUPT REGISTER 1 BANK0:PIR1.ADIF 6 A/D Converter Interrupt Flag bit BANK0:PIR1.SSPIF 3 Synchronous Serial Port (SSP) Interrupt Flag BANK0:PIR1.CCP1IF 2 CCP1 Interrupt Flag bit BANK0:PIR1.TMR2IF 1 TMR2 to PR2 Match Interrupt Flag bit BANK0:PIR1.TMR1IF 0 TMR1 Overflow Interrupt Flag bit BANK0:PIR2 0x000D PERIPHERAL INTERRUPT REGISTER 2 BANK0:PIR2.LVDIF 7 Low Voltage Detect Interrupt Flag bit BANK0:PIR2.BCLIF 3 Bus Collision Interrupt Flag bit BANK0:TMR1L 0x000E Holding register for the Least Significant Byte of the 16-bit TMR1 register BANK0:TMR1H 0x000F Holding register for the Most Significant Byte of the 16-bit TMR1 register BANK0:T1CON 0x0010 TIMER1 CONTROL REGISTER BANK0:T1CON.T1CKPS1 5 Timer1 Input Clock Prescale Select bit 1 BANK0:T1CON.T1CKPS0 4 Timer1 Input Clock Prescale Select bit 0 BANK0:T1CON.T1OSCEN 3 Timer1 Oscillator Enable Control bit BANK0:T1CON.T1SYNC 2 Timer1 External Clock Input Synchronization Control bit BANK0:T1CON.TMR1CS 1 Timer1 Clock Source Select bit BANK0:T1CON.TMR1ON 0 Timer1 On bit BANK0:TMR2 0x0011 Timer2 module's register BANK0:T2CON 0x0012 TIMER2 CONTROL REGISTER BANK0:T2CON.TOUTPS3 6 Timer2 Output Postscale Select bit 3 BANK0:T2CON.TOUTPS2 5 Timer2 Output Postscale Select bit 2 BANK0:T2CON.TOUTPS1 4 Timer2 Output Postscale Select bit 1 BANK0:T2CON.TOUTPS0 3 Timer2 Output Postscale Select bit 0 BANK0:T2CON.TMR2ON 2 Timer2 On bit BANK0:T2CON.T2CKPS1 1 Timer2 Clock Prescale Select bit 1 BANK0:T2CON.T2CKPS0 0 Timer2 Clock Prescale Select bit 0 BANK0:SSPBUF 0x0013 Synchronous Serial Port Receive Buffer/Transmit Register BANK0:SSPCON 0x0014 SYNC SERIAL PORT CONTROL REGISTER BANK0:SSPCON.WCOL 7 Write Collision Detect bit BANK0:SSPCON.SSPOV 6 Receive Overflow Indicator bit BANK0:SSPCON.SSPEN 5 Synchronous Serial Port Enable bit BANK0:SSPCON.CKP 4 Clock Polarity Select bit BANK0:SSPCON.SSPM3 3 Synchronous Serial Port Mode Select bit 3 BANK0:SSPCON.SSPM2 2 Synchronous Serial Port Mode Select bit 2 BANK0:SSPCON.SSPM1 1 Synchronous Serial Port Mode Select bit 1 BANK0:SSPCON.SSPM0 0 Synchronous Serial Port Mode Select bit 0 BANK0:CCPR1L 0x0015 Capture/Compare/PWM Register1 (LSB) BANK0:CCPR1H 0x0016 Capture/Compare/PWM Register1 (MSB) BANK0:CCP1CON 0x0017 CCP1 CONTROL REGISTER BANK0:CCP1CON.PWM1M1 7 PWM Output Configuration 1 BANK0:CCP1CON.PWM1M0 6 PWM Output Configuration 0 BANK0:CCP1CON.DC1B1 5 PWM Duty Cycle Least Significant bit 1 BANK0:CCP1CON.DC1B0 4 PWM Duty Cycle Least Significant bit 0 BANK0:CCP1CON.CCP1M3 3 ECCP Mode Select bit 3 BANK0:CCP1CON.CCP1M2 2 ECCP Mode Select bit 2 BANK0:CCP1CON.CCP1M1 1 ECCP Mode Select bit 1 BANK0:CCP1CON.CCP1M0 0 ECCP Mode Select bit 0 BANK0:RESERVED0018 0x0018 RESERVED BANK0:RESERVED0019 0x0019 RESERVED BANK0:RESERVED001A 0x001A RESERVED BANK0:RESERVED001B 0x001B RESERVED BANK0:RESERVED001C 0x001C RESERVED BANK0:RESERVED001D 0x001D RESERVED BANK0:ADRESH 0x001E A/D High Byte Result Register BANK0:ADCON0 0x001F A/D CONTROL REGISTER 0 BANK0:ADCON0.ADCS1 7 A/D Conversion Clock Select bit 1 BANK0:ADCON0.ADCS0 6 A/D Conversion Clock Select bit 0 BANK0:ADCON0.CHS2 5 Analog Channel Select bit 2 BANK0:ADCON0.CHS1 4 Analog Channel Select bit 1 BANK0:ADCON0.CHS0 3 Analog Channel Select bit 0 BANK0:ADCON0.GO_DONE 2 A/D Conversion Status bit BANK0:ADCON0.CHS3 1 Analog Channel Select bit 3 BANK0:ADCON0.ADON 0 A/D On bit ; BANK1 (0x0080:0x0100) BANK1:INDF 0x0080 INDF (not a physical register) BANK1:OPTION 0x0081 OPTION REGISTER BANK1:OPTION.RBPU 7 PORTB Pull-up Enable bit BANK1:OPTION.INTEDG 6 Interrupt Edge Select bit BANK1:OPTION.T0CS 5 TMR0 Clock Source Select bit BANK1:OPTION.T0SE 4 TMR0 Source Edge Select bit BANK1:OPTION.PSA 3 Prescaler Assignment bit BANK1:OPTION.PS2 2 Prescaler Rate Select bit 2 BANK1:OPTION.PS1 1 Prescaler Rate Select bit 1 BANK1:OPTION.PS0 0 Prescaler Rate Select bit 0 BANK1:PCL 0x0082 Program Counter's (PC) Least Significant Byte BANK1:STATUS 0x0083 STATUS REGISTER BANK1:STATUS.IRP 7 Register Bank Select bit BANK1:STATUS.RP1 6 Register Bank Select bit 1 BANK1:STATUS.RP0 5 Register Bank Select bit 0 BANK1:STATUS.TO 4 Time-out bit BANK1:STATUS.PD 3 Power-down bit BANK1:STATUS.Z 2 Zero bit BANK1:STATUS.DC 1 Digit carry/borrow bit BANK1:STATUS.C 0 Carry/borrow bit BANK1:FSR 0x0084 Indirect data memory address pointer BANK1:TRISA 0x0085 PORTA Data Direction Register BANK1:TRISA.TRISA7 7 PORTA Data Direction Register bit 7 BANK1:TRISA.TRISA6 6 PORTA Data Direction Register bit 6 BANK1:TRISA.TRISA5 5 PORTA Data Direction Register bit 5 BANK1:TRISA.TRISA4 4 PORTA Data Direction Register bit 4 BANK1:TRISA.TRISA3 3 PORTA Data Direction Register bit 3 BANK1:TRISA.TRISA2 2 PORTA Data Direction Register bit 2 BANK1:TRISA.TRISA1 1 PORTA Data Direction Register bit 1 BANK1:TRISA.TRISA0 0 PORTA Data Direction Register bit 0 BANK1:TRISB 0x0086 PORTB Data Direction Register BANK1:TRISB.TRISB7 7 PORTB Data Direction Register bit 7 BANK1:TRISB.TRISB6 6 PORTB Data Direction Register bit 6 BANK1:TRISB.TRISB5 5 PORTB Data Direction Register bit 5 BANK1:TRISB.TRISB4 4 PORTB Data Direction Register bit 4 BANK1:TRISB.TRISB3 3 PORTB Data Direction Register bit 3 BANK1:TRISB.TRISB2 2 PORTB Data Direction Register bit 2 BANK1:TRISB.TRISB1 1 PORTB Data Direction Register bit 1 BANK1:TRISB.TRISB0 0 PORTB Data Direction Register bit 0 BANK1:RESERVED0087 0x0087 RESERVED BANK1:RESERVED0088 0x0088 RESERVED BANK1:RESERVED0089 0x0089 RESERVED BANK1:PCLATH 0x008A Write Buffer for the upper 5 bits of the Program Counter BANK1:INTCON 0x008B INTERRUPT CONTROL REGISTER BANK1:INTCON.GIE 7 Global Interrupt Enable bit BANK1:INTCON.PEIE 6 Peripheral Interrupt Enable bit BANK1:INTCON.T0IE 5 TMR0 Overflow Interrupt Enable bit BANK1:INTCON.INTE 4 RB0/INT External Interrupt Enable bit BANK1:INTCON.RBIE 3 RB Port Change Interrupt Enable bit BANK1:INTCON.T0IF 2 TMR0 Overflow Interrupt Flag bit BANK1:INTCON.INTF 1 RB0/INT External Interrupt Flag bit BANK1:INTCON.RBIF 0 RB Port Change Interrupt Flag bit BANK1:PIE1 0x008C PERIPHERAL INTERRUPT ENABLE REGISTER 1 BANK1:PIE1.ADIE 6 A/D Converter Interrupt Enable bit BANK1:PIE1.SSPIE 3 Synchronous Serial Port Interrupt Enable bit BANK1:PIE1.CCP1IE 2 CCP1 Interrupt Enable bit BANK1:PIE1.TMR2IE 1 TMR2 to PR2 Match Interrupt Enable bit BANK1:PIE1.TMR1IE 0 TMR1 Overflow Interrupt Enable bit BANK1:PIE2 0x008D PERIPHERAL INTERRUPT ENABLE REGISTER 2 BANK1:PIE2.LVDIE 7 Low Voltage Detect Interrupt Enable bit BANK1:PIE2.BCLIE 3 Bus Collision Interrupt Enable bit BANK1:PCON 0x008E POWER CONTROL REGISTER BANK1:PCON.OSCF 3 Oscillator Speed bit BANK1:PCON.POR 1 Power-on Reset Status bit BANK1:PCON.BOR 0 Brown-out Reset Status bit BANK1:RESERVED008F 0x008F RESERVED BANK1:RESERVED0090 0x0090 RESERVED BANK1:SSPCON2 0x0091 SYNC SERIAL PORT CONTROL REGISTER2 BANK1:SSPCON2.GCEN 7 General Call Enable bit (In I2C Slave mode only) BANK1:SSPCON2.ACKSTAT 6 Acknowledge Status bit (In I2C Master mode only) BANK1:SSPCON2.ACKDT 5 Acknowledge Data bit (In I2C Master mode only) BANK1:SSPCON2.ACKEN 4 Acknowledge Sequence Enable bit (In I2C Master mode only) BANK1:SSPCON2.RCEN 3 Receive Enable bit (In I2C Master mode only) BANK1:SSPCON2.PEN 2 STOP Condition Enable bit (In I2C Master mode only) BANK1:SSPCON2.RSEN 1 Repeated START Condition Enabled bit (In I2C Master mode only) BANK1:SSPCON2.SEN 0 START Condition Enabled bit (In I2C Master mode only) BANK1:PR2 0x0092 Timer2 Period Register BANK1:SSPADD 0x0093 Synchronous Serial Port (I2C mode) Address Register BANK1:SSPSTAT 0x0094 SYNC SERIAL PORT STATUS REGISTER BANK1:SSPSTAT.SMP 7 Sample bit BANK1:SSPSTAT.CKE 6 SPI Clock Edge Select BANK1:SSPSTAT.D_A 5 Data/Address bit (I2C mode only) BANK1:SSPSTAT.P 4 STOP bit (I2C mode only) BANK1:SSPSTAT.S 3 START bit (I2C mode only) BANK1:SSPSTAT.R_W 2 Read/Write bit information (I2C mode only) BANK1:SSPSTAT.UA 1 Update Address (I2C mode only) BANK1:SSPSTAT.BF 0 Buffer Full Status bit BANK1:WPUB 0x0095 PORTB Weak Pull-up Control BANK1:WPUB.WPUB7 7 PORTB Weak Pull-Up Control bit 7 BANK1:WPUB.WPUB6 6 PORTB Weak Pull-Up Control bit 6 BANK1:WPUB.WPUB5 5 PORTB Weak Pull-Up Control bit 5 BANK1:WPUB.WPUB4 4 PORTB Weak Pull-Up Control bit 4 BANK1:WPUB.WPUB3 3 PORTB Weak Pull-Up Control bit 3 BANK1:WPUB.WPUB2 2 PORTB Weak Pull-Up Control bit 2 BANK1:WPUB.WPUB1 1 PORTB Weak Pull-Up Control bit 1 BANK1:WPUB.WPUB0 0 PORTB Weak Pull-Up Control bit 0 BANK1:IOCB 0x0096 PORTB Interrupt on Change Control BANK1:IOCB.IOCB7 7 Interrupt-on-Change PORTB Control bit 7 BANK1:IOCB.IOCB6 6 Interrupt-on-Change PORTB Control bit 6 BANK1:IOCB.IOCB5 5 Interrupt-on-Change PORTB Control bit 5 BANK1:IOCB.IOCB4 4 Interrupt-on-Change PORTB Control bit 4 BANK1:IOCB.IOCB3 3 Interrupt-on-Change PORTB Control bit 3 BANK1:IOCB.IOCB2 2 Interrupt-on-Change PORTB Control bit 2 BANK1:IOCB.IOCB1 1 Interrupt-on-Change PORTB Control bit 1 BANK1:IOCB.IOCB0 0 Interrupt-on-Change PORTB Control bit 0 BANK1:P1DEL 0x0097 PWM 1 Delay value BANK1:P1DEL.P1DEL7 7 PWM Delay Count for Half-Bridge Output Mode 7 BANK1:P1DEL.P1DEL6 6 PWM Delay Count for Half-Bridge Output Mode 6 BANK1:P1DEL.P1DEL5 5 PWM Delay Count for Half-Bridge Output Mode 5 BANK1:P1DEL.P1DEL4 4 PWM Delay Count for Half-Bridge Output Mode 4 BANK1:P1DEL.P1DEL3 3 PWM Delay Count for Half-Bridge Output Mode 3 BANK1:P1DEL.P1DEL2 2 PWM Delay Count for Half-Bridge Output Mode 2 BANK1:P1DEL.P1DEL1 1 PWM Delay Count for Half-Bridge Output Mode 1 BANK1:P1DEL.P1DEL0 0 PWM Delay Count for Half-Bridge Output Mode 0 BANK1:RESERVED0098 0x0098 RESERVED BANK1:RESERVED0099 0x0099 RESERVED BANK1:RESERVED009A 0x009A RESERVED BANK1:REFCON 0x009B VOLTAGE REFERENCE CONTROL REGISTER BANK1:REFCON.VRHEN 7 Voltage Reference High Enable bit BANK1:REFCON.VRLEN 6 Voltage Reference Low Enable bit BANK1:REFCON.VRHOEN 5 High Voltage Reference Output Enable bit BANK1:REFCON.VRLOEN 4 Low Voltage Reference Output Enable bit BANK1:LVDCON 0x009C LOW-VOLTAGE DETECT CONTROL REGISTER BANK1:LVDCON.BGST 5 Bandgap Stable Status Flag bit BANK1:LVDCON.LVDEN 4 Low-voltage Detect Power Enable bit BANK1:LVDCON.LVV3 3 Low Voltage Detection Limit bit 3 BANK1:LVDCON.LVV2 2 Low Voltage Detection Limit bit 2 BANK1:LVDCON.LVV1 1 Low Voltage Detection Limit bit 1 BANK1:LVDCON.LVV0 0 Low Voltage Detection Limit bit 0 BANK1:ANSEL 0x009D Analog Channel Select BANK1:ADRESL 0x009E A/D Low Byte Result Register BANK1:ADCON1 0x009F A/D CONTROL REGISTER 1 BANK1:ADCON1.ADFM 7 A/D Result Format Select bit BANK1:ADCON1.VCFG2 6 Voltage Reference Configuration bit 2 BANK1:ADCON1.VCFG1 5 Voltage Reference Configuration bit 1 BANK1:ADCON1.VCFG0 4 Voltage Reference Configuration bit 0 ; BANK2 (0x0100:0x0180) BANK2:INDF 0x0100 INDF (not a physical register) BANK2:TMR0 0x0101 Timer0 module's register BANK2:PCL 0x0102 Program Counter's (PC) Least Significant Byte BANK2:STATUS 0x0103 STATUS REGISTER BANK2:STATUS.IRP 7 Register Bank Select bit BANK2:STATUS.RP1 6 Register Bank Select bit 1 BANK2:STATUS.RP0 5 Register Bank Select bit 0 BANK2:STATUS.TO 4 Time-out bit BANK2:STATUS.PD 3 Power-down bit BANK2:STATUS.Z 2 Zero bit BANK2:STATUS.DC 1 Digit carry/borrow bit BANK2:STATUS.C 0 Carry/borrow bit BANK2:FSR 0x0104 Indirect data memory address pointer BANK2:RESERVED0105 0x0105 RESERVED BANK2:PORTB 0x0106 PORTB REGISTER BANK2:PORTB.RB7 7 PORTB bit 7 BANK2:PORTB.RB6 6 PORTB bit 6 BANK2:PORTB.RB5 5 PORTB bit 5 BANK2:PORTB.RB4 4 PORTB bit 4 BANK2:PORTB.RB3 3 PORTB bit 3 BANK2:PORTB.RB2 2 PORTB bit 2 BANK2:PORTB.RB1 1 PORTB bit 1 BANK2:PORTB.RB0 0 PORTB bit 0 BANK2:RESERVED0107 0x0107 RESERVED BANK2:RESERVED0108 0x0108 RESERVED BANK2:RESERVED0109 0x0109 RESERVED BANK2:PCLATH 0x010A Write Buffer for the upper 5 bits of the Program Counter BANK2:INTCON 0x010B INTERRUPT CONTROL REGISTER BANK2:INTCON.GIE 7 Global Interrupt Enable bit BANK2:INTCON.PEIE 6 Peripheral Interrupt Enable bit BANK2:INTCON.T0IE 5 TMR0 Overflow Interrupt Enable bit BANK2:INTCON.INTE 4 RB0/INT External Interrupt Enable bit BANK2:INTCON.RBIE 3 RB Port Change Interrupt Enable bit BANK2:INTCON.T0IF 2 TMR0 Overflow Interrupt Flag bit BANK2:INTCON.INTF 1 RB0/INT External Interrupt Flag bit BANK2:INTCON.RBIF 0 RB Port Change Interrupt Flag bit BANK2:PMDATL 0x010C Program memory read data low BANK2:PMDATL.PMD7 7 BANK2:PMDATL.PMD6 6 BANK2:PMDATL.PMD5 5 BANK2:PMDATL.PMD4 4 BANK2:PMDATL.PMD3 3 BANK2:PMDATL.PMD2 2 BANK2:PMDATL.PMD1 1 BANK2:PMDATL.PMD0 0 BANK2:PMADRL 0x010D Program memory read address low BANK2:PMADRL.PMA7 7 BANK2:PMADRL.PMA6 6 BANK2:PMADRL.PMA5 5 BANK2:PMADRL.PMA4 4 BANK2:PMADRL.PMA3 3 BANK2:PMADRL.PMA2 2 BANK2:PMADRL.PMA1 1 BANK2:PMADRL.PMA0 0 BANK2:PMDATH 0x010E Program memory read data high BANK2:PMDATH.PMD13 5 BANK2:PMDATH.PMD12 4 BANK2:PMDATH.PMD11 3 BANK2:PMDATH.PMD10 2 BANK2:PMDATH.PMD9 1 BANK2:PMDATH.PMD8 0 BANK2:PMADRH 0x010F Program memory read address high BANK2:PMADRH.PMA11 3 BANK2:PMADRH.PMA10 2 BANK2:PMADRH.PMA9 1 BANK2:PMADRH.PMA8 0 BANK2:RESERVED0110 0x0110 RESERVED BANK2:RESERVED0111 0x0111 RESERVED BANK2:RESERVED0112 0x0112 RESERVED BANK2:RESERVED0113 0x0113 RESERVED BANK2:RESERVED0114 0x0114 RESERVED BANK2:RESERVED0115 0x0115 RESERVED BANK2:RESERVED0116 0x0116 RESERVED BANK2:RESERVED0117 0x0117 RESERVED BANK2:RESERVED0118 0x0118 RESERVED BANK2:RESERVED0119 0x0119 RESERVED BANK2:RESERVED011A 0x011A RESERVED BANK2:RESERVED011B 0x011B RESERVED BANK2:RESERVED011C 0x011C RESERVED BANK2:RESERVED011D 0x011D RESERVED BANK2:RESERVED011E 0x011E RESERVED BANK2:RESERVED011F 0x011F RESERVED ; BANK3 (0x0180:0x0200) BANK3:INDF 0x0180 INDF (not a physical register) BANK3:OPTION 0x0181 OPTION REGISTER BANK3:OPTION.RBPU 7 PORTB Pull-up Enable bit BANK3:OPTION.INTEDG 6 Interrupt Edge Select bit BANK3:OPTION.T0CS 5 TMR0 Clock Source Select bit BANK3:OPTION.T0SE 4 TMR0 Source Edge Select bit BANK3:OPTION.PSA 3 Prescaler Assignment bit BANK3:OPTION.PS2 2 Prescaler Rate Select bit 2 BANK3:OPTION.PS1 1 Prescaler Rate Select bit 1 BANK3:OPTION.PS0 0 Prescaler Rate Select bit 0 BANK3:PCL 0x0182 Program Counter's (PC) Least Significant Byte BANK3:STATUS 0x0183 STATUS REGISTER BANK3:STATUS.IRP 7 Register Bank Select bit BANK3:STATUS.RP1 6 Register Bank Select bit 1 BANK3:STATUS.RP0 5 Register Bank Select bit 0 BANK3:STATUS.TO 4 Time-out bit BANK3:STATUS.PD 3 Power-down bit BANK3:STATUS.Z 2 Zero bit BANK3:STATUS.DC 1 Digit carry/borrow bit BANK3:STATUS.C 0 Carry/borrow bit BANK3:FSR 0x0184 Indirect data memory address pointer BANK3:RESERVED0185 0x0185 RESERVED BANK3:TRISB 0x0186 PORTB Data Direction Register BANK3:TRISB.TRISB7 7 PORTB Data Direction Register bit 7 BANK3:TRISB.TRISB6 6 PORTB Data Direction Register bit 6 BANK3:TRISB.TRISB5 5 PORTB Data Direction Register bit 5 BANK3:TRISB.TRISB4 4 PORTB Data Direction Register bit 4 BANK3:TRISB.TRISB3 3 PORTB Data Direction Register bit 3 BANK3:TRISB.TRISB2 2 PORTB Data Direction Register bit 2 BANK3:TRISB.TRISB1 1 PORTB Data Direction Register bit 1 BANK3:TRISB.TRISB0 0 PORTB Data Direction Register bit 0 BANK3:RESERVED0187 0x0187 RESERVED BANK3:RESERVED0188 0x0188 RESERVED BANK3:RESERVED0189 0x0189 RESERVED BANK3:PCLATH 0x018A Write Buffer for the upper 5 bits of the Program Counter BANK3:INTCON 0x018B INTERRUPT CONTROL REGISTER BANK3:INTCON.GIE 7 Global Interrupt Enable bit BANK3:INTCON.PEIE 6 Peripheral Interrupt Enable bit BANK3:INTCON.T0IE 5 TMR0 Overflow Interrupt Enable bit BANK3:INTCON.INTE 4 RB0/INT External Interrupt Enable bit BANK3:INTCON.RBIE 3 RB Port Change Interrupt Enable bit BANK3:INTCON.T0IF 2 TMR0 Overflow Interrupt Flag bit BANK3:INTCON.INTF 1 RB0/INT External Interrupt Flag bit BANK3:INTCON.RBIF 0 RB Port Change Interrupt Flag bit BANK3:PMCON1 0x018C PROGRAM MEMORY READ CONTROL REGISTER 1 BANK3:PMCON1.RD 0 Read Control bit BANK3:RESERVED018D 0x018D RESERVED BANK3:RESERVED018E 0x018E RESERVED BANK3:RESERVED018F 0x018F RESERVED BANK3:RESERVED0190 0x0190 RESERVED BANK3:RESERVED0191 0x0191 RESERVED BANK3:RESERVED0192 0x0192 RESERVED BANK3:RESERVED0193 0x0193 RESERVED BANK3:RESERVED0194 0x0194 RESERVED BANK3:RESERVED0195 0x0195 RESERVED BANK3:RESERVED0196 0x0196 RESERVED BANK3:RESERVED0197 0x0197 RESERVED BANK3:RESERVED0198 0x0198 RESERVED BANK3:RESERVED0199 0x0199 RESERVED BANK3:RESERVED019A 0x019A RESERVED BANK3:RESERVED019B 0x019B RESERVED BANK3:RESERVED019C 0x019C RESERVED BANK3:RESERVED019D 0x019D RESERVED BANK3:RESERVED019E 0x019E RESERVED BANK3:RESERVED019F 0x019F RESERVED .16C770 ; http://www.microchip.com/download/lit/pline/picmicro/families/16c71x/41120b.pdf ; PIC16C717_70_71.pdf ; MEMORY MAP ; BANK_0 area DATA FSR_ 0x0000:0x0020 area DATA Gen_Purp 0x0020:0x0080 General Purpose Register area DATA MEM_Program 0x0080:0x0800 On-chip Program Memory ; BANK_1 ; area DATA FSR_ 0x0080:0x00A0 ; area DATA Gen_Purp 0x00A0:0x00F0 General Purpose Register ; area DATA Gen_Purp_BANK0 0x00F0:0x0100 accesses 70h-7Fh ; area DATA MEM_Program 0x0100:0x0800 On-chip Program Memory ; BANK_2 ; area DATA FSR_ 0x0100:0x0120 ; area DATA Gen_Purp 0x0120:0x0170 General Purpose Register ; area DATA Gen_Purp_BANK0 0x0170:0x0180 accesses 70h-7Fh ; area DATA MEM_Program 0x0180:0x0800 On-chip Program Memory ; BANK_3 ; area DATA FSR_ 0x0180:0x01A0 ; area BSS RESERVED 0x01A0:0x01F0 ; area DATA Gen_Purp_BANK0 0x01F0:0x0200 accesses 70h-7Fh ; area DATA MEM_Program 0x0200:0x0800 On-chip Program Memory ; Interrupt and reset vector assignments interrupt RESET 0x0000 RESET ; INPUT/OUTPUT PORTS ; BANK0 (0x0000:0x0080) BANK0:INDF 0x0000 INDF (not a physical register) BANK0:TMR0 0x0001 Timer0 module's register BANK0:PCL 0x0002 Program Counter's (PC) Least Significant Byte BANK0:STATUS 0x0003 STATUS REGISTER BANK0:STATUS.IRP 7 Register Bank Select bit BANK0:STATUS.RP1 6 Register Bank Select bit 1 BANK0:STATUS.RP0 5 Register Bank Select bit 0 BANK0:STATUS.TO 4 Time-out bit BANK0:STATUS.PD 3 Power-down bit BANK0:STATUS.Z 2 Zero bit BANK0:STATUS.DC 1 Digit carry/borrow bit BANK0:STATUS.C 0 Carry/borrow bit BANK0:FSR 0x0004 Indirect data memory address pointer BANK0:PORTA 0x0005 PORTA REGISTER BANK0:PORTA.RA7 7 PORTA bit 7 BANK0:PORTA.RA6 6 PORTA bit 6 BANK0:PORTA.RA5 5 PORTA bit 5 BANK0:PORTA.RA4 4 PORTA bit 4 BANK0:PORTA.RA3 3 PORTA bit 3 BANK0:PORTA.RA2 2 PORTA bit 2 BANK0:PORTA.RA1 1 PORTA bit 1 BANK0:PORTA.RA0 0 PORTA bit 0 BANK0:PORTB 0x0006 PORTB REGISTER BANK0:PORTB.RB7 7 PORTB bit 7 BANK0:PORTB.RB6 6 PORTB bit 6 BANK0:PORTB.RB5 5 PORTB bit 5 BANK0:PORTB.RB4 4 PORTB bit 4 BANK0:PORTB.RB3 3 PORTB bit 3 BANK0:PORTB.RB2 2 PORTB bit 2 BANK0:PORTB.RB1 1 PORTB bit 1 BANK0:PORTB.RB0 0 PORTB bit 0 BANK0:RESERVED0007 0x0007 RESERVED BANK0:RESERVED0008 0x0008 RESERVED BANK0:RESERVED0009 0x0009 RESERVED BANK0:PCLATH 0x000A Write Buffer for the upper 5 bits of the Program Counter BANK0:INTCON 0x000B INTERRUPT CONTROL REGISTER BANK0:INTCON.GIE 7 Global Interrupt Enable bit BANK0:INTCON.PEIE 6 Peripheral Interrupt Enable bit BANK0:INTCON.T0IE 5 TMR0 Overflow Interrupt Enable bit BANK0:INTCON.INTE 4 RB0/INT External Interrupt Enable bit BANK0:INTCON.RBIE 3 RB Port Change Interrupt Enable bit BANK0:INTCON.T0IF 2 TMR0 Overflow Interrupt Flag bit BANK0:INTCON.INTF 1 RB0/INT External Interrupt Flag bit BANK0:INTCON.RBIF 0 RB Port Change Interrupt Flag bit BANK0:PIR1 0x000C PERIPHERAL INTERRUPT REGISTER 1 BANK0:PIR1.ADIF 6 A/D Converter Interrupt Flag bit BANK0:PIR1.SSPIF 3 Synchronous Serial Port (SSP) Interrupt Flag BANK0:PIR1.CCP1IF 2 CCP1 Interrupt Flag bit BANK0:PIR1.TMR2IF 1 TMR2 to PR2 Match Interrupt Flag bit BANK0:PIR1.TMR1IF 0 TMR1 Overflow Interrupt Flag bit BANK0:PIR2 0x000D PERIPHERAL INTERRUPT REGISTER 2 BANK0:PIR2.LVDIF 7 Low Voltage Detect Interrupt Flag bit BANK0:PIR2.BCLIF 3 Bus Collision Interrupt Flag bit BANK0:TMR1L 0x000E Holding register for the Least Significant Byte of the 16-bit TMR1 register BANK0:TMR1H 0x000F Holding register for the Most Significant Byte of the 16-bit TMR1 register BANK0:T1CON 0x0010 TIMER1 CONTROL REGISTER BANK0:T1CON.T1CKPS1 5 Timer1 Input Clock Prescale Select bit 1 BANK0:T1CON.T1CKPS0 4 Timer1 Input Clock Prescale Select bit 0 BANK0:T1CON.T1OSCEN 3 Timer1 Oscillator Enable Control bit BANK0:T1CON.T1SYNC 2 Timer1 External Clock Input Synchronization Control bit BANK0:T1CON.TMR1CS 1 Timer1 Clock Source Select bit BANK0:T1CON.TMR1ON 0 Timer1 On bit BANK0:TMR2 0x0011 Timer2 module's register BANK0:T2CON 0x0012 TIMER2 CONTROL REGISTER BANK0:T2CON.TOUTPS3 6 Timer2 Output Postscale Select bit 3 BANK0:T2CON.TOUTPS2 5 Timer2 Output Postscale Select bit 2 BANK0:T2CON.TOUTPS1 4 Timer2 Output Postscale Select bit 1 BANK0:T2CON.TOUTPS0 3 Timer2 Output Postscale Select bit 0 BANK0:T2CON.TMR2ON 2 Timer2 On bit BANK0:T2CON.T2CKPS1 1 Timer2 Clock Prescale Select bit 1 BANK0:T2CON.T2CKPS0 0 Timer2 Clock Prescale Select bit 0 BANK0:SSPBUF 0x0013 Synchronous Serial Port Receive Buffer/Transmit Register BANK0:SSPCON 0x0014 SYNC SERIAL PORT CONTROL REGISTER BANK0:SSPCON.WCOL 7 Write Collision Detect bit BANK0:SSPCON.SSPOV 6 Receive Overflow Indicator bit BANK0:SSPCON.SSPEN 5 Synchronous Serial Port Enable bit BANK0:SSPCON.CKP 4 Clock Polarity Select bit BANK0:SSPCON.SSPM3 3 Synchronous Serial Port Mode Select bit 3 BANK0:SSPCON.SSPM2 2 Synchronous Serial Port Mode Select bit 2 BANK0:SSPCON.SSPM1 1 Synchronous Serial Port Mode Select bit 1 BANK0:SSPCON.SSPM0 0 Synchronous Serial Port Mode Select bit 0 BANK0:CCPR1L 0x0015 Capture/Compare/PWM Register1 (LSB) BANK0:CCPR1H 0x0016 Capture/Compare/PWM Register1 (MSB) BANK0:CCP1CON 0x0017 CCP1 CONTROL REGISTER BANK0:CCP1CON.PWM1M1 7 PWM Output Configuration 1 BANK0:CCP1CON.PWM1M0 6 PWM Output Configuration 0 BANK0:CCP1CON.DC1B1 5 PWM Duty Cycle Least Significant bit 1 BANK0:CCP1CON.DC1B0 4 PWM Duty Cycle Least Significant bit 0 BANK0:CCP1CON.CCP1M3 3 ECCP Mode Select bit 3 BANK0:CCP1CON.CCP1M2 2 ECCP Mode Select bit 2 BANK0:CCP1CON.CCP1M1 1 ECCP Mode Select bit 1 BANK0:CCP1CON.CCP1M0 0 ECCP Mode Select bit 0 BANK0:RESERVED0018 0x0018 RESERVED BANK0:RESERVED0019 0x0019 RESERVED BANK0:RESERVED001A 0x001A RESERVED BANK0:RESERVED001B 0x001B RESERVED BANK0:RESERVED001C 0x001C RESERVED BANK0:RESERVED001D 0x001D RESERVED BANK0:ADRESH 0x001E A/D High Byte Result Register BANK0:ADCON0 0x001F A/D CONTROL REGISTER 0 BANK0:ADCON0.ADCS1 7 A/D Conversion Clock Select bit 1 BANK0:ADCON0.ADCS0 6 A/D Conversion Clock Select bit 0 BANK0:ADCON0.CHS2 5 Analog Channel Select bit 2 BANK0:ADCON0.CHS1 4 Analog Channel Select bit 1 BANK0:ADCON0.CHS0 3 Analog Channel Select bit 0 BANK0:ADCON0.GO_DONE 2 A/D Conversion Status bit BANK0:ADCON0.CHS3 1 Analog Channel Select bit 3 BANK0:ADCON0.ADON 0 A/D On bit ; BANK1 (0x0080:0x0100) BANK1:INDF 0x0080 INDF (not a physical register) BANK1:OPTION 0x0081 OPTION REGISTER BANK1:OPTION.RBPU 7 PORTB Pull-up Enable bit BANK1:OPTION.INTEDG 6 Interrupt Edge Select bit BANK1:OPTION.T0CS 5 TMR0 Clock Source Select bit BANK1:OPTION.T0SE 4 TMR0 Source Edge Select bit BANK1:OPTION.PSA 3 Prescaler Assignment bit BANK1:OPTION.PS2 2 Prescaler Rate Select bit 2 BANK1:OPTION.PS1 1 Prescaler Rate Select bit 1 BANK1:OPTION.PS0 0 Prescaler Rate Select bit 0 BANK1:PCL 0x0082 Program Counter's (PC) Least Significant Byte BANK1:STATUS 0x0083 STATUS REGISTER BANK1:STATUS.IRP 7 Register Bank Select bit BANK1:STATUS.RP1 6 Register Bank Select bit 1 BANK1:STATUS.RP0 5 Register Bank Select bit 0 BANK1:STATUS.TO 4 Time-out bit BANK1:STATUS.PD 3 Power-down bit BANK1:STATUS.Z 2 Zero bit BANK1:STATUS.DC 1 Digit carry/borrow bit BANK1:STATUS.C 0 Carry/borrow bit BANK1:FSR 0x0084 Indirect data memory address pointer BANK1:TRISA 0x0085 PORTA Data Direction Register BANK1:TRISA.TRISA7 7 PORTA Data Direction Register bit 7 BANK1:TRISA.TRISA6 6 PORTA Data Direction Register bit 6 BANK1:TRISA.TRISA5 5 PORTA Data Direction Register bit 5 BANK1:TRISA.TRISA4 4 PORTA Data Direction Register bit 4 BANK1:TRISA.TRISA3 3 PORTA Data Direction Register bit 3 BANK1:TRISA.TRISA2 2 PORTA Data Direction Register bit 2 BANK1:TRISA.TRISA1 1 PORTA Data Direction Register bit 1 BANK1:TRISA.TRISA0 0 PORTA Data Direction Register bit 0 BANK1:TRISB 0x0086 PORTB Data Direction Register BANK1:TRISB.TRISB7 7 PORTB Data Direction Register bit 7 BANK1:TRISB.TRISB6 6 PORTB Data Direction Register bit 6 BANK1:TRISB.TRISB5 5 PORTB Data Direction Register bit 5 BANK1:TRISB.TRISB4 4 PORTB Data Direction Register bit 4 BANK1:TRISB.TRISB3 3 PORTB Data Direction Register bit 3 BANK1:TRISB.TRISB2 2 PORTB Data Direction Register bit 2 BANK1:TRISB.TRISB1 1 PORTB Data Direction Register bit 1 BANK1:TRISB.TRISB0 0 PORTB Data Direction Register bit 0 BANK1:RESERVED0087 0x0087 RESERVED BANK1:RESERVED0088 0x0088 RESERVED BANK1:RESERVED0089 0x0089 RESERVED BANK1:PCLATH 0x008A Write Buffer for the upper 5 bits of the Program Counter BANK1:INTCON 0x008B INTERRUPT CONTROL REGISTER BANK1:INTCON.GIE 7 Global Interrupt Enable bit BANK1:INTCON.PEIE 6 Peripheral Interrupt Enable bit BANK1:INTCON.T0IE 5 TMR0 Overflow Interrupt Enable bit BANK1:INTCON.INTE 4 RB0/INT External Interrupt Enable bit BANK1:INTCON.RBIE 3 RB Port Change Interrupt Enable bit BANK1:INTCON.T0IF 2 TMR0 Overflow Interrupt Flag bit BANK1:INTCON.INTF 1 RB0/INT External Interrupt Flag bit BANK1:INTCON.RBIF 0 RB Port Change Interrupt Flag bit BANK1:PIE1 0x008C PERIPHERAL INTERRUPT ENABLE REGISTER 1 BANK1:PIE1.ADIE 6 A/D Converter Interrupt Enable bit BANK1:PIE1.SSPIE 3 Synchronous Serial Port Interrupt Enable bit BANK1:PIE1.CCP1IE 2 CCP1 Interrupt Enable bit BANK1:PIE1.TMR2IE 1 TMR2 to PR2 Match Interrupt Enable bit BANK1:PIE1.TMR1IE 0 TMR1 Overflow Interrupt Enable bit BANK1:PIE2 0x008D PERIPHERAL INTERRUPT ENABLE REGISTER 2 BANK1:PIE2.LVDIE 7 Low Voltage Detect Interrupt Enable bit BANK1:PIE2.BCLIE 3 Bus Collision Interrupt Enable bit BANK1:PCON 0x008E POWER CONTROL REGISTER BANK1:PCON.OSCF 3 Oscillator Speed bit BANK1:PCON.POR 1 Power-on Reset Status bit BANK1:PCON.BOR 0 Brown-out Reset Status bit BANK1:RESERVED008F 0x008F RESERVED BANK1:RESERVED0090 0x0090 RESERVED BANK1:SSPCON2 0x0091 SYNC SERIAL PORT CONTROL REGISTER2 BANK1:SSPCON2.GCEN 7 General Call Enable bit (In I2C Slave mode only) BANK1:SSPCON2.ACKSTAT 6 Acknowledge Status bit (In I2C Master mode only) BANK1:SSPCON2.ACKDT 5 Acknowledge Data bit (In I2C Master mode only) BANK1:SSPCON2.ACKEN 4 Acknowledge Sequence Enable bit (In I2C Master mode only) BANK1:SSPCON2.RCEN 3 Receive Enable bit (In I2C Master mode only) BANK1:SSPCON2.PEN 2 STOP Condition Enable bit (In I2C Master mode only) BANK1:SSPCON2.RSEN 1 Repeated START Condition Enabled bit (In I2C Master mode only) BANK1:SSPCON2.SEN 0 START Condition Enabled bit (In I2C Master mode only) BANK1:PR2 0x0092 Timer2 Period Register BANK1:SSPADD 0x0093 Synchronous Serial Port (I2C mode) Address Register BANK1:SSPSTAT 0x0094 SYNC SERIAL PORT STATUS REGISTER BANK1:SSPSTAT.SMP 7 Sample bit BANK1:SSPSTAT.CKE 6 SPI Clock Edge Select BANK1:SSPSTAT.D_A 5 Data/Address bit (I2C mode only) BANK1:SSPSTAT.P 4 STOP bit (I2C mode only) BANK1:SSPSTAT.S 3 START bit (I2C mode only) BANK1:SSPSTAT.R_W 2 Read/Write bit information (I2C mode only) BANK1:SSPSTAT.UA 1 Update Address (I2C mode only) BANK1:SSPSTAT.BF 0 Buffer Full Status bit BANK1:WPUB 0x0095 PORTB Weak Pull-up Control BANK1:WPUB.WPUB7 7 PORTB Weak Pull-Up Control bit 7 BANK1:WPUB.WPUB6 6 PORTB Weak Pull-Up Control bit 6 BANK1:WPUB.WPUB5 5 PORTB Weak Pull-Up Control bit 5 BANK1:WPUB.WPUB4 4 PORTB Weak Pull-Up Control bit 4 BANK1:WPUB.WPUB3 3 PORTB Weak Pull-Up Control bit 3 BANK1:WPUB.WPUB2 2 PORTB Weak Pull-Up Control bit 2 BANK1:WPUB.WPUB1 1 PORTB Weak Pull-Up Control bit 1 BANK1:WPUB.WPUB0 0 PORTB Weak Pull-Up Control bit 0 BANK1:IOCB 0x0096 PORTB Interrupt on Change Control BANK1:IOCB.IOCB7 7 Interrupt-on-Change PORTB Control bit 7 BANK1:IOCB.IOCB6 6 Interrupt-on-Change PORTB Control bit 6 BANK1:IOCB.IOCB5 5 Interrupt-on-Change PORTB Control bit 5 BANK1:IOCB.IOCB4 4 Interrupt-on-Change PORTB Control bit 4 BANK1:IOCB.IOCB3 3 Interrupt-on-Change PORTB Control bit 3 BANK1:IOCB.IOCB2 2 Interrupt-on-Change PORTB Control bit 2 BANK1:IOCB.IOCB1 1 Interrupt-on-Change PORTB Control bit 1 BANK1:IOCB.IOCB0 0 Interrupt-on-Change PORTB Control bit 0 BANK1:P1DEL 0x0097 PWM 1 Delay value BANK1:P1DEL.P1DEL7 7 PWM Delay Count for Half-Bridge Output Mode 7 BANK1:P1DEL.P1DEL6 6 PWM Delay Count for Half-Bridge Output Mode 6 BANK1:P1DEL.P1DEL5 5 PWM Delay Count for Half-Bridge Output Mode 5 BANK1:P1DEL.P1DEL4 4 PWM Delay Count for Half-Bridge Output Mode 4 BANK1:P1DEL.P1DEL3 3 PWM Delay Count for Half-Bridge Output Mode 3 BANK1:P1DEL.P1DEL2 2 PWM Delay Count for Half-Bridge Output Mode 2 BANK1:P1DEL.P1DEL1 1 PWM Delay Count for Half-Bridge Output Mode 1 BANK1:P1DEL.P1DEL0 0 PWM Delay Count for Half-Bridge Output Mode 0 BANK1:RESERVED0098 0x0098 RESERVED BANK1:RESERVED0099 0x0099 RESERVED BANK1:RESERVED009A 0x009A RESERVED BANK1:REFCON 0x009B VOLTAGE REFERENCE CONTROL REGISTER BANK1:REFCON.VRHEN 7 Voltage Reference High Enable bit BANK1:REFCON.VRLEN 6 Voltage Reference Low Enable bit BANK1:REFCON.VRHOEN 5 High Voltage Reference Output Enable bit BANK1:REFCON.VRLOEN 4 Low Voltage Reference Output Enable bit BANK1:LVDCON 0x009C LOW-VOLTAGE DETECT CONTROL REGISTER BANK1:LVDCON.BGST 5 Bandgap Stable Status Flag bit BANK1:LVDCON.LVDEN 4 Low-voltage Detect Power Enable bit BANK1:LVDCON.LVV3 3 Low Voltage Detection Limit bit 3 BANK1:LVDCON.LVV2 2 Low Voltage Detection Limit bit 2 BANK1:LVDCON.LVV1 1 Low Voltage Detection Limit bit 1 BANK1:LVDCON.LVV0 0 Low Voltage Detection Limit bit 0 BANK1:ANSEL 0x009D Analog Channel Select BANK1:ADRESL 0x009E A/D Low Byte Result Register BANK1:ADCON1 0x009F A/D CONTROL REGISTER 1 BANK1:ADCON1.ADFM 7 A/D Result Format Select bit BANK1:ADCON1.VCFG2 6 Voltage Reference Configuration bit 2 BANK1:ADCON1.VCFG1 5 Voltage Reference Configuration bit 1 BANK1:ADCON1.VCFG0 4 Voltage Reference Configuration bit 0 ; BANK2 (0x0100:0x0180) BANK2:INDF 0x0100 INDF (not a physical register) BANK2:TMR0 0x0101 Timer0 module's register BANK2:PCL 0x0102 Program Counter's (PC) Least Significant Byte BANK2:STATUS 0x0103 STATUS REGISTER BANK2:STATUS.IRP 7 Register Bank Select bit BANK2:STATUS.RP1 6 Register Bank Select bit 1 BANK2:STATUS.RP0 5 Register Bank Select bit 0 BANK2:STATUS.TO 4 Time-out bit BANK2:STATUS.PD 3 Power-down bit BANK2:STATUS.Z 2 Zero bit BANK2:STATUS.DC 1 Digit carry/borrow bit BANK2:STATUS.C 0 Carry/borrow bit BANK2:FSR 0x0104 Indirect data memory address pointer BANK2:RESERVED0105 0x0105 RESERVED BANK2:PORTB 0x0106 PORTB REGISTER BANK2:PORTB.RB7 7 PORTB bit 7 BANK2:PORTB.RB6 6 PORTB bit 6 BANK2:PORTB.RB5 5 PORTB bit 5 BANK2:PORTB.RB4 4 PORTB bit 4 BANK2:PORTB.RB3 3 PORTB bit 3 BANK2:PORTB.RB2 2 PORTB bit 2 BANK2:PORTB.RB1 1 PORTB bit 1 BANK2:PORTB.RB0 0 PORTB bit 0 BANK2:RESERVED0107 0x0107 RESERVED BANK2:RESERVED0108 0x0108 RESERVED BANK2:RESERVED0109 0x0109 RESERVED BANK2:PCLATH 0x010A Write Buffer for the upper 5 bits of the Program Counter BANK2:INTCON 0x010B INTERRUPT CONTROL REGISTER BANK2:INTCON.GIE 7 Global Interrupt Enable bit BANK2:INTCON.PEIE 6 Peripheral Interrupt Enable bit BANK2:INTCON.T0IE 5 TMR0 Overflow Interrupt Enable bit BANK2:INTCON.INTE 4 RB0/INT External Interrupt Enable bit BANK2:INTCON.RBIE 3 RB Port Change Interrupt Enable bit BANK2:INTCON.T0IF 2 TMR0 Overflow Interrupt Flag bit BANK2:INTCON.INTF 1 RB0/INT External Interrupt Flag bit BANK2:INTCON.RBIF 0 RB Port Change Interrupt Flag bit BANK2:PMDATL 0x010C Program memory read data low BANK2:PMDATL.PMD7 7 BANK2:PMDATL.PMD6 6 BANK2:PMDATL.PMD5 5 BANK2:PMDATL.PMD4 4 BANK2:PMDATL.PMD3 3 BANK2:PMDATL.PMD2 2 BANK2:PMDATL.PMD1 1 BANK2:PMDATL.PMD0 0 BANK2:PMADRL 0x010D Program memory read address low BANK2:PMADRL.PMA7 7 BANK2:PMADRL.PMA6 6 BANK2:PMADRL.PMA5 5 BANK2:PMADRL.PMA4 4 BANK2:PMADRL.PMA3 3 BANK2:PMADRL.PMA2 2 BANK2:PMADRL.PMA1 1 BANK2:PMADRL.PMA0 0 BANK2:PMDATH 0x010E Program memory read data high BANK2:PMDATH.PMD13 5 BANK2:PMDATH.PMD12 4 BANK2:PMDATH.PMD11 3 BANK2:PMDATH.PMD10 2 BANK2:PMDATH.PMD9 1 BANK2:PMDATH.PMD8 0 BANK2:PMADRH 0x010F Program memory read address high BANK2:PMADRH.PMA11 3 BANK2:PMADRH.PMA10 2 BANK2:PMADRH.PMA9 1 BANK2:PMADRH.PMA8 0 BANK2:RESERVED0110 0x0110 RESERVED BANK2:RESERVED0111 0x0111 RESERVED BANK2:RESERVED0112 0x0112 RESERVED BANK2:RESERVED0113 0x0113 RESERVED BANK2:RESERVED0114 0x0114 RESERVED BANK2:RESERVED0115 0x0115 RESERVED BANK2:RESERVED0116 0x0116 RESERVED BANK2:RESERVED0117 0x0117 RESERVED BANK2:RESERVED0118 0x0118 RESERVED BANK2:RESERVED0119 0x0119 RESERVED BANK2:RESERVED011A 0x011A RESERVED BANK2:RESERVED011B 0x011B RESERVED BANK2:RESERVED011C 0x011C RESERVED BANK2:RESERVED011D 0x011D RESERVED BANK2:RESERVED011E 0x011E RESERVED BANK2:RESERVED011F 0x011F RESERVED ; BANK3 (0x0180:0x0200) BANK3:INDF 0x0180 INDF (not a physical register) BANK3:OPTION 0x0181 OPTION REGISTER BANK3:OPTION.RBPU 7 PORTB Pull-up Enable bit BANK3:OPTION.INTEDG 6 Interrupt Edge Select bit BANK3:OPTION.T0CS 5 TMR0 Clock Source Select bit BANK3:OPTION.T0SE 4 TMR0 Source Edge Select bit BANK3:OPTION.PSA 3 Prescaler Assignment bit BANK3:OPTION.PS2 2 Prescaler Rate Select bit 2 BANK3:OPTION.PS1 1 Prescaler Rate Select bit 1 BANK3:OPTION.PS0 0 Prescaler Rate Select bit 0 BANK3:PCL 0x0182 Program Counter's (PC) Least Significant Byte BANK3:STATUS 0x0183 STATUS REGISTER BANK3:STATUS.IRP 7 Register Bank Select bit BANK3:STATUS.RP1 6 Register Bank Select bit 1 BANK3:STATUS.RP0 5 Register Bank Select bit 0 BANK3:STATUS.TO 4 Time-out bit BANK3:STATUS.PD 3 Power-down bit BANK3:STATUS.Z 2 Zero bit BANK3:STATUS.DC 1 Digit carry/borrow bit BANK3:STATUS.C 0 Carry/borrow bit BANK3:FSR 0x0184 Indirect data memory address pointer BANK3:RESERVED0185 0x0185 RESERVED BANK3:TRISB 0x0186 PORTB Data Direction Register BANK3:TRISB.TRISB7 7 PORTB Data Direction Register bit 7 BANK3:TRISB.TRISB6 6 PORTB Data Direction Register bit 6 BANK3:TRISB.TRISB5 5 PORTB Data Direction Register bit 5 BANK3:TRISB.TRISB4 4 PORTB Data Direction Register bit 4 BANK3:TRISB.TRISB3 3 PORTB Data Direction Register bit 3 BANK3:TRISB.TRISB2 2 PORTB Data Direction Register bit 2 BANK3:TRISB.TRISB1 1 PORTB Data Direction Register bit 1 BANK3:TRISB.TRISB0 0 PORTB Data Direction Register bit 0 BANK3:RESERVED0187 0x0187 RESERVED BANK3:RESERVED0188 0x0188 RESERVED BANK3:RESERVED0189 0x0189 RESERVED BANK3:PCLATH 0x018A Write Buffer for the upper 5 bits of the Program Counter BANK3:INTCON 0x018B INTERRUPT CONTROL REGISTER BANK3:INTCON.GIE 7 Global Interrupt Enable bit BANK3:INTCON.PEIE 6 Peripheral Interrupt Enable bit BANK3:INTCON.T0IE 5 TMR0 Overflow Interrupt Enable bit BANK3:INTCON.INTE 4 RB0/INT External Interrupt Enable bit BANK3:INTCON.RBIE 3 RB Port Change Interrupt Enable bit BANK3:INTCON.T0IF 2 TMR0 Overflow Interrupt Flag bit BANK3:INTCON.INTF 1 RB0/INT External Interrupt Flag bit BANK3:INTCON.RBIF 0 RB Port Change Interrupt Flag bit BANK3:PMCON1 0x018C PROGRAM MEMORY READ CONTROL REGISTER 1 BANK3:PMCON1.RD 0 Read Control bit BANK3:RESERVED018D 0x018D RESERVED BANK3:RESERVED018E 0x018E RESERVED BANK3:RESERVED018F 0x018F RESERVED BANK3:RESERVED0190 0x0190 RESERVED BANK3:RESERVED0191 0x0191 RESERVED BANK3:RESERVED0192 0x0192 RESERVED BANK3:RESERVED0193 0x0193 RESERVED BANK3:RESERVED0194 0x0194 RESERVED BANK3:RESERVED0195 0x0195 RESERVED BANK3:RESERVED0196 0x0196 RESERVED BANK3:RESERVED0197 0x0197 RESERVED BANK3:RESERVED0198 0x0198 RESERVED BANK3:RESERVED0199 0x0199 RESERVED BANK3:RESERVED019A 0x019A RESERVED BANK3:RESERVED019B 0x019B RESERVED BANK3:RESERVED019C 0x019C RESERVED BANK3:RESERVED019D 0x019D RESERVED BANK3:RESERVED019E 0x019E RESERVED BANK3:RESERVED019F 0x019F RESERVED .16C771 ; http://www.microchip.com/download/lit/pline/picmicro/families/16c71x/41120b.pdf ; PIC16C717_70_71.pdf ; MEMORY MAP ; BANK_0 area DATA FSR_ 0x0000:0x0020 area DATA Gen_Purp 0x0020:0x0080 General Purpose Register area DATA MEM_Program0 0x0080:0x0800 On-chip Program Memory (Page 0) area DATA MEM_Program1 0x0800:0x1000 On-chip Program Memory (Page 1) ; BANK_1 ; area DATA FSR_ 0x0080:0x00A0 ; area DATA Gen_Purp 0x00A0:0x00F0 General Purpose Register ; area DATA Gen_Purp_BANK0 0x00F0:0x0100 accesses 70h-7Fh ; area DATA MEM_Program0 0x0100:0x0800 On-chip Program Memory (Page 0) ; area DATA MEM_Program1 0x0800:0x1000 On-chip Program Memory (Page 1) ; BANK_2 ; area DATA FSR_ 0x0100:0x0120 ; area DATA Gen_Purp 0x0120:0x0170 General Purpose Register ; area DATA Gen_Purp_BANK0 0x0170:0x0180 accesses 70h-7Fh ; area DATA MEM_Program0 0x0180:0x0800 On-chip Program Memory (Page 0) ; area DATA MEM_Program1 0x0800:0x1000 On-chip Program Memory (Page 1) ; BANK_3 ; area DATA FSR_ 0x0180:0x01A0 ; area BSS RESERVED 0x01A0:0x01F0 ; area DATA Gen_Purp_BANK0 0x01F0:0x0200 accesses 70h-7Fh ; area DATA MEM_Program0 0x0200:0x0800 On-chip Program Memory (Page 0) ; area DATA MEM_Program1 0x0800:0x1000 On-chip Program Memory (Page 1) ; Interrupt and reset vector assignments interrupt RESET 0x0000 RESET ; INPUT/OUTPUT PORTS ; BANK0 (0x0000:0x0080) BANK0:INDF 0x0000 INDF (not a physical register) BANK0:TMR0 0x0001 Timer0 module's register BANK0:PCL 0x0002 Program Counter's (PC) Least Significant Byte BANK0:STATUS 0x0003 STATUS REGISTER BANK0:STATUS.IRP 7 Register Bank Select bit BANK0:STATUS.RP1 6 Register Bank Select bit 1 BANK0:STATUS.RP0 5 Register Bank Select bit 0 BANK0:STATUS.TO 4 Time-out bit BANK0:STATUS.PD 3 Power-down bit BANK0:STATUS.Z 2 Zero bit BANK0:STATUS.DC 1 Digit carry/borrow bit BANK0:STATUS.C 0 Carry/borrow bit BANK0:FSR 0x0004 Indirect data memory address pointer BANK0:PORTA 0x0005 PORTA REGISTER BANK0:PORTA.RA7 7 PORTA bit 7 BANK0:PORTA.RA6 6 PORTA bit 6 BANK0:PORTA.RA5 5 PORTA bit 5 BANK0:PORTA.RA4 4 PORTA bit 4 BANK0:PORTA.RA3 3 PORTA bit 3 BANK0:PORTA.RA2 2 PORTA bit 2 BANK0:PORTA.RA1 1 PORTA bit 1 BANK0:PORTA.RA0 0 PORTA bit 0 BANK0:PORTB 0x0006 PORTB REGISTER BANK0:PORTB.RB7 7 PORTB bit 7 BANK0:PORTB.RB6 6 PORTB bit 6 BANK0:PORTB.RB5 5 PORTB bit 5 BANK0:PORTB.RB4 4 PORTB bit 4 BANK0:PORTB.RB3 3 PORTB bit 3 BANK0:PORTB.RB2 2 PORTB bit 2 BANK0:PORTB.RB1 1 PORTB bit 1 BANK0:PORTB.RB0 0 PORTB bit 0 BANK0:RESERVED0007 0x0007 RESERVED BANK0:RESERVED0008 0x0008 RESERVED BANK0:RESERVED0009 0x0009 RESERVED BANK0:PCLATH 0x000A Write Buffer for the upper 5 bits of the Program Counter BANK0:INTCON 0x000B INTERRUPT CONTROL REGISTER BANK0:INTCON.GIE 7 Global Interrupt Enable bit BANK0:INTCON.PEIE 6 Peripheral Interrupt Enable bit BANK0:INTCON.T0IE 5 TMR0 Overflow Interrupt Enable bit BANK0:INTCON.INTE 4 RB0/INT External Interrupt Enable bit BANK0:INTCON.RBIE 3 RB Port Change Interrupt Enable bit BANK0:INTCON.T0IF 2 TMR0 Overflow Interrupt Flag bit BANK0:INTCON.INTF 1 RB0/INT External Interrupt Flag bit BANK0:INTCON.RBIF 0 RB Port Change Interrupt Flag bit BANK0:PIR1 0x000C PERIPHERAL INTERRUPT REGISTER 1 BANK0:PIR1.ADIF 6 A/D Converter Interrupt Flag bit BANK0:PIR1.SSPIF 3 Synchronous Serial Port (SSP) Interrupt Flag BANK0:PIR1.CCP1IF 2 CCP1 Interrupt Flag bit BANK0:PIR1.TMR2IF 1 TMR2 to PR2 Match Interrupt Flag bit BANK0:PIR1.TMR1IF 0 TMR1 Overflow Interrupt Flag bit BANK0:PIR2 0x000D PERIPHERAL INTERRUPT REGISTER 2 BANK0:PIR2.LVDIF 7 Low Voltage Detect Interrupt Flag bit BANK0:PIR2.BCLIF 3 Bus Collision Interrupt Flag bit BANK0:TMR1L 0x000E Holding register for the Least Significant Byte of the 16-bit TMR1 register BANK0:TMR1H 0x000F Holding register for the Most Significant Byte of the 16-bit TMR1 register BANK0:T1CON 0x0010 TIMER1 CONTROL REGISTER BANK0:T1CON.T1CKPS1 5 Timer1 Input Clock Prescale Select bit 1 BANK0:T1CON.T1CKPS0 4 Timer1 Input Clock Prescale Select bit 0 BANK0:T1CON.T1OSCEN 3 Timer1 Oscillator Enable Control bit BANK0:T1CON.T1SYNC 2 Timer1 External Clock Input Synchronization Control bit BANK0:T1CON.TMR1CS 1 Timer1 Clock Source Select bit BANK0:T1CON.TMR1ON 0 Timer1 On bit BANK0:TMR2 0x0011 Timer2 module's register BANK0:T2CON 0x0012 TIMER2 CONTROL REGISTER BANK0:T2CON.TOUTPS3 6 Timer2 Output Postscale Select bit 3 BANK0:T2CON.TOUTPS2 5 Timer2 Output Postscale Select bit 2 BANK0:T2CON.TOUTPS1 4 Timer2 Output Postscale Select bit 1 BANK0:T2CON.TOUTPS0 3 Timer2 Output Postscale Select bit 0 BANK0:T2CON.TMR2ON 2 Timer2 On bit BANK0:T2CON.T2CKPS1 1 Timer2 Clock Prescale Select bit 1 BANK0:T2CON.T2CKPS0 0 Timer2 Clock Prescale Select bit 0 BANK0:SSPBUF 0x0013 Synchronous Serial Port Receive Buffer/Transmit Register BANK0:SSPCON 0x0014 SYNC SERIAL PORT CONTROL REGISTER BANK0:SSPCON.WCOL 7 Write Collision Detect bit BANK0:SSPCON.SSPOV 6 Receive Overflow Indicator bit BANK0:SSPCON.SSPEN 5 Synchronous Serial Port Enable bit BANK0:SSPCON.CKP 4 Clock Polarity Select bit BANK0:SSPCON.SSPM3 3 Synchronous Serial Port Mode Select bit 3 BANK0:SSPCON.SSPM2 2 Synchronous Serial Port Mode Select bit 2 BANK0:SSPCON.SSPM1 1 Synchronous Serial Port Mode Select bit 1 BANK0:SSPCON.SSPM0 0 Synchronous Serial Port Mode Select bit 0 BANK0:CCPR1L 0x0015 Capture/Compare/PWM Register1 (LSB) BANK0:CCPR1H 0x0016 Capture/Compare/PWM Register1 (MSB) BANK0:CCP1CON 0x0017 CCP1 CONTROL REGISTER BANK0:CCP1CON.PWM1M1 7 PWM Output Configuration 1 BANK0:CCP1CON.PWM1M0 6 PWM Output Configuration 0 BANK0:CCP1CON.DC1B1 5 PWM Duty Cycle Least Significant bit 1 BANK0:CCP1CON.DC1B0 4 PWM Duty Cycle Least Significant bit 0 BANK0:CCP1CON.CCP1M3 3 ECCP Mode Select bit 3 BANK0:CCP1CON.CCP1M2 2 ECCP Mode Select bit 2 BANK0:CCP1CON.CCP1M1 1 ECCP Mode Select bit 1 BANK0:CCP1CON.CCP1M0 0 ECCP Mode Select bit 0 BANK0:RESERVED0018 0x0018 RESERVED BANK0:RESERVED0019 0x0019 RESERVED BANK0:RESERVED001A 0x001A RESERVED BANK0:RESERVED001B 0x001B RESERVED BANK0:RESERVED001C 0x001C RESERVED BANK0:RESERVED001D 0x001D RESERVED BANK0:ADRESH 0x001E A/D High Byte Result Register BANK0:ADCON0 0x001F A/D CONTROL REGISTER 0 BANK0:ADCON0.ADCS1 7 A/D Conversion Clock Select bit 1 BANK0:ADCON0.ADCS0 6 A/D Conversion Clock Select bit 0 BANK0:ADCON0.CHS2 5 Analog Channel Select bit 2 BANK0:ADCON0.CHS1 4 Analog Channel Select bit 1 BANK0:ADCON0.CHS0 3 Analog Channel Select bit 0 BANK0:ADCON0.GO_DONE 2 A/D Conversion Status bit BANK0:ADCON0.CHS3 1 Analog Channel Select bit 3 BANK0:ADCON0.ADON 0 A/D On bit ; BANK1 (0x0080:0x0100) BANK1:INDF 0x0080 INDF (not a physical register) BANK1:OPTION 0x0081 OPTION REGISTER BANK1:OPTION.RBPU 7 PORTB Pull-up Enable bit BANK1:OPTION.INTEDG 6 Interrupt Edge Select bit BANK1:OPTION.T0CS 5 TMR0 Clock Source Select bit BANK1:OPTION.T0SE 4 TMR0 Source Edge Select bit BANK1:OPTION.PSA 3 Prescaler Assignment bit BANK1:OPTION.PS2 2 Prescaler Rate Select bit 2 BANK1:OPTION.PS1 1 Prescaler Rate Select bit 1 BANK1:OPTION.PS0 0 Prescaler Rate Select bit 0 BANK1:PCL 0x0082 Program Counter's (PC) Least Significant Byte BANK1:STATUS 0x0083 STATUS REGISTER BANK1:STATUS.IRP 7 Register Bank Select bit BANK1:STATUS.RP1 6 Register Bank Select bit 1 BANK1:STATUS.RP0 5 Register Bank Select bit 0 BANK1:STATUS.TO 4 Time-out bit BANK1:STATUS.PD 3 Power-down bit BANK1:STATUS.Z 2 Zero bit BANK1:STATUS.DC 1 Digit carry/borrow bit BANK1:STATUS.C 0 Carry/borrow bit BANK1:FSR 0x0084 Indirect data memory address pointer BANK1:TRISA 0x0085 PORTA Data Direction Register BANK1:TRISA.TRISA7 7 PORTA Data Direction Register bit 7 BANK1:TRISA.TRISA6 6 PORTA Data Direction Register bit 6 BANK1:TRISA.TRISA5 5 PORTA Data Direction Register bit 5 BANK1:TRISA.TRISA4 4 PORTA Data Direction Register bit 4 BANK1:TRISA.TRISA3 3 PORTA Data Direction Register bit 3 BANK1:TRISA.TRISA2 2 PORTA Data Direction Register bit 2 BANK1:TRISA.TRISA1 1 PORTA Data Direction Register bit 1 BANK1:TRISA.TRISA0 0 PORTA Data Direction Register bit 0 BANK1:TRISB 0x0086 PORTB Data Direction Register BANK1:TRISB.TRISB7 7 PORTB Data Direction Register bit 7 BANK1:TRISB.TRISB6 6 PORTB Data Direction Register bit 6 BANK1:TRISB.TRISB5 5 PORTB Data Direction Register bit 5 BANK1:TRISB.TRISB4 4 PORTB Data Direction Register bit 4 BANK1:TRISB.TRISB3 3 PORTB Data Direction Register bit 3 BANK1:TRISB.TRISB2 2 PORTB Data Direction Register bit 2 BANK1:TRISB.TRISB1 1 PORTB Data Direction Register bit 1 BANK1:TRISB.TRISB0 0 PORTB Data Direction Register bit 0 BANK1:RESERVED0087 0x0087 RESERVED BANK1:RESERVED0088 0x0088 RESERVED BANK1:RESERVED0089 0x0089 RESERVED BANK1:PCLATH 0x008A Write Buffer for the upper 5 bits of the Program Counter BANK1:INTCON 0x008B INTERRUPT CONTROL REGISTER BANK1:INTCON.GIE 7 Global Interrupt Enable bit BANK1:INTCON.PEIE 6 Peripheral Interrupt Enable bit BANK1:INTCON.T0IE 5 TMR0 Overflow Interrupt Enable bit BANK1:INTCON.INTE 4 RB0/INT External Interrupt Enable bit BANK1:INTCON.RBIE 3 RB Port Change Interrupt Enable bit BANK1:INTCON.T0IF 2 TMR0 Overflow Interrupt Flag bit BANK1:INTCON.INTF 1 RB0/INT External Interrupt Flag bit BANK1:INTCON.RBIF 0 RB Port Change Interrupt Flag bit BANK1:PIE1 0x008C PERIPHERAL INTERRUPT ENABLE REGISTER 1 BANK1:PIE1.ADIE 6 A/D Converter Interrupt Enable bit BANK1:PIE1.SSPIE 3 Synchronous Serial Port Interrupt Enable bit BANK1:PIE1.CCP1IE 2 CCP1 Interrupt Enable bit BANK1:PIE1.TMR2IE 1 TMR2 to PR2 Match Interrupt Enable bit BANK1:PIE1.TMR1IE 0 TMR1 Overflow Interrupt Enable bit BANK1:PIE2 0x008D PERIPHERAL INTERRUPT ENABLE REGISTER 2 BANK1:PIE2.LVDIE 7 Low Voltage Detect Interrupt Enable bit BANK1:PIE2.BCLIE 3 Bus Collision Interrupt Enable bit BANK1:PCON 0x008E POWER CONTROL REGISTER BANK1:PCON.OSCF 3 Oscillator Speed bit BANK1:PCON.POR 1 Power-on Reset Status bit BANK1:PCON.BOR 0 Brown-out Reset Status bit BANK1:RESERVED008F 0x008F RESERVED BANK1:RESERVED0090 0x0090 RESERVED BANK1:SSPCON2 0x0091 SYNC SERIAL PORT CONTROL REGISTER2 BANK1:SSPCON2.GCEN 7 General Call Enable bit (In I2C Slave mode only) BANK1:SSPCON2.ACKSTAT 6 Acknowledge Status bit (In I2C Master mode only) BANK1:SSPCON2.ACKDT 5 Acknowledge Data bit (In I2C Master mode only) BANK1:SSPCON2.ACKEN 4 Acknowledge Sequence Enable bit (In I2C Master mode only) BANK1:SSPCON2.RCEN 3 Receive Enable bit (In I2C Master mode only) BANK1:SSPCON2.PEN 2 STOP Condition Enable bit (In I2C Master mode only) BANK1:SSPCON2.RSEN 1 Repeated START Condition Enabled bit (In I2C Master mode only) BANK1:SSPCON2.SEN 0 START Condition Enabled bit (In I2C Master mode only) BANK1:PR2 0x0092 Timer2 Period Register BANK1:SSPADD 0x0093 Synchronous Serial Port (I2C mode) Address Register BANK1:SSPSTAT 0x0094 SYNC SERIAL PORT STATUS REGISTER BANK1:SSPSTAT.SMP 7 Sample bit BANK1:SSPSTAT.CKE 6 SPI Clock Edge Select BANK1:SSPSTAT.D_A 5 Data/Address bit (I2C mode only) BANK1:SSPSTAT.P 4 STOP bit (I2C mode only) BANK1:SSPSTAT.S 3 START bit (I2C mode only) BANK1:SSPSTAT.R_W 2 Read/Write bit information (I2C mode only) BANK1:SSPSTAT.UA 1 Update Address (I2C mode only) BANK1:SSPSTAT.BF 0 Buffer Full Status bit BANK1:WPUB 0x0095 PORTB Weak Pull-up Control BANK1:WPUB.WPUB7 7 PORTB Weak Pull-Up Control bit 7 BANK1:WPUB.WPUB6 6 PORTB Weak Pull-Up Control bit 6 BANK1:WPUB.WPUB5 5 PORTB Weak Pull-Up Control bit 5 BANK1:WPUB.WPUB4 4 PORTB Weak Pull-Up Control bit 4 BANK1:WPUB.WPUB3 3 PORTB Weak Pull-Up Control bit 3 BANK1:WPUB.WPUB2 2 PORTB Weak Pull-Up Control bit 2 BANK1:WPUB.WPUB1 1 PORTB Weak Pull-Up Control bit 1 BANK1:WPUB.WPUB0 0 PORTB Weak Pull-Up Control bit 0 BANK1:IOCB 0x0096 PORTB Interrupt on Change Control BANK1:IOCB.IOCB7 7 Interrupt-on-Change PORTB Control bit 7 BANK1:IOCB.IOCB6 6 Interrupt-on-Change PORTB Control bit 6 BANK1:IOCB.IOCB5 5 Interrupt-on-Change PORTB Control bit 5 BANK1:IOCB.IOCB4 4 Interrupt-on-Change PORTB Control bit 4 BANK1:IOCB.IOCB3 3 Interrupt-on-Change PORTB Control bit 3 BANK1:IOCB.IOCB2 2 Interrupt-on-Change PORTB Control bit 2 BANK1:IOCB.IOCB1 1 Interrupt-on-Change PORTB Control bit 1 BANK1:IOCB.IOCB0 0 Interrupt-on-Change PORTB Control bit 0 BANK1:P1DEL 0x0097 PWM 1 Delay value BANK1:P1DEL.P1DEL7 7 PWM Delay Count for Half-Bridge Output Mode 7 BANK1:P1DEL.P1DEL6 6 PWM Delay Count for Half-Bridge Output Mode 6 BANK1:P1DEL.P1DEL5 5 PWM Delay Count for Half-Bridge Output Mode 5 BANK1:P1DEL.P1DEL4 4 PWM Delay Count for Half-Bridge Output Mode 4 BANK1:P1DEL.P1DEL3 3 PWM Delay Count for Half-Bridge Output Mode 3 BANK1:P1DEL.P1DEL2 2 PWM Delay Count for Half-Bridge Output Mode 2 BANK1:P1DEL.P1DEL1 1 PWM Delay Count for Half-Bridge Output Mode 1 BANK1:P1DEL.P1DEL0 0 PWM Delay Count for Half-Bridge Output Mode 0 BANK1:RESERVED0098 0x0098 RESERVED BANK1:RESERVED0099 0x0099 RESERVED BANK1:RESERVED009A 0x009A RESERVED BANK1:REFCON 0x009B VOLTAGE REFERENCE CONTROL REGISTER BANK1:REFCON.VRHEN 7 Voltage Reference High Enable bit BANK1:REFCON.VRLEN 6 Voltage Reference Low Enable bit BANK1:REFCON.VRHOEN 5 High Voltage Reference Output Enable bit BANK1:REFCON.VRLOEN 4 Low Voltage Reference Output Enable bit BANK1:LVDCON 0x009C LOW-VOLTAGE DETECT CONTROL REGISTER BANK1:LVDCON.BGST 5 Bandgap Stable Status Flag bit BANK1:LVDCON.LVDEN 4 Low-voltage Detect Power Enable bit BANK1:LVDCON.LVV3 3 Low Voltage Detection Limit bit 3 BANK1:LVDCON.LVV2 2 Low Voltage Detection Limit bit 2 BANK1:LVDCON.LVV1 1 Low Voltage Detection Limit bit 1 BANK1:LVDCON.LVV0 0 Low Voltage Detection Limit bit 0 BANK1:ANSEL 0x009D Analog Channel Select BANK1:ADRESL 0x009E A/D Low Byte Result Register BANK1:ADCON1 0x009F A/D CONTROL REGISTER 1 BANK1:ADCON1.ADFM 7 A/D Result Format Select bit BANK1:ADCON1.VCFG2 6 Voltage Reference Configuration bit 2 BANK1:ADCON1.VCFG1 5 Voltage Reference Configuration bit 1 BANK1:ADCON1.VCFG0 4 Voltage Reference Configuration bit 0 ; BANK2 (0x0100:0x0180) BANK2:INDF 0x0100 INDF (not a physical register) BANK2:TMR0 0x0101 Timer0 module's register BANK2:PCL 0x0102 Program Counter's (PC) Least Significant Byte BANK2:STATUS 0x0103 STATUS REGISTER BANK2:STATUS.IRP 7 Register Bank Select bit BANK2:STATUS.RP1 6 Register Bank Select bit 1 BANK2:STATUS.RP0 5 Register Bank Select bit 0 BANK2:STATUS.TO 4 Time-out bit BANK2:STATUS.PD 3 Power-down bit BANK2:STATUS.Z 2 Zero bit BANK2:STATUS.DC 1 Digit carry/borrow bit BANK2:STATUS.C 0 Carry/borrow bit BANK2:FSR 0x0104 Indirect data memory address pointer BANK2:RESERVED0105 0x0105 RESERVED BANK2:PORTB 0x0106 PORTB REGISTER BANK2:PORTB.RB7 7 PORTB bit 7 BANK2:PORTB.RB6 6 PORTB bit 6 BANK2:PORTB.RB5 5 PORTB bit 5 BANK2:PORTB.RB4 4 PORTB bit 4 BANK2:PORTB.RB3 3 PORTB bit 3 BANK2:PORTB.RB2 2 PORTB bit 2 BANK2:PORTB.RB1 1 PORTB bit 1 BANK2:PORTB.RB0 0 PORTB bit 0 BANK2:RESERVED0107 0x0107 RESERVED BANK2:RESERVED0108 0x0108 RESERVED BANK2:RESERVED0109 0x0109 RESERVED BANK2:PCLATH 0x010A Write Buffer for the upper 5 bits of the Program Counter BANK2:INTCON 0x010B INTERRUPT CONTROL REGISTER BANK2:INTCON.GIE 7 Global Interrupt Enable bit BANK2:INTCON.PEIE 6 Peripheral Interrupt Enable bit BANK2:INTCON.T0IE 5 TMR0 Overflow Interrupt Enable bit BANK2:INTCON.INTE 4 RB0/INT External Interrupt Enable bit BANK2:INTCON.RBIE 3 RB Port Change Interrupt Enable bit BANK2:INTCON.T0IF 2 TMR0 Overflow Interrupt Flag bit BANK2:INTCON.INTF 1 RB0/INT External Interrupt Flag bit BANK2:INTCON.RBIF 0 RB Port Change Interrupt Flag bit BANK2:PMDATL 0x010C Program memory read data low BANK2:PMDATL.PMD7 7 BANK2:PMDATL.PMD6 6 BANK2:PMDATL.PMD5 5 BANK2:PMDATL.PMD4 4 BANK2:PMDATL.PMD3 3 BANK2:PMDATL.PMD2 2 BANK2:PMDATL.PMD1 1 BANK2:PMDATL.PMD0 0 BANK2:PMADRL 0x010D Program memory read address low BANK2:PMADRL.PMA7 7 BANK2:PMADRL.PMA6 6 BANK2:PMADRL.PMA5 5 BANK2:PMADRL.PMA4 4 BANK2:PMADRL.PMA3 3 BANK2:PMADRL.PMA2 2 BANK2:PMADRL.PMA1 1 BANK2:PMADRL.PMA0 0 BANK2:PMDATH 0x010E Program memory read data high BANK2:PMDATH.PMD13 5 BANK2:PMDATH.PMD12 4 BANK2:PMDATH.PMD11 3 BANK2:PMDATH.PMD10 2 BANK2:PMDATH.PMD9 1 BANK2:PMDATH.PMD8 0 BANK2:PMADRH 0x010F Program memory read address high BANK2:PMADRH.PMA11 3 BANK2:PMADRH.PMA10 2 BANK2:PMADRH.PMA9 1 BANK2:PMADRH.PMA8 0 BANK2:RESERVED0110 0x0110 RESERVED BANK2:RESERVED0111 0x0111 RESERVED BANK2:RESERVED0112 0x0112 RESERVED BANK2:RESERVED0113 0x0113 RESERVED BANK2:RESERVED0114 0x0114 RESERVED BANK2:RESERVED0115 0x0115 RESERVED BANK2:RESERVED0116 0x0116 RESERVED BANK2:RESERVED0117 0x0117 RESERVED BANK2:RESERVED0118 0x0118 RESERVED BANK2:RESERVED0119 0x0119 RESERVED BANK2:RESERVED011A 0x011A RESERVED BANK2:RESERVED011B 0x011B RESERVED BANK2:RESERVED011C 0x011C RESERVED BANK2:RESERVED011D 0x011D RESERVED BANK2:RESERVED011E 0x011E RESERVED BANK2:RESERVED011F 0x011F RESERVED ; BANK3 (0x0180:0x0200) BANK3:INDF 0x0180 INDF (not a physical register) BANK3:OPTION 0x0181 OPTION REGISTER BANK3:OPTION.RBPU 7 PORTB Pull-up Enable bit BANK3:OPTION.INTEDG 6 Interrupt Edge Select bit BANK3:OPTION.T0CS 5 TMR0 Clock Source Select bit BANK3:OPTION.T0SE 4 TMR0 Source Edge Select bit BANK3:OPTION.PSA 3 Prescaler Assignment bit BANK3:OPTION.PS2 2 Prescaler Rate Select bit 2 BANK3:OPTION.PS1 1 Prescaler Rate Select bit 1 BANK3:OPTION.PS0 0 Prescaler Rate Select bit 0 BANK3:PCL 0x0182 Program Counter's (PC) Least Significant Byte BANK3:STATUS 0x0183 STATUS REGISTER BANK3:STATUS.IRP 7 Register Bank Select bit BANK3:STATUS.RP1 6 Register Bank Select bit 1 BANK3:STATUS.RP0 5 Register Bank Select bit 0 BANK3:STATUS.TO 4 Time-out bit BANK3:STATUS.PD 3 Power-down bit BANK3:STATUS.Z 2 Zero bit BANK3:STATUS.DC 1 Digit carry/borrow bit BANK3:STATUS.C 0 Carry/borrow bit BANK3:FSR 0x0184 Indirect data memory address pointer BANK3:RESERVED0185 0x0185 RESERVED BANK3:TRISB 0x0186 PORTB Data Direction Register BANK3:TRISB.TRISB7 7 PORTB Data Direction Register bit 7 BANK3:TRISB.TRISB6 6 PORTB Data Direction Register bit 6 BANK3:TRISB.TRISB5 5 PORTB Data Direction Register bit 5 BANK3:TRISB.TRISB4 4 PORTB Data Direction Register bit 4 BANK3:TRISB.TRISB3 3 PORTB Data Direction Register bit 3 BANK3:TRISB.TRISB2 2 PORTB Data Direction Register bit 2 BANK3:TRISB.TRISB1 1 PORTB Data Direction Register bit 1 BANK3:TRISB.TRISB0 0 PORTB Data Direction Register bit 0 BANK3:RESERVED0187 0x0187 RESERVED BANK3:RESERVED0188 0x0188 RESERVED BANK3:RESERVED0189 0x0189 RESERVED BANK3:PCLATH 0x018A Write Buffer for the upper 5 bits of the Program Counter BANK3:INTCON 0x018B INTERRUPT CONTROL REGISTER BANK3:INTCON.GIE 7 Global Interrupt Enable bit BANK3:INTCON.PEIE 6 Peripheral Interrupt Enable bit BANK3:INTCON.T0IE 5 TMR0 Overflow Interrupt Enable bit BANK3:INTCON.INTE 4 RB0/INT External Interrupt Enable bit BANK3:INTCON.RBIE 3 RB Port Change Interrupt Enable bit BANK3:INTCON.T0IF 2 TMR0 Overflow Interrupt Flag bit BANK3:INTCON.INTF 1 RB0/INT External Interrupt Flag bit BANK3:INTCON.RBIF 0 RB Port Change Interrupt Flag bit BANK3:PMCON1 0x018C PROGRAM MEMORY READ CONTROL REGISTER 1 BANK3:PMCON1.RD 0 Read Control bit BANK3:RESERVED018D 0x018D RESERVED BANK3:RESERVED018E 0x018E RESERVED BANK3:RESERVED018F 0x018F RESERVED BANK3:RESERVED0190 0x0190 RESERVED BANK3:RESERVED0191 0x0191 RESERVED BANK3:RESERVED0192 0x0192 RESERVED BANK3:RESERVED0193 0x0193 RESERVED BANK3:RESERVED0194 0x0194 RESERVED BANK3:RESERVED0195 0x0195 RESERVED BANK3:RESERVED0196 0x0196 RESERVED BANK3:RESERVED0197 0x0197 RESERVED BANK3:RESERVED0198 0x0198 RESERVED BANK3:RESERVED0199 0x0199 RESERVED BANK3:RESERVED019A 0x019A RESERVED BANK3:RESERVED019B 0x019B RESERVED BANK3:RESERVED019C 0x019C RESERVED BANK3:RESERVED019D 0x019D RESERVED BANK3:RESERVED019E 0x019E RESERVED BANK3:RESERVED019F 0x019F RESERVED .16C71 ; http://www.microchip.com/download/lit/pline/picmicro/families/16c7x/30272a.pdf ; PIC16C71X.pdf ; MEMORY MAP ; BANK_0 area DATA FSR_ 0x0000:0x000C area DATA Gen_Purp 0x000C:0x0030 General Purpose Register area BSS RESERVED 0x0030:0x0080 area DATA MEM_Program 0x0080:0x0400 On-chip Program Memory ; BANK_1 ; area DATA FSR_ 0x0080:0x008C ; area DATA Gen_Purp 0x008C:0x00B0 Mapped in Bank 0 ; area BSS RESERVED 0x00B0:0x0100 ; area DATA MEM_Program 0x0100:0x0400 On-chip Program Memory ; Interrupt and reset vector assignments interrupt RESET 0x0000 RESET ; INPUT/OUTPUT PORTS ; BANK0 (0x0000:0x0080) BANK0:INDF 0x0000 INDF (not a physical register) BANK0:TMR0 0x0001 Timer0 module's register BANK0:PCL 0x0002 Program Counter's (PC) Least Significant Byte BANK0:STATUS 0x0003 STATUS REGISTER BANK0:STATUS.RP0 5 Register Bank Select bit 0 BANK0:STATUS.TO 4 Time-out bit BANK0:STATUS.PD 3 Power-down bit BANK0:STATUS.Z 2 Zero bit BANK0:STATUS.DC 1 Digit carry/borrow bit BANK0:STATUS.C 0 Carry/borrow bit BANK0:FSR 0x0004 Indirect data memory address pointer BANK0:PORTA 0x0005 PORTA REGISTER BANK0:PORTA.RA4 4 PORTA bit 4 BANK0:PORTA.RA3 3 PORTA bit 3 BANK0:PORTA.RA2 2 PORTA bit 2 BANK0:PORTA.RA1 1 PORTA bit 1 BANK0:PORTA.RA0 0 PORTA bit 0 BANK0:PORTB 0x0006 PORTB REGISTER BANK0:PORTB.RB7 7 PORTB bit 7 BANK0:PORTB.RB6 6 PORTB bit 6 BANK0:PORTB.RB5 5 PORTB bit 5 BANK0:PORTB.RB4 4 PORTB bit 4 BANK0:PORTB.RB3 3 PORTB bit 3 BANK0:PORTB.RB2 2 PORTB bit 2 BANK0:PORTB.RB1 1 PORTB bit 1 BANK0:PORTB.RB0 0 PORTB bit 0 BANK0:RESERVED0007 0x0007 RESERVED BANK0:ADCON0 0x0008 ADCON0 REGISTER BANK0:ADCON0.ADCS1 7 A/D Conversion Clock Select bit 1 BANK0:ADCON0.ADCS0 6 A/D Conversion Clock Select bit 0 BANK0:ADCON0.CHS1 4 Analog Channel Select bit 1 BANK0:ADCON0.CHS0 3 Analog Channel Select bit 0 BANK0:ADCON0.GO_DONE 2 A/D Conversion Status bit BANK0:ADCON0.ADIF 1 A/D Conversion Complete Interrupt Flag bit BANK0:ADCON0.ADON 0 A/D On bit BANK0:ADRES 0x0009 A/D Result Register BANK0:PCLATH 0x000A Write Buffer for the upper 5 bits of the Program Counter BANK0:INTCON 0x000B INTCON REGISTER BANK0:INTCON.GIE 7 Global Interrupt Enable bit BANK0:INTCON.ADIE 6 A/D Converter Interrupt Enable bit BANK0:INTCON.T0IE 5 TMR0 Overflow Interrupt Enable bit BANK0:INTCON.INTE 4 RB0/INT External Interrupt Enable bit BANK0:INTCON.RBIE 3 RB Port Change Interrupt Enable bit BANK0:INTCON.T0IF 2 TMR0 Overflow Interrupt Flag bit BANK0:INTCON.INTF 1 RB0/INT External Interrupt Flag bit BANK0:INTCON.RBIF 0 RB Port Change Interrupt Flag bit ; BANK1 (0x0080:0x0100) BANK1:INDF 0x0080 INDF (not a physical register) BANK1:OPTION 0x0081 OPTION REGISTER BANK1:OPTION.RBPU 7 PORTB Pull-up Enable bit BANK1:OPTION.INTEDG 6 Interrupt Edge Select bit BANK1:OPTION.T0CS 5 TMR0 Clock Source Select bit BANK1:OPTION.T0SE 4 TMR0 Source Edge Select bit BANK1:OPTION.PSA 3 Prescaler Assignment bit BANK1:OPTION.PS2 2 Prescaler Rate Select bit 2 BANK1:OPTION.PS1 1 Prescaler Rate Select bit 1 BANK1:OPTION.PS0 0 Prescaler Rate Select bit 0 BANK1:PCL 0x0082 Program Counter's (PC) Least Significant Byte BANK1:STATUS 0x0083 STATUS REGISTER BANK1:STATUS.RP0 5 Register Bank Select bit 0 BANK1:STATUS.TO 4 Time-out bit BANK1:STATUS.PD 3 Power-down bit BANK1:STATUS.Z 2 Zero bit BANK1:STATUS.DC 1 Digit carry/borrow bit BANK1:STATUS.C 0 Carry/borrow bit BANK1:FSR 0x0084 Indirect data memory address pointer BANK1:TRISA 0x0085 PORTA Data Direction Register BANK1:TRISA.TRISA4 4 PORTA Data Direction Register bit 4 BANK1:TRISA.TRISA3 3 PORTA Data Direction Register bit 3 BANK1:TRISA.TRISA2 2 PORTA Data Direction Register bit 2 BANK1:TRISA.TRISA1 1 PORTA Data Direction Register bit 1 BANK1:TRISA.TRISA0 0 PORTA Data Direction Register bit 0 BANK1:TRISB 0x0086 PORTB Data Direction Control Register BANK1:TRISB.TRISB7 7 PORTB Data Direction Control Register bit 7 BANK1:TRISB.TRISB6 6 PORTB Data Direction Control Register bit 6 BANK1:TRISB.TRISB5 5 PORTB Data Direction Control Register bit 5 BANK1:TRISB.TRISB4 4 PORTB Data Direction Control Register bit 4 BANK1:TRISB.TRISB3 3 PORTB Data Direction Control Register bit 3 BANK1:TRISB.TRISB2 2 PORTB Data Direction Control Register bit 2 BANK1:TRISB.TRISB1 1 PORTB Data Direction Control Register bit 1 BANK1:TRISB.TRISB0 0 PORTB Data Direction Control Register bit 0 BANK1:RESERVED0087 0x0087 RESERVED BANK1:ADCON1 0x0088 ADCON1 REGISTER BANK1:ADCON1.PCFG1 1 A/D Port Configuration Control bit 1 BANK1:ADCON1.PCFG0 0 A/D Port Configuration Control bit 0 BANK1:ADRES 0x0089 A/D Result Register BANK1:PCLATH 0x008A Write Buffer for the upper 5 bits of the Program Counter BANK1:INTCON 0x008B INTCON REGISTER BANK1:INTCON.GIE 7 Global Interrupt Enable bit BANK1:INTCON.ADIE 6 A/D Converter Interrupt Enable bit BANK1:INTCON.T0IE 5 TMR0 Overflow Interrupt Enable bit BANK1:INTCON.INTE 4 RB0/INT External Interrupt Enable bit BANK1:INTCON.RBIE 3 RB Port Change Interrupt Enable bit BANK1:INTCON.T0IF 2 TMR0 Overflow Interrupt Flag bit BANK1:INTCON.INTF 1 RB0/INT External Interrupt Flag bit BANK1:INTCON.RBIF 0 RB Port Change Interrupt Flag bit .16C710 ; http://www.microchip.com/download/lit/pline/picmicro/families/16c7x/30272a.pdf ; PIC16C71X.pdf ; MEMORY MAP ; BANK_0 area DATA FSR_ 0x0000:0x000C area DATA Gen_Purp 0x000C:0x0030 General Purpose Register area BSS RESERVED 0x0030:0x0080 area DATA MEM_Program 0x0080:0x0200 On-chip Program Memory ; BANK_1 ; area DATA FSR_ 0x0080:0x008C ; area DATA Gen_Purp 0x008C:0x00B0 Mapped in Bank 0 ; area BSS RESERVED 0x00B0:0x0100 ; area DATA MEM_Program 0x0100:0x0200 On-chip Program Memory ; Interrupt and reset vector assignments interrupt RESET 0x0000 RESET ; INPUT/OUTPUT PORTS ; BANK0 (0x0000:0x0080) BANK0:INDF 0x0000 INDF (not a physical register) BANK0:TMR0 0x0001 Timer0 module's register BANK0:PCL 0x0002 Program Counter's (PC) Least Significant Byte BANK0:STATUS 0x0003 STATUS REGISTER BANK0:STATUS.RP0 5 Register Bank Select bit 0 BANK0:STATUS.TO 4 Time-out bit BANK0:STATUS.PD 3 Power-down bit BANK0:STATUS.Z 2 Zero bit BANK0:STATUS.DC 1 Digit carry/borrow bit BANK0:STATUS.C 0 Carry/borrow bit BANK0:FSR 0x0004 Indirect data memory address pointer BANK0:PORTA 0x0005 PORTA REGISTER BANK0:PORTA.RA4 4 PORTA bit 4 BANK0:PORTA.RA3 3 PORTA bit 3 BANK0:PORTA.RA2 2 PORTA bit 2 BANK0:PORTA.RA1 1 PORTA bit 1 BANK0:PORTA.RA0 0 PORTA bit 0 BANK0:PORTB 0x0006 PORTB REGISTER BANK0:PORTB.RB7 7 PORTB bit 7 BANK0:PORTB.RB6 6 PORTB bit 6 BANK0:PORTB.RB5 5 PORTB bit 5 BANK0:PORTB.RB4 4 PORTB bit 4 BANK0:PORTB.RB3 3 PORTB bit 3 BANK0:PORTB.RB2 2 PORTB bit 2 BANK0:PORTB.RB1 1 PORTB bit 1 BANK0:PORTB.RB0 0 PORTB bit 0 BANK0:RESERVED0007 0x0007 RESERVED BANK0:ADCON0 0x0008 ADCON0 REGISTER BANK0:ADCON0.ADCS1 7 A/D Conversion Clock Select bit 1 BANK0:ADCON0.ADCS0 6 A/D Conversion Clock Select bit 0 BANK0:ADCON0.CHS1 4 Analog Channel Select bit 1 BANK0:ADCON0.CHS0 3 Analog Channel Select bit 0 BANK0:ADCON0.GO_DONE 2 A/D Conversion Status bit BANK0:ADCON0.ADIF 1 A/D Conversion Complete Interrupt Flag bit BANK0:ADCON0.ADON 0 A/D On bit BANK0:ADRES 0x0009 A/D Result Register BANK0:PCLATH 0x000A Write Buffer for the upper 5 bits of the Program Counter BANK0:INTCON 0x000B INTCON REGISTER BANK0:INTCON.GIE 7 Global Interrupt Enable bit BANK0:INTCON.ADIE 6 A/D Converter Interrupt Enable bit BANK0:INTCON.T0IE 5 TMR0 Overflow Interrupt Enable bit BANK0:INTCON.INTE 4 RB0/INT External Interrupt Enable bit BANK0:INTCON.RBIE 3 RB Port Change Interrupt Enable bit BANK0:INTCON.T0IF 2 TMR0 Overflow Interrupt Flag bit BANK0:INTCON.INTF 1 RB0/INT External Interrupt Flag bit BANK0:INTCON.RBIF 0 RB Port Change Interrupt Flag bit ; BANK1 (0x0080:0x0100) BANK1:INDF 0x0080 INDF (not a physical register) BANK1:OPTION 0x0081 OPTION REGISTER BANK1:OPTION.RBPU 7 PORTB Pull-up Enable bit BANK1:OPTION.INTEDG 6 Interrupt Edge Select bit BANK1:OPTION.T0CS 5 TMR0 Clock Source Select bit BANK1:OPTION.T0SE 4 TMR0 Source Edge Select bit BANK1:OPTION.PSA 3 Prescaler Assignment bit BANK1:OPTION.PS2 2 Prescaler Rate Select bit 2 BANK1:OPTION.PS1 1 Prescaler Rate Select bit 1 BANK1:OPTION.PS0 0 Prescaler Rate Select bit 0 BANK1:PCL 0x0082 Program Counter's (PC) Least Significant Byte BANK1:STATUS 0x0083 STATUS REGISTER BANK1:STATUS.RP0 5 Register Bank Select bit 0 BANK1:STATUS.TO 4 Time-out bit BANK1:STATUS.PD 3 Power-down bit BANK1:STATUS.Z 2 Zero bit BANK1:STATUS.DC 1 Digit carry/borrow bit BANK1:STATUS.C 0 Carry/borrow bit BANK1:FSR 0x0084 Indirect data memory address pointer BANK1:TRISA 0x0085 PORTA Data Direction Register BANK1:TRISA.TRISA4 4 PORTA Data Direction Register bit 4 BANK1:TRISA.TRISA3 3 PORTA Data Direction Register bit 3 BANK1:TRISA.TRISA2 2 PORTA Data Direction Register bit 2 BANK1:TRISA.TRISA1 1 PORTA Data Direction Register bit 1 BANK1:TRISA.TRISA0 0 PORTA Data Direction Register bit 0 BANK1:TRISB 0x0086 PORTB Data Direction Control Register BANK1:TRISB.TRISB7 7 PORTB Data Direction Control Register bit 7 BANK1:TRISB.TRISB6 6 PORTB Data Direction Control Register bit 6 BANK1:TRISB.TRISB5 5 PORTB Data Direction Control Register bit 5 BANK1:TRISB.TRISB4 4 PORTB Data Direction Control Register bit 4 BANK1:TRISB.TRISB3 3 PORTB Data Direction Control Register bit 3 BANK1:TRISB.TRISB2 2 PORTB Data Direction Control Register bit 2 BANK1:TRISB.TRISB1 1 PORTB Data Direction Control Register bit 1 BANK1:TRISB.TRISB0 0 PORTB Data Direction Control Register bit 0 BANK1:PCON 0x0087 PCON REGISTER BANK1:PCON.POR 1 Power-on Reset Status bit BANK1:PCON.BOR 0 Brown-out Reset Status bit BANK1:ADCON1 0x0088 ADCON1 REGISTER BANK1:ADCON1.PCFG1 1 A/D Port Configuration Control bit 1 BANK1:ADCON1.PCFG0 0 A/D Port Configuration Control bit 0 BANK1:ADRES 0x0089 A/D Result Register BANK1:PCLATH 0x008A Write Buffer for the upper 5 bits of the Program Counter BANK1:INTCON 0x008B INTCON REGISTER BANK1:INTCON.GIE 7 Global Interrupt Enable bit BANK1:INTCON.ADIE 6 A/D Converter Interrupt Enable bit BANK1:INTCON.T0IE 5 TMR0 Overflow Interrupt Enable bit BANK1:INTCON.INTE 4 RB0/INT External Interrupt Enable bit BANK1:INTCON.RBIE 3 RB Port Change Interrupt Enable bit BANK1:INTCON.T0IF 2 TMR0 Overflow Interrupt Flag bit BANK1:INTCON.INTF 1 RB0/INT External Interrupt Flag bit BANK1:INTCON.RBIF 0 RB Port Change Interrupt Flag bit .16C711 ; http://www.microchip.com/download/lit/pline/picmicro/families/16c7x/30272a.pdf ; PIC16C71X.pdf ; MEMORY MAP ; BANK_0 area DATA FSR_ 0x0000:0x000C area DATA Gen_Purp 0x000C:0x0050 General Purpose Register area BSS RESERVED 0x0050:0x0080 area DATA MEM_Program 0x0080:0x0400 On-chip Program Memory ; BANK_1 ; area DATA FSR_ 0x0080:0x008C ; area DATA Gen_Purp 0x008C:0x00D0 Mapped in Bank 0 ; area BSS RESERVED 0x00D0:0x0100 ; area DATA MEM_Program 0x0100:0x0400 On-chip Program Memory ; Interrupt and reset vector assignments interrupt RESET 0x0000 RESET ; INPUT/OUTPUT PORTS ; BANK0 (0x0000:0x0080) BANK0:INDF 0x0000 INDF (not a physical register) BANK0:TMR0 0x0001 Timer0 module's register BANK0:PCL 0x0002 Program Counter's (PC) Least Significant Byte BANK0:STATUS 0x0003 STATUS REGISTER BANK0:STATUS.RP0 5 Register Bank Select bit 0 BANK0:STATUS.TO 4 Time-out bit BANK0:STATUS.PD 3 Power-down bit BANK0:STATUS.Z 2 Zero bit BANK0:STATUS.DC 1 Digit carry/borrow bit BANK0:STATUS.C 0 Carry/borrow bit BANK0:FSR 0x0004 Indirect data memory address pointer BANK0:PORTA 0x0005 PORTA REGISTER BANK0:PORTA.RA4 4 PORTA bit 4 BANK0:PORTA.RA3 3 PORTA bit 3 BANK0:PORTA.RA2 2 PORTA bit 2 BANK0:PORTA.RA1 1 PORTA bit 1 BANK0:PORTA.RA0 0 PORTA bit 0 BANK0:PORTB 0x0006 PORTB REGISTER BANK0:PORTB.RB7 7 PORTB bit 7 BANK0:PORTB.RB6 6 PORTB bit 6 BANK0:PORTB.RB5 5 PORTB bit 5 BANK0:PORTB.RB4 4 PORTB bit 4 BANK0:PORTB.RB3 3 PORTB bit 3 BANK0:PORTB.RB2 2 PORTB bit 2 BANK0:PORTB.RB1 1 PORTB bit 1 BANK0:PORTB.RB0 0 PORTB bit 0 BANK0:RESERVED0007 0x0007 RESERVED BANK0:ADCON0 0x0008 ADCON0 REGISTER BANK0:ADCON0.ADCS1 7 A/D Conversion Clock Select bit 1 BANK0:ADCON0.ADCS0 6 A/D Conversion Clock Select bit 0 BANK0:ADCON0.CHS1 4 Analog Channel Select bit 1 BANK0:ADCON0.CHS0 3 Analog Channel Select bit 0 BANK0:ADCON0.GO_DONE 2 A/D Conversion Status bit BANK0:ADCON0.ADIF 1 A/D Conversion Complete Interrupt Flag bit BANK0:ADCON0.ADON 0 A/D On bit BANK0:ADRES 0x0009 A/D Result Register BANK0:PCLATH 0x000A Write Buffer for the upper 5 bits of the Program Counter BANK0:INTCON 0x000B INTCON REGISTER BANK0:INTCON.GIE 7 Global Interrupt Enable bit BANK0:INTCON.ADIE 6 A/D Converter Interrupt Enable bit BANK0:INTCON.T0IE 5 TMR0 Overflow Interrupt Enable bit BANK0:INTCON.INTE 4 RB0/INT External Interrupt Enable bit BANK0:INTCON.RBIE 3 RB Port Change Interrupt Enable bit BANK0:INTCON.T0IF 2 TMR0 Overflow Interrupt Flag bit BANK0:INTCON.INTF 1 RB0/INT External Interrupt Flag bit BANK0:INTCON.RBIF 0 RB Port Change Interrupt Flag bit ; BANK1 (0x0080:0x0100) BANK1:INDF 0x0080 INDF (not a physical register) BANK1:OPTION 0x0081 OPTION REGISTER BANK1:OPTION.RBPU 7 PORTB Pull-up Enable bit BANK1:OPTION.INTEDG 6 Interrupt Edge Select bit BANK1:OPTION.T0CS 5 TMR0 Clock Source Select bit BANK1:OPTION.T0SE 4 TMR0 Source Edge Select bit BANK1:OPTION.PSA 3 Prescaler Assignment bit BANK1:OPTION.PS2 2 Prescaler Rate Select bit 2 BANK1:OPTION.PS1 1 Prescaler Rate Select bit 1 BANK1:OPTION.PS0 0 Prescaler Rate Select bit 0 BANK1:PCL 0x0082 Program Counter's (PC) Least Significant Byte BANK1:STATUS 0x0083 STATUS REGISTER BANK1:STATUS.RP0 5 Register Bank Select bit 0 BANK1:STATUS.TO 4 Time-out bit BANK1:STATUS.PD 3 Power-down bit BANK1:STATUS.Z 2 Zero bit BANK1:STATUS.DC 1 Digit carry/borrow bit BANK1:STATUS.C 0 Carry/borrow bit BANK1:FSR 0x0084 Indirect data memory address pointer BANK1:TRISA 0x0085 PORTA Data Direction Register BANK1:TRISA.TRISA4 4 PORTA Data Direction Register bit 4 BANK1:TRISA.TRISA3 3 PORTA Data Direction Register bit 3 BANK1:TRISA.TRISA2 2 PORTA Data Direction Register bit 2 BANK1:TRISA.TRISA1 1 PORTA Data Direction Register bit 1 BANK1:TRISA.TRISA0 0 PORTA Data Direction Register bit 0 BANK1:TRISB 0x0086 PORTB Data Direction Control Register BANK1:TRISB.TRISB7 7 PORTB Data Direction Control Register bit 7 BANK1:TRISB.TRISB6 6 PORTB Data Direction Control Register bit 6 BANK1:TRISB.TRISB5 5 PORTB Data Direction Control Register bit 5 BANK1:TRISB.TRISB4 4 PORTB Data Direction Control Register bit 4 BANK1:TRISB.TRISB3 3 PORTB Data Direction Control Register bit 3 BANK1:TRISB.TRISB2 2 PORTB Data Direction Control Register bit 2 BANK1:TRISB.TRISB1 1 PORTB Data Direction Control Register bit 1 BANK1:TRISB.TRISB0 0 PORTB Data Direction Control Register bit 0 BANK1:PCON 0x0087 PCON REGISTER BANK1:PCON.POR 1 Power-on Reset Status bit BANK1:PCON.BOR 0 Brown-out Reset Status bit BANK1:ADCON1 0x0088 ADCON1 REGISTER BANK1:ADCON1.PCFG1 1 A/D Port Configuration Control bit 1 BANK1:ADCON1.PCFG0 0 A/D Port Configuration Control bit 0 BANK1:ADRES 0x0089 A/D Result Register BANK1:PCLATH 0x008A Write Buffer for the upper 5 bits of the Program Counter BANK1:INTCON 0x008B INTCON REGISTER BANK1:INTCON.GIE 7 Global Interrupt Enable bit BANK1:INTCON.ADIE 6 A/D Converter Interrupt Enable bit BANK1:INTCON.T0IE 5 TMR0 Overflow Interrupt Enable bit BANK1:INTCON.INTE 4 RB0/INT External Interrupt Enable bit BANK1:INTCON.RBIE 3 RB Port Change Interrupt Enable bit BANK1:INTCON.T0IF 2 TMR0 Overflow Interrupt Flag bit BANK1:INTCON.INTF 1 RB0/INT External Interrupt Flag bit BANK1:INTCON.RBIF 0 RB Port Change Interrupt Flag bit .16C715 ; http://www.microchip.com/download/lit/pline/picmicro/families/16c7x/30272a.pdf ; PIC16C71X.pdf ; MEMORY MAP ; BANK_0 area DATA FSR_ 0x0000:0x0020 area DATA Gen_Purp 0x0020:0x0080 General Purpose Register area DATA MEM_Program 0x0080:0x0800 On-chip Program Memory ; BANK_1 ; area DATA FSR_ 0x0080:0x00A0 ; area DATA Gen_Purp 0x00A0:0x00C0 Mapped in Bank 0 ; area BSS RESERVED 0x00C0:0x0100 ; area DATA MEM_Program 0x0100:0x0800 On-chip Program Memory ; Interrupt and reset vector assignments interrupt RESET 0x0000 RESET ; INPUT/OUTPUT PORTS ; BANK0 (0x0000:0x0080) BANK0:INDF 0x0000 INDF (not a physical register) BANK0:TMR0 0x0001 Timer0 module's register BANK0:PCL 0x0002 Program Counter's (PC) Least Significant Byte BANK0:STATUS 0x0003 STATUS REGISTER BANK0:STATUS.RP0 5 Register Bank Select bit 0 BANK0:STATUS.TO 4 Time-out bit BANK0:STATUS.PD 3 Power-down bit BANK0:STATUS.Z 2 Zero bit BANK0:STATUS.DC 1 Digit carry/borrow bit BANK0:STATUS.C 0 Carry/borrow bit BANK0:FSR 0x0004 Indirect data memory address pointer BANK0:PORTA 0x0005 PORTA REGISTER BANK0:PORTA.RA4 4 PORTA bit 4 BANK0:PORTA.RA3 3 PORTA bit 3 BANK0:PORTA.RA2 2 PORTA bit 2 BANK0:PORTA.RA1 1 PORTA bit 1 BANK0:PORTA.RA0 0 PORTA bit 0 BANK0:PORTB 0x0006 PORTB REGISTER BANK0:PORTB.RB7 7 PORTB bit 7 BANK0:PORTB.RB6 6 PORTB bit 6 BANK0:PORTB.RB5 5 PORTB bit 5 BANK0:PORTB.RB4 4 PORTB bit 4 BANK0:PORTB.RB3 3 PORTB bit 3 BANK0:PORTB.RB2 2 PORTB bit 2 BANK0:PORTB.RB1 1 PORTB bit 1 BANK0:PORTB.RB0 0 PORTB bit 0 BANK0:RESERVED0007 0x0007 RESERVED BANK0:RESERVED0008 0x0008 RESERVED BANK0:RESERVED0009 0x0009 RESERVED BANK0:PCLATH 0x000A Write Buffer for the upper 5 bits of the Program Counter BANK0:INTCON 0x000B INTCON REGISTER BANK0:INTCON.GIE 7 Global Interrupt Enable bit BANK0:INTCON.ADIE 6 A/D Converter Interrupt Enable bit BANK0:INTCON.T0IE 5 TMR0 Overflow Interrupt Enable bit BANK0:INTCON.INTE 4 RB0/INT External Interrupt Enable bit BANK0:INTCON.RBIE 3 RB Port Change Interrupt Enable bit BANK0:INTCON.T0IF 2 TMR0 Overflow Interrupt Flag bit BANK0:INTCON.INTF 1 RB0/INT External Interrupt Flag bit BANK0:INTCON.RBIF 0 RB Port Change Interrupt Flag bit BANK0:PIR1 0x000C PIR1 REGISTER BANK0:PIR1.ADIF 6 A/D Converter Interrupt Flag bit BANK0:RESERVED000D 0x000D RESERVED BANK0:RESERVED000E 0x000E RESERVED BANK0:RESERVED000F 0x000F RESERVED BANK0:RESERVED0010 0x0010 RESERVED BANK0:RESERVED0011 0x0011 RESERVED BANK0:RESERVED0012 0x0012 RESERVED BANK0:RESERVED0013 0x0013 RESERVED BANK0:RESERVED0014 0x0014 RESERVED BANK0:RESERVED0015 0x0015 RESERVED BANK0:RESERVED0016 0x0016 RESERVED BANK0:RESERVED0017 0x0017 RESERVED BANK0:RESERVED0018 0x0018 RESERVED BANK0:RESERVED0019 0x0019 RESERVED BANK0:RESERVED001A 0x001A RESERVED BANK0:RESERVED001B 0x001B RESERVED BANK0:RESERVED001C 0x001C RESERVED BANK0:RESERVED001D 0x001D RESERVED BANK0:ADRES 0x001E A/D Result Register BANK0:ADCON0 0x001F ADCON0 REGISTER BANK0:ADCON0.ADCS1 7 A/D Conversion Clock Select bit 1 BANK0:ADCON0.ADCS0 6 A/D Conversion Clock Select bit 0 BANK0:ADCON0.CHS1 4 Analog Channel Select bit 1 BANK0:ADCON0.CHS0 3 Analog Channel Select bit 0 BANK0:ADCON0.GO_DONE 2 A/D Conversion Status bit BANK0:ADCON0.ADON 0 A/D On bit ; BANK1 (0x0080:0x0100) BANK1:INDF 0x0080 INDF (not a physical register) BANK1:OPTION 0x0081 OPTION REGISTER BANK1:OPTION.RBPU 7 PORTB Pull-up Enable bit BANK1:OPTION.INTEDG 6 Interrupt Edge Select bit BANK1:OPTION.T0CS 5 TMR0 Clock Source Select bit BANK1:OPTION.T0SE 4 TMR0 Source Edge Select bit BANK1:OPTION.PSA 3 Prescaler Assignment bit BANK1:OPTION.PS2 2 Prescaler Rate Select bit 2 BANK1:OPTION.PS1 1 Prescaler Rate Select bit 1 BANK1:OPTION.PS0 0 Prescaler Rate Select bit 0 BANK1:PCL 0x0082 Program Counter's (PC) Least Significant Byte BANK1:STATUS 0x0083 STATUS REGISTER BANK1:STATUS.RP0 5 Register Bank Select bit 0 BANK1:STATUS.TO 4 Time-out bit BANK1:STATUS.PD 3 Power-down bit BANK1:STATUS.Z 2 Zero bit BANK1:STATUS.DC 1 Digit carry/borrow bit BANK1:STATUS.C 0 Carry/borrow bit BANK1:FSR 0x0084 Indirect data memory address pointer BANK1:TRISA 0x0085 PORTA Data Direction Register BANK1:TRISA.TRISA4 4 PORTA Data Direction Register bit 4 BANK1:TRISA.TRISA3 3 PORTA Data Direction Register bit 3 BANK1:TRISA.TRISA2 2 PORTA Data Direction Register bit 2 BANK1:TRISA.TRISA1 1 PORTA Data Direction Register bit 1 BANK1:TRISA.TRISA0 0 PORTA Data Direction Register bit 0 BANK1:TRISB 0x0086 PORTB Data Direction Register BANK1:TRISB.TRISB7 7 PORTB Data Direction Register bit 7 BANK1:TRISB.TRISB6 6 PORTB Data Direction Register bit 6 BANK1:TRISB.TRISB5 5 PORTB Data Direction Register bit 5 BANK1:TRISB.TRISB4 4 PORTB Data Direction Register bit 4 BANK1:TRISB.TRISB3 3 PORTB Data Direction Register bit 3 BANK1:TRISB.TRISB2 2 PORTB Data Direction Register bit 2 BANK1:TRISB.TRISB1 1 PORTB Data Direction Register bit 1 BANK1:TRISB.TRISB0 0 PORTB Data Direction Register bit 0 BANK1:RESERVED0087 0x0087 RESERVED BANK1:RESERVED0088 0x0088 RESERVED BANK1:RESERVED0089 0x0089 RESERVED BANK1:PCLATH 0x008A Write Buffer for the upper 5 bits of the PC BANK1:INTCON 0x008B INTCON REGISTER BANK1:INTCON.GIE 7 Global Interrupt Enable bit BANK1:INTCON.ADIE 6 A/D Converter Interrupt Enable bit BANK1:INTCON.T0IE 5 TMR0 Overflow Interrupt Enable bit BANK1:INTCON.INTE 4 RB0/INT External Interrupt Enable bit BANK1:INTCON.RBIE 3 RB Port Change Interrupt Enable bit BANK1:INTCON.T0IF 2 TMR0 Overflow Interrupt Flag bit BANK1:INTCON.INTF 1 RB0/INT External Interrupt Flag bit BANK1:INTCON.RBIF 0 RB Port Change Interrupt Flag bit BANK1:PIE1 0x008C PIE1 REGISTER BANK1:PIE1.ADIE 6 A/D Converter Interrupt Enable bit BANK1:RESERVED008D 0x008D RESERVED BANK1:PCON 0x008E PCON REGISTER BANK1:PCON.MPEEN 7 Memory Parity Error Circuitry Status bit BANK1:PCON.PER 2 Memory Parity Error Reset Status bit BANK1:PCON.POR 1 Power-on Reset Status bit BANK1:PCON.BOR 0 Brown-out Reset Status bit BANK1:RESERVED008F 0x008F RESERVED BANK1:RESERVED0090 0x0090 RESERVED BANK1:RESERVED0091 0x0091 RESERVED BANK1:RESERVED0092 0x0092 RESERVED BANK1:RESERVED0093 0x0093 RESERVED BANK1:RESERVED0094 0x0094 RESERVED BANK1:RESERVED0095 0x0095 RESERVED BANK1:RESERVED0096 0x0096 RESERVED BANK1:RESERVED0097 0x0097 RESERVED BANK1:RESERVED0098 0x0098 RESERVED BANK1:RESERVED0099 0x0099 RESERVED BANK1:RESERVED009A 0x009A RESERVED BANK1:RESERVED009B 0x009B RESERVED BANK1:RESERVED009C 0x009C RESERVED BANK1:RESERVED009D 0x009D RESERVED BANK1:RESERVED009E 0x009E RESERVED BANK1:ADCON1 0x009F ADCON1 REGISTER BANK1:ADCON1.PCFG1 1 A/D Port Configuration Control bit 1 BANK1:ADCON1.PCFG0 0 A/D Port Configuration Control bit 0 .16C72 ; http://www.microchip.com/download/lit/pline/picmicro/families/16c7x/39016a.pdf ; PIC16C72_CR72.pdf ; MEMORY MAP ; BANK_0 area DATA FSR_ 0x0000:0x0020 area DATA Gen_Purp 0x0020:0x0080 General Purpose Register area DATA MEM_Program 0x0080:0x0800 On-chip Program Memory ; BANK_1 ; area DATA FSR_ 0x0080:0x00A0 ; area DATA Gen_Purp 0x00A0:0x00C0 General Purpose Register ; area BSS RESERVED 0x00C0:0x0100 ; area DATA MEM_Program 0x0100:0x0800 On-chip Program Memory ; Interrupt and reset vector assignments interrupt RESET 0x0000 RESET ; INPUT/OUTPUT PORTS ; BANK0 (0x0000:0x0080) BANK0:INDF 0x0000 INDF (not a physical register) BANK0:TMR0 0x0001 Timer0 module's register BANK0:PCL 0x0002 Program Counter's (PC) Least Significant Byte BANK0:STATUS 0x0003 STATUS REGISTER BANK0:STATUS.RP0 5 Register Bank Select bit 0 BANK0:STATUS.TO 4 Time-out bit BANK0:STATUS.PD 3 Power-down bit BANK0:STATUS.Z 2 Zero bit BANK0:STATUS.DC 1 Digit carry/borrow bit BANK0:STATUS.C 0 Carry/borrow bit BANK0:FSR 0x0004 Indirect data memory address pointer BANK0:PORTA 0x0005 PORTA REGISTER BANK0:PORTA.RA5 5 PORTA bit 5 BANK0:PORTA.RA4 4 PORTA bit 4 BANK0:PORTA.RA3 3 PORTA bit 3 BANK0:PORTA.RA2 2 PORTA bit 2 BANK0:PORTA.RA1 1 PORTA bit 1 BANK0:PORTA.RA0 0 PORTA bit 0 BANK0:PORTB 0x0006 PORTB REGISTER BANK0:PORTB.RB7 7 PORTB bit 7 BANK0:PORTB.RB6 6 PORTB bit 6 BANK0:PORTB.RB5 5 PORTB bit 5 BANK0:PORTB.RB4 4 PORTB bit 4 BANK0:PORTB.RB3 3 PORTB bit 3 BANK0:PORTB.RB2 2 PORTB bit 2 BANK0:PORTB.RB1 1 PORTB bit 1 BANK0:PORTB.RB0 0 PORTB bit 0 BANK0:PORTC 0x0007 PORTC REGISTER BANK0:PORTC.RC7 7 PORTC bit 7 BANK0:PORTC.RC6 6 PORTC bit 6 BANK0:PORTC.RC5 5 PORTC bit 5 BANK0:PORTC.RC4 4 PORTC bit 4 BANK0:PORTC.RC3 3 PORTC bit 3 BANK0:PORTC.RC2 2 PORTC bit 2 BANK0:PORTC.RC1 1 PORTC bit 1 BANK0:PORTC.RC0 0 PORTC bit 0 BANK0:RESERVED0008 0x0008 RESERVED BANK0:RESERVED0009 0x0009 RESERVED BANK0:PCLATH 0x000A Write Buffer for the upper 5 bits of the Program Counter BANK0:INTCON 0x000B INTCON REGISTER BANK0:INTCON.GIE 7 Global Interrupt Enable bit BANK0:INTCON.PEIE 6 Peripheral Interrupt Enable bit BANK0:INTCON.T0IE 5 TMR0 Overflow Interrupt Enable bit BANK0:INTCON.INTE 4 RB0/INT External Interrupt Enable bit BANK0:INTCON.RBIE 3 RB Port Change Interrupt Enable bit BANK0:INTCON.T0IF 2 TMR0 Overflow Interrupt Flag bit BANK0:INTCON.INTF 1 RB0/INT External Interrupt Flag bit BANK0:INTCON.RBIF 0 RB Port Change Interrupt Flag bit BANK0:PIR1 0x000C PIR1 REGISTER BANK0:PIR1.ADIF 6 A/D Converter Interrupt Flag bit (NOT IN PIC16C62B) BANK0:PIR1.SSPIF 3 Synchronous Serial Port Interrupt Flag bit BANK0:PIR1.CCP1IF 2 CCP1 Interrupt Flag bit BANK0:PIR1.TMR2IF 1 TMR2 to PR2 Match Interrupt Flag bit BANK0:PIR1.TMR1IF 0 TMR1 Overflow Interrupt Flag bit BANK0:RESERVED000D 0x000D RESERVED BANK0:TMR1L 0x000E Holding register for the Least Significant Byte of the 16-bit TMR1 register BANK0:TMR1H 0x000F Holding register for the Most Significant Byte of the 16-bit TMR1 register BANK0:T1CON 0x0010 TIMER1 CONTROL REGISTER BANK0:T1CON.T1CKPS1 5 Timer1 Input Clock Prescale Select bit 1 BANK0:T1CON.T1CKPS0 4 Timer1 Input Clock Prescale Select bit 0 BANK0:T1CON.T1OSCEN 3 Timer1 Oscillator Enable Control bit BANK0:T1CON.T1SYNC 2 Timer1 External Clock Input Synchronization Control bit BANK0:T1CON.TMR1CS 1 Timer1 Clock Source Select bit BANK0:T1CON.TMR1ON 0 Timer1 On bit BANK0:TMR2 0x0011 Timer2 module's register BANK0:T2CON 0x0012 TIMER2 CONTROL REGISTER BANK0:T2CON.TOUTPS3 6 Timer2 Output Postscale Select bit 3 BANK0:T2CON.TOUTPS2 5 Timer2 Output Postscale Select bit 2 BANK0:T2CON.TOUTPS1 4 Timer2 Output Postscale Select bit 1 BANK0:T2CON.TOUTPS0 3 Timer2 Output Postscale Select bit 0 BANK0:T2CON.TMR2ON 2 Timer2 On bit BANK0:T2CON.T2CKPS1 1 Timer2 Clock Prescale Select bit 1 BANK0:T2CON.T2CKPS0 0 Timer2 Clock Prescale Select bit 0 BANK0:SSPBUF 0x0013 Synchronous Serial Port Receive Buffer/Transmit Register BANK0:SSPCON 0x0014 SYNC SERIAL PORT CONTROL REGISTER BANK0:SSPCON.WCOL 7 Write Collision Detect bit BANK0:SSPCON.SSPOV 6 Receive Overflow Indicator bit BANK0:SSPCON.SSPEN 5 Synchronous Serial Port Enable bit BANK0:SSPCON.CKP 4 Clock Polarity Select bit BANK0:SSPCON.SSPM3 3 Synchronous Serial Port Mode Select bit 3 BANK0:SSPCON.SSPM2 2 Synchronous Serial Port Mode Select bit 2 BANK0:SSPCON.SSPM1 1 Synchronous Serial Port Mode Select bit 1 BANK0:SSPCON.SSPM0 0 Synchronous Serial Port Mode Select bit 0 BANK0:CCPR1L 0x0015 Capture/Compare/PWM Register1 (LSB) BANK0:CCPR1H 0x0016 Capture/Compare/PWM Register1 (MSB) BANK0:CCP1CON 0x0017 CCP1CON REGISTER BANK0:CCP1CON.CCP1X 5 PWM Least Significant bit BANK0:CCP1CON.CCP1Y 4 PWM Least Significant bit BANK0:CCP1CON.CCP1M3 3 CCP1 Mode Select bit 3 BANK0:CCP1CON.CCP1M2 2 CCP1 Mode Select bit 2 BANK0:CCP1CON.CCP1M1 1 CCP1 Mode Select bit 1 BANK0:CCP1CON.CCP1M0 0 CCP1 Mode Select bit 0 BANK0:RESERVED0018 0x0018 RESERVED BANK0:RESERVED0019 0x0019 RESERVED BANK0:RESERVED001A 0x001A RESERVED BANK0:RESERVED001B 0x001B RESERVED BANK0:RESERVED001C 0x001C RESERVED BANK0:RESERVED001D 0x001D RESERVED BANK0:ADRES 0x001E A/D Result Register BANK0:ADCON0 0x001F ADCON0 REGISTER BANK0:ADCON0.ADCS1 7 A/D Conversion Clock Select bit 1 BANK0:ADCON0.ADCS0 6 A/D Conversion Clock Select bit 0 BANK0:ADCON0.CHS2 5 Analog Channel Select bit 2 BANK0:ADCON0.CHS1 4 Analog Channel Select bit 1 BANK0:ADCON0.CHS0 3 Analog Channel Select bit 0 BANK0:ADCON0.GO_DONE 2 A/D Conversion Status bit BANK0:ADCON0.ADON 0 A/D On bit ; BANK1 (0x0080:0x0100) BANK1:INDF 0x0080 INDF (not a physical register) BANK1:OPTION 0x0081 OPTION REGISTER BANK1:OPTION.RBPU 7 PORTB Pull-up Enable bit BANK1:OPTION.INTEDG 6 Interrupt Edge Select bit BANK1:OPTION.T0CS 5 TMR0 Clock Source Select bit BANK1:OPTION.T0SE 4 TMR0 Source Edge Select bit BANK1:OPTION.PSA 3 Prescaler Assignment bit BANK1:OPTION.PS2 2 Prescaler Rate Select bit 2 BANK1:OPTION.PS1 1 Prescaler Rate Select bit 1 BANK1:OPTION.PS0 0 Prescaler Rate Select bit 0 BANK1:PCL 0x0082 Program Counter's (PC) Least Significant Byte BANK1:STATUS 0x0083 STATUS REGISTER BANK1:STATUS.RP0 5 Register Bank Select bit 0 BANK1:STATUS.TO 4 Time-out bit BANK1:STATUS.PD 3 Power-down bit BANK1:STATUS.Z 2 Zero bit BANK1:STATUS.DC 1 Digit carry/borrow bit BANK1:STATUS.C 0 Carry/borrow bit BANK1:FSR 0x0084 Indirect data memory address pointer BANK1:TRISA 0x0085 PORTA Data Direction Register BANK1:TRISA.TRISA5 5 PORTA Data Direction Register bit 5 BANK1:TRISA.TRISA4 4 PORTA Data Direction Register bit 4 BANK1:TRISA.TRISA3 3 PORTA Data Direction Register bit 3 BANK1:TRISA.TRISA2 2 PORTA Data Direction Register bit 2 BANK1:TRISA.TRISA1 1 PORTA Data Direction Register bit 1 BANK1:TRISA.TRISA0 0 PORTA Data Direction Register bit 0 BANK1:TRISB 0x0086 PORTB Data Direction Register BANK1:TRISB.TRISB7 7 PORTB Data Direction Register bit 7 BANK1:TRISB.TRISB6 6 PORTB Data Direction Register bit 6 BANK1:TRISB.TRISB5 5 PORTB Data Direction Register bit 5 BANK1:TRISB.TRISB4 4 PORTB Data Direction Register bit 4 BANK1:TRISB.TRISB3 3 PORTB Data Direction Register bit 3 BANK1:TRISB.TRISB2 2 PORTB Data Direction Register bit 2 BANK1:TRISB.TRISB1 1 PORTB Data Direction Register bit 1 BANK1:TRISB.TRISB0 0 PORTB Data Direction Register bit 0 BANK1:TRISC 0x0087 PORTC Data Direction Register BANK1:TRISC.TRISC7 7 PORTC Data Direction Register bit 7 BANK1:TRISC.TRISC6 6 PORTC Data Direction Register bit 6 BANK1:TRISC.TRISC5 5 PORTC Data Direction Register bit 5 BANK1:TRISC.TRISC4 4 PORTC Data Direction Register bit 4 BANK1:TRISC.TRISC3 3 PORTC Data Direction Register bit 3 BANK1:TRISC.TRISC2 2 PORTC Data Direction Register bit 2 BANK1:TRISC.TRISC1 1 PORTC Data Direction Register bit 1 BANK1:TRISC.TRISC0 0 PORTC Data Direction Register bit 0 BANK1:RESERVED0088 0x0088 RESERVED BANK1:RESERVED0089 0x0089 RESERVED BANK1:PCLATH 0x008A Write Buffer for the upper 5 bits of the Program Counter BANK1:INTCON 0x008B INTCON REGISTER BANK1:INTCON.GIE 7 Global Interrupt Enable bit BANK1:INTCON.PEIE 6 Peripheral Interrupt Enable bit BANK1:INTCON.T0IE 5 TMR0 Overflow Interrupt Enable bit BANK1:INTCON.INTE 4 RB0/INT External Interrupt Enable bit BANK1:INTCON.RBIE 3 RB Port Change Interrupt Enable bit BANK1:INTCON.T0IF 2 TMR0 Overflow Interrupt Flag bit BANK1:INTCON.INTF 1 RB0/INT External Interrupt Flag bit BANK1:INTCON.RBIF 0 RB Port Change Interrupt Flag bit BANK1:PIE1 0x008C PIE1 REGISTER BANK1:PIE1.ADIE 6 A/D Converter Interrupt Enable bit (NOT IN PIC16C62B) BANK1:PIE1.SSPIE 3 Synchronous Serial Port Interrupt Enable bit BANK1:PIE1.CCP1IE 2 CCP1 Interrupt Enable bit BANK1:PIE1.TMR2IE 1 TMR2 to PR2 Match Interrupt Enable bit BANK1:PIE1.TMR1IE 0 TMR1 Overflow Interrupt Enable bit BANK1:RESERVED008D 0x008D RESERVED BANK1:PCON 0x008E PCON REGISTER BANK1:PCON.POR 1 Power-on Reset Status bit BANK1:PCON.BOR 0 Brown-out Reset Status bit BANK1:RESERVED008F 0x008F RESERVED BANK1:RESERVED0090 0x0090 RESERVED BANK1:RESERVED0091 0x0091 RESERVED BANK1:PR2 0x0092 Timer2 Period Register BANK1:SSPADD 0x0093 Synchronous Serial Port (I2C mode) Address Register BANK1:SSPSTAT 0x0094 SYNC SERIAL PORT STATUS REGISTER BANK1:SSPSTAT.D_A 5 Data/Address bit (I2C mode only) BANK1:SSPSTAT.P 4 Stop bit (I2C mode only) BANK1:SSPSTAT.S 3 Start bit (I2C mode only) BANK1:SSPSTAT.R_W 2 Read/Write bit information (I2C mode only) BANK1:SSPSTAT.UA 1 Update Address (I2C mode only) BANK1:SSPSTAT.BF 0 Buffer Full Status bit BANK1:RESERVED0095 0x0095 RESERVED BANK1:RESERVED0096 0x0096 RESERVED BANK1:RESERVED0097 0x0097 RESERVED BANK1:RESERVED0098 0x0098 RESERVED BANK1:RESERVED0099 0x0099 RESERVED BANK1:RESERVED009A 0x009A RESERVED BANK1:RESERVED009B 0x009B RESERVED BANK1:RESERVED009C 0x009C RESERVED BANK1:RESERVED009D 0x009D RESERVED BANK1:RESERVED009E 0x009E RESERVED BANK1:ADCON1 0x009F ADCON1 REGISTER BANK1:ADCON1.PCFG2 2 A/D Port Configuration Control bit 2 BANK1:ADCON1.PCFG1 1 A/D Port Configuration Control bit 1 BANK1:ADCON1.PCFG0 0 A/D Port Configuration Control bit 0 .16CR72 ; http://www.microchip.com/download/lit/pline/picmicro/families/16c7x/39016a.pdf ; PIC16C72_CR72.pdf ; MEMORY MAP ; BANK_0 area DATA FSR_ 0x0000:0x0020 area DATA Gen_Purp 0x0020:0x0080 General Purpose Register area DATA MEM_Program 0x0080:0x0800 On-chip Program Memory ; BANK_1 ; area DATA FSR_ 0x0080:0x00A0 ; area DATA Gen_Purp 0x00A0:0x00C0 General Purpose Register ; area BSS RESERVED 0x00C0:0x0100 ; area DATA MEM_Program 0x0100:0x0800 On-chip Program Memory ; Interrupt and reset vector assignments interrupt RESET 0x0000 RESET ; INPUT/OUTPUT PORTS ; BANK0 (0x0000:0x0080) BANK0:INDF 0x0000 INDF (not a physical register) BANK0:TMR0 0x0001 Timer0 module's register BANK0:PCL 0x0002 Program Counter's (PC) Least Significant Byte BANK0:STATUS 0x0003 STATUS REGISTER BANK0:STATUS.RP0 5 Register Bank Select bit 0 BANK0:STATUS.TO 4 Time-out bit BANK0:STATUS.PD 3 Power-down bit BANK0:STATUS.Z 2 Zero bit BANK0:STATUS.DC 1 Digit carry/borrow bit BANK0:STATUS.C 0 Carry/borrow bit BANK0:FSR 0x0004 Indirect data memory address pointer BANK0:PORTA 0x0005 PORTA REGISTER BANK0:PORTA.RA5 5 PORTA bit 5 BANK0:PORTA.RA4 4 PORTA bit 4 BANK0:PORTA.RA3 3 PORTA bit 3 BANK0:PORTA.RA2 2 PORTA bit 2 BANK0:PORTA.RA1 1 PORTA bit 1 BANK0:PORTA.RA0 0 PORTA bit 0 BANK0:PORTB 0x0006 PORTB REGISTER BANK0:PORTB.RB7 7 PORTB bit 7 BANK0:PORTB.RB6 6 PORTB bit 6 BANK0:PORTB.RB5 5 PORTB bit 5 BANK0:PORTB.RB4 4 PORTB bit 4 BANK0:PORTB.RB3 3 PORTB bit 3 BANK0:PORTB.RB2 2 PORTB bit 2 BANK0:PORTB.RB1 1 PORTB bit 1 BANK0:PORTB.RB0 0 PORTB bit 0 BANK0:PORTC 0x0007 PORTC REGISTER BANK0:PORTC.RC7 7 PORTC bit 7 BANK0:PORTC.RC6 6 PORTC bit 6 BANK0:PORTC.RC5 5 PORTC bit 5 BANK0:PORTC.RC4 4 PORTC bit 4 BANK0:PORTC.RC3 3 PORTC bit 3 BANK0:PORTC.RC2 2 PORTC bit 2 BANK0:PORTC.RC1 1 PORTC bit 1 BANK0:PORTC.RC0 0 PORTC bit 0 BANK0:RESERVED0008 0x0008 RESERVED BANK0:RESERVED0009 0x0009 RESERVED BANK0:PCLATH 0x000A Write Buffer for the upper 5 bits of the Program Counter BANK0:INTCON 0x000B INTCON REGISTER BANK0:INTCON.GIE 7 Global Interrupt Enable bit BANK0:INTCON.PEIE 6 Peripheral Interrupt Enable bit BANK0:INTCON.T0IE 5 TMR0 Overflow Interrupt Enable bit BANK0:INTCON.INTE 4 RB0/INT External Interrupt Enable bit BANK0:INTCON.RBIE 3 RB Port Change Interrupt Enable bit BANK0:INTCON.T0IF 2 TMR0 Overflow Interrupt Flag bit BANK0:INTCON.INTF 1 RB0/INT External Interrupt Flag bit BANK0:INTCON.RBIF 0 RB Port Change Interrupt Flag bit BANK0:PIR1 0x000C PIR1 REGISTER BANK0:PIR1.ADIF 6 A/D Converter Interrupt Flag bit (NOT IN PIC16C62B) BANK0:PIR1.SSPIF 3 Synchronous Serial Port Interrupt Flag bit BANK0:PIR1.CCP1IF 2 CCP1 Interrupt Flag bit BANK0:PIR1.TMR2IF 1 TMR2 to PR2 Match Interrupt Flag bit BANK0:PIR1.TMR1IF 0 TMR1 Overflow Interrupt Flag bit BANK0:RESERVED000D 0x000D RESERVED BANK0:TMR1L 0x000E Holding register for the Least Significant Byte of the 16-bit TMR1 register BANK0:TMR1H 0x000F Holding register for the Most Significant Byte of the 16-bit TMR1 register BANK0:T1CON 0x0010 TIMER1 CONTROL REGISTER BANK0:T1CON.T1CKPS1 5 Timer1 Input Clock Prescale Select bit 1 BANK0:T1CON.T1CKPS0 4 Timer1 Input Clock Prescale Select bit 0 BANK0:T1CON.T1OSCEN 3 Timer1 Oscillator Enable Control bit BANK0:T1CON.T1SYNC 2 Timer1 External Clock Input Synchronization Control bit BANK0:T1CON.TMR1CS 1 Timer1 Clock Source Select bit BANK0:T1CON.TMR1ON 0 Timer1 On bit BANK0:TMR2 0x0011 Timer2 module's register BANK0:T2CON 0x0012 TIMER2 CONTROL REGISTER BANK0:T2CON.TOUTPS3 6 Timer2 Output Postscale Select bit 3 BANK0:T2CON.TOUTPS2 5 Timer2 Output Postscale Select bit 2 BANK0:T2CON.TOUTPS1 4 Timer2 Output Postscale Select bit 1 BANK0:T2CON.TOUTPS0 3 Timer2 Output Postscale Select bit 0 BANK0:T2CON.TMR2ON 2 Timer2 On bit BANK0:T2CON.T2CKPS1 1 Timer2 Clock Prescale Select bit 1 BANK0:T2CON.T2CKPS0 0 Timer2 Clock Prescale Select bit 0 BANK0:SSPBUF 0x0013 Synchronous Serial Port Receive Buffer/Transmit Register BANK0:SSPCON 0x0014 SYNC SERIAL PORT CONTROL REGISTER BANK0:SSPCON.WCOL 7 Write Collision Detect bit BANK0:SSPCON.SSPOV 6 Receive Overflow Indicator bit BANK0:SSPCON.SSPEN 5 Synchronous Serial Port Enable bit BANK0:SSPCON.CKP 4 Clock Polarity Select bit BANK0:SSPCON.SSPM3 3 Synchronous Serial Port Mode Select bit 3 BANK0:SSPCON.SSPM2 2 Synchronous Serial Port Mode Select bit 2 BANK0:SSPCON.SSPM1 1 Synchronous Serial Port Mode Select bit 1 BANK0:SSPCON.SSPM0 0 Synchronous Serial Port Mode Select bit 0 BANK0:CCPR1L 0x0015 Capture/Compare/PWM Register1 (LSB) BANK0:CCPR1H 0x0016 Capture/Compare/PWM Register1 (MSB) BANK0:CCP1CON 0x0017 CCP1CON REGISTER BANK0:CCP1CON.CCP1X 5 PWM Least Significant bit BANK0:CCP1CON.CCP1Y 4 PWM Least Significant bit BANK0:CCP1CON.CCP1M3 3 CCP1 Mode Select bit 3 BANK0:CCP1CON.CCP1M2 2 CCP1 Mode Select bit 2 BANK0:CCP1CON.CCP1M1 1 CCP1 Mode Select bit 1 BANK0:CCP1CON.CCP1M0 0 CCP1 Mode Select bit 0 BANK0:RESERVED0018 0x0018 RESERVED BANK0:RESERVED0019 0x0019 RESERVED BANK0:RESERVED001A 0x001A RESERVED BANK0:RESERVED001B 0x001B RESERVED BANK0:RESERVED001C 0x001C RESERVED BANK0:RESERVED001D 0x001D RESERVED BANK0:ADRES 0x001E A/D Result Register BANK0:ADCON0 0x001F ADCON0 REGISTER BANK0:ADCON0.ADCS1 7 A/D Conversion Clock Select bit 1 BANK0:ADCON0.ADCS0 6 A/D Conversion Clock Select bit 0 BANK0:ADCON0.CHS2 5 Analog Channel Select bit 2 BANK0:ADCON0.CHS1 4 Analog Channel Select bit 1 BANK0:ADCON0.CHS0 3 Analog Channel Select bit 0 BANK0:ADCON0.GO_DONE 2 A/D Conversion Status bit BANK0:ADCON0.ADON 0 A/D On bit ; BANK1 (0x0080:0x0100) BANK1:INDF 0x0080 INDF (not a physical register) BANK1:OPTION 0x0081 OPTION REGISTER BANK1:OPTION.RBPU 7 PORTB Pull-up Enable bit BANK1:OPTION.INTEDG 6 Interrupt Edge Select bit BANK1:OPTION.T0CS 5 TMR0 Clock Source Select bit BANK1:OPTION.T0SE 4 TMR0 Source Edge Select bit BANK1:OPTION.PSA 3 Prescaler Assignment bit BANK1:OPTION.PS2 2 Prescaler Rate Select bit 2 BANK1:OPTION.PS1 1 Prescaler Rate Select bit 1 BANK1:OPTION.PS0 0 Prescaler Rate Select bit 0 BANK1:PCL 0x0082 Program Counter's (PC) Least Significant Byte BANK1:STATUS 0x0083 STATUS REGISTER BANK1:STATUS.RP0 5 Register Bank Select bit 0 BANK1:STATUS.TO 4 Time-out bit BANK1:STATUS.PD 3 Power-down bit BANK1:STATUS.Z 2 Zero bit BANK1:STATUS.DC 1 Digit carry/borrow bit BANK1:STATUS.C 0 Carry/borrow bit BANK1:FSR 0x0084 Indirect data memory address pointer BANK1:TRISA 0x0085 PORTA Data Direction Register BANK1:TRISA.TRISA5 5 PORTA Data Direction Register bit 5 BANK1:TRISA.TRISA4 4 PORTA Data Direction Register bit 4 BANK1:TRISA.TRISA3 3 PORTA Data Direction Register bit 3 BANK1:TRISA.TRISA2 2 PORTA Data Direction Register bit 2 BANK1:TRISA.TRISA1 1 PORTA Data Direction Register bit 1 BANK1:TRISA.TRISA0 0 PORTA Data Direction Register bit 0 BANK1:TRISB 0x0086 PORTB Data Direction Register BANK1:TRISB.TRISB7 7 PORTB Data Direction Register bit 7 BANK1:TRISB.TRISB6 6 PORTB Data Direction Register bit 6 BANK1:TRISB.TRISB5 5 PORTB Data Direction Register bit 5 BANK1:TRISB.TRISB4 4 PORTB Data Direction Register bit 4 BANK1:TRISB.TRISB3 3 PORTB Data Direction Register bit 3 BANK1:TRISB.TRISB2 2 PORTB Data Direction Register bit 2 BANK1:TRISB.TRISB1 1 PORTB Data Direction Register bit 1 BANK1:TRISB.TRISB0 0 PORTB Data Direction Register bit 0 BANK1:TRISC 0x0087 PORTC Data Direction Register BANK1:TRISC.TRISC7 7 PORTC Data Direction Register bit 7 BANK1:TRISC.TRISC6 6 PORTC Data Direction Register bit 6 BANK1:TRISC.TRISC5 5 PORTC Data Direction Register bit 5 BANK1:TRISC.TRISC4 4 PORTC Data Direction Register bit 4 BANK1:TRISC.TRISC3 3 PORTC Data Direction Register bit 3 BANK1:TRISC.TRISC2 2 PORTC Data Direction Register bit 2 BANK1:TRISC.TRISC1 1 PORTC Data Direction Register bit 1 BANK1:TRISC.TRISC0 0 PORTC Data Direction Register bit 0 BANK1:RESERVED0088 0x0088 RESERVED BANK1:RESERVED0089 0x0089 RESERVED BANK1:PCLATH 0x008A Write Buffer for the upper 5 bits of the Program Counter BANK1:INTCON 0x008B INTCON REGISTER BANK1:INTCON.GIE 7 Global Interrupt Enable bit BANK1:INTCON.PEIE 6 Peripheral Interrupt Enable bit BANK1:INTCON.T0IE 5 TMR0 Overflow Interrupt Enable bit BANK1:INTCON.INTE 4 RB0/INT External Interrupt Enable bit BANK1:INTCON.RBIE 3 RB Port Change Interrupt Enable bit BANK1:INTCON.T0IF 2 TMR0 Overflow Interrupt Flag bit BANK1:INTCON.INTF 1 RB0/INT External Interrupt Flag bit BANK1:INTCON.RBIF 0 RB Port Change Interrupt Flag bit BANK1:PIE1 0x008C PIE1 REGISTER BANK1:PIE1.ADIE 6 A/D Converter Interrupt Enable bit (NOT IN PIC16C62B) BANK1:PIE1.SSPIE 3 Synchronous Serial Port Interrupt Enable bit BANK1:PIE1.CCP1IE 2 CCP1 Interrupt Enable bit BANK1:PIE1.TMR2IE 1 TMR2 to PR2 Match Interrupt Enable bit BANK1:PIE1.TMR1IE 0 TMR1 Overflow Interrupt Enable bit BANK1:RESERVED008D 0x008D RESERVED BANK1:PCON 0x008E PCON REGISTER BANK1:PCON.POR 1 Power-on Reset Status bit BANK1:PCON.BOR 0 Brown-out Reset Status bit BANK1:RESERVED008F 0x008F RESERVED BANK1:RESERVED0090 0x0090 RESERVED BANK1:RESERVED0091 0x0091 RESERVED BANK1:PR2 0x0092 Timer2 Period Register BANK1:SSPADD 0x0093 Synchronous Serial Port (I2C mode) Address Register BANK1:SSPSTAT 0x0094 SYNC SERIAL PORT STATUS REGISTER BANK1:SSPSTAT.SMP 7 SPI data input sample phase BANK1:SSPSTAT.CKE 6 SPI Clock Edge Select BANK1:SSPSTAT.D_A 5 Data/Address bit (I2C mode only) BANK1:SSPSTAT.P 4 Stop bit (I2C mode only) BANK1:SSPSTAT.S 3 Start bit (I2C mode only) BANK1:SSPSTAT.R_W 2 Read/Write bit information (I2C mode only) BANK1:SSPSTAT.UA 1 Update Address (I2C mode only) BANK1:SSPSTAT.BF 0 Buffer Full Status bit BANK1:RESERVED0095 0x0095 RESERVED BANK1:RESERVED0096 0x0096 RESERVED BANK1:RESERVED0097 0x0097 RESERVED BANK1:RESERVED0098 0x0098 RESERVED BANK1:RESERVED0099 0x0099 RESERVED BANK1:RESERVED009A 0x009A RESERVED BANK1:RESERVED009B 0x009B RESERVED BANK1:RESERVED009C 0x009C RESERVED BANK1:RESERVED009D 0x009D RESERVED BANK1:RESERVED009E 0x009E RESERVED BANK1:ADCON1 0x009F ADCON1 REGISTER BANK1:ADCON1.PCFG2 2 A/D Port Configuration Control bit 2 BANK1:ADCON1.PCFG1 1 A/D Port Configuration Control bit 1 BANK1:ADCON1.PCFG0 0 A/D Port Configuration Control bit 0 .16C745 ; http://www.microchip.com/download/lit/pline/picmicro/families/16c7xx/41124c.pdf ; PIC16C745_65.pdf ; MEMORY MAP ; BANK_0 area DATA FSR_ 0x0000:0x0020 area DATA Gen_Purp 0x0020:0x0080 General Purpose Register area DATA MEM_Program0 0x0080:0x0800 On-chip Program Memory (Page 0) area DATA MEM_Program1 0x0800:0x1000 On-chip Program Memory (Page 1) area DATA MEM_Program2 0x1000:0x1800 On-chip Program Memory (Page 2) area DATA MEM_Program3 0x1800:0x2000 On-chip Program Memory (Page 3) ; BANK_1 ; area DATA FSR_ 0x0080:0x00A0 ; area DATA Gen_Purp 0x00A0:0x00F0 General Purpose Register ; area DATA Gen_Purp_BANK0 0x00F0:0x0100 accesses 70h-7Fh ; area DATA MEM_Program0 0x0100:0x0800 On-chip Program Memory (Page 0) ; area DATA MEM_Program1 0x0800:0x1000 On-chip Program Memory (Page 1) ; area DATA MEM_Program2 0x1000:0x1800 On-chip Program Memory (Page 2) ; area DATA MEM_Program3 0x1800:0x2000 On-chip Program Memory (Page 3) ; BANK_2 ; area DATA FSR_ 0x0100:0x0120 ; area DATA Gen_Purp 0x0120:0x0170 General Purpose Register ; area DATA Gen_Purp_BANK0 0x0170:0x0180 accesses 70h-7Fh ; area DATA MEM_Program0 0x0180:0x0800 On-chip Program Memory (Page 0) ; area DATA MEM_Program1 0x0800:0x1000 On-chip Program Memory (Page 1) ; area DATA MEM_Program2 0x1000:0x1800 On-chip Program Memory (Page 2) ; area DATA MEM_Program3 0x1800:0x2000 On-chip Program Memory (Page 3) ; BANK_3 ; area DATA FSR_ 0x0180:0x01A0 ; area DATA USB_ 0x01A0:0x01B8 USB Dual Port Memory ; area DATA USB_BUFF 0x01B8:0x01E0 USB Buffer (40 byte) ; area BSS RESERVED 0x01E0:0x01F0 ; area DATA Gen_Purp_BANK0 0x01F0:0x0200 accesses 70h-7Fh ; area DATA MEM_Program0 0x0200:0x0800 On-chip Program Memory (Page 0) ; area DATA MEM_Program1 0x0800:0x1000 On-chip Program Memory (Page 1) ; area DATA MEM_Program2 0x1000:0x1800 On-chip Program Memory (Page 2) ; area DATA MEM_Program3 0x1800:0x2000 On-chip Program Memory (Page 3) ; Interrupt and reset vector assignments interrupt RESET 0x0000 RESET ; INPUT/OUTPUT PORTS ; BANK0 (0x0000:0x0080) BANK0:INDF 0x0000 INDF (not a physical register) BANK0:TMR0 0x0001 Timer0 module's register BANK0:PCL 0x0002 Program Counter's (PC) Least Significant Byte BANK0:STATUS 0x0003 STATUS REGISTER BANK0:STATUS.IRP 7 Register Bank Select bit BANK0:STATUS.RP1 6 Register Bank Select bit 1 BANK0:STATUS.RP0 5 Register Bank Select bit 0 BANK0:STATUS.TO 4 Time-out bit BANK0:STATUS.PD 3 Power-down bit BANK0:STATUS.Z 2 Zero bit BANK0:STATUS.DC 1 Digit carry/borrow bit BANK0:STATUS.C 0 Carry/borrow bit BANK0:FSR 0x0004 Indirect data memory address pointer BANK0:PORTA 0x0005 PORTA REGISTER BANK0:PORTA.RA5 5 PORTA bit 5 BANK0:PORTA.RA4 4 PORTA bit 4 BANK0:PORTA.RA3 3 PORTA bit 3 BANK0:PORTA.RA2 2 PORTA bit 2 BANK0:PORTA.RA1 1 PORTA bit 1 BANK0:PORTA.RA0 0 PORTA bit 0 BANK0:PORTB 0x0006 PORTB REGISTER BANK0:PORTB.RB7 7 PORTB bit 7 BANK0:PORTB.RB6 6 PORTB bit 6 BANK0:PORTB.RB5 5 PORTB bit 5 BANK0:PORTB.RB4 4 PORTB bit 4 BANK0:PORTB.RB3 3 PORTB bit 3 BANK0:PORTB.RB2 2 PORTB bit 2 BANK0:PORTB.RB1 1 PORTB bit 1 BANK0:PORTB.RB0 0 PORTB bit 0 BANK0:PORTC 0x0007 PORTC REGISTER BANK0:PORTC.RC7 7 PORTC bit 7 BANK0:PORTC.RC6 6 PORTC bit 6 BANK0:PORTC.RC2 2 PORTC bit 2 BANK0:PORTC.RC1 1 PORTC bit 1 BANK0:PORTC.RC0 0 PORTC bit 0 BANK0:RESERVED0008 0x0008 RESERVED BANK0:RESERVED0009 0x0009 RESERVED BANK0:PCLATH 0x000A Write Buffer for the upper 5 bits of the Program Counter BANK0:INTCON 0x000B INTCON REGISTER BANK0:INTCON.GIE 7 Global Interrupt Enable bit BANK0:INTCON.PEIE 6 Peripheral Interrupt Enable bit BANK0:INTCON.T0IE 5 TMR0 Overflow Interrupt Enable bit BANK0:INTCON.INTE 4 RB0/INT External Interrupt Enable bit BANK0:INTCON.RBIE 3 RB Port Change Interrupt Enable bit BANK0:INTCON.T0IF 2 TMR0 Overflow Interrupt Flag bit BANK0:INTCON.INTF 1 RB0/INT External Interrupt Flag bit BANK0:INTCON.RBIF 0 RB Port Change Interrupt Flag bit BANK0:PIR1 0x000C PIR1 REGISTER BANK0:PIR1.PSPIF 7 Parallel Slave Port Read/Write Interrupt Flag bit BANK0:PIR1.ADIF 6 A/D Converter Interrupt Flag bit BANK0:PIR1.RCIF 5 USART Receive Interrupt Flag bit BANK0:PIR1.TXIF 4 USART Transmit Interrupt Flag bit BANK0:PIR1.USBIF 3 Universal Serial Bus (USB) Interrupt Flag BANK0:PIR1.CCP1IF 2 CCP1 Interrupt Flag bit BANK0:PIR1.TMR2IF 1 TMR2 to PR2 Match Interrupt Flag bit BANK0:PIR1.TMR1IF 0 TMR1 Overflow Interrupt Flag bit BANK0:PIR2 0x000D PIR2 REGISTER BANK0:PIR2.CCP2IF 0 CCP2 Interrupt Flag bit BANK0:TMR1L 0x000E Holding register for the Least Significant Byte of the 16-bit TMR1 register BANK0:TMR1H 0x000F Holding register for the Most Significant Byte of the 16-bit TMR1 register BANK0:T1CON 0x0010 TIMER1 CONTROL REGISTER BANK0:T1CON.T1CKPS1 5 Timer1 Input Clock Prescale Select bit 1 BANK0:T1CON.T1CKPS0 4 Timer1 Input Clock Prescale Select bit 0 BANK0:T1CON.T1OSCEN 3 Timer1 Oscillator Enable Control bit BANK0:T1CON.T1SYNC 2 Timer1 External Clock Input Synchronization Control bit BANK0:T1CON.TMR1CS 1 Timer1 Clock Source Select bit BANK0:T1CON.TMR1ON 0 Timer1 On bit BANK0:TMR2 0x0011 Timer2 module's register BANK0:T2CON 0x0012 TIMER2 CONTROL REGISTER BANK0:T2CON.TOUTPS3 6 Timer2 Output Postscale Select bit 3 BANK0:T2CON.TOUTPS2 5 Timer2 Output Postscale Select bit 2 BANK0:T2CON.TOUTPS1 4 Timer2 Output Postscale Select bit 1 BANK0:T2CON.TOUTPS0 3 Timer2 Output Postscale Select bit 0 BANK0:T2CON.TMR2ON 2 Timer2 On bit BANK0:T2CON.T2CKPS1 1 Timer2 Clock Prescale Select bit 1 BANK0:T2CON.T2CKPS0 0 Timer2 Clock Prescale Select bit 0 BANK0:RESERVED0013 0x0013 RESERVED BANK0:RESERVED0014 0x0014 RESERVED BANK0:CCPR1L 0x0015 Capture/Compare/PWM Register1 (LSB) BANK0:CCPR1H 0x0016 Capture/Compare/PWM Register1 (MSB) BANK0:CCP1CON 0x0017 CCP1CON REGISTER BANK0:CCP1CON.DC1B1 5 PWM Least Significant bit 1 BANK0:CCP1CON.DC1B0 4 PWM Least Significant bit 0 BANK0:CCP1CON.CCP1M3 3 CCP1 Mode Select bit 3 BANK0:CCP1CON.CCP1M2 2 CCP1 Mode Select bit 2 BANK0:CCP1CON.CCP1M1 1 CCP1 Mode Select bit 1 BANK0:CCP1CON.CCP1M0 0 CCP1 Mode Select bit 0 BANK0:RCSTA 0x0018 RECEIVE STATUS AND CONTROL REGISTER BANK0:RCSTA.SPEN 7 Serial Port Enable bit BANK0:RCSTA.RX9 6 9-bit Receive Enable bit BANK0:RCSTA.SREN 5 Single Receive Enable bit BANK0:RCSTA.CREN 4 Continuous Receive Enable bit BANK0:RCSTA.FERR 2 Framing Error bit BANK0:RCSTA.OERR 1 Overrun Error bit BANK0:RCSTA.RX9D 0 9th bit of received data BANK0:TXREG 0x0019 USART Transmit Data Register BANK0:RCREG 0x001A USART Receive Data Register BANK0:CCPR2L 0x001B Capture/Compare/PWM Register2 (LSB) BANK0:CCPR2H 0x001C Capture/Compare/PWM Register2 (MSB) BANK0:CCP2CON 0x001D CCP2CON REGISTER BANK0:CCP2CON.DC2B1 5 PWM Least Significant bit 1 BANK0:CCP2CON.DC2B0 4 PWM Least Significant bit 0 BANK0:CCP2CON.CCP2M3 3 CCP2 Mode Select bit 3 BANK0:CCP2CON.CCP2M2 2 CCP2 Mode Select bit 2 BANK0:CCP2CON.CCP2M1 1 CCP2 Mode Select bit 1 BANK0:CCP2CON.CCP2M0 0 CCP2 Mode Select bit 0 BANK0:ADRES 0x001E A/D Result Register BANK0:ADCON0 0x001F ADCON0 REGISTER BANK0:ADCON0.ADCS1 7 A/D Conversion Clock Select bit 1 BANK0:ADCON0.ADCS0 6 A/D Conversion Clock Select bit 0 BANK0:ADCON0.CHS2 5 Analog Channel Select bit 2 BANK0:ADCON0.CHS1 4 Analog Channel Select bit 1 BANK0:ADCON0.CHS0 3 Analog Channel Select bit 0 BANK0:ADCON0.GO_DONE 2 A/D Conversion Status bit BANK0:ADCON0.ADON 0 A/D On bit ; BANK1 (0x0080:0x0100) BANK1:INDF 0x0080 INDF (not a physical register) BANK1:OPTION 0x0081 OPTION REGISTER BANK1:OPTION.RBPU 7 PORTB Pull-up Enable bit BANK1:OPTION.INTEDG 6 Interrupt Edge Select bit BANK1:OPTION.T0CS 5 TMR0 Clock Source Select bit BANK1:OPTION.T0SE 4 TMR0 Source Edge Select bit BANK1:OPTION.PSA 3 Prescaler Assignment bit BANK1:OPTION.PS2 2 Prescaler Rate Select bit 2 BANK1:OPTION.PS1 1 Prescaler Rate Select bit 1 BANK1:OPTION.PS0 0 Prescaler Rate Select bit 0 BANK1:PCL 0x0082 Program Counter's (PC) Least Significant Byte BANK1:STATUS 0x0083 STATUS REGISTER BANK1:STATUS.IRP 7 Register Bank Select bit BANK1:STATUS.RP1 6 Register Bank Select bit 1 BANK1:STATUS.RP0 5 Register Bank Select bit 0 BANK1:STATUS.TO 4 Time-out bit BANK1:STATUS.PD 3 Power-down bit BANK1:STATUS.Z 2 Zero bit BANK1:STATUS.DC 1 Digit carry/borrow bit BANK1:STATUS.C 0 Carry/borrow bit BANK1:FSR 0x0084 Indirect data memory address pointer BANK1:TRISA 0x0085 PORTA Data Direction Register BANK1:TRISA.TRISA5 5 PORTA Data Direction Register bit 5 BANK1:TRISA.TRISA4 4 PORTA Data Direction Register bit 4 BANK1:TRISA.TRISA3 3 PORTA Data Direction Register bit 3 BANK1:TRISA.TRISA2 2 PORTA Data Direction Register bit 2 BANK1:TRISA.TRISA1 1 PORTA Data Direction Register bit 1 BANK1:TRISA.TRISA0 0 PORTA Data Direction Register bit 0 BANK1:TRISB 0x0086 PORTB Data Direction Register BANK1:TRISB.TRISB7 7 PORTB Data Direction Register bit 7 BANK1:TRISB.TRISB6 6 PORTB Data Direction Register bit 6 BANK1:TRISB.TRISB5 5 PORTB Data Direction Register bit 5 BANK1:TRISB.TRISB4 4 PORTB Data Direction Register bit 4 BANK1:TRISB.TRISB3 3 PORTB Data Direction Register bit 3 BANK1:TRISB.TRISB2 2 PORTB Data Direction Register bit 2 BANK1:TRISB.TRISB1 1 PORTB Data Direction Register bit 1 BANK1:TRISB.TRISB0 0 PORTB Data Direction Register bit 0 BANK1:TRISC 0x0087 PORTC Data Direction Register BANK1:TRISC.TRISC7 7 PORTC Data Direction Register bit 7 BANK1:TRISC.TRISC6 6 PORTC Data Direction Register bit 6 BANK1:TRISC.TRISC2 2 PORTC Data Direction Register bit 2 BANK1:TRISC.TRISC1 1 PORTC Data Direction Register bit 1 BANK1:TRISC.TRISC0 0 PORTC Data Direction Register bit 0 BANK1:RESERVED0088 0x0088 RESERVED BANK1:RESERVED0089 0x0089 RESERVED BANK1:PCLATH 0x008A Write Buffer for the upper 5 bits of the Program Counter BANK1:INTCON 0x008B INTCON REGISTER BANK1:INTCON.GIE 7 Global Interrupt Enable bit BANK1:INTCON.PEIE 6 Peripheral Interrupt Enable bit BANK1:INTCON.T0IE 5 TMR0 Overflow Interrupt Enable bit BANK1:INTCON.INTE 4 RB0/INT External Interrupt Enable bit BANK1:INTCON.RBIE 3 RB Port Change Interrupt Enable bit BANK1:INTCON.T0IF 2 TMR0 Overflow Interrupt Flag bit BANK1:INTCON.INTF 1 RB0/INT External Interrupt Flag bit BANK1:INTCON.RBIF 0 RB Port Change Interrupt Flag bit BANK1:PIE1 0x008C PIE1 REGISTER BANK1:PIE1.PSPIE 7 Parallel Slave Port Read/Write Interrupt Enable bit BANK1:PIE1.ADIE 6 A/D Converter Interrupt Enable bit BANK1:PIE1.RCIE 5 USART Receive Interrupt Enable bit BANK1:PIE1.TXIE 4 USART Transmit Interrupt Enable bit BANK1:PIE1.USBIE 3 Universal Serial Bus Interrupt Enable bit BANK1:PIE1.CCP1IE 2 CCP1 Interrupt Enable bit BANK1:PIE1.TMR2IE 1 TMR2 to PR2 Match Interrupt Enable bit BANK1:PIE1.TMR1IE 0 TMR1 Overflow Interrupt Enable bit BANK1:PIE2 0x008D PIE2 REGISTER BANK1:PIE2.CCP2IE 0 CCP2 Interrupt Enable bit BANK1:PCON 0x008E PCON REGISTER BANK1:PCON.POR 1 Power-on Reset Status bit BANK1:PCON.BOR 0 Brown-out Reset Status bit BANK1:RESERVED008F 0x008F RESERVED BANK1:RESERVED0090 0x0090 RESERVED BANK1:RESERVED0091 0x0091 RESERVED BANK1:PR2 0x0092 Timer2 Period Register BANK1:RESERVED0093 0x0093 RESERVED BANK1:RESERVED0094 0x0094 RESERVED BANK1:RESERVED0095 0x0095 RESERVED BANK1:RESERVED0096 0x0096 RESERVED BANK1:RESERVED0097 0x0097 RESERVED BANK1:TXSTA 0x0098 TRANSMIT STATUS AND CONTROL REGISTER BANK1:TXSTA.CSRC 7 Clock Source Select bit BANK1:TXSTA.TX9 6 9-bit Transmit Enable bit BANK1:TXSTA.TXEN 5 Transmit Enable bit BANK1:TXSTA.SYNC 4 USART Mode Select bit BANK1:TXSTA.BRGH 2 High Baud Rate Select bit BANK1:TXSTA.TRMT 1 Transmit Shift Register Status bit BANK1:TXSTA.TX9D 0 9th bit of transmit data. Can be parity bit BANK1:SPBRG 0x0099 Baud Rate Generator Register BANK1:RESERVED009A 0x009A RESERVED BANK1:RESERVED009B 0x009B RESERVED BANK1:RESERVED009C 0x009C RESERVED BANK1:RESERVED009D 0x009D RESERVED BANK1:RESERVED009E 0x009E RESERVED BANK1:ADCON1 0x009F ADCON1 REGISTER BANK1:ADCON1.PCFG2 2 A/D Port Configuration Control bit 2 BANK1:ADCON1.PCFG1 1 A/D Port Configuration Control bit 1 BANK1:ADCON1.PCFG0 0 A/D Port Configuration Control bit 0 ; BANK2 (0x0100:0x0180) BANK2:INDF 0x0100 INDF (not a physical register) BANK2:TMR0 0x0101 Timer0 module's register BANK2:PCL 0x0102 Program Counter's (PC) Least Significant Byte BANK2:STATUS 0x0103 STATUS REGISTER BANK2:STATUS.IRP 7 Register Bank Select bit BANK2:STATUS.RP1 6 Register Bank Select bit 1 BANK2:STATUS.RP0 5 Register Bank Select bit 0 BANK2:STATUS.TO 4 Time-out bit BANK2:STATUS.PD 3 Power-down bit BANK2:STATUS.Z 2 Zero bit BANK2:STATUS.DC 1 Digit carry/borrow bit BANK2:STATUS.C 0 Carry/borrow bit BANK2:FSR 0x0104 Indirect data memory address pointer BANK2:RESERVED0105 0x0105 RESERVED BANK2:PORTB 0x0106 PORTB REGISTER BANK2:PORTB.RB7 7 PORTB bit 7 BANK2:PORTB.RB6 6 PORTB bit 6 BANK2:PORTB.RB5 5 PORTB bit 5 BANK2:PORTB.RB4 4 PORTB bit 4 BANK2:PORTB.RB3 3 PORTB bit 3 BANK2:PORTB.RB2 2 PORTB bit 2 BANK2:PORTB.RB1 1 PORTB bit 1 BANK2:PORTB.RB0 0 PORTB bit 0 BANK2:RESERVED0107 0x0107 RESERVED BANK2:RESERVED0108 0x0108 RESERVED BANK2:RESERVED0109 0x0109 RESERVED BANK2:PCLATH 0x010A Write Buffer for the upper 5 bits of the Program Counter BANK2:INTCON 0x010B INTCON REGISTER BANK2:INTCON.GIE 7 Global Interrupt Enable bit BANK2:INTCON.PEIE 6 Peripheral Interrupt Enable bit BANK2:INTCON.T0IE 5 TMR0 Overflow Interrupt Enable bit BANK2:INTCON.INTE 4 RB0/INT External Interrupt Enable bit BANK2:INTCON.RBIE 3 RB Port Change Interrupt Enable bit BANK2:INTCON.T0IF 2 TMR0 Overflow Interrupt Flag bit BANK2:INTCON.INTF 1 RB0/INT External Interrupt Flag bit BANK2:INTCON.RBIF 0 RB Port Change Interrupt Flag bit BANK2:RESERVED010C 0x010C RESERVED BANK2:RESERVED010D 0x010D RESERVED BANK2:RESERVED010E 0x010E RESERVED BANK2:RESERVED010F 0x010F RESERVED BANK2:RESERVED0110 0x0110 RESERVED BANK2:RESERVED0111 0x0111 RESERVED BANK2:RESERVED0112 0x0112 RESERVED BANK2:RESERVED0113 0x0113 RESERVED BANK2:RESERVED0114 0x0114 RESERVED BANK2:RESERVED0115 0x0115 RESERVED BANK2:RESERVED0116 0x0116 RESERVED BANK2:RESERVED0117 0x0117 RESERVED BANK2:RESERVED0118 0x0118 RESERVED BANK2:RESERVED0119 0x0119 RESERVED BANK2:RESERVED011A 0x011A RESERVED BANK2:RESERVED011B 0x011B RESERVED BANK2:RESERVED011C 0x011C RESERVED BANK2:RESERVED011D 0x011D RESERVED BANK2:RESERVED011E 0x011E RESERVED BANK2:RESERVED011F 0x011F RESERVED ; BANK3 (0x0180:0x0200) BANK3:INDF 0x0180 INDF (not a physical register) BANK3:OPTION 0x0181 OPTION REGISTER BANK3:OPTION.RBPU 7 PORTB Pull-up Enable bit BANK3:OPTION.INTEDG 6 Interrupt Edge Select bit BANK3:OPTION.T0CS 5 TMR0 Clock Source Select bit BANK3:OPTION.T0SE 4 TMR0 Source Edge Select bit BANK3:OPTION.PSA 3 Prescaler Assignment bit BANK3:OPTION.PS2 2 Prescaler Rate Select bit 2 BANK3:OPTION.PS1 1 Prescaler Rate Select bit 1 BANK3:OPTION.PS0 0 Prescaler Rate Select bit 0 BANK3:PCL 0x0182 Program Counter's (PC) Least Significant Byte BANK3:STATUS 0x0183 STATUS REGISTER BANK3:STATUS.IRP 7 Register Bank Select bit BANK3:STATUS.RP1 6 Register Bank Select bit 1 BANK3:STATUS.RP0 5 Register Bank Select bit 0 BANK3:STATUS.TO 4 Time-out bit BANK3:STATUS.PD 3 Power-down bit BANK3:STATUS.Z 2 Zero bit BANK3:STATUS.DC 1 Digit carry/borrow bit BANK3:STATUS.C 0 Carry/borrow bit BANK3:FSR 0x0184 Indirect data memory address pointer BANK3:RESERVED0185 0x0185 RESERVED BANK3:TRISB 0x0186 PORTB Data Direction Register BANK3:TRISB.TRISB7 7 PORTB Data Direction Register bit 7 BANK3:TRISB.TRISB6 6 PORTB Data Direction Register bit 6 BANK3:TRISB.TRISB5 5 PORTB Data Direction Register bit 5 BANK3:TRISB.TRISB4 4 PORTB Data Direction Register bit 4 BANK3:TRISB.TRISB3 3 PORTB Data Direction Register bit 3 BANK3:TRISB.TRISB2 2 PORTB Data Direction Register bit 2 BANK3:TRISB.TRISB1 1 PORTB Data Direction Register bit 1 BANK3:TRISB.TRISB0 0 PORTB Data Direction Register bit 0 BANK3:RESERVED0187 0x0187 RESERVED BANK3:RESERVED0188 0x0188 RESERVED BANK3:RESERVED0189 0x0189 RESERVED BANK3:PCLATH 0x018A Write Buffer for the upper 5 bits of the Program Counter BANK3:INTCON 0x018B INTCON REGISTER BANK3:INTCON.GIE 7 Global Interrupt Enable bit BANK3:INTCON.PEIE 6 Peripheral Interrupt Enable bit BANK3:INTCON.T0IE 5 TMR0 Overflow Interrupt Enable bit BANK3:INTCON.INTE 4 RB0/INT External Interrupt Enable bit BANK3:INTCON.RBIE 3 RB Port Change Interrupt Enable bit BANK3:INTCON.T0IF 2 TMR0 Overflow Interrupt Flag bit BANK3:INTCON.INTF 1 RB0/INT External Interrupt Flag bit BANK3:INTCON.RBIF 0 RB Port Change Interrupt Flag bit BANK3:RESERVED018C 0x018C RESERVED BANK3:RESERVED018D 0x018D RESERVED BANK3:RESERVED018E 0x018E RESERVED BANK3:RESERVED018F 0x018F RESERVED BANK3:UIR 0x0190 USB INTERRUPT FLAGS REGISTER BANK3:UIR.STALL 5 A STALL handshake was sent by the SIE BANK3:UIR.UIDLE 4 BANK3:UIR.TOK_DNE 3 BANK3:UIR.ACTIVITY 2 BANK3:UIR.UERR 1 BANK3:UIR.USB_RST 0 BANK3:UIE 0x0191 USB INTERRUPT ENABLE REGISTER BANK3:UIE.STALL 5 Set to enable STALL interrupts BANK3:UIE.UIDLE 4 Set to enable IDLE interrupts BANK3:UIE.TOK_DNE 3 Set to enable TOK_DNE interrupts BANK3:UIE.ACTIVITY 2 Set to enable ACTIVITY interrupts BANK3:UIE.UERR 1 Set to enable ERROR interrupts BANK3:UIE.USB_RST 0 Set to enable USB_RST interrupts BANK3:UEIR 0x0192 USB ERROR INTERRUPT FLAGS STATUS REGISTER BANK3:UEIR.BTS_ERR 7 A bit stuff error has been detected BANK3:UEIR.OWN_ERR 6 BANK3:UEIR.WRT_ERR 5 Write Error BANK3:UEIR.BTO_ERR 4 BANK3:UEIR.DFN8 3 BANK3:UEIR.CRC16 2 The CRC16 failed BANK3:UEIR.CRC5 1 BANK3:UEIR.PID_ERR 0 The PID check field failed BANK3:UEIE 0x0193 USB ERROR INTERRUPT ENABLE REGISTER BANK3:UEIE.BTS_ERR 7 Set this bit to enable BTS_ERR interrupts BANK3:UEIE.OWN_ERR 6 Set this bit to enable OWN_ERR interrupts BANK3:UEIE.WRT_ERR 5 Set this bit to enable WRT_ERR interrupts BANK3:UEIE.BTO_ERR 4 Set this bit to enable BTO_ERR interrupts BANK3:UEIE.DFN8 3 Set this bit to enable DFN8 interrupts BANK3:UEIE.CRC16 2 Set this bit to enable CRC16 interrupts BANK3:UEIE.CRC5 1 Set this bit to enable CRC5 interrupts BANK3:UEIE.PID_ERR 0 Set this bit to enable PID_ERR interrupts BANK3:USTAT 0x0194 USB STATUS REGISTER BANK3:USTAT.ENDP1 4 BANK3:USTAT.ENDP0 3 BANK3:USTAT.IN 2 BANK3:UCTRL 0x0195 USB CONTROL REGISTER BANK3:UCTRL.SEO 5 Live Single Ended Zero BANK3:UCTRL.PKT_DIS 4 BANK3:UCTRL.DEV_ATT 3 Device Attach BANK3:UCTRL.RESUME 2 BANK3:UCTRL.SUSPND 1 BANK3:UADDR 0x0196 USB ADDRESS REGISTER BANK3:UADDR.ADDR6 6 BANK3:UADDR.ADDR5 5 BANK3:UADDR.ADDR4 4 BANK3:UADDR.ADDR3 3 BANK3:UADDR.ADDR2 2 BANK3:UADDR.ADDR1 1 BANK3:UADDR.ADDR0 0 BANK3:USWSTAT 0x0197 RESERVED SOFTWARE LIBRARY REGISTER BANK3:USWSTAT.SWSTAT7 7 BANK3:USWSTAT.SWSTAT6 6 BANK3:USWSTAT.SWSTAT5 5 BANK3:USWSTAT.SWSTAT4 4 BANK3:USWSTAT.SWSTAT3 3 BANK3:USWSTAT.SWSTAT2 2 BANK3:USWSTAT.SWSTAT1 1 BANK3:USWSTAT.SWSTAT0 0 BANK3:UEP0 0x0198 USB ENDPOINT CONTROL REGISTER 0 BANK3:UEP0.EP_CTL_DIS 3 BANK3:UEP0.EP_OUT_EN 2 BANK3:UEP0.EP_IN_EN 1 BANK3:UEP0.EP_STALL 0 BANK3:UEP1 0x0199 USB ENDPOINT CONTROL REGISTER 1 BANK3:UEP1.EP_CTL_DIS 3 BANK3:UEP1.EP_OUT_EN 2 BANK3:UEP1.EP_IN_EN 1 BANK3:UEP1.EP_STALL 0 BANK3:UEP2 0x019A USB ENDPOINT CONTROL REGISTER 2 BANK3:UEP2.EP_CTL_DIS 3 BANK3:UEP2.EP_OUT_EN 2 BANK3:UEP2.EP_IN_EN 1 BANK3:UEP2.EP_STALL 0 BANK3:RESERVED019B 0x019B RESERVED BANK3:RESERVED019C 0x019C RESERVED BANK3:RESERVED019D 0x019D RESERVED BANK3:RESERVED019E 0x019E RESERVED BANK3:RESERVED019F 0x019F RESERVED ; USB DUAL PORT RAM BANK3:BD0OST 0x01A0 BUFFER DESCRIPTOR STATUS REGISTER 0 BANK3:BD0OST.UOWN_UOWN 7 USB Own BANK3:BD0OST.DATA0_1_DATA0_1 6 Data 0/1 packet BANK3:BD0OST.PID3 5 Packet Identifier 3 BANK3:BD0OST.PID2 4 Packet Identifier 2 BANK3:BD0OST.PID1_DTS 3 Packet Identifier 1 BANK3:BD0OST.PID0_BSTALL 2 Buffer Stall BANK3:BD0OBC 0x01A1 BUFFER DESCRIPTOR Byte Count (3-0) BANK3:BD0OBC.BC3 3 BANK3:BD0OBC.BC2 2 BANK3:BD0OBC.BC1 1 BANK3:BD0OBC.BC0 0 BANK3:BD0OAL 0x01A2 Buffer Address Low BANK3:BD0OAL.BA7 7 Buffer Address 7 BANK3:BD0OAL.BA6 6 Buffer Address 6 BANK3:BD0OAL.BA5 5 Buffer Address 5 BANK3:BD0OAL.BA4 4 Buffer Address 4 BANK3:BD0OAL.BA3 3 Buffer Address 3 BANK3:BD0OAL.BA2 2 Buffer Address 2 BANK3:BD0OAL.BA1 1 Buffer Address 1 BANK3:BD0OAL.BA0 0 Buffer Address 0 BANK3:RESERVED01A3 0x01A3 RESERVED BANK3:BD0IST 0x01A4 BUFFER DESCRIPTOR STATUS REGISTER 0 BANK3:BD0IST.UOWN_UOWN 7 USB Own BANK3:BD0IST.DATA0_1_DATA0_1 6 Data 0/1 packet BANK3:BD0IST.PID3 5 Packet Identifier 3 BANK3:BD0IST.PID2 4 Packet Identifier 2 BANK3:BD0IST.PID1_DTS 3 Packet Identifier 1 BANK3:BD0IST.PID0_BSTALL 2 Buffer Stall BANK3:BD0IBC 0x01A5 BUFFER DESCRIPTOR Byte Count (3-0) BANK3:BD0IBC.BC3 3 BANK3:BD0IBC.BC2 2 BANK3:BD0IBC.BC1 1 BANK3:BD0IBC.BC0 0 BANK3:BD0IAL 0x01A6 Buffer Address Low BANK3:BD0IAL.BA7 7 Buffer Address 7 BANK3:BD0IAL.BA6 6 Buffer Address 6 BANK3:BD0IAL.BA5 5 Buffer Address 5 BANK3:BD0IAL.BA4 4 Buffer Address 4 BANK3:BD0IAL.BA3 3 Buffer Address 3 BANK3:BD0IAL.BA2 2 Buffer Address 2 BANK3:BD0IAL.BA1 1 Buffer Address 1 BANK3:BD0IAL.BA0 0 Buffer Address 0 BANK3:RESERVED01A7 0x01A7 RESERVED BANK3:BD1OST 0x01A8 BUFFER DESCRIPTOR STATUS REGISTER 1 BANK3:BD1OST.UOWN_UOWN 7 USB Own BANK3:BD1OST.DATA0_1_DATA0_1 6 Data 0/1 packet BANK3:BD1OST.PID3 5 Packet Identifier 3 BANK3:BD1OST.PID2 4 Packet Identifier 2 BANK3:BD1OST.PID1_DTS 3 Packet Identifier 1 BANK3:BD1OST.PID0_BSTALL 2 Buffer Stall BANK3:BD1OBC 0x01A9 BUFFER DESCRIPTOR Byte Count (3-0) BANK3:BD1OBC.BC3 3 BANK3:BD1OBC.BC2 2 BANK3:BD1OBC.BC1 1 BANK3:BD1OBC.BC0 0 BANK3:BD1OAL 0x01AA Buffer Address Low BANK3:BD1OAL.BA7 7 Buffer Address 7 BANK3:BD1OAL.BA6 6 Buffer Address 6 BANK3:BD1OAL.BA5 5 Buffer Address 5 BANK3:BD1OAL.BA4 4 Buffer Address 4 BANK3:BD1OAL.BA3 3 Buffer Address 3 BANK3:BD1OAL.BA2 2 Buffer Address 2 BANK3:BD1OAL.BA1 1 Buffer Address 1 BANK3:BD1OAL.BA0 0 Buffer Address 0 BANK3:RESERVED01AB 0x01AB RESERVED BANK3:BD1IST 0x01AC BUFFER DESCRIPTOR STATUS REGISTER 1 BANK3:BD1IST.UOWN_UOWN 7 USB Own BANK3:BD1IST.DATA0_1_DATA0_1 6 Data 0/1 packet BANK3:BD1IST.PID3 5 Packet Identifier 3 BANK3:BD1IST.PID2 4 Packet Identifier 2 BANK3:BD1IST.PID1_DTS 3 Packet Identifier 1 BANK3:BD1IST.PID0_BSTALL 2 Buffer Stall BANK3:BD1IBC 0x01AD BUFFER DESCRIPTOR Byte Count (3-0) BANK3:BD1IBC.BC3 3 BANK3:BD1IBC.BC2 2 BANK3:BD1IBC.BC1 1 BANK3:BD1IBC.BC0 0 BANK3:BD1IAL 0x01AE Buffer Address Low BANK3:BD1IAL.BA7 7 Buffer Address 7 BANK3:BD1IAL.BA6 6 Buffer Address 6 BANK3:BD1IAL.BA5 5 Buffer Address 5 BANK3:BD1IAL.BA4 4 Buffer Address 4 BANK3:BD1IAL.BA3 3 Buffer Address 3 BANK3:BD1IAL.BA2 2 Buffer Address 2 BANK3:BD1IAL.BA1 1 Buffer Address 1 BANK3:BD1IAL.BA0 0 Buffer Address 0 BANK3:RESERVED01AF 0x01AF RESERVED BANK3:BD2OST 0x01B0 BUFFER DESCRIPTOR STATUS REGISTER 2 BANK3:BD2OST.UOWN_UOWN 7 USB Own BANK3:BD2OST.DATA0_1_DATA0_1 6 Data 0/1 packet BANK3:BD2OST.PID3 5 Packet Identifier 3 BANK3:BD2OST.PID2 4 Packet Identifier 2 BANK3:BD2OST.PID1_DTS 3 Packet Identifier 1 BANK3:BD2OST.PID0_BSTALL 2 Buffer Stall BANK3:BD2OBC 0x01B1 BUFFER DESCRIPTOR Byte Count (3-0) BANK3:BD2OBC.BC3 3 BANK3:BD2OBC.BC2 2 BANK3:BD2OBC.BC1 1 BANK3:BD2OBC.BC0 0 BANK3:BD2OAL 0x01B2 Buffer Address Low BANK3:BD2OAL.BA7 7 Buffer Address 7 BANK3:BD2OAL.BA6 6 Buffer Address 6 BANK3:BD2OAL.BA5 5 Buffer Address 5 BANK3:BD2OAL.BA4 4 Buffer Address 4 BANK3:BD2OAL.BA3 3 Buffer Address 3 BANK3:BD2OAL.BA2 2 Buffer Address 2 BANK3:BD2OAL.BA1 1 Buffer Address 1 BANK3:BD2OAL.BA0 0 Buffer Address 0 BANK3:RESERVED01B3 0x01B3 RESERVED BANK3:BD2IST 0x01B4 BUFFER DESCRIPTOR STATUS REGISTER 2 BANK3:BD2IST.UOWN_UOWN 7 USB Own BANK3:BD2IST.DATA0_1_DATA0_1 6 Data 0/1 packet BANK3:BD2IST.PID3 5 Packet Identifier 3 BANK3:BD2IST.PID2 4 Packet Identifier 2 BANK3:BD2IST.PID1_DTS 3 Packet Identifier 1 BANK3:BD2IST.PID0_BSTALL 2 Buffer Stall BANK3:BD2IBC 0x01B5 BUFFER DESCRIPTOR Byte Count (3-0) BANK3:BD2IBC.BC3 3 BANK3:BD2IBC.BC2 2 BANK3:BD2IBC.BC1 1 BANK3:BD2IBC.BC0 0 BANK3:BD2IAL 0x01B6 Buffer Address Low BANK3:BD2IAL.BA7 7 Buffer Address 7 BANK3:BD2IAL.BA6 6 Buffer Address 6 BANK3:BD2IAL.BA5 5 Buffer Address 5 BANK3:BD2IAL.BA4 4 Buffer Address 4 BANK3:BD2IAL.BA3 3 Buffer Address 3 BANK3:BD2IAL.BA2 2 Buffer Address 2 BANK3:BD2IAL.BA1 1 Buffer Address 1 BANK3:BD2IAL.BA0 0 Buffer Address 0 BANK3:RESERVED01B7 0x01B7 RESERVED .16C765 ; http://www.microchip.com/download/lit/pline/picmicro/families/16c7xx/41124c.pdf ; PIC16C745_65.pdf ; MEMORY MAP ; BANK_0 area DATA FSR_ 0x0000:0x0020 area DATA Gen_Purp 0x0020:0x0080 General Purpose Register area DATA MEM_Program0 0x0080:0x0800 On-chip Program Memory (Page 0) area DATA MEM_Program1 0x0800:0x1000 On-chip Program Memory (Page 1) area DATA MEM_Program2 0x1000:0x1800 On-chip Program Memory (Page 2) area DATA MEM_Program3 0x1800:0x2000 On-chip Program Memory (Page 3) ; BANK_1 ; area DATA FSR_ 0x0080:0x00A0 ; area DATA Gen_Purp 0x00A0:0x00F0 General Purpose Register ; area DATA Gen_Purp_BANK0 0x00F0:0x0100 accesses 70h-7Fh ; area DATA MEM_Program0 0x0100:0x0800 On-chip Program Memory (Page 0) ; area DATA MEM_Program1 0x0800:0x1000 On-chip Program Memory (Page 1) ; area DATA MEM_Program2 0x1000:0x1800 On-chip Program Memory (Page 2) ; area DATA MEM_Program3 0x1800:0x2000 On-chip Program Memory (Page 3) ; BANK_2 ; area DATA FSR_ 0x0100:0x0120 ; area DATA Gen_Purp 0x0120:0x0170 General Purpose Register ; area DATA Gen_Purp_BANK0 0x0170:0x0180 accesses 70h-7Fh ; area DATA MEM_Program0 0x0180:0x0800 On-chip Program Memory (Page 0) ; area DATA MEM_Program1 0x0800:0x1000 On-chip Program Memory (Page 1) ; area DATA MEM_Program2 0x1000:0x1800 On-chip Program Memory (Page 2) ; area DATA MEM_Program3 0x1800:0x2000 On-chip Program Memory (Page 3) ; BANK_3 ; area DATA FSR_ 0x0180:0x01A0 ; area DATA USB_ 0x01A0:0x01B8 USB Dual Port Memory ; area DATA USB_BUFF 0x01B8:0x01E0 USB Buffer (40 byte) ; area BSS RESERVED 0x01E0:0x01F0 ; area DATA Gen_Purp_BANK0 0x01F0:0x0200 accesses 70h-7Fh ; area DATA MEM_Program0 0x0200:0x0800 On-chip Program Memory (Page 0) ; area DATA MEM_Program1 0x0800:0x1000 On-chip Program Memory (Page 1) ; area DATA MEM_Program2 0x1000:0x1800 On-chip Program Memory (Page 2) ; area DATA MEM_Program3 0x1800:0x2000 On-chip Program Memory (Page 3) ; Interrupt and reset vector assignments interrupt RESET 0x0000 RESET ; INPUT/OUTPUT PORTS ; BANK0 (0x0000:0x0080) BANK0:INDF 0x0000 INDF (not a physical register) BANK0:TMR0 0x0001 Timer0 module's register BANK0:PCL 0x0002 Program Counter's (PC) Least Significant Byte BANK0:STATUS 0x0003 STATUS REGISTER BANK0:STATUS.IRP 7 Register Bank Select bit BANK0:STATUS.RP1 6 Register Bank Select bit 1 BANK0:STATUS.RP0 5 Register Bank Select bit 0 BANK0:STATUS.TO 4 Time-out bit BANK0:STATUS.PD 3 Power-down bit BANK0:STATUS.Z 2 Zero bit BANK0:STATUS.DC 1 Digit carry/borrow bit BANK0:STATUS.C 0 Carry/borrow bit BANK0:FSR 0x0004 Indirect data memory address pointer BANK0:PORTA 0x0005 PORTA REGISTER BANK0:PORTA.RA5 5 PORTA bit 5 BANK0:PORTA.RA4 4 PORTA bit 4 BANK0:PORTA.RA3 3 PORTA bit 3 BANK0:PORTA.RA2 2 PORTA bit 2 BANK0:PORTA.RA1 1 PORTA bit 1 BANK0:PORTA.RA0 0 PORTA bit 0 BANK0:PORTB 0x0006 PORTB REGISTER BANK0:PORTB.RB7 7 PORTB bit 7 BANK0:PORTB.RB6 6 PORTB bit 6 BANK0:PORTB.RB5 5 PORTB bit 5 BANK0:PORTB.RB4 4 PORTB bit 4 BANK0:PORTB.RB3 3 PORTB bit 3 BANK0:PORTB.RB2 2 PORTB bit 2 BANK0:PORTB.RB1 1 PORTB bit 1 BANK0:PORTB.RB0 0 PORTB bit 0 BANK0:PORTC 0x0007 PORTC REGISTER BANK0:PORTC.RC7 7 PORTC bit 7 BANK0:PORTC.RC6 6 PORTC bit 6 BANK0:PORTC.RC2 2 PORTC bit 2 BANK0:PORTC.RC1 1 PORTC bit 1 BANK0:PORTC.RC0 0 PORTC bit 0 BANK0:PORTD 0x0008 PORTD REGISTER BANK0:PORTD.RD7 7 PORTD bit 7 BANK0:PORTD.RD6 6 PORTD bit 6 BANK0:PORTD.RD5 5 PORTD bit 5 BANK0:PORTD.RD4 4 PORTD bit 4 BANK0:PORTD.RD3 3 PORTD bit 3 BANK0:PORTD.RD2 2 PORTD bit 2 BANK0:PORTD.RD1 1 PORTD bit 1 BANK0:PORTD.RD0 0 PORTD bit 0 BANK0:PORTE 0x0009 PORTE REGISTER BANK0:PORTE.RE2 2 PORTE bit 2 BANK0:PORTE.RE1 1 PORTE bit 1 BANK0:PORTE.RE0 0 PORTE bit 0 BANK0:PCLATH 0x000A Write Buffer for the upper 5 bits of the Program Counter BANK0:INTCON 0x000B INTCON REGISTER BANK0:INTCON.GIE 7 Global Interrupt Enable bit BANK0:INTCON.PEIE 6 Peripheral Interrupt Enable bit BANK0:INTCON.T0IE 5 TMR0 Overflow Interrupt Enable bit BANK0:INTCON.INTE 4 RB0/INT External Interrupt Enable bit BANK0:INTCON.RBIE 3 RB Port Change Interrupt Enable bit BANK0:INTCON.T0IF 2 TMR0 Overflow Interrupt Flag bit BANK0:INTCON.INTF 1 RB0/INT External Interrupt Flag bit BANK0:INTCON.RBIF 0 RB Port Change Interrupt Flag bit BANK0:PIR1 0x000C PIR1 REGISTER BANK0:PIR1.PSPIF 7 Parallel Slave Port Read/Write Interrupt Flag bit BANK0:PIR1.ADIF 6 A/D Converter Interrupt Flag bit BANK0:PIR1.RCIF 5 USART Receive Interrupt Flag bit BANK0:PIR1.TXIF 4 USART Transmit Interrupt Flag bit BANK0:PIR1.USBIF 3 Universal Serial Bus (USB) Interrupt Flag BANK0:PIR1.CCP1IF 2 CCP1 Interrupt Flag bit BANK0:PIR1.TMR2IF 1 TMR2 to PR2 Match Interrupt Flag bit BANK0:PIR1.TMR1IF 0 TMR1 Overflow Interrupt Flag bit BANK0:PIR2 0x000D PIR2 REGISTER BANK0:PIR2.CCP2IF 0 CCP2 Interrupt Flag bit BANK0:TMR1L 0x000E Holding register for the Least Significant Byte of the 16-bit TMR1 register BANK0:TMR1H 0x000F Holding register for the Most Significant Byte of the 16-bit TMR1 register BANK0:T1CON 0x0010 TIMER1 CONTROL REGISTER BANK0:T1CON.T1CKPS1 5 Timer1 Input Clock Prescale Select bit 1 BANK0:T1CON.T1CKPS0 4 Timer1 Input Clock Prescale Select bit 0 BANK0:T1CON.T1OSCEN 3 Timer1 Oscillator Enable Control bit BANK0:T1CON.T1SYNC 2 Timer1 External Clock Input Synchronization Control bit BANK0:T1CON.TMR1CS 1 Timer1 Clock Source Select bit BANK0:T1CON.TMR1ON 0 Timer1 On bit BANK0:TMR2 0x0011 Timer2 module's register BANK0:T2CON 0x0012 TIMER2 CONTROL REGISTER BANK0:T2CON.TOUTPS3 6 Timer2 Output Postscale Select bit 3 BANK0:T2CON.TOUTPS2 5 Timer2 Output Postscale Select bit 2 BANK0:T2CON.TOUTPS1 4 Timer2 Output Postscale Select bit 1 BANK0:T2CON.TOUTPS0 3 Timer2 Output Postscale Select bit 0 BANK0:T2CON.TMR2ON 2 Timer2 On bit BANK0:T2CON.T2CKPS1 1 Timer2 Clock Prescale Select bit 1 BANK0:T2CON.T2CKPS0 0 Timer2 Clock Prescale Select bit 0 BANK0:RESERVED0013 0x0013 RESERVED BANK0:RESERVED0014 0x0014 RESERVED BANK0:CCPR1L 0x0015 Capture/Compare/PWM Register1 (LSB) BANK0:CCPR1H 0x0016 Capture/Compare/PWM Register1 (MSB) BANK0:CCP1CON 0x0017 CCP1CON REGISTER BANK0:CCP1CON.DC1B1 5 PWM Least Significant bit 1 BANK0:CCP1CON.DC1B0 4 PWM Least Significant bit 0 BANK0:CCP1CON.CCP1M3 3 CCP1 Mode Select bit 3 BANK0:CCP1CON.CCP1M2 2 CCP1 Mode Select bit 2 BANK0:CCP1CON.CCP1M1 1 CCP1 Mode Select bit 1 BANK0:CCP1CON.CCP1M0 0 CCP1 Mode Select bit 0 BANK0:RCSTA 0x0018 RECEIVE STATUS AND CONTROL REGISTER BANK0:RCSTA.SPEN 7 Serial Port Enable bit BANK0:RCSTA.RX9 6 9-bit Receive Enable bit BANK0:RCSTA.SREN 5 Single Receive Enable bit BANK0:RCSTA.CREN 4 Continuous Receive Enable bit BANK0:RCSTA.FERR 2 Framing Error bit BANK0:RCSTA.OERR 1 Overrun Error bit BANK0:RCSTA.RX9D 0 9th bit of received data BANK0:TXREG 0x0019 USART Transmit Data Register BANK0:RCREG 0x001A USART Receive Data Register BANK0:CCPR2L 0x001B Capture/Compare/PWM Register2 (LSB) BANK0:CCPR2H 0x001C Capture/Compare/PWM Register2 (MSB) BANK0:CCP2CON 0x001D CCP2CON REGISTER BANK0:CCP2CON.DC2B1 5 PWM Least Significant bit 1 BANK0:CCP2CON.DC2B0 4 PWM Least Significant bit 0 BANK0:CCP2CON.CCP2M3 3 CCP2 Mode Select bit 3 BANK0:CCP2CON.CCP2M2 2 CCP2 Mode Select bit 2 BANK0:CCP2CON.CCP2M1 1 CCP2 Mode Select bit 1 BANK0:CCP2CON.CCP2M0 0 CCP2 Mode Select bit 0 BANK0:ADRES 0x001E A/D Result Register BANK0:ADCON0 0x001F ADCON0 REGISTER BANK0:ADCON0.ADCS1 7 A/D Conversion Clock Select bit 1 BANK0:ADCON0.ADCS0 6 A/D Conversion Clock Select bit 0 BANK0:ADCON0.CHS2 5 Analog Channel Select bit 2 BANK0:ADCON0.CHS1 4 Analog Channel Select bit 1 BANK0:ADCON0.CHS0 3 Analog Channel Select bit 0 BANK0:ADCON0.GO_DONE 2 A/D Conversion Status bit BANK0:ADCON0.ADON 0 A/D On bit ; BANK1 (0x0080:0x0100) BANK1:INDF 0x0080 INDF (not a physical register) BANK1:OPTION 0x0081 OPTION REGISTER BANK1:OPTION.RBPU 7 PORTB Pull-up Enable bit BANK1:OPTION.INTEDG 6 Interrupt Edge Select bit BANK1:OPTION.T0CS 5 TMR0 Clock Source Select bit BANK1:OPTION.T0SE 4 TMR0 Source Edge Select bit BANK1:OPTION.PSA 3 Prescaler Assignment bit BANK1:OPTION.PS2 2 Prescaler Rate Select bit 2 BANK1:OPTION.PS1 1 Prescaler Rate Select bit 1 BANK1:OPTION.PS0 0 Prescaler Rate Select bit 0 BANK1:PCL 0x0082 Program Counter's (PC) Least Significant Byte BANK1:STATUS 0x0083 STATUS REGISTER BANK1:STATUS.IRP 7 Register Bank Select bit BANK1:STATUS.RP1 6 Register Bank Select bit 1 BANK1:STATUS.RP0 5 Register Bank Select bit 0 BANK1:STATUS.TO 4 Time-out bit BANK1:STATUS.PD 3 Power-down bit BANK1:STATUS.Z 2 Zero bit BANK1:STATUS.DC 1 Digit carry/borrow bit BANK1:STATUS.C 0 Carry/borrow bit BANK1:FSR 0x0084 Indirect data memory address pointer BANK1:TRISA 0x0085 PORTA Data Direction Register BANK1:TRISA.TRISA5 5 PORTA Data Direction Register bit 5 BANK1:TRISA.TRISA4 4 PORTA Data Direction Register bit 4 BANK1:TRISA.TRISA3 3 PORTA Data Direction Register bit 3 BANK1:TRISA.TRISA2 2 PORTA Data Direction Register bit 2 BANK1:TRISA.TRISA1 1 PORTA Data Direction Register bit 1 BANK1:TRISA.TRISA0 0 PORTA Data Direction Register bit 0 BANK1:TRISB 0x0086 PORTB Data Direction Register BANK1:TRISB.TRISB7 7 PORTB Data Direction Register bit 7 BANK1:TRISB.TRISB6 6 PORTB Data Direction Register bit 6 BANK1:TRISB.TRISB5 5 PORTB Data Direction Register bit 5 BANK1:TRISB.TRISB4 4 PORTB Data Direction Register bit 4 BANK1:TRISB.TRISB3 3 PORTB Data Direction Register bit 3 BANK1:TRISB.TRISB2 2 PORTB Data Direction Register bit 2 BANK1:TRISB.TRISB1 1 PORTB Data Direction Register bit 1 BANK1:TRISB.TRISB0 0 PORTB Data Direction Register bit 0 BANK1:TRISC 0x0087 PORTC Data Direction Register BANK1:TRISC.TRISC7 7 PORTC Data Direction Register bit 7 BANK1:TRISC.TRISC6 6 PORTC Data Direction Register bit 6 BANK1:TRISC.TRISC2 2 PORTC Data Direction Register bit 2 BANK1:TRISC.TRISC1 1 PORTC Data Direction Register bit 1 BANK1:TRISC.TRISC0 0 PORTC Data Direction Register bit 0 BANK1:TRISD 0x0088 PORTD Data Direction Register BANK1:TRISD.TRISD7 7 PORTD Data Direction Register bit 7 BANK1:TRISD.TRISD6 6 PORTD Data Direction Register bit 6 BANK1:TRISD.TRISD5 5 PORTD Data Direction Register bit 5 BANK1:TRISD.TRISD4 4 PORTD Data Direction Register bit 4 BANK1:TRISD.TRISD3 3 PORTD Data Direction Register bit 3 BANK1:TRISD.TRISD2 2 PORTD Data Direction Register bit 2 BANK1:TRISD.TRISD1 1 PORTD Data Direction Register bit 1 BANK1:TRISD.TRISD0 0 PORTD Data Direction Register bit 0 BANK1:TRISE 0x0089 TRISE REGISTER BANK1:TRISE.IBF 7 Input Buffer Full Status bit BANK1:TRISE.OBF 6 Output Buffer Full Status bit BANK1:TRISE.IBOV 5 Input Buffer Overflow Detect bit BANK1:TRISE.PSPMODE 4 Parallel Slave Port Mode Select bit BANK1:TRISE.TRISE2 2 Direction Control bit for pin RE2/CS/AN7 BANK1:TRISE.TRISE1 1 Direction Control bit for pin RE1/WR/AN6 BANK1:TRISE.TRISE0 0 Direction Control bit for pin RE0/RD/AN5 BANK1:PCLATH 0x008A Write Buffer for the upper 5 bits of the Program Counter BANK1:INTCON 0x008B INTCON REGISTER BANK1:INTCON.GIE 7 Global Interrupt Enable bit BANK1:INTCON.PEIE 6 Peripheral Interrupt Enable bit BANK1:INTCON.T0IE 5 TMR0 Overflow Interrupt Enable bit BANK1:INTCON.INTE 4 RB0/INT External Interrupt Enable bit BANK1:INTCON.RBIE 3 RB Port Change Interrupt Enable bit BANK1:INTCON.T0IF 2 TMR0 Overflow Interrupt Flag bit BANK1:INTCON.INTF 1 RB0/INT External Interrupt Flag bit BANK1:INTCON.RBIF 0 RB Port Change Interrupt Flag bit BANK1:PIE1 0x008C PIE1 REGISTER BANK1:PIE1.PSPIE 7 Parallel Slave Port Read/Write Interrupt Enable bit BANK1:PIE1.ADIE 6 A/D Converter Interrupt Enable bit BANK1:PIE1.RCIE 5 USART Receive Interrupt Enable bit BANK1:PIE1.TXIE 4 USART Transmit Interrupt Enable bit BANK1:PIE1.USBIE 3 Universal Serial Bus Interrupt Enable bit BANK1:PIE1.CCP1IE 2 CCP1 Interrupt Enable bit BANK1:PIE1.TMR2IE 1 TMR2 to PR2 Match Interrupt Enable bit BANK1:PIE1.TMR1IE 0 TMR1 Overflow Interrupt Enable bit BANK1:PIE2 0x008D PIE2 REGISTER BANK1:PIE2.CCP2IE 0 CCP2 Interrupt Enable bit BANK1:PCON 0x008E PCON REGISTER BANK1:PCON.POR 1 Power-on Reset Status bit BANK1:PCON.BOR 0 Brown-out Reset Status bit BANK1:RESERVED008F 0x008F RESERVED BANK1:RESERVED0090 0x0090 RESERVED BANK1:RESERVED0091 0x0091 RESERVED BANK1:PR2 0x0092 Timer2 Period Register BANK1:RESERVED0093 0x0093 RESERVED BANK1:RESERVED0094 0x0094 RESERVED BANK1:RESERVED0095 0x0095 RESERVED BANK1:RESERVED0096 0x0096 RESERVED BANK1:RESERVED0097 0x0097 RESERVED BANK1:TXSTA 0x0098 TRANSMIT STATUS AND CONTROL REGISTER BANK1:TXSTA.CSRC 7 Clock Source Select bit BANK1:TXSTA.TX9 6 9-bit Transmit Enable bit BANK1:TXSTA.TXEN 5 Transmit Enable bit BANK1:TXSTA.SYNC 4 USART Mode Select bit BANK1:TXSTA.BRGH 2 High Baud Rate Select bit BANK1:TXSTA.TRMT 1 Transmit Shift Register Status bit BANK1:TXSTA.TX9D 0 9th bit of transmit data. Can be parity bit BANK1:SPBRG 0x0099 Baud Rate Generator Register BANK1:RESERVED009A 0x009A RESERVED BANK1:RESERVED009B 0x009B RESERVED BANK1:RESERVED009C 0x009C RESERVED BANK1:RESERVED009D 0x009D RESERVED BANK1:RESERVED009E 0x009E RESERVED BANK1:ADCON1 0x009F ADCON1 REGISTER BANK1:ADCON1.PCFG2 2 A/D Port Configuration Control bit 2 BANK1:ADCON1.PCFG1 1 A/D Port Configuration Control bit 1 BANK1:ADCON1.PCFG0 0 A/D Port Configuration Control bit 0 ; BANK2 (0x0100:0x0180) BANK2:INDF 0x0100 INDF (not a physical register) BANK2:TMR0 0x0101 Timer0 module's register BANK2:PCL 0x0102 Program Counter's (PC) Least Significant Byte BANK2:STATUS 0x0103 STATUS REGISTER BANK2:STATUS.IRP 7 Register Bank Select bit BANK2:STATUS.RP1 6 Register Bank Select bit 1 BANK2:STATUS.RP0 5 Register Bank Select bit 0 BANK2:STATUS.TO 4 Time-out bit BANK2:STATUS.PD 3 Power-down bit BANK2:STATUS.Z 2 Zero bit BANK2:STATUS.DC 1 Digit carry/borrow bit BANK2:STATUS.C 0 Carry/borrow bit BANK2:FSR 0x0104 Indirect data memory address pointer BANK2:RESERVED0105 0x0105 RESERVED BANK2:PORTB 0x0106 PORTB REGISTER BANK2:PORTB.RB7 7 PORTB bit 7 BANK2:PORTB.RB6 6 PORTB bit 6 BANK2:PORTB.RB5 5 PORTB bit 5 BANK2:PORTB.RB4 4 PORTB bit 4 BANK2:PORTB.RB3 3 PORTB bit 3 BANK2:PORTB.RB2 2 PORTB bit 2 BANK2:PORTB.RB1 1 PORTB bit 1 BANK2:PORTB.RB0 0 PORTB bit 0 BANK2:RESERVED0107 0x0107 RESERVED BANK2:RESERVED0108 0x0108 RESERVED BANK2:RESERVED0109 0x0109 RESERVED BANK2:PCLATH 0x010A Write Buffer for the upper 5 bits of the Program Counter BANK2:INTCON 0x010B INTCON REGISTER BANK2:INTCON.GIE 7 Global Interrupt Enable bit BANK2:INTCON.PEIE 6 Peripheral Interrupt Enable bit BANK2:INTCON.T0IE 5 TMR0 Overflow Interrupt Enable bit BANK2:INTCON.INTE 4 RB0/INT External Interrupt Enable bit BANK2:INTCON.RBIE 3 RB Port Change Interrupt Enable bit BANK2:INTCON.T0IF 2 TMR0 Overflow Interrupt Flag bit BANK2:INTCON.INTF 1 RB0/INT External Interrupt Flag bit BANK2:INTCON.RBIF 0 RB Port Change Interrupt Flag bit BANK2:RESERVED010C 0x010C RESERVED BANK2:RESERVED010D 0x010D RESERVED BANK2:RESERVED010E 0x010E RESERVED BANK2:RESERVED010F 0x010F RESERVED BANK2:RESERVED0110 0x0110 RESERVED BANK2:RESERVED0111 0x0111 RESERVED BANK2:RESERVED0112 0x0112 RESERVED BANK2:RESERVED0113 0x0113 RESERVED BANK2:RESERVED0114 0x0114 RESERVED BANK2:RESERVED0115 0x0115 RESERVED BANK2:RESERVED0116 0x0116 RESERVED BANK2:RESERVED0117 0x0117 RESERVED BANK2:RESERVED0118 0x0118 RESERVED BANK2:RESERVED0119 0x0119 RESERVED BANK2:RESERVED011A 0x011A RESERVED BANK2:RESERVED011B 0x011B RESERVED BANK2:RESERVED011C 0x011C RESERVED BANK2:RESERVED011D 0x011D RESERVED BANK2:RESERVED011E 0x011E RESERVED BANK2:RESERVED011F 0x011F RESERVED ; BANK3 (0x0180:0x0200) BANK3:INDF 0x0180 INDF (not a physical register) BANK3:OPTION 0x0181 OPTION REGISTER BANK3:OPTION.RBPU 7 PORTB Pull-up Enable bit BANK3:OPTION.INTEDG 6 Interrupt Edge Select bit BANK3:OPTION.T0CS 5 TMR0 Clock Source Select bit BANK3:OPTION.T0SE 4 TMR0 Source Edge Select bit BANK3:OPTION.PSA 3 Prescaler Assignment bit BANK3:OPTION.PS2 2 Prescaler Rate Select bit 2 BANK3:OPTION.PS1 1 Prescaler Rate Select bit 1 BANK3:OPTION.PS0 0 Prescaler Rate Select bit 0 BANK3:PCL 0x0182 Program Counter's (PC) Least Significant Byte BANK3:STATUS 0x0183 STATUS REGISTER BANK3:STATUS.IRP 7 Register Bank Select bit BANK3:STATUS.RP1 6 Register Bank Select bit 1 BANK3:STATUS.RP0 5 Register Bank Select bit 0 BANK3:STATUS.TO 4 Time-out bit BANK3:STATUS.PD 3 Power-down bit BANK3:STATUS.Z 2 Zero bit BANK3:STATUS.DC 1 Digit carry/borrow bit BANK3:STATUS.C 0 Carry/borrow bit BANK3:FSR 0x0184 Indirect data memory address pointer BANK3:RESERVED0185 0x0185 RESERVED BANK3:TRISB 0x0186 PORTB Data Direction Register BANK3:TRISB.TRISB7 7 PORTB Data Direction Register bit 7 BANK3:TRISB.TRISB6 6 PORTB Data Direction Register bit 6 BANK3:TRISB.TRISB5 5 PORTB Data Direction Register bit 5 BANK3:TRISB.TRISB4 4 PORTB Data Direction Register bit 4 BANK3:TRISB.TRISB3 3 PORTB Data Direction Register bit 3 BANK3:TRISB.TRISB2 2 PORTB Data Direction Register bit 2 BANK3:TRISB.TRISB1 1 PORTB Data Direction Register bit 1 BANK3:TRISB.TRISB0 0 PORTB Data Direction Register bit 0 BANK3:RESERVED0187 0x0187 RESERVED BANK3:RESERVED0188 0x0188 RESERVED BANK3:RESERVED0189 0x0189 RESERVED BANK3:PCLATH 0x018A Write Buffer for the upper 5 bits of the Program Counter BANK3:INTCON 0x018B INTCON REGISTER BANK3:INTCON.GIE 7 Global Interrupt Enable bit BANK3:INTCON.PEIE 6 Peripheral Interrupt Enable bit BANK3:INTCON.T0IE 5 TMR0 Overflow Interrupt Enable bit BANK3:INTCON.INTE 4 RB0/INT External Interrupt Enable bit BANK3:INTCON.RBIE 3 RB Port Change Interrupt Enable bit BANK3:INTCON.T0IF 2 TMR0 Overflow Interrupt Flag bit BANK3:INTCON.INTF 1 RB0/INT External Interrupt Flag bit BANK3:INTCON.RBIF 0 RB Port Change Interrupt Flag bit BANK3:RESERVED018C 0x018C RESERVED BANK3:RESERVED018D 0x018D RESERVED BANK3:RESERVED018E 0x018E RESERVED BANK3:RESERVED018F 0x018F RESERVED BANK3:UIR 0x0190 USB INTERRUPT FLAGS REGISTER BANK3:UIR.STALL 5 A STALL handshake was sent by the SIE BANK3:UIR.UIDLE 4 BANK3:UIR.TOK_DNE 3 BANK3:UIR.ACTIVITY 2 BANK3:UIR.UERR 1 BANK3:UIR.USB_RST 0 BANK3:UIE 0x0191 USB INTERRUPT ENABLE REGISTER BANK3:UIE.STALL 5 Set to enable STALL interrupts BANK3:UIE.UIDLE 4 Set to enable IDLE interrupts BANK3:UIE.TOK_DNE 3 Set to enable TOK_DNE interrupts BANK3:UIE.ACTIVITY 2 Set to enable ACTIVITY interrupts BANK3:UIE.UERR 1 Set to enable ERROR interrupts BANK3:UIE.USB_RST 0 Set to enable USB_RST interrupts BANK3:UEIR 0x0192 USB ERROR INTERRUPT FLAGS STATUS REGISTER BANK3:UEIR.BTS_ERR 7 A bit stuff error has been detected BANK3:UEIR.OWN_ERR 6 BANK3:UEIR.WRT_ERR 5 Write Error BANK3:UEIR.BTO_ERR 4 BANK3:UEIR.DFN8 3 BANK3:UEIR.CRC16 2 The CRC16 failed BANK3:UEIR.CRC5 1 BANK3:UEIR.PID_ERR 0 The PID check field failed BANK3:UEIE 0x0193 USB ERROR INTERRUPT ENABLE REGISTER BANK3:UEIE.BTS_ERR 7 Set this bit to enable BTS_ERR interrupts BANK3:UEIE.OWN_ERR 6 Set this bit to enable OWN_ERR interrupts BANK3:UEIE.WRT_ERR 5 Set this bit to enable WRT_ERR interrupts BANK3:UEIE.BTO_ERR 4 Set this bit to enable BTO_ERR interrupts BANK3:UEIE.DFN8 3 Set this bit to enable DFN8 interrupts BANK3:UEIE.CRC16 2 Set this bit to enable CRC16 interrupts BANK3:UEIE.CRC5 1 Set this bit to enable CRC5 interrupts BANK3:UEIE.PID_ERR 0 Set this bit to enable PID_ERR interrupts BANK3:USTAT 0x0194 USB STATUS REGISTER BANK3:USTAT.ENDP1 4 BANK3:USTAT.ENDP0 3 BANK3:USTAT.IN 2 BANK3:UCTRL 0x0195 USB CONTROL REGISTER BANK3:UCTRL.SEO 5 Live Single Ended Zero BANK3:UCTRL.PKT_DIS 4 BANK3:UCTRL.DEV_ATT 3 Device Attach BANK3:UCTRL.RESUME 2 BANK3:UCTRL.SUSPND 1 BANK3:UADDR 0x0196 USB ADDRESS REGISTER BANK3:UADDR.ADDR6 6 BANK3:UADDR.ADDR5 5 BANK3:UADDR.ADDR4 4 BANK3:UADDR.ADDR3 3 BANK3:UADDR.ADDR2 2 BANK3:UADDR.ADDR1 1 BANK3:UADDR.ADDR0 0 BANK3:USWSTAT 0x0197 RESERVED SOFTWARE LIBRARY REGISTER BANK3:USWSTAT.SWSTAT7 7 BANK3:USWSTAT.SWSTAT6 6 BANK3:USWSTAT.SWSTAT5 5 BANK3:USWSTAT.SWSTAT4 4 BANK3:USWSTAT.SWSTAT3 3 BANK3:USWSTAT.SWSTAT2 2 BANK3:USWSTAT.SWSTAT1 1 BANK3:USWSTAT.SWSTAT0 0 BANK3:UEP0 0x0198 USB ENDPOINT CONTROL REGISTER 0 BANK3:UEP0.EP_CTL_DIS 3 BANK3:UEP0.EP_OUT_EN 2 BANK3:UEP0.EP_IN_EN 1 BANK3:UEP0.EP_STALL 0 BANK3:UEP1 0x0199 USB ENDPOINT CONTROL REGISTER 1 BANK3:UEP1.EP_CTL_DIS 3 BANK3:UEP1.EP_OUT_EN 2 BANK3:UEP1.EP_IN_EN 1 BANK3:UEP1.EP_STALL 0 BANK3:UEP2 0x019A USB ENDPOINT CONTROL REGISTER 2 BANK3:UEP2.EP_CTL_DIS 3 BANK3:UEP2.EP_OUT_EN 2 BANK3:UEP2.EP_IN_EN 1 BANK3:UEP2.EP_STALL 0 BANK3:RESERVED019B 0x019B RESERVED BANK3:RESERVED019C 0x019C RESERVED BANK3:RESERVED019D 0x019D RESERVED BANK3:RESERVED019E 0x019E RESERVED BANK3:RESERVED019F 0x019F RESERVED ; USB DUAL PORT RAM BANK3:BD0OST 0x01A0 BUFFER DESCRIPTOR STATUS REGISTER 0 BANK3:BD0OST.UOWN_UOWN 7 USB Own BANK3:BD0OST.DATA0_1_DATA0_1 6 Data 0/1 packet BANK3:BD0OST.PID3 5 Packet Identifier 3 BANK3:BD0OST.PID2 4 Packet Identifier 2 BANK3:BD0OST.PID1_DTS 3 Packet Identifier 1 BANK3:BD0OST.PID0_BSTALL 2 Buffer Stall BANK3:BD0OBC 0x01A1 BUFFER DESCRIPTOR Byte Count (3-0) BANK3:BD0OBC.BC3 3 BANK3:BD0OBC.BC2 2 BANK3:BD0OBC.BC1 1 BANK3:BD0OBC.BC0 0 BANK3:BD0OAL 0x01A2 Buffer Address Low BANK3:BD0OAL.BA7 7 Buffer Address 7 BANK3:BD0OAL.BA6 6 Buffer Address 6 BANK3:BD0OAL.BA5 5 Buffer Address 5 BANK3:BD0OAL.BA4 4 Buffer Address 4 BANK3:BD0OAL.BA3 3 Buffer Address 3 BANK3:BD0OAL.BA2 2 Buffer Address 2 BANK3:BD0OAL.BA1 1 Buffer Address 1 BANK3:BD0OAL.BA0 0 Buffer Address 0 BANK3:RESERVED01A3 0x01A3 RESERVED BANK3:BD0IST 0x01A4 BUFFER DESCRIPTOR STATUS REGISTER 0 BANK3:BD0IST.UOWN_UOWN 7 USB Own BANK3:BD0IST.DATA0_1_DATA0_1 6 Data 0/1 packet BANK3:BD0IST.PID3 5 Packet Identifier 3 BANK3:BD0IST.PID2 4 Packet Identifier 2 BANK3:BD0IST.PID1_DTS 3 Packet Identifier 1 BANK3:BD0IST.PID0_BSTALL 2 Buffer Stall BANK3:BD0IBC 0x01A5 BUFFER DESCRIPTOR Byte Count (3-0) BANK3:BD0IBC.BC3 3 BANK3:BD0IBC.BC2 2 BANK3:BD0IBC.BC1 1 BANK3:BD0IBC.BC0 0 BANK3:BD0IAL 0x01A6 Buffer Address Low BANK3:BD0IAL.BA7 7 Buffer Address 7 BANK3:BD0IAL.BA6 6 Buffer Address 6 BANK3:BD0IAL.BA5 5 Buffer Address 5 BANK3:BD0IAL.BA4 4 Buffer Address 4 BANK3:BD0IAL.BA3 3 Buffer Address 3 BANK3:BD0IAL.BA2 2 Buffer Address 2 BANK3:BD0IAL.BA1 1 Buffer Address 1 BANK3:BD0IAL.BA0 0 Buffer Address 0 BANK3:RESERVED01A7 0x01A7 RESERVED BANK3:BD1OST 0x01A8 BUFFER DESCRIPTOR STATUS REGISTER 1 BANK3:BD1OST.UOWN_UOWN 7 USB Own BANK3:BD1OST.DATA0_1_DATA0_1 6 Data 0/1 packet BANK3:BD1OST.PID3 5 Packet Identifier 3 BANK3:BD1OST.PID2 4 Packet Identifier 2 BANK3:BD1OST.PID1_DTS 3 Packet Identifier 1 BANK3:BD1OST.PID0_BSTALL 2 Buffer Stall BANK3:BD1OBC 0x01A9 BUFFER DESCRIPTOR Byte Count (3-0) BANK3:BD1OBC.BC3 3 BANK3:BD1OBC.BC2 2 BANK3:BD1OBC.BC1 1 BANK3:BD1OBC.BC0 0 BANK3:BD1OAL 0x01AA Buffer Address Low BANK3:BD1OAL.BA7 7 Buffer Address 7 BANK3:BD1OAL.BA6 6 Buffer Address 6 BANK3:BD1OAL.BA5 5 Buffer Address 5 BANK3:BD1OAL.BA4 4 Buffer Address 4 BANK3:BD1OAL.BA3 3 Buffer Address 3 BANK3:BD1OAL.BA2 2 Buffer Address 2 BANK3:BD1OAL.BA1 1 Buffer Address 1 BANK3:BD1OAL.BA0 0 Buffer Address 0 BANK3:RESERVED01AB 0x01AB RESERVED BANK3:BD1IST 0x01AC BUFFER DESCRIPTOR STATUS REGISTER 1 BANK3:BD1IST.UOWN_UOWN 7 USB Own BANK3:BD1IST.DATA0_1_DATA0_1 6 Data 0/1 packet BANK3:BD1IST.PID3 5 Packet Identifier 3 BANK3:BD1IST.PID2 4 Packet Identifier 2 BANK3:BD1IST.PID1_DTS 3 Packet Identifier 1 BANK3:BD1IST.PID0_BSTALL 2 Buffer Stall BANK3:BD1IBC 0x01AD BUFFER DESCRIPTOR Byte Count (3-0) BANK3:BD1IBC.BC3 3 BANK3:BD1IBC.BC2 2 BANK3:BD1IBC.BC1 1 BANK3:BD1IBC.BC0 0 BANK3:BD1IAL 0x01AE Buffer Address Low BANK3:BD1IAL.BA7 7 Buffer Address 7 BANK3:BD1IAL.BA6 6 Buffer Address 6 BANK3:BD1IAL.BA5 5 Buffer Address 5 BANK3:BD1IAL.BA4 4 Buffer Address 4 BANK3:BD1IAL.BA3 3 Buffer Address 3 BANK3:BD1IAL.BA2 2 Buffer Address 2 BANK3:BD1IAL.BA1 1 Buffer Address 1 BANK3:BD1IAL.BA0 0 Buffer Address 0 BANK3:RESERVED01AF 0x01AF RESERVED BANK3:BD2OST 0x01B0 BUFFER DESCRIPTOR STATUS REGISTER 2 BANK3:BD2OST.UOWN_UOWN 7 USB Own BANK3:BD2OST.DATA0_1_DATA0_1 6 Data 0/1 packet BANK3:BD2OST.PID3 5 Packet Identifier 3 BANK3:BD2OST.PID2 4 Packet Identifier 2 BANK3:BD2OST.PID1_DTS 3 Packet Identifier 1 BANK3:BD2OST.PID0_BSTALL 2 Buffer Stall BANK3:BD2OBC 0x01B1 BUFFER DESCRIPTOR Byte Count (3-0) BANK3:BD2OBC.BC3 3 BANK3:BD2OBC.BC2 2 BANK3:BD2OBC.BC1 1 BANK3:BD2OBC.BC0 0 BANK3:BD2OAL 0x01B2 Buffer Address Low BANK3:BD2OAL.BA7 7 Buffer Address 7 BANK3:BD2OAL.BA6 6 Buffer Address 6 BANK3:BD2OAL.BA5 5 Buffer Address 5 BANK3:BD2OAL.BA4 4 Buffer Address 4 BANK3:BD2OAL.BA3 3 Buffer Address 3 BANK3:BD2OAL.BA2 2 Buffer Address 2 BANK3:BD2OAL.BA1 1 Buffer Address 1 BANK3:BD2OAL.BA0 0 Buffer Address 0 BANK3:RESERVED01B3 0x01B3 RESERVED BANK3:BD2IST 0x01B4 BUFFER DESCRIPTOR STATUS REGISTER 2 BANK3:BD2IST.UOWN_UOWN 7 USB Own BANK3:BD2IST.DATA0_1_DATA0_1 6 Data 0/1 packet BANK3:BD2IST.PID3 5 Packet Identifier 3 BANK3:BD2IST.PID2 4 Packet Identifier 2 BANK3:BD2IST.PID1_DTS 3 Packet Identifier 1 BANK3:BD2IST.PID0_BSTALL 2 Buffer Stall BANK3:BD2IBC 0x01B5 BUFFER DESCRIPTOR Byte Count (3-0) BANK3:BD2IBC.BC3 3 BANK3:BD2IBC.BC2 2 BANK3:BD2IBC.BC1 1 BANK3:BD2IBC.BC0 0 BANK3:BD2IAL 0x01B6 Buffer Address Low BANK3:BD2IAL.BA7 7 Buffer Address 7 BANK3:BD2IAL.BA6 6 Buffer Address 6 BANK3:BD2IAL.BA5 5 Buffer Address 5 BANK3:BD2IAL.BA4 4 Buffer Address 4 BANK3:BD2IAL.BA3 3 Buffer Address 3 BANK3:BD2IAL.BA2 2 Buffer Address 2 BANK3:BD2IAL.BA1 1 Buffer Address 1 BANK3:BD2IAL.BA0 0 Buffer Address 0 BANK3:RESERVED01B7 0x01B7 RESERVED .16C773 ; http://www.microchip.com/download/lit/pline/picmicro/families/16c77x/30275a.pdf ; PIC16C773_4.pdf ; MEMORY MAP ; BANK_0 area DATA FSR_ 0x0000:0x0020 area DATA Gen_Purp 0x0020:0x0080 General Purpose Register area DATA MEM_Program0 0x0080:0x0800 On-chip Program Memory (Page 0) area DATA MEM_Program1 0x0800:0x1000 On-chip Program Memory (Page 1) ; BANK_1 ; area DATA FSR_ 0x0080:0x00A0 ; area DATA Gen_Purp 0x00A0:0x00F0 General Purpose Register ; area DATA Gen_Purp_BANK0 0x00F0:0x0100 accesses 70h-7Fh ; area DATA MEM_Program0 0x0100:0x0800 On-chip Program Memory (Page 0) ; area DATA MEM_Program1 0x0800:0x1000 On-chip Program Memory (Page 1) ; BANK_2 ; area DATA FSR_ 0x0100:0x0120 ; area DATA Gen_Purp 0x0120:0x0170 General Purpose Register ; area DATA Gen_Purp_BANK0 0x0170:0x0180 accesses 70h-7Fh ; area DATA MEM_Program0 0x0180:0x0800 On-chip Program Memory (Page 0) ; area DATA MEM_Program1 0x0800:0x1000 On-chip Program Memory (Page 1) ; BANK_3 ; area DATA FSR_ 0x0180:0x01A0 ; area BSS RESERVED 0x01A0:0x01F0 ; area DATA Gen_Purp_BANK0 0x01F0:0x0200 accesses 70h-7Fh ; area DATA MEM_Program0 0x0200:0x0800 On-chip Program Memory (Page 0) ; area DATA MEM_Program1 0x0800:0x1000 On-chip Program Memory (Page 1) ; Interrupt and reset vector assignments interrupt RESET 0x0000 RESET ; INPUT/OUTPUT PORTS ; BANK0 (0x0000:0x0080) BANK0:INDF 0x0000 INDF (not a physical register) BANK0:TMR0 0x0001 Timer0 module's register BANK0:PCL 0x0002 Program Counter's (PC) Least Significant Byte BANK0:STATUS 0x0003 STATUS REGISTER BANK0:STATUS.IRP 7 Register Bank Select bit BANK0:STATUS.RP1 6 Register Bank Select bit 1 BANK0:STATUS.RP0 5 Register Bank Select bit 0 BANK0:STATUS.TO 4 Time-out bit BANK0:STATUS.PD 3 Power-down bit BANK0:STATUS.Z 2 Zero bit BANK0:STATUS.DC 1 Digit carry/borrow bit BANK0:STATUS.C 0 Carry/borrow bit BANK0:FSR 0x0004 Indirect data memory address pointer BANK0:PORTA 0x0005 PORTA REGISTER BANK0:PORTA.RA5 5 PORTA bit 5 (not implemented on the 28-pin devices) BANK0:PORTA.RA4 4 PORTA bit 4 BANK0:PORTA.RA3 3 PORTA bit 3 BANK0:PORTA.RA2 2 PORTA bit 2 BANK0:PORTA.RA1 1 PORTA bit 1 BANK0:PORTA.RA0 0 PORTA bit 0 BANK0:PORTB 0x0006 PORTB REGISTER BANK0:PORTB.RB7 7 PORTB bit 7 BANK0:PORTB.RB6 6 PORTB bit 6 BANK0:PORTB.RB5 5 PORTB bit 5 BANK0:PORTB.RB4 4 PORTB bit 4 BANK0:PORTB.RB3 3 PORTB bit 3 BANK0:PORTB.RB2 2 PORTB bit 2 BANK0:PORTB.RB1 1 PORTB bit 1 BANK0:PORTB.RB0 0 PORTB bit 0 BANK0:PORTC 0x0007 PORTC REGISTER BANK0:PORTC.RC7 7 PORTC bit 7 BANK0:PORTC.RC6 6 PORTC bit 6 BANK0:PORTC.RC5 5 PORTC bit 5 BANK0:PORTC.RC4 4 PORTC bit 4 BANK0:PORTC.RC3 3 PORTC bit 3 BANK0:PORTC.RC2 2 PORTC bit 2 BANK0:PORTC.RC1 1 PORTC bit 1 BANK0:PORTC.RC0 0 PORTC bit 0 BANK0:RESERVED0008 0x0008 RESERVED BANK0:RESERVED0009 0x0009 RESERVED BANK0:PCLATH 0x000A Write Buffer for the upper 5 bits of the Program Counter BANK0:INTCON 0x000B INTCON REGISTER BANK0:INTCON.GIE 7 Global Interrupt Enable bit BANK0:INTCON.PEIE 6 Peripheral Interrupt Enable bit BANK0:INTCON.T0IE 5 TMR0 Overflow Interrupt Enable bit BANK0:INTCON.INTE 4 RB0/INT External Interrupt Enable bit BANK0:INTCON.RBIE 3 RB Port Change Interrupt Enable bit BANK0:INTCON.T0IF 2 TMR0 Overflow Interrupt Flag bit BANK0:INTCON.INTF 1 RB0/INT External Interrupt Flag bit BANK0:INTCON.RBIF 0 RB Port Change Interrupt Flag bit BANK0:PIR1 0x000C PIR1 REGISTER BANK0:PIR1.PSPIF 7 Parallel Slave Port Read/Write Interrupt Flag bit (reserved on the 28-pin devices) BANK0:PIR1.ADIF 6 A/D Converter Interrupt Flag bit BANK0:PIR1.RCIF 5 USART Receive Interrupt Flag bit BANK0:PIR1.TXIF 4 USART Transmit Interrupt Flag bit BANK0:PIR1.SSPIF 3 Synchronous Serial Port Interrupt Flag bit BANK0:PIR1.CCP1IF 2 CCP1 Interrupt Flag bit BANK0:PIR1.TMR2IF 1 TMR2 to PR2 Match Interrupt Flag bit BANK0:PIR1.TMR1IF 0 TMR1 Overflow Interrupt Flag bit BANK0:PIR2 0x000D PIR2 REGISTER BANK0:PIR2.LVDIF 7 Low-voltage Detect Interrupt Flag bit BANK0:PIR2.BCLIF 3 Bus Collision Interrupt Flag bit BANK0:PIR2.CCP2IF 0 CCP2 Interrupt Flag bit BANK0:TMR1L 0x000E Holding register for the Least Significant Byte of the 16-bit TMR1 register BANK0:TMR1H 0x000F Holding register for the Most Significant Byte of the 16-bit TMR1 register BANK0:T1CON 0x0010 TIMER1 CONTROL REGISTER BANK0:T1CON.T1CKPS1 5 Timer1 Input Clock Prescale Select bit 1 BANK0:T1CON.T1CKPS0 4 Timer1 Input Clock Prescale Select bit 0 BANK0:T1CON.T1OSCEN 3 Timer1 Oscillator Enable Control bit BANK0:T1CON.T1SYNC 2 Timer1 External Clock Input Synchronization Control bit BANK0:T1CON.TMR1CS 1 Timer1 Clock Source Select bit BANK0:T1CON.TMR1ON 0 Timer1 On bit BANK0:TMR2 0x0011 Timer2 module's register BANK0:T2CON 0x0012 TIMER2 CONTROL REGISTER BANK0:T2CON.TOUTPS3 6 Timer2 Output Postscale Select bit 3 BANK0:T2CON.TOUTPS2 5 Timer2 Output Postscale Select bit 2 BANK0:T2CON.TOUTPS1 4 Timer2 Output Postscale Select bit 1 BANK0:T2CON.TOUTPS0 3 Timer2 Output Postscale Select bit 0 BANK0:T2CON.TMR2ON 2 Timer2 On bit BANK0:T2CON.T2CKPS1 1 Timer2 Clock Prescale Select bit 1 BANK0:T2CON.T2CKPS0 0 Timer2 Clock Prescale Select bit 0 BANK0:SSPBUF 0x0013 Synchronous Serial Port Receive Buffer/Transmit Register BANK0:SSPCON 0x0014 SYNC SERIAL PORT CONTROL REGISTER BANK0:SSPCON.WCOL 7 Write Collision Detect bit BANK0:SSPCON.SSPOV 6 Receive Overflow Indicator bit BANK0:SSPCON.SSPEN 5 Synchronous Serial Port Enable bit BANK0:SSPCON.CKP 4 Clock Polarity Select bit BANK0:SSPCON.SSPM3 3 Synchronous Serial Port Mode Select bit 3 BANK0:SSPCON.SSPM2 2 Synchronous Serial Port Mode Select bit 2 BANK0:SSPCON.SSPM1 1 Synchronous Serial Port Mode Select bit 1 BANK0:SSPCON.SSPM0 0 Synchronous Serial Port Mode Select bit 0 BANK0:CCPR1L 0x0015 Capture/Compare/PWM Register1 (LSB) BANK0:CCPR1H 0x0016 Capture/Compare/PWM Register1 (MSB) BANK0:CCP1CON 0x0017 CCP1CON REGISTER BANK0:CCP1CON.CCP1X 5 PWM Least Significant bit BANK0:CCP1CON.CCP1Y 4 PWM Least Significant bit BANK0:CCP1CON.CCP1M3 3 CCP1 Mode Select bit 3 BANK0:CCP1CON.CCP1M2 2 CCP1 Mode Select bit 2 BANK0:CCP1CON.CCP1M1 1 CCP1 Mode Select bit 1 BANK0:CCP1CON.CCP1M0 0 CCP1 Mode Select bit 0 BANK0:RCSTA 0x0018 RECEIVE STATUS AND CONTROL REGISTER BANK0:RCSTA.SPEN 7 Serial Port Enable bit BANK0:RCSTA.RX9 6 9-bit Receive Enable bit BANK0:RCSTA.SREN 5 Single Receive Enable bit BANK0:RCSTA.CREN 4 Continuous Receive Enable bit BANK0:RCSTA.FERR 2 Framing Error bit BANK0:RCSTA.OERR 1 Overrun Error bit BANK0:RCSTA.RX9D 0 9th bit of received data BANK0:TXREG 0x0019 USART Transmit Data Register BANK0:RCREG 0x001A USART Receive Data Register BANK0:CCPR2L 0x001B Capture/Compare/PWM Register2 (LSB) BANK0:CCPR2H 0x001C Capture/Compare/PWM Register2 (MSB) BANK0:CCP2CON 0x001D CCP2CON REGISTER BANK0:CCP2CON.CCP2X 5 PWM Least Significant bit BANK0:CCP2CON.CCP2Y 4 PWM Least Significant bit BANK0:CCP2CON.CCP2M3 3 CCP2 Mode Select bit 3 BANK0:CCP2CON.CCP2M2 2 CCP2 Mode Select bit 2 BANK0:CCP2CON.CCP2M1 1 CCP2 Mode Select bit 1 BANK0:CCP2CON.CCP2M0 0 CCP2 Mode Select bit 0 BANK0:ADRES 0x001E A/D Result Register BANK0:ADCON0 0x001F ADCON0 REGISTER BANK0:ADCON0.ADCS1 7 A/D Conversion Clock Select bit 1 BANK0:ADCON0.ADCS0 6 A/D Conversion Clock Select bit 0 BANK0:ADCON0.CHS2 5 Analog Channel Select bit 2 BANK0:ADCON0.CHS1 4 Analog Channel Select bit 1 BANK0:ADCON0.CHS0 3 Analog Channel Select bit 0 BANK0:ADCON0.GO_DONE 2 A/D Conversion Status bit BANK0:ADCON0.CHS3 1 Analog Channel Select bit 3 BANK0:ADCON0.ADON 0 A/D On bit ; BANK1 (0x0080:0x0100) BANK1:INDF 0x0080 INDF (not a physical register) BANK1:OPTION 0x0081 OPTION REGISTER BANK1:OPTION.RBPU 7 PORTB Pull-up Enable bit BANK1:OPTION.INTEDG 6 Interrupt Edge Select bit BANK1:OPTION.T0CS 5 TMR0 Clock Source Select bit BANK1:OPTION.T0SE 4 TMR0 Source Edge Select bit BANK1:OPTION.PSA 3 Prescaler Assignment bit BANK1:OPTION.PS2 2 Prescaler Rate Select bit 2 BANK1:OPTION.PS1 1 Prescaler Rate Select bit 1 BANK1:OPTION.PS0 0 Prescaler Rate Select bit 0 BANK1:PCL 0x0082 Program Counter's (PC) Least Significant Byte BANK1:STATUS 0x0083 STATUS REGISTER BANK1:STATUS.IRP 7 Register Bank Select bit BANK1:STATUS.RP1 6 Register Bank Select bit 1 BANK1:STATUS.RP0 5 Register Bank Select bit 0 BANK1:STATUS.TO 4 Time-out bit BANK1:STATUS.PD 3 Power-down bit BANK1:STATUS.Z 2 Zero bit BANK1:STATUS.DC 1 Digit carry/borrow bit BANK1:STATUS.C 0 Carry/borrow bit BANK1:FSR 0x0084 Indirect data memory address pointer BANK1:TRISA 0x0085 PORTA Data Direction Register BANK1:TRISA.TRISA5 5 PORTA Data Direction Register bit 5 (not implemented on the 28-pin devices) BANK1:TRISA.TRISA4 4 PORTA Data Direction Register bit 4 BANK1:TRISA.TRISA3 3 PORTA Data Direction Register bit 3 BANK1:TRISA.TRISA2 2 PORTA Data Direction Register bit 2 BANK1:TRISA.TRISA1 1 PORTA Data Direction Register bit 1 BANK1:TRISA.TRISA0 0 PORTA Data Direction Register bit 0 BANK1:TRISB 0x0086 PORTB Data Direction Register BANK1:TRISB.TRISB7 7 PORTB Data Direction Register bit 7 BANK1:TRISB.TRISB6 6 PORTB Data Direction Register bit 6 BANK1:TRISB.TRISB5 5 PORTB Data Direction Register bit 5 BANK1:TRISB.TRISB4 4 PORTB Data Direction Register bit 4 BANK1:TRISB.TRISB3 3 PORTB Data Direction Register bit 3 BANK1:TRISB.TRISB2 2 PORTB Data Direction Register bit 2 BANK1:TRISB.TRISB1 1 PORTB Data Direction Register bit 1 BANK1:TRISB.TRISB0 0 PORTB Data Direction Register bit 0 BANK1:TRISC 0x0087 PORTC Data Direction Register BANK1:TRISC.TRISC7 7 PORTC Data Direction Register bit 7 BANK1:TRISC.TRISC6 6 PORTC Data Direction Register bit 6 BANK1:TRISC.TRISC5 5 PORTC Data Direction Register bit 5 BANK1:TRISC.TRISC4 4 PORTC Data Direction Register bit 4 BANK1:TRISC.TRISC3 3 PORTC Data Direction Register bit 3 BANK1:TRISC.TRISC2 2 PORTC Data Direction Register bit 2 BANK1:TRISC.TRISC1 1 PORTC Data Direction Register bit 1 BANK1:TRISC.TRISC0 0 PORTC Data Direction Register bit 0 BANK1:RESERVED0088 0x0088 RESERVED BANK1:RESERVED0089 0x0089 RESERVED BANK1:PCLATH 0x008A Write Buffer for the upper 5 bits of the Program Counter BANK1:INTCON 0x008B INTCON REGISTER BANK1:INTCON.GIE 7 Global Interrupt Enable bit BANK1:INTCON.PEIE 6 Peripheral Interrupt Enable bit BANK1:INTCON.T0IE 5 TMR0 Overflow Interrupt Enable bit BANK1:INTCON.INTE 4 RB0/INT External Interrupt Enable bit BANK1:INTCON.RBIE 3 RB Port Change Interrupt Enable bit BANK1:INTCON.T0IF 2 TMR0 Overflow Interrupt Flag bit BANK1:INTCON.INTF 1 RB0/INT External Interrupt Flag bit BANK1:INTCON.RBIF 0 RB Port Change Interrupt Flag bit BANK1:PIE1 0x008C PIE1 REGISTER BANK1:PIE1.PSPIE 7 Parallel Slave Port Read/Write Interrupt Enable bit (reserved on the 28-pin devices) BANK1:PIE1.ADIE 6 A/D Converter Interrupt Enable bit BANK1:PIE1.RCIE 5 USART Receive Interrupt Enable bit BANK1:PIE1.TXIE 4 USART Transmit Interrupt Enable bit BANK1:PIE1.SSPIE 3 Synchronous Serial Port Interrupt Enable bit BANK1:PIE1.CCP1IE 2 CCP1 Interrupt Enable bit BANK1:PIE1.TMR2IE 1 TMR2 to PR2 Match Interrupt Enable bit BANK1:PIE1.TMR1IE 0 TMR1 Overflow Interrupt Enable bit BANK1:PIE2 0x008D PIE2 REGISTER BANK1:PIE2.LVDIE 7 Low-voltage Detect Interrupt Enable bit BANK1:PIE2.BCLIE 3 Bus Collision Interrupt Enable bit BANK1:PIE2.CCP2IE 0 CCP2 Interrupt Enable bit BANK1:PCON 0x008E PCON REGISTER BANK1:PCON.POR 1 Power-on Reset Status bit BANK1:PCON.BOR 0 Brown-out Reset Status bit BANK1:RESERVED008F 0x008F RESERVED BANK1:RESERVED0090 0x0090 RESERVED BANK1:SSPCON2 0x0091 SYNC SERIAL PORT CONTROL REGISTER2 BANK1:SSPCON2.GCEN 7 General Call Enable bit (In I2C slave mode only) BANK1:SSPCON2.AKSTAT 6 Acknowledge Status bit (In I2C master mode only) BANK1:SSPCON2.AKDT 5 Acknowledge Data bit (In I2C master mode only) BANK1:SSPCON2.AKEN 4 Acknowledge Sequence Enable bit (In I2C master mode only) BANK1:SSPCON2.RCEN 3 Receive Enable bit (In I2C master mode only) BANK1:SSPCON2.PEN 2 Stop Condition Enable bit (In I2C master mode only) BANK1:SSPCON2.RSEN 1 Repeated Start Condition Enabled bit (In I2C master mode only) BANK1:SSPCON2.SEN 0 Start Condition Enabled bit (In I2C master mode only) BANK1:PR2 0x0092 Timer2 Period Register BANK1:SSPADD 0x0093 Synchronous Serial Port (I2C mode) Address Register BANK1:SSPSTAT 0x0094 SYNC SERIAL PORT STATUS REGISTER BANK1:SSPSTAT.SMP 7 SPI data input sample phase BANK1:SSPSTAT.CKE 6 SPI Clock Edge Select BANK1:SSPSTAT.D_A 5 Data/Address bit (I2C mode only) BANK1:SSPSTAT.P 4 Stop bit (I2C mode only) BANK1:SSPSTAT.S 3 Start bit (I2C mode only) BANK1:SSPSTAT.R_W 2 Read/Write bit information (I2C mode only) BANK1:SSPSTAT.UA 1 Update Address (I2C mode only) BANK1:SSPSTAT.BF 0 Buffer Full Status bit BANK1:RESERVED0095 0x0095 RESERVED BANK1:RESERVED0096 0x0096 RESERVED BANK1:RESERVED0097 0x0097 RESERVED BANK1:TXSTA 0x0098 TRANSMIT STATUS AND CONTROL REGISTER BANK1:TXSTA.CSRC 7 Clock Source Select bit BANK1:TXSTA.TX9 6 9-bit Transmit Enable bit BANK1:TXSTA.TXEN 5 Transmit Enable bit BANK1:TXSTA.SYNC 4 USART Mode Select bit BANK1:TXSTA.BRGH 2 High Baud Rate Select bit BANK1:TXSTA.TRMT 1 Transmit Shift Register Status bit BANK1:TXSTA.TX9D 0 9th bit of transmit data. Can be parity bit BANK1:SPBRG 0x0099 Baud Rate Generator Register BANK1:RESERVED009A 0x009A RESERVED BANK1:REFCON 0x009B VOLTAGE REFERENCE CONTROL REGISTER BANK1:REFCON.VRHEN 7 Voltage Reference High Enable bit (VRH = 4.096V) BANK1:REFCON.VRLEN 6 Voltage Reference Low Enable bit (VRL = 2.048V) BANK1:REFCON.VRHOEN 5 High Voltage Reference Output Enable bit BANK1:REFCON.VRLOEN 4 Low Voltage Reference Output Enable bit BANK1:LVDCON 0x009C LOW-VOLTAGE DETECT CONTROL REGISTER BANK1:LVDCON.BGST 5 Bandgap Stable Status Flag bit BANK1:LVDCON.LVDEN 4 Low-voltage Detect Power Enable bit BANK1:LVDCON.LV3 3 Low Voltage Detection Limit bit 3 BANK1:LVDCON.LV2 2 Low Voltage Detection Limit bit 2 BANK1:LVDCON.LV1 1 Low Voltage Detection Limit bit 1 BANK1:LVDCON.LV0 0 Low Voltage Detection Limit bit 0 BANK1:RESERVED009D 0x009D RESERVED BANK1:ADRESL 0x009E A/D Low Byte Result Register BANK1:ADCON1 0x009F ADCON1 REGISTER BANK1:ADCON1.ADFM 7 A/D Result Format Select bit BANK1:ADCON1.VCFG2 6 Voltage reference configuration bit 2 BANK1:ADCON1.VCFG1 5 Voltage reference configuration bit 1 BANK1:ADCON1.VCFG0 4 Voltage reference configuration bit 0 BANK1:ADCON1.PCFG3 3 A/D Port Configuration Control bit 3 BANK1:ADCON1.PCFG2 2 A/D Port Configuration Control bit 2 BANK1:ADCON1.PCFG1 1 A/D Port Configuration Control bit 1 BANK1:ADCON1.PCFG0 0 A/D Port Configuration Control bit 0 ; BANK2 (0x0100:0x0180) BANK2:INDF 0x0100 INDF (not a physical register) BANK2:TMR0 0x0101 Timer0 module's register BANK2:PCL 0x0102 Program Counter's (PC) Least Significant Byte BANK2:STATUS 0x0103 STATUS REGISTER BANK2:STATUS.IRP 7 Register Bank Select bit BANK2:STATUS.RP1 6 Register Bank Select bit 1 BANK2:STATUS.RP0 5 Register Bank Select bit 0 BANK2:STATUS.TO 4 Time-out bit BANK2:STATUS.PD 3 Power-down bit BANK2:STATUS.Z 2 Zero bit BANK2:STATUS.DC 1 Digit carry/borrow bit BANK2:STATUS.C 0 Carry/borrow bit BANK2:FSR 0x0104 Indirect data memory address pointer BANK2:RESERVED0105 0x0105 RESERVED BANK2:PORTB 0x0106 PORTB REGISTER BANK2:PORTB.RB7 7 PORTB bit 7 BANK2:PORTB.RB6 6 PORTB bit 6 BANK2:PORTB.RB5 5 PORTB bit 5 BANK2:PORTB.RB4 4 PORTB bit 4 BANK2:PORTB.RB3 3 PORTB bit 3 BANK2:PORTB.RB2 2 PORTB bit 2 BANK2:PORTB.RB1 1 PORTB bit 1 BANK2:PORTB.RB0 0 PORTB bit 0 BANK2:RESERVED0107 0x0107 RESERVED BANK2:RESERVED0108 0x0108 RESERVED BANK2:RESERVED0109 0x0109 RESERVED BANK2:PCLATH 0x010A Write Buffer for the upper 5 bits of the Program Counter BANK2:INTCON 0x010B INTCON REGISTER BANK2:INTCON.GIE 7 Global Interrupt Enable bit BANK2:INTCON.PEIE 6 Peripheral Interrupt Enable bit BANK2:INTCON.T0IE 5 TMR0 Overflow Interrupt Enable bit BANK2:INTCON.INTE 4 RB0/INT External Interrupt Enable bit BANK2:INTCON.RBIE 3 RB Port Change Interrupt Enable bit BANK2:INTCON.T0IF 2 TMR0 Overflow Interrupt Flag bit BANK2:INTCON.INTF 1 RB0/INT External Interrupt Flag bit BANK2:INTCON.RBIF 0 RB Port Change Interrupt Flag bit BANK2:RESERVED010C 0x010C RESERVED BANK2:RESERVED010D 0x010D RESERVED BANK2:RESERVED010E 0x010E RESERVED BANK2:RESERVED010F 0x010F RESERVED BANK2:RESERVED0110 0x0110 RESERVED BANK2:RESERVED0111 0x0111 RESERVED BANK2:RESERVED0112 0x0112 RESERVED BANK2:RESERVED0113 0x0113 RESERVED BANK2:RESERVED0114 0x0114 RESERVED BANK2:RESERVED0115 0x0115 RESERVED BANK2:RESERVED0116 0x0116 RESERVED BANK2:RESERVED0117 0x0117 RESERVED BANK2:RESERVED0118 0x0118 RESERVED BANK2:RESERVED0119 0x0119 RESERVED BANK2:RESERVED011A 0x011A RESERVED BANK2:RESERVED011B 0x011B RESERVED BANK2:RESERVED011C 0x011C RESERVED BANK2:RESERVED011D 0x011D RESERVED BANK2:RESERVED011E 0x011E RESERVED BANK2:RESERVED011F 0x011F RESERVED ; BANK3 (0x0180:0x0200) BANK3:INDF 0x0180 INDF (not a physical register) BANK3:OPTION 0x0181 OPTION REGISTER BANK3:OPTION.RBPU 7 PORTB Pull-up Enable bit BANK3:OPTION.INTEDG 6 Interrupt Edge Select bit BANK3:OPTION.T0CS 5 TMR0 Clock Source Select bit BANK3:OPTION.T0SE 4 TMR0 Source Edge Select bit BANK3:OPTION.PSA 3 Prescaler Assignment bit BANK3:OPTION.PS2 2 Prescaler Rate Select bit 2 BANK3:OPTION.PS1 1 Prescaler Rate Select bit 1 BANK3:OPTION.PS0 0 Prescaler Rate Select bit 0 BANK3:PCL 0x0182 Program Counter's (PC) Least Significant Byte BANK3:STATUS 0x0183 STATUS REGISTER BANK3:STATUS.IRP 7 Register Bank Select bit BANK3:STATUS.RP1 6 Register Bank Select bit 1 BANK3:STATUS.RP0 5 Register Bank Select bit 0 BANK3:STATUS.TO 4 Time-out bit BANK3:STATUS.PD 3 Power-down bit BANK3:STATUS.Z 2 Zero bit BANK3:STATUS.DC 1 Digit carry/borrow bit BANK3:STATUS.C 0 Carry/borrow bit BANK3:FSR 0x0184 Indirect data memory address pointer BANK3:RESERVED0185 0x0185 RESERVED BANK3:TRISB 0x0186 PORTB Data Direction Register BANK3:TRISB.TRISB7 7 PORTB Data Direction Register bit 7 BANK3:TRISB.TRISB6 6 PORTB Data Direction Register bit 6 BANK3:TRISB.TRISB5 5 PORTB Data Direction Register bit 5 BANK3:TRISB.TRISB4 4 PORTB Data Direction Register bit 4 BANK3:TRISB.TRISB3 3 PORTB Data Direction Register bit 3 BANK3:TRISB.TRISB2 2 PORTB Data Direction Register bit 2 BANK3:TRISB.TRISB1 1 PORTB Data Direction Register bit 1 BANK3:TRISB.TRISB0 0 PORTB Data Direction Register bit 0 BANK3:RESERVED0187 0x0187 RESERVED BANK3:RESERVED0188 0x0188 RESERVED BANK3:RESERVED0189 0x0189 RESERVED BANK3:PCLATH 0x018A Write Buffer for the upper 5 bits of the Program Counter BANK3:INTCON 0x018B INTCON REGISTER BANK3:INTCON.GIE 7 Global Interrupt Enable bit BANK3:INTCON.PEIE 6 Peripheral Interrupt Enable bit BANK3:INTCON.T0IE 5 TMR0 Overflow Interrupt Enable bit BANK3:INTCON.INTE 4 RB0/INT External Interrupt Enable bit BANK3:INTCON.RBIE 3 RB Port Change Interrupt Enable bit BANK3:INTCON.T0IF 2 TMR0 Overflow Interrupt Flag bit BANK3:INTCON.INTF 1 RB0/INT External Interrupt Flag bit BANK3:INTCON.RBIF 0 RB Port Change Interrupt Flag bit BANK3:RESERVED018C 0x018C RESERVED BANK3:RESERVED018D 0x018D RESERVED BANK3:RESERVED018E 0x018E RESERVED BANK3:RESERVED018F 0x018F RESERVED BANK3:RESERVED0190 0x0190 RESERVED BANK3:RESERVED0191 0x0191 RESERVED BANK3:RESERVED0192 0x0192 RESERVED BANK3:RESERVED0193 0x0193 RESERVED BANK3:RESERVED0194 0x0194 RESERVED BANK3:RESERVED0195 0x0195 RESERVED BANK3:RESERVED0196 0x0196 RESERVED BANK3:RESERVED0197 0x0197 RESERVED BANK3:RESERVED0198 0x0198 RESERVED BANK3:RESERVED0199 0x0199 RESERVED BANK3:RESERVED019A 0x019A RESERVED BANK3:RESERVED019B 0x019B RESERVED BANK3:RESERVED019C 0x019C RESERVED BANK3:RESERVED019D 0x019D RESERVED BANK3:RESERVED019E 0x019E RESERVED BANK3:RESERVED019F 0x019F RESERVED .16C774 ; http://www.microchip.com/download/lit/pline/picmicro/families/16c77x/30275a.pdf ; PIC16C773_4.pdf ; MEMORY MAP ; BANK_0 area DATA FSR_ 0x0000:0x0020 area DATA Gen_Purp 0x0020:0x0080 General Purpose Register area DATA MEM_Program0 0x0080:0x0800 On-chip Program Memory (Page 0) area DATA MEM_Program1 0x0800:0x1000 On-chip Program Memory (Page 1) ; BANK_1 ; area DATA FSR_ 0x0080:0x00A0 ; area DATA Gen_Purp 0x00A0:0x00F0 General Purpose Register ; area DATA Gen_Purp_BANK0 0x00F0:0x0100 accesses 70h-7Fh ; area DATA MEM_Program0 0x0100:0x0800 On-chip Program Memory (Page 0) ; area DATA MEM_Program1 0x0800:0x1000 On-chip Program Memory (Page 1) ; BANK_2 ; area DATA FSR_ 0x0100:0x0120 ; area DATA Gen_Purp 0x0120:0x0170 General Purpose Register ; area DATA Gen_Purp_BANK0 0x0170:0x0180 accesses 70h-7Fh ; area DATA MEM_Program0 0x0180:0x0800 On-chip Program Memory (Page 0) ; area DATA MEM_Program1 0x0800:0x1000 On-chip Program Memory (Page 1) ; BANK_3 ; area DATA FSR_ 0x0180:0x01A0 ; area BSS RESERVED 0x01A0:0x01F0 ; area DATA Gen_Purp_BANK0 0x01F0:0x0200 accesses 70h-7Fh ; area DATA MEM_Program0 0x0200:0x0800 On-chip Program Memory (Page 0) ; area DATA MEM_Program1 0x0800:0x1000 On-chip Program Memory (Page 1) ; Interrupt and reset vector assignments interrupt RESET 0x0000 RESET ; INPUT/OUTPUT PORTS ; BANK0 (0x0000:0x0080) BANK0:INDF 0x0000 INDF (not a physical register) BANK0:TMR0 0x0001 Timer0 module's register BANK0:PCL 0x0002 Program Counter's (PC) Least Significant Byte BANK0:STATUS 0x0003 STATUS REGISTER BANK0:STATUS.IRP 7 Register Bank Select bit BANK0:STATUS.RP1 6 Register Bank Select bit 1 BANK0:STATUS.RP0 5 Register Bank Select bit 0 BANK0:STATUS.TO 4 Time-out bit BANK0:STATUS.PD 3 Power-down bit BANK0:STATUS.Z 2 Zero bit BANK0:STATUS.DC 1 Digit carry/borrow bit BANK0:STATUS.C 0 Carry/borrow bit BANK0:FSR 0x0004 Indirect data memory address pointer BANK0:PORTA 0x0005 PORTA REGISTER BANK0:PORTA.RA5 5 PORTA bit 5 not implemented on the 28-pin devices BANK0:PORTA.RA4 4 PORTA bit 4 BANK0:PORTA.RA3 3 PORTA bit 3 BANK0:PORTA.RA2 2 PORTA bit 2 BANK0:PORTA.RA1 1 PORTA bit 1 BANK0:PORTA.RA0 0 PORTA bit 0 BANK0:PORTB 0x0006 PORTB REGISTER BANK0:PORTB.RB7 7 PORTB bit 7 BANK0:PORTB.RB6 6 PORTB bit 6 BANK0:PORTB.RB5 5 PORTB bit 5 BANK0:PORTB.RB4 4 PORTB bit 4 BANK0:PORTB.RB3 3 PORTB bit 3 BANK0:PORTB.RB2 2 PORTB bit 2 BANK0:PORTB.RB1 1 PORTB bit 1 BANK0:PORTB.RB0 0 PORTB bit 0 BANK0:PORTC 0x0007 PORTC REGISTER BANK0:PORTC.RC7 7 PORTC bit 7 BANK0:PORTC.RC6 6 PORTC bit 6 BANK0:PORTC.RC5 5 PORTC bit 5 BANK0:PORTC.RC4 4 PORTC bit 4 BANK0:PORTC.RC3 3 PORTC bit 3 BANK0:PORTC.RC2 2 PORTC bit 2 BANK0:PORTC.RC1 1 PORTC bit 1 BANK0:PORTC.RC0 0 PORTC bit 0 BANK0:PORTD 0x0008 PORTD REGISTER (not implemented on the 28-pin devices) BANK0:PORTD.RD7 7 PORTD bit 7 BANK0:PORTD.RD6 6 PORTD bit 6 BANK0:PORTD.RD5 5 PORTD bit 5 BANK0:PORTD.RD4 4 PORTD bit 4 BANK0:PORTD.RD3 3 PORTD bit 3 BANK0:PORTD.RD2 2 PORTD bit 2 BANK0:PORTD.RD1 1 PORTD bit 1 BANK0:PORTD.RD0 0 PORTD bit 0 BANK0:PORTE 0x0009 PORTE REGISTER (not implemented on the 28-pin devices) BANK0:PORTE.RE2 2 PORTE bit 2 BANK0:PORTE.RE1 1 PORTE bit 1 BANK0:PORTE.RE0 0 PORTE bit 0 BANK0:PCLATH 0x000A Write Buffer for the upper 5 bits of the Program Counter BANK0:INTCON 0x000B INTCON REGISTER BANK0:INTCON.GIE 7 Global Interrupt Enable bit BANK0:INTCON.PEIE 6 Peripheral Interrupt Enable bit BANK0:INTCON.T0IE 5 TMR0 Overflow Interrupt Enable bit BANK0:INTCON.INTE 4 RB0/INT External Interrupt Enable bit BANK0:INTCON.RBIE 3 RB Port Change Interrupt Enable bit BANK0:INTCON.T0IF 2 TMR0 Overflow Interrupt Flag bit BANK0:INTCON.INTF 1 RB0/INT External Interrupt Flag bit BANK0:INTCON.RBIF 0 RB Port Change Interrupt Flag bit BANK0:PIR1 0x000C PIR1 REGISTER BANK0:PIR1.PSPIF 7 Parallel Slave Port Read/Write Interrupt Flag bit (reserved on the 28-pin devices) BANK0:PIR1.ADIF 6 A/D Converter Interrupt Flag bit BANK0:PIR1.RCIF 5 USART Receive Interrupt Flag bit BANK0:PIR1.TXIF 4 USART Transmit Interrupt Flag bit BANK0:PIR1.SSPIF 3 Synchronous Serial Port Interrupt Flag bit BANK0:PIR1.CCP1IF 2 CCP1 Interrupt Flag bit BANK0:PIR1.TMR2IF 1 TMR2 to PR2 Match Interrupt Flag bit BANK0:PIR1.TMR1IF 0 TMR1 Overflow Interrupt Flag bit BANK0:PIR2 0x000D PIR2 REGISTER BANK0:PIR2.LVDIF 7 Low-voltage Detect Interrupt Flag bit BANK0:PIR2.BCLIF 3 Bus Collision Interrupt Flag bit BANK0:PIR2.CCP2IF 0 CCP2 Interrupt Flag bit BANK0:TMR1L 0x000E Holding register for the Least Significant Byte of the 16-bit TMR1 register BANK0:TMR1H 0x000F Holding register for the Most Significant Byte of the 16-bit TMR1 register BANK0:T1CON 0x0010 TIMER1 CONTROL REGISTER BANK0:T1CON.T1CKPS1 5 Timer1 Input Clock Prescale Select bit 1 BANK0:T1CON.T1CKPS0 4 Timer1 Input Clock Prescale Select bit 0 BANK0:T1CON.T1OSCEN 3 Timer1 Oscillator Enable Control bit BANK0:T1CON.T1SYNC 2 Timer1 External Clock Input Synchronization Control bit BANK0:T1CON.TMR1CS 1 Timer1 Clock Source Select bit BANK0:T1CON.TMR1ON 0 Timer1 On bit BANK0:TMR2 0x0011 Timer2 module's register BANK0:T2CON 0x0012 TIMER2 CONTROL REGISTER BANK0:T2CON.TOUTPS3 6 Timer2 Output Postscale Select bit 3 BANK0:T2CON.TOUTPS2 5 Timer2 Output Postscale Select bit 2 BANK0:T2CON.TOUTPS1 4 Timer2 Output Postscale Select bit 1 BANK0:T2CON.TOUTPS0 3 Timer2 Output Postscale Select bit 0 BANK0:T2CON.TMR2ON 2 Timer2 On bit BANK0:T2CON.T2CKPS1 1 Timer2 Clock Prescale Select bit 1 BANK0:T2CON.T2CKPS0 0 Timer2 Clock Prescale Select bit 0 BANK0:SSPBUF 0x0013 Synchronous Serial Port Receive Buffer/Transmit Register BANK0:SSPCON 0x0014 SYNC SERIAL PORT CONTROL REGISTER BANK0:SSPCON.WCOL 7 Write Collision Detect bit BANK0:SSPCON.SSPOV 6 Receive Overflow Indicator bit BANK0:SSPCON.SSPEN 5 Synchronous Serial Port Enable bit BANK0:SSPCON.CKP 4 Clock Polarity Select bit BANK0:SSPCON.SSPM3 3 Synchronous Serial Port Mode Select bit 3 BANK0:SSPCON.SSPM2 2 Synchronous Serial Port Mode Select bit 2 BANK0:SSPCON.SSPM1 1 Synchronous Serial Port Mode Select bit 1 BANK0:SSPCON.SSPM0 0 Synchronous Serial Port Mode Select bit 0 BANK0:CCPR1L 0x0015 Capture/Compare/PWM Register1 (LSB) BANK0:CCPR1H 0x0016 Capture/Compare/PWM Register1 (MSB) BANK0:CCP1CON 0x0017 CCP1CON REGISTER BANK0:CCP1CON.CCP1X 5 PWM Least Significant bit BANK0:CCP1CON.CCP1Y 4 PWM Least Significant bit BANK0:CCP1CON.CCP1M3 3 CCP1 Mode Select bit 3 BANK0:CCP1CON.CCP1M2 2 CCP1 Mode Select bit 2 BANK0:CCP1CON.CCP1M1 1 CCP1 Mode Select bit 1 BANK0:CCP1CON.CCP1M0 0 CCP1 Mode Select bit 0 BANK0:RCSTA 0x0018 RECEIVE STATUS AND CONTROL REGISTER BANK0:RCSTA.SPEN 7 Serial Port Enable bit BANK0:RCSTA.RX9 6 9-bit Receive Enable bit BANK0:RCSTA.SREN 5 Single Receive Enable bit BANK0:RCSTA.CREN 4 Continuous Receive Enable bit BANK0:RCSTA.FERR 2 Framing Error bit BANK0:RCSTA.OERR 1 Overrun Error bit BANK0:RCSTA.RX9D 0 9th bit of received data BANK0:TXREG 0x0019 USART Transmit Data Register BANK0:RCREG 0x001A USART Receive Data Register BANK0:CCPR2L 0x001B Capture/Compare/PWM Register2 (LSB) BANK0:CCPR2H 0x001C Capture/Compare/PWM Register2 (MSB) BANK0:CCP2CON 0x001D CCP2CON REGISTER BANK0:CCP2CON.CCP2X 5 PWM Least Significant bit BANK0:CCP2CON.CCP2Y 4 PWM Least Significant bit BANK0:CCP2CON.CCP2M3 3 CCP2 Mode Select bit 3 BANK0:CCP2CON.CCP2M2 2 CCP2 Mode Select bit 2 BANK0:CCP2CON.CCP2M1 1 CCP2 Mode Select bit 1 BANK0:CCP2CON.CCP2M0 0 CCP2 Mode Select bit 0 BANK0:ADRES 0x001E A/D Result Register BANK0:ADCON0 0x001F ADCON0 REGISTER BANK0:ADCON0.ADCS1 7 A/D Conversion Clock Select bit 1 BANK0:ADCON0.ADCS0 6 A/D Conversion Clock Select bit 0 BANK0:ADCON0.CHS2 5 Analog Channel Select bit 2 BANK0:ADCON0.CHS1 4 Analog Channel Select bit 1 BANK0:ADCON0.CHS0 3 Analog Channel Select bit 0 BANK0:ADCON0.GO_DONE 2 A/D Conversion Status bit BANK0:ADCON0.CHS3 1 Analog Channel Select bit 3 BANK0:ADCON0.ADON 0 A/D On bit ; BANK1 (0x0080:0x0100) BANK1:INDF 0x0080 INDF (not a physical register) BANK1:OPTION 0x0081 OPTION REGISTER BANK1:OPTION.RBPU 7 PORTB Pull-up Enable bit BANK1:OPTION.INTEDG 6 Interrupt Edge Select bit BANK1:OPTION.T0CS 5 TMR0 Clock Source Select bit BANK1:OPTION.T0SE 4 TMR0 Source Edge Select bit BANK1:OPTION.PSA 3 Prescaler Assignment bit BANK1:OPTION.PS2 2 Prescaler Rate Select bit 2 BANK1:OPTION.PS1 1 Prescaler Rate Select bit 1 BANK1:OPTION.PS0 0 Prescaler Rate Select bit 0 BANK1:PCL 0x0082 Program Counter's (PC) Least Significant Byte BANK1:STATUS 0x0083 STATUS REGISTER BANK1:STATUS.IRP 7 Register Bank Select bit BANK1:STATUS.RP1 6 Register Bank Select bit 1 BANK1:STATUS.RP0 5 Register Bank Select bit 0 BANK1:STATUS.TO 4 Time-out bit BANK1:STATUS.PD 3 Power-down bit BANK1:STATUS.Z 2 Zero bit BANK1:STATUS.DC 1 Digit carry/borrow bit BANK1:STATUS.C 0 Carry/borrow bit BANK1:FSR 0x0084 Indirect data memory address pointer BANK1:TRISA 0x0085 PORTA Data Direction Register BANK1:TRISA.TRISA5 5 PORTA Data Direction Register bit 5 (not implemented on the 28-pin devices) BANK1:TRISA.TRISA4 4 PORTA Data Direction Register bit 4 BANK1:TRISA.TRISA3 3 PORTA Data Direction Register bit 3 BANK1:TRISA.TRISA2 2 PORTA Data Direction Register bit 2 BANK1:TRISA.TRISA1 1 PORTA Data Direction Register bit 1 BANK1:TRISA.TRISA0 0 PORTA Data Direction Register bit 0 BANK1:TRISB 0x0086 PORTB Data Direction Register BANK1:TRISB.TRISB7 7 PORTB Data Direction Register bit 7 BANK1:TRISB.TRISB6 6 PORTB Data Direction Register bit 6 BANK1:TRISB.TRISB5 5 PORTB Data Direction Register bit 5 BANK1:TRISB.TRISB4 4 PORTB Data Direction Register bit 4 BANK1:TRISB.TRISB3 3 PORTB Data Direction Register bit 3 BANK1:TRISB.TRISB2 2 PORTB Data Direction Register bit 2 BANK1:TRISB.TRISB1 1 PORTB Data Direction Register bit 1 BANK1:TRISB.TRISB0 0 PORTB Data Direction Register bit 0 BANK1:TRISC 0x0087 PORTC Data Direction Register BANK1:TRISC.TRISC7 7 PORTC Data Direction Register bit 7 BANK1:TRISC.TRISC6 6 PORTC Data Direction Register bit 6 BANK1:TRISC.TRISC5 5 PORTC Data Direction Register bit 5 BANK1:TRISC.TRISC4 4 PORTC Data Direction Register bit 4 BANK1:TRISC.TRISC3 3 PORTC Data Direction Register bit 3 BANK1:TRISC.TRISC2 2 PORTC Data Direction Register bit 2 BANK1:TRISC.TRISC1 1 PORTC Data Direction Register bit 1 BANK1:TRISC.TRISC0 0 PORTC Data Direction Register bit 0 BANK1:TRISD 0x0088 PORTD Data Direction Register (not implemented on the 28-pin devices) BANK1:TRISD.TRISD7 7 PORTD Data Direction Register bit 7 BANK1:TRISD.TRISD6 6 PORTD Data Direction Register bit 6 BANK1:TRISD.TRISD5 5 PORTD Data Direction Register bit 5 BANK1:TRISD.TRISD4 4 PORTD Data Direction Register bit 4 BANK1:TRISD.TRISD3 3 PORTD Data Direction Register bit 3 BANK1:TRISD.TRISD2 2 PORTD Data Direction Register bit 2 BANK1:TRISD.TRISD1 1 PORTD Data Direction Register bit 1 BANK1:TRISD.TRISD0 0 PORTD Data Direction Register bit 0 BANK1:TRISE 0x0089 TRISE REGISTER (not implemented on the 28-pin devices) BANK1:TRISE.IBF 7 Input Buffer Full Status bit BANK1:TRISE.OBF 6 Output Buffer Full Status bit BANK1:TRISE.IBOV 5 Input Buffer Overflow Detect bit BANK1:TRISE.PSPMODE 4 Parallel Slave Port Mode Select bit BANK1:TRISE.TRISE2 2 Direction Control bit for pin RE2/CS/AN7 BANK1:TRISE.TRISE1 1 Direction Control bit for pin RE1/WR/AN6 BANK1:TRISE.TRISE0 0 Direction Control bit for pin RE0/RD/AN5 BANK1:PCLATH 0x008A Write Buffer for the upper 5 bits of the Program Counter BANK1:INTCON 0x008B INTCON REGISTER BANK1:INTCON.GIE 7 Global Interrupt Enable bit BANK1:INTCON.PEIE 6 Peripheral Interrupt Enable bit BANK1:INTCON.T0IE 5 TMR0 Overflow Interrupt Enable bit BANK1:INTCON.INTE 4 RB0/INT External Interrupt Enable bit BANK1:INTCON.RBIE 3 RB Port Change Interrupt Enable bit BANK1:INTCON.T0IF 2 TMR0 Overflow Interrupt Flag bit BANK1:INTCON.INTF 1 RB0/INT External Interrupt Flag bit BANK1:INTCON.RBIF 0 RB Port Change Interrupt Flag bit BANK1:PIE1 0x008C PIE1 REGISTER BANK1:PIE1.PSPIE 7 Parallel Slave Port Read/Write Interrupt Enable bit (reserved on the 28-pin devices) BANK1:PIE1.ADIE 6 A/D Converter Interrupt Enable bit BANK1:PIE1.RCIE 5 USART Receive Interrupt Enable bit BANK1:PIE1.TXIE 4 USART Transmit Interrupt Enable bit BANK1:PIE1.SSPIE 3 Synchronous Serial Port Interrupt Enable bit BANK1:PIE1.CCP1IE 2 CCP1 Interrupt Enable bit BANK1:PIE1.TMR2IE 1 TMR2 to PR2 Match Interrupt Enable bit BANK1:PIE1.TMR1IE 0 TMR1 Overflow Interrupt Enable bit BANK1:PIE2 0x008D PIE2 REGISTER BANK1:PIE2.LVDIE 7 Low-voltage Detect Interrupt Enable bit BANK1:PIE2.BCLIE 3 Bus Collision Interrupt Enable bit BANK1:PIE2.CCP2IE 0 CCP2 Interrupt Enable bit BANK1:PCON 0x008E PCON REGISTER BANK1:PCON.POR 1 Power-on Reset Status bit BANK1:PCON.BOR 0 Brown-out Reset Status bit BANK1:RESERVED008F 0x008F RESERVED BANK1:RESERVED0090 0x0090 RESERVED BANK1:SSPCON2 0x0091 SYNC SERIAL PORT CONTROL REGISTER2 BANK1:SSPCON2.GCEN 7 General Call Enable bit (In I2C slave mode only) BANK1:SSPCON2.AKSTAT 6 Acknowledge Status bit (In I2C master mode only) BANK1:SSPCON2.AKDT 5 Acknowledge Data bit (In I2C master mode only) BANK1:SSPCON2.AKEN 4 Acknowledge Sequence Enable bit (In I2C master mode only) BANK1:SSPCON2.RCEN 3 Receive Enable bit (In I2C master mode only) BANK1:SSPCON2.PEN 2 Stop Condition Enable bit (In I2C master mode only) BANK1:SSPCON2.RSEN 1 Repeated Start Condition Enabled bit (In I2C master mode only) BANK1:SSPCON2.SEN 0 Start Condition Enabled bit (In I2C master mode only) BANK1:PR2 0x0092 Timer2 Period Register BANK1:SSPADD 0x0093 Synchronous Serial Port (I2C mode) Address Register BANK1:SSPSTAT 0x0094 SYNC SERIAL PORT STATUS REGISTER BANK1:SSPSTAT.SMP 7 SPI data input sample phase BANK1:SSPSTAT.CKE 6 SPI Clock Edge Select BANK1:SSPSTAT.D_A 5 Data/Address bit (I2C mode only) BANK1:SSPSTAT.P 4 Stop bit (I2C mode only) BANK1:SSPSTAT.S 3 Start bit (I2C mode only) BANK1:SSPSTAT.R_W 2 Read/Write bit information (I2C mode only) BANK1:SSPSTAT.UA 1 Update Address (I2C mode only) BANK1:SSPSTAT.BF 0 Buffer Full Status bit BANK1:RESERVED0095 0x0095 RESERVED BANK1:RESERVED0096 0x0096 RESERVED BANK1:RESERVED0097 0x0097 RESERVED BANK1:TXSTA 0x0098 TRANSMIT STATUS AND CONTROL REGISTER BANK1:TXSTA.CSRC 7 Clock Source Select bit BANK1:TXSTA.TX9 6 9-bit Transmit Enable bit BANK1:TXSTA.TXEN 5 Transmit Enable bit BANK1:TXSTA.SYNC 4 USART Mode Select bit BANK1:TXSTA.BRGH 2 High Baud Rate Select bit BANK1:TXSTA.TRMT 1 Transmit Shift Register Status bit BANK1:TXSTA.TX9D 0 9th bit of transmit data. Can be parity bit BANK1:SPBRG 0x0099 Baud Rate Generator Register BANK1:RESERVED009A 0x009A RESERVED BANK1:REFCON 0x009B VOLTAGE REFERENCE CONTROL REGISTER BANK1:REFCON.VRHEN 7 Voltage Reference High Enable bit (VRH = 4.096V) BANK1:REFCON.VRLEN 6 Voltage Reference Low Enable bit (VRL = 2.048V) BANK1:REFCON.VRHOEN 5 High Voltage Reference Output Enable bit BANK1:REFCON.VRLOEN 4 Low Voltage Reference Output Enable bit BANK1:LVDCON 0x009C LOW-VOLTAGE DETECT CONTROL REGISTER BANK1:LVDCON.BGST 5 Bandgap Stable Status Flag bit BANK1:LVDCON.LVDEN 4 Low-voltage Detect Power Enable bit BANK1:LVDCON.LV3 3 Low Voltage Detection Limit bit 3 BANK1:LVDCON.LV2 2 Low Voltage Detection Limit bit 2 BANK1:LVDCON.LV1 1 Low Voltage Detection Limit bit 1 BANK1:LVDCON.LV0 0 Low Voltage Detection Limit bit 0 BANK1:RESERVED009D 0x009D RESERVED BANK1:ADRESL 0x009E A/D Low Byte Result Register BANK1:ADCON1 0x009F ADCON1 REGISTER BANK1:ADCON1.ADFM 7 A/D Result Format Select bit BANK1:ADCON1.VCFG2 6 Voltage reference configuration bit 2 BANK1:ADCON1.VCFG1 5 Voltage reference configuration bit 1 BANK1:ADCON1.VCFG0 4 Voltage reference configuration bit 0 BANK1:ADCON1.PCFG3 3 A/D Port Configuration Control bit 3 BANK1:ADCON1.PCFG2 2 A/D Port Configuration Control bit 2 BANK1:ADCON1.PCFG1 1 A/D Port Configuration Control bit 1 BANK1:ADCON1.PCFG0 0 A/D Port Configuration Control bit 0 ; BANK2 (0x0100:0x0180) BANK2:INDF 0x0100 INDF (not a physical register) BANK2:TMR0 0x0101 Timer0 module's register BANK2:PCL 0x0102 Program Counter's (PC) Least Significant Byte BANK2:STATUS 0x0103 STATUS REGISTER BANK2:STATUS.IRP 7 Register Bank Select bit BANK2:STATUS.RP1 6 Register Bank Select bit 1 BANK2:STATUS.RP0 5 Register Bank Select bit 0 BANK2:STATUS.TO 4 Time-out bit BANK2:STATUS.PD 3 Power-down bit BANK2:STATUS.Z 2 Zero bit BANK2:STATUS.DC 1 Digit carry/borrow bit BANK2:STATUS.C 0 Carry/borrow bit BANK2:FSR 0x0104 Indirect data memory address pointer BANK2:RESERVED0105 0x0105 RESERVED BANK2:PORTB 0x0106 PORTB REGISTER BANK2:PORTB.RB7 7 PORTB bit 7 BANK2:PORTB.RB6 6 PORTB bit 6 BANK2:PORTB.RB5 5 PORTB bit 5 BANK2:PORTB.RB4 4 PORTB bit 4 BANK2:PORTB.RB3 3 PORTB bit 3 BANK2:PORTB.RB2 2 PORTB bit 2 BANK2:PORTB.RB1 1 PORTB bit 1 BANK2:PORTB.RB0 0 PORTB bit 0 BANK2:RESERVED0107 0x0107 RESERVED BANK2:RESERVED0108 0x0108 RESERVED BANK2:RESERVED0109 0x0109 RESERVED BANK2:PCLATH 0x010A Write Buffer for the upper 5 bits of the Program Counter BANK2:INTCON 0x010B INTCON REGISTER BANK2:INTCON.GIE 7 Global Interrupt Enable bit BANK2:INTCON.PEIE 6 Peripheral Interrupt Enable bit BANK2:INTCON.T0IE 5 TMR0 Overflow Interrupt Enable bit BANK2:INTCON.INTE 4 RB0/INT External Interrupt Enable bit BANK2:INTCON.RBIE 3 RB Port Change Interrupt Enable bit BANK2:INTCON.T0IF 2 TMR0 Overflow Interrupt Flag bit BANK2:INTCON.INTF 1 RB0/INT External Interrupt Flag bit BANK2:INTCON.RBIF 0 RB Port Change Interrupt Flag bit BANK2:RESERVED010C 0x010C RESERVED BANK2:RESERVED010D 0x010D RESERVED BANK2:RESERVED010E 0x010E RESERVED BANK2:RESERVED010F 0x010F RESERVED BANK2:RESERVED0110 0x0110 RESERVED BANK2:RESERVED0111 0x0111 RESERVED BANK2:RESERVED0112 0x0112 RESERVED BANK2:RESERVED0113 0x0113 RESERVED BANK2:RESERVED0114 0x0114 RESERVED BANK2:RESERVED0115 0x0115 RESERVED BANK2:RESERVED0116 0x0116 RESERVED BANK2:RESERVED0117 0x0117 RESERVED BANK2:RESERVED0118 0x0118 RESERVED BANK2:RESERVED0119 0x0119 RESERVED BANK2:RESERVED011A 0x011A RESERVED BANK2:RESERVED011B 0x011B RESERVED BANK2:RESERVED011C 0x011C RESERVED BANK2:RESERVED011D 0x011D RESERVED BANK2:RESERVED011E 0x011E RESERVED BANK2:RESERVED011F 0x011F RESERVED ; BANK3 (0x0180:0x0200) BANK3:INDF 0x0180 INDF (not a physical register) BANK3:OPTION 0x0181 OPTION REGISTER BANK3:OPTION.RBPU 7 PORTB Pull-up Enable bit BANK3:OPTION.INTEDG 6 Interrupt Edge Select bit BANK3:OPTION.T0CS 5 TMR0 Clock Source Select bit BANK3:OPTION.T0SE 4 TMR0 Source Edge Select bit BANK3:OPTION.PSA 3 Prescaler Assignment bit BANK3:OPTION.PS2 2 Prescaler Rate Select bit 2 BANK3:OPTION.PS1 1 Prescaler Rate Select bit 1 BANK3:OPTION.PS0 0 Prescaler Rate Select bit 0 BANK3:PCL 0x0182 Program Counter's (PC) Least Significant Byte BANK3:STATUS 0x0183 STATUS REGISTER BANK3:STATUS.IRP 7 Register Bank Select bit BANK3:STATUS.RP1 6 Register Bank Select bit 1 BANK3:STATUS.RP0 5 Register Bank Select bit 0 BANK3:STATUS.TO 4 Time-out bit BANK3:STATUS.PD 3 Power-down bit BANK3:STATUS.Z 2 Zero bit BANK3:STATUS.DC 1 Digit carry/borrow bit BANK3:STATUS.C 0 Carry/borrow bit BANK3:FSR 0x0184 Indirect data memory address pointer BANK3:RESERVED0185 0x0185 RESERVED BANK3:TRISB 0x0186 PORTB Data Direction Register BANK3:TRISB.TRISB7 7 PORTB Data Direction Register bit 7 BANK3:TRISB.TRISB6 6 PORTB Data Direction Register bit 6 BANK3:TRISB.TRISB5 5 PORTB Data Direction Register bit 5 BANK3:TRISB.TRISB4 4 PORTB Data Direction Register bit 4 BANK3:TRISB.TRISB3 3 PORTB Data Direction Register bit 3 BANK3:TRISB.TRISB2 2 PORTB Data Direction Register bit 2 BANK3:TRISB.TRISB1 1 PORTB Data Direction Register bit 1 BANK3:TRISB.TRISB0 0 PORTB Data Direction Register bit 0 BANK3:RESERVED0187 0x0187 RESERVED BANK3:RESERVED0188 0x0188 RESERVED BANK3:RESERVED0189 0x0189 RESERVED BANK3:PCLATH 0x018A Write Buffer for the upper 5 bits of the Program Counter BANK3:INTCON 0x018B INTCON REGISTER BANK3:INTCON.GIE 7 Global Interrupt Enable bit BANK3:INTCON.PEIE 6 Peripheral Interrupt Enable bit BANK3:INTCON.T0IE 5 TMR0 Overflow Interrupt Enable bit BANK3:INTCON.INTE 4 RB0/INT External Interrupt Enable bit BANK3:INTCON.RBIE 3 RB Port Change Interrupt Enable bit BANK3:INTCON.T0IF 2 TMR0 Overflow Interrupt Flag bit BANK3:INTCON.INTF 1 RB0/INT External Interrupt Flag bit BANK3:INTCON.RBIF 0 RB Port Change Interrupt Flag bit BANK3:RESERVED018C 0x018C RESERVED BANK3:RESERVED018D 0x018D RESERVED BANK3:RESERVED018E 0x018E RESERVED BANK3:RESERVED018F 0x018F RESERVED BANK3:RESERVED0190 0x0190 RESERVED BANK3:RESERVED0191 0x0191 RESERVED BANK3:RESERVED0192 0x0192 RESERVED BANK3:RESERVED0193 0x0193 RESERVED BANK3:RESERVED0194 0x0194 RESERVED BANK3:RESERVED0195 0x0195 RESERVED BANK3:RESERVED0196 0x0196 RESERVED BANK3:RESERVED0197 0x0197 RESERVED BANK3:RESERVED0198 0x0198 RESERVED BANK3:RESERVED0199 0x0199 RESERVED BANK3:RESERVED019A 0x019A RESERVED BANK3:RESERVED019B 0x019B RESERVED BANK3:RESERVED019C 0x019C RESERVED BANK3:RESERVED019D 0x019D RESERVED BANK3:RESERVED019E 0x019E RESERVED BANK3:RESERVED019F 0x019F RESERVED .16C781 ; http://www.microchip.com/download/lit/pline/picmicro/families/16c78x/41171a.pdf ; PIC16C781_2.pdf ; MEMORY MAP ; BANK_0 area DATA FSR_ 0x0000:0x0020 area DATA Gen_Purp 0x0020:0x0080 General Purpose Register area DATA MEM_Program 0x0080:0x0400 On-chip Program Memory ; BANK_1 ; area DATA FSR_ 0x0080:0x00A0 ; area DATA Gen_Purp 0x00A0:0x00C0 General Purpose Register ; area BSS RESERVED 0x00C0:0x00F0 ; area DATA Gen_Purp_BANK0 0x00F0:0x0100 accesses 70h-7Fh ; area DATA MEM_Program 0x0100:0x0400 On-chip Program Memory ; BANK_2 ; area DATA FSR_ 0x0100:0x0120 ; area BSS RESERVED 0x0120:0x0170 ; area DATA Gen_Purp_BANK0 0x0170:0x0180 accesses 70h-7Fh ; area DATA MEM_Program 0x0180:0x0400 On-chip Program Memory ; BANK_3 ; area DATA FSR_ 0x0180:0x01A0 ; area BSS RESERVED 0x01A0:0x01F0 ; area DATA Gen_Purp_BANK0 0x01F0:0x0200 accesses 70h-7Fh ; area DATA MEM_Program 0x0200:0x0400 On-chip Program Memory ; Interrupt and reset vector assignments interrupt RESET 0x0000 RESET ; INPUT/OUTPUT PORTS ; BANK0 (0x0000:0x0080) BANK0:INDF 0x0000 INDF (not a physical register) BANK0:TMR0 0x0001 Timer0 module's register BANK0:PCL 0x0002 Program Counter's (PC) Least Significant Byte BANK0:STATUS 0x0003 STATUS REGISTER BANK0:STATUS.IRP 7 Register Bank Select bit BANK0:STATUS.RP1 6 Register Bank Select bit 1 BANK0:STATUS.RP0 5 Register Bank Select bit 0 BANK0:STATUS.TO 4 Time-out bit BANK0:STATUS.PD 3 Power-down bit BANK0:STATUS.Z 2 Zero bit BANK0:STATUS.DC 1 Digit carry/borrow bit BANK0:STATUS.C 0 Carry/borrow bit BANK0:FSR 0x0004 Indirect data memory address pointer BANK0:PORTA 0x0005 PORTA REGISTER BANK0:PORTA.RA7 7 PORTA bit 7 BANK0:PORTA.RA6 6 PORTA bit 6 BANK0:PORTA.RA5 5 PORTA bit 5 BANK0:PORTA.RA4 4 PORTA bit 4 BANK0:PORTA.RA3 3 PORTA bit 3 BANK0:PORTA.RA2 2 PORTA bit 2 BANK0:PORTA.RA1 1 PORTA bit 1 BANK0:PORTA.RA0 0 PORTA bit 0 BANK0:PORTB 0x0006 PORTB REGISTER BANK0:PORTB.RB7 7 PORTB bit 7 BANK0:PORTB.RB6 6 PORTB bit 6 BANK0:PORTB.RB5 5 PORTB bit 5 BANK0:PORTB.RB4 4 PORTB bit 4 BANK0:PORTB.RB3 3 PORTB bit 3 BANK0:PORTB.RB2 2 PORTB bit 2 BANK0:PORTB.RB1 1 PORTB bit 1 BANK0:PORTB.RB0 0 PORTB bit 0 BANK0:RESERVED0007 0x0007 RESERVED BANK0:RESERVED0008 0x0008 RESERVED BANK0:RESERVED0009 0x0009 RESERVED BANK0:PCLATH 0x000A Write Buffer for the upper 5 bits of the Program Counter BANK0:INTCON 0x000B INTCON REGISTER BANK0:INTCON.GIE 7 Global Interrupt Enable bit BANK0:INTCON.PEIE 6 Peripheral Interrupt Enable bit BANK0:INTCON.T0IE 5 TMR0 Overflow Interrupt Enable bit BANK0:INTCON.INTE 4 RB0/INT External Interrupt Enable bit BANK0:INTCON.RBIE 3 RB Port Change Interrupt Enable bit BANK0:INTCON.T0IF 2 TMR0 Overflow Interrupt Flag bit BANK0:INTCON.INTF 1 RB0/INT External Interrupt Flag bit BANK0:INTCON.RBIF 0 RB Port Change Interrupt Flag bit BANK0:PIR1 0x000C PIR1 REGISTER BANK0:PIR1.LVDIF 7 Low Voltage Detect Interrupt Flag bit BANK0:PIR1.ADIF 6 A/D Converter Interrupt Flag bit BANK0:PIR1.C2IF 5 Comparator C2 Interrupt Flag bit BANK0:PIR1.C1IF 4 Comparator C1 Interrupt Flag bit BANK0:PIR1.TMR1IF 0 TMR1 Overflow Interrupt Flag bit BANK0:RESERVED000D 0x000D RESERVED BANK0:TMR1L 0x000E Holding register for the Least Significant Byte of the 16-bit TMR1 register BANK0:TMR1H 0x000F Holding register for the Most Significant Byte of the 16-bit TMR1 register BANK0:T1CON 0x0010 TIMER1 CONTROL REGISTER BANK0:T1CON.TMR1GE 6 Timer1 Gate Enable bit BANK0:T1CON.T1CKPS1 5 Timer1 Input Clock Prescale Select bit 1 BANK0:T1CON.T1CKPS0 4 Timer1 Input Clock Prescale Select bit 0 BANK0:T1CON.T1OSCEN 3 Timer1 Oscillator Enable Control bit BANK0:T1CON.T1SYNC 2 Timer1 External Clock Input Synchronization Control bit BANK0:T1CON.TMR1CS 1 Timer1 Clock Source Select bit BANK0:T1CON.TMR1ON 0 Timer1 On bit BANK0:RESERVED0011 0x0011 RESERVED BANK0:RESERVED0012 0x0012 RESERVED BANK0:RESERVED0013 0x0013 RESERVED BANK0:RESERVED0014 0x0014 RESERVED BANK0:RESERVED0015 0x0015 RESERVED BANK0:RESERVED0016 0x0016 RESERVED BANK0:RESERVED0017 0x0017 RESERVED BANK0:RESERVED0018 0x0018 RESERVED BANK0:RESERVED0019 0x0019 RESERVED BANK0:RESERVED001A 0x001A RESERVED BANK0:RESERVED001B 0x001B RESERVED BANK0:RESERVED001C 0x001C RESERVED BANK0:RESERVED001D 0x001D RESERVED BANK0:ADRES 0x001E ADC Result Register BANK0:ADCON0 0x001F ADCON0 REGISTER BANK0:ADCON0.ADCS1 7 A/D Conversion Clock Select bit 1 BANK0:ADCON0.ADCS0 6 A/D Conversion Clock Select bit 0 BANK0:ADCON0.CHS2 5 Analog Channel Select bit 2 BANK0:ADCON0.CHS1 4 Analog Channel Select bit 1 BANK0:ADCON0.CHS0 3 Analog Channel Select bit 0 BANK0:ADCON0.GO_DONE 2 A/D Conversion Status bit BANK0:ADCON0.CHS3 1 Analog Channel Select bit 3 BANK0:ADCON0.ADON 0 A/D On bit ; BANK1 (0x0080:0x0100) BANK1:INDF 0x0080 INDF (not a physical register) BANK1:OPTION 0x0081 OPTION REGISTER BANK1:OPTION.RBPU 7 PORTB Pull-up Enable bit BANK1:OPTION.INTEDG 6 Interrupt Edge Select bit BANK1:OPTION.T0CS 5 TMR0 Clock Source Select bit BANK1:OPTION.T0SE 4 TMR0 Source Edge Select bit BANK1:OPTION.PSA 3 Prescaler Assignment bit BANK1:OPTION.PS2 2 Prescaler Rate Select bit 2 BANK1:OPTION.PS1 1 Prescaler Rate Select bit 1 BANK1:OPTION.PS0 0 Prescaler Rate Select bit 0 BANK1:PCL 0x0082 Program Counter's (PC) Least Significant Byte BANK1:STATUS 0x0083 STATUS REGISTER BANK1:STATUS.IRP 7 Register Bank Select bit BANK1:STATUS.RP1 6 Register Bank Select bit 1 BANK1:STATUS.RP0 5 Register Bank Select bit 0 BANK1:STATUS.TO 4 Time-out bit BANK1:STATUS.PD 3 Power-down bit BANK1:STATUS.Z 2 Zero bit BANK1:STATUS.DC 1 Digit carry/borrow bit BANK1:STATUS.C 0 Carry/borrow bit BANK1:FSR 0x0084 Indirect data memory address pointer BANK1:TRISA 0x0085 PORTA Data Direction Register BANK1:TRISA.TRISA7 7 PORTA Data Direction Register bit 7 BANK1:TRISA.TRISA6 6 PORTA Data Direction Register bit 6 BANK1:TRISA.TRISA5 5 PORTA Data Direction Register bit 5 BANK1:TRISA.TRISA4 4 PORTA Data Direction Register bit 4 BANK1:TRISA.TRISA3 3 PORTA Data Direction Register bit 3 BANK1:TRISA.TRISA2 2 PORTA Data Direction Register bit 2 BANK1:TRISA.TRISA1 1 PORTA Data Direction Register bit 1 BANK1:TRISA.TRISA0 0 PORTA Data Direction Register bit 0 BANK1:TRISB 0x0086 PORTB Data Direction Register BANK1:TRISB.TRISB7 7 PORTB Data Direction Register bit 7 BANK1:TRISB.TRISB6 6 PORTB Data Direction Register bit 6 BANK1:TRISB.TRISB5 5 PORTB Data Direction Register bit 5 BANK1:TRISB.TRISB4 4 PORTB Data Direction Register bit 4 BANK1:TRISB.TRISB3 3 PORTB Data Direction Register bit 3 BANK1:TRISB.TRISB2 2 PORTB Data Direction Register bit 2 BANK1:TRISB.TRISB1 1 PORTB Data Direction Register bit 1 BANK1:TRISB.TRISB0 0 PORTB Data Direction Register bit 0 BANK1:RESERVED0087 0x0087 RESERVED BANK1:RESERVED0088 0x0088 RESERVED BANK1:RESERVED0089 0x0089 RESERVED BANK1:PCLATH 0x008A Write Buffer for the upper 5 bits of the Program Counter BANK1:INTCON 0x008B INTCON REGISTER BANK1:INTCON.GIE 7 Global Interrupt Enable bit BANK1:INTCON.PEIE 6 Peripheral Interrupt Enable bit BANK1:INTCON.T0IE 5 TMR0 Overflow Interrupt Enable bit BANK1:INTCON.INTE 4 RB0/INT External Interrupt Enable bit BANK1:INTCON.RBIE 3 RB Port Change Interrupt Enable bit BANK1:INTCON.T0IF 2 TMR0 Overflow Interrupt Flag bit BANK1:INTCON.INTF 1 RB0/INT External Interrupt Flag bit BANK1:INTCON.RBIF 0 RB Port Change Interrupt Flag bit BANK1:PIE1 0x008C PIE1 REGISTER BANK1:PIE1.LVDIE 7 Low Voltage Detect Interrupt Enable bit BANK1:PIE1.ADIE 6 A/D Converter Interrupt Enable bit BANK1:PIE1.C2IE 5 Comparator C2 Interrupt Enable bit BANK1:PIE1.C1IE 4 Comparator C1 Interrupt Enable bit BANK1:PIE1.TMR1IE 0 TMR1 Overflow Interrupt Enable bit BANK1:RESERVED008D 0x008D RESERVED BANK1:PCON 0x008E PCON REGISTER BANK1:PCON.WDTON 4 WDT Software Enable bit BANK1:PCON.OSCF 3 Oscillator Speed INTRC Mode bit BANK1:PCON.POR 1 Power-on Reset Status bit BANK1:PCON.BOR 0 Brown-out Reset Status bit BANK1:RESERVED008F 0x008F RESERVED BANK1:RESERVED0090 0x0090 RESERVED BANK1:RESERVED0091 0x0091 RESERVED BANK1:RESERVED0092 0x0092 RESERVED BANK1:RESERVED0093 0x0093 RESERVED BANK1:RESERVED0094 0x0094 RESERVED BANK1:WPUB 0x0095 PORTB Weak Pull-up Control BANK1:IOCB 0x0096 PORTB Interrupt-on-Change Control BANK1:RESERVED0097 0x0097 RESERVED BANK1:RESERVED0098 0x0098 RESERVED BANK1:RESERVED0099 0x0099 RESERVED BANK1:RESERVED009A 0x009A RESERVED BANK1:REFCON 0x009B VOLTAGE REFERENCE CONTROL REGISTER BANK1:REFCON.VREN 3 Voltage Reference Enable bit BANK1:REFCON.VROE 2 Voltage Reference Output Enable bit BANK1:LVDCON 0x009C PROGRAMMABLE LOW VOLTAGE DETECT REGISTER BANK1:LVDCON.BGST 5 Internal Reference Voltage Stable Flag bit BANK1:LVDCON.LVDEN 4 Low Voltage Detect Power Enable bit BANK1:LVDCON.LV3 3 Low Voltage Detection Limit bit 3 BANK1:LVDCON.LV2 2 Low Voltage Detection Limit bit 2 BANK1:LVDCON.LV1 1 Low Voltage Detection Limit bit 1 BANK1:LVDCON.LV0 0 Low Voltage Detection Limit bit 0 BANK1:ANSEL 0x009D Analog Channel Select BANK1:RESERVED009E 0x009E RESERVED BANK1:ADCON1 0x009F ADCON1 REGISTER BANK1:ADCON1.VCFG1 5 Voltage reference configuration bit 1 BANK1:ADCON1.VCFG0 4 Voltage reference configuration bit 0 ; BANK2 (0x0100:0x0180) BANK2:INDF 0x0100 INDF (not a physical register) BANK2:TMR0 0x0101 Timer0 module's register BANK2:PCL 0x0102 Program Counter's (PC) Least Significant Byte BANK2:STATUS 0x0103 STATUS REGISTER BANK2:STATUS.IRP 7 Register Bank Select bit BANK2:STATUS.RP1 6 Register Bank Select bit 1 BANK2:STATUS.RP0 5 Register Bank Select bit 0 BANK2:STATUS.TO 4 Time-out bit BANK2:STATUS.PD 3 Power-down bit BANK2:STATUS.Z 2 Zero bit BANK2:STATUS.DC 1 Digit carry/borrow bit BANK2:STATUS.C 0 Carry/borrow bit BANK2:FSR 0x0104 Indirect data memory address pointer BANK2:RESERVED0105 0x0105 RESERVED BANK2:PORTB 0x0106 PORTB REGISTER BANK2:PORTB.RB7 7 PORTB bit 7 BANK2:PORTB.RB6 6 PORTB bit 6 BANK2:PORTB.RB5 5 PORTB bit 5 BANK2:PORTB.RB4 4 PORTB bit 4 BANK2:PORTB.RB3 3 PORTB bit 3 BANK2:PORTB.RB2 2 PORTB bit 2 BANK2:PORTB.RB1 1 PORTB bit 1 BANK2:PORTB.RB0 0 PORTB bit 0 BANK2:RESERVED0107 0x0107 RESERVED BANK2:RESERVED0108 0x0108 RESERVED BANK2:RESERVED0109 0x0109 RESERVED BANK2:PCLATH 0x010A Write Buffer for the upper 5 bits of the Program Counter BANK2:INTCON 0x010B INTCON REGISTER BANK2:INTCON.GIE 7 Global Interrupt Enable bit BANK2:INTCON.PEIE 6 Peripheral Interrupt Enable bit BANK2:INTCON.T0IE 5 TMR0 Overflow Interrupt Enable bit BANK2:INTCON.INTE 4 RB0/INT External Interrupt Enable bit BANK2:INTCON.RBIE 3 RB Port Change Interrupt Enable bit BANK2:INTCON.T0IF 2 TMR0 Overflow Interrupt Flag bit BANK2:INTCON.INTF 1 RB0/INT External Interrupt Flag bit BANK2:INTCON.RBIF 0 RB Port Change Interrupt Flag bit BANK2:PMDATL 0x010C PROGRAM MEMORY DATA LOW BANK2:PMDATL.PMD7 7 Program Memory Data bit 7 BANK2:PMDATL.PMD6 6 Program Memory Data bit 6 BANK2:PMDATL.PMD5 5 Program Memory Data bit 5 BANK2:PMDATL.PMD4 4 Program Memory Data bit 4 BANK2:PMDATL.PMD3 3 Program Memory Data bit 3 BANK2:PMDATL.PMD2 2 Program Memory Data bit 2 BANK2:PMDATL.PMD1 1 Program Memory Data bit 1 BANK2:PMDATL.PMD0 0 Program Memory Data bit 0 BANK2:PMADRL 0x010D PROGRAM MEMORY ADDRESS LOW BANK2:PMADRL.PMA7 7 PMR Address bit 7 BANK2:PMADRL.PMA6 6 PMR Address bit 6 BANK2:PMADRL.PMA5 5 PMR Address bit 5 BANK2:PMADRL.PMA4 4 PMR Address bit 4 BANK2:PMADRL.PMA3 3 PMR Address bit 3 BANK2:PMADRL.PMA2 2 PMR Address bit 2 BANK2:PMADRL.PMA1 1 PMR Address bit 1 BANK2:PMADRL.PMA0 0 PMR Address bit 0 BANK2:PMDATH 0x010E PROGRAM MEMORY DATA HIGH BANK2:PMDATH.PMD13 5 Program Memory Data bit 13 BANK2:PMDATH.PMD12 4 Program Memory Data bit 12 BANK2:PMDATH.PMD11 3 Program Memory Data bit 11 BANK2:PMDATH.PMD10 2 Program Memory Data bit 10 BANK2:PMDATH.PMD9 1 Program Memory Data bit 9 BANK2:PMDATH.PMD8 0 Program Memory Data bit 8 BANK2:PMADRH 0x010F PROGRAM MEMORY ADDRESS HIGH BANK2:PMADRH.PMA10 2 PMR Address bit 10 BANK2:PMADRH.PMA9 1 PMR Address bit 9 BANK2:PMADRH.PMA8 0 PMR Address bit 8 BANK2:CALCON 0x0110 CALIBRATION CONTROL REGISTER BANK2:CALCON.CAL 7 Start and Status bit BANK2:CALCON.CALERR 6 Calibration Error Indicator bit BANK2:CALCON.CALREF 5 Calibration Voltage Select bit BANK2:PSMCCON0 0x0111 PSMC CONTROL REGISTER0 BANK2:PSMCCON0.SMCCL1 7 Clock Frequency Select bit 1 BANK2:PSMCCON0.SMCCL0 6 Clock Frequency Select bit 0 BANK2:PSMCCON0.MINDC1 5 Minimum Duty Cycle Select bit 1 for PWM Mode BANK2:PSMCCON0.MINDC0 4 Minimum Duty Cycle Select bit 0 for PWM Mode BANK2:PSMCCON0.MAXDC1 3 Maximum Duty Cycle Select bit 1 for PWM Mode BANK2:PSMCCON0.MAXDC0 2 Maximum Duty Cycle Select bit 0 for PWM Mode BANK2:PSMCCON0.DC1 1 Duty Cycle Select bit 1 for PSM Mode BANK2:PSMCCON0.DC0 0 Duty Cycle Select bit 0 for PSM Mode BANK2:PSMCCON1 0x0112 PSMC CONTROL REGISTER1 BANK2:PSMCCON1.SMCON 7 PSMC Module Enable bit BANK2:PSMCCON1.S1APOL 6 PSMC1A Output Polarity Control bit BANK2:PSMCCON1.S1BPOL 5 PSMC1B Output Polarity Control bit BANK2:PSMCCON1.SCEN 3 Slope Compensation Output Enable bit BANK2:PSMCCON1.SMCOM 2 PSMC Output Mode bit BANK2:PSMCCON1.PWM_PSM 1 PSMC Modulation Mode Select bit BANK2:PSMCCON1.SMCCS 0 PSMC Comparator Select bit BANK2:RESERVED0113 0x0113 RESERVED BANK2:RESERVED0114 0x0114 RESERVED BANK2:RESERVED0115 0x0115 RESERVED BANK2:RESERVED0116 0x0116 RESERVED BANK2:RESERVED0117 0x0117 RESERVED BANK2:RESERVED0118 0x0118 RESERVED BANK2:CM1CON0 0x0119 COMPARATOR C1 CONTROL REGISTER0 BANK2:CM1CON0.C1ON 7 Comparator C1 Enable bit BANK2:CM1CON0.C1OUT 6 Comparator C1 Output bit BANK2:CM1CON0.C1OE 5 Comparator C1 Output Enable bit BANK2:CM1CON0.C1POL 4 Comparator C1 Output Polarity Select bit BANK2:CM1CON0.C1SP 3 Comparator C1 Speed Select bit BANK2:CM1CON0.C1R 2 Comparator C1 Reference Select bits (non-inverting input) BANK2:CM1CON0.C1CH1 1 Comparator C1 Channel Select bit 1 BANK2:CM1CON0.C1CH0 0 Comparator C1 Channel Select bit 0 BANK2:CM2CON0 0x011A COMPARATOR C2 CONTROL REGISTER0 BANK2:CM2CON0.C2ON 7 Comparator C2 Enable bit BANK2:CM2CON0.C2OUT 6 Comparator C2 Output bit BANK2:CM2CON0.C2OE 5 Comparator C2 Output Enable bit BANK2:CM2CON0.C2POL 4 Comparator C2 Output Polarity Select bit BANK2:CM2CON0.C2SP 3 Comparator C2 Speed Select bit BANK2:CM2CON0.C2R 2 Comparator C2 Reference Select bits (non-inverting input) BANK2:CM2CON0.C2CH1 1 Comparator C2 Channel Select bit 1 BANK2:CM2CON0.C2CH0 0 Comparator C2 Channel Select bit 0 BANK2:CM2CON1 0x011B COMPARATOR C2 CONTROL REGISTER1 BANK2:CM2CON1.MC1OUT 7 Mirror Copy of C1OUT (CM1CON0<6>) BANK2:CM2CON1.MC2OUT 6 Copy of C2OUT (CM2CON0<6>) BANK2:CM2CON1.C2SYNC 0 C2 Output Synchronous Mode bit BANK2:OPACON 0x011C OPAMP CONTROL REGISTER BANK2:OPACON.OPAON 7 OPAMP Enable bit BANK2:OPACON.CMPEN 6 Comparator Mode Enable bit BANK2:OPACON.GBWP 0 Gain Bandwidth Product Select bits BANK2:RESERVED011D 0x011D RESERVED BANK2:DAC 0x011E DIGITAL-TO-ANALOG CONVERTER REGISTER BANK2:DAC.DA7 7 Digital-to-Analog Converter Digital Input bit 7 BANK2:DAC.DA6 6 Digital-to-Analog Converter Digital Input bit 6 BANK2:DAC.DA5 5 Digital-to-Analog Converter Digital Input bit 5 BANK2:DAC.DA4 4 Digital-to-Analog Converter Digital Input bit 4 BANK2:DAC.DA3 3 Digital-to-Analog Converter Digital Input bit 3 BANK2:DAC.DA2 2 Digital-to-Analog Converter Digital Input bit 2 BANK2:DAC.DA1 1 Digital-to-Analog Converter Digital Input bit 1 BANK2:DAC.DA0 0 Digital-to-Analog Converter Digital Input bit 0 BANK2:DACON0 0x011F DIGITAL-TO-ANALOG CONVERTER CONTROL REGISTER0 BANK2:DACON0.DAON 7 Digital-to-Analog Converter Enable bit BANK2:DACON0.DAOE 6 Digital-to-Analog Converter Output Enable bit BANK2:DACON0.DARS1 1 Digital-to-Analog Converter Voltage Reference Select bit 1 BANK2:DACON0.DARS0 0 Digital-to-Analog Converter Voltage Reference Select bit 0 ; BANK3 (0x0180:0x0200) BANK3:INDF 0x0180 INDF (not a physical register) BANK3:OPTION 0x0181 OPTION REGISTER BANK3:OPTION.RBPU 7 PORTB Pull-up Enable bit BANK3:OPTION.INTEDG 6 Interrupt Edge Select bit BANK3:OPTION.T0CS 5 TMR0 Clock Source Select bit BANK3:OPTION.T0SE 4 TMR0 Source Edge Select bit BANK3:OPTION.PSA 3 Prescaler Assignment bit BANK3:OPTION.PS2 2 Prescaler Rate Select bit 2 BANK3:OPTION.PS1 1 Prescaler Rate Select bit 1 BANK3:OPTION.PS0 0 Prescaler Rate Select bit 0 BANK3:PCL 0x0182 Program Counter's (PC) Least Significant Byte BANK3:STATUS 0x0183 STATUS REGISTER BANK3:STATUS.IRP 7 Register Bank Select bit BANK3:STATUS.RP1 6 Register Bank Select bit 1 BANK3:STATUS.RP0 5 Register Bank Select bit 0 BANK3:STATUS.TO 4 Time-out bit BANK3:STATUS.PD 3 Power-down bit BANK3:STATUS.Z 2 Zero bit BANK3:STATUS.DC 1 Digit carry/borrow bit BANK3:STATUS.C 0 Carry/borrow bit BANK3:FSR 0x0184 Indirect data memory address pointer BANK3:RESERVED 0x0185 RESERVED BANK3:TRISB 0x0186 PORTB Data Direction Register BANK3:TRISB.TRISB7 7 PORTB Data Direction Register bit 7 BANK3:TRISB.TRISB6 6 PORTB Data Direction Register bit 6 BANK3:TRISB.TRISB5 5 PORTB Data Direction Register bit 5 BANK3:TRISB.TRISB4 4 PORTB Data Direction Register bit 4 BANK3:TRISB.TRISB3 3 PORTB Data Direction Register bit 3 BANK3:TRISB.TRISB2 2 PORTB Data Direction Register bit 2 BANK3:TRISB.TRISB1 1 PORTB Data Direction Register bit 1 BANK3:TRISB.TRISB0 0 PORTB Data Direction Register bit 0 BANK3:RESERVED0187 0x0187 RESERVED BANK3:RESERVED0188 0x0188 RESERVED BANK3:RESERVED0189 0x0189 RESERVED BANK3:PCLATH 0x018A Write Buffer for the upper 5 bits of the Program Counter BANK3:INTCON 0x018B INTCON REGISTER BANK3:INTCON.GIE 7 Global Interrupt Enable bit BANK3:INTCON.PEIE 6 Peripheral Interrupt Enable bit BANK3:INTCON.T0IE 5 TMR0 Overflow Interrupt Enable bit BANK3:INTCON.INTE 4 RB0/INT External Interrupt Enable bit BANK3:INTCON.RBIE 3 RB Port Change Interrupt Enable bit BANK3:INTCON.T0IF 2 TMR0 Overflow Interrupt Flag bit BANK3:INTCON.INTF 1 RB0/INT External Interrupt Flag bit BANK3:INTCON.RBIF 0 RB Port Change Interrupt Flag bit BANK3:PMCON1 0x018C PROGRAM MEMORY READ CONTROL REGISTER 1 BANK3:PMCON1.RD 0 Read Control bit BANK3:RESERVED018D 0x018D RESERVED BANK3:RESERVED018E 0x018E RESERVED BANK3:RESERVED018F 0x018F RESERVED BANK3:RESERVED0190 0x0190 RESERVED BANK3:RESERVED0191 0x0191 RESERVED BANK3:RESERVED0192 0x0192 RESERVED BANK3:RESERVED0193 0x0193 RESERVED BANK3:RESERVED0194 0x0194 RESERVED BANK3:RESERVED0195 0x0195 RESERVED BANK3:RESERVED0196 0x0196 RESERVED BANK3:RESERVED0197 0x0197 RESERVED BANK3:RESERVED0198 0x0198 RESERVED BANK3:RESERVED0199 0x0199 RESERVED BANK3:RESERVED019A 0x019A RESERVED BANK3:RESERVED019B 0x019B RESERVED BANK3:RESERVED019C 0x019C RESERVED BANK3:RESERVED019D 0x019D RESERVED BANK3:RESERVED019E 0x019E RESERVED BANK3:RESERVED019F 0x019F RESERVED .16C782 ; http://www.microchip.com/download/lit/pline/picmicro/families/16c78x/41171a.pdf ; PIC16C781_2.pdf ; MEMORY MAP ; BANK_0 area DATA FSR_ 0x0000:0x0020 area DATA Gen_Purp 0x0020:0x0080 General Purpose Register area DATA MEM_Program 0x0080:0x0800 On-chip Program Memory ; BANK_1 ; area DATA FSR_ 0x0080:0x00A0 ; area DATA Gen_Purp 0x00A0:0x00C0 General Purpose Register ; area BSS RESERVED 0x00C0:0x00F0 ; area DATA Gen_Purp_BANK0 0x00F0:0x0100 accesses 70h-7Fh ; area DATA MEM_Program 0x0100:0x0800 On-chip Program Memory ; BANK_2 ; area DATA FSR_ 0x0100:0x0120 ; area BSS RESERVED 0x0120:0x0170 ; area DATA Gen_Purp_BANK0 0x0170:0x0180 accesses 70h-7Fh ; area DATA MEM_Program 0x0180:0x0800 On-chip Program Memory ; BANK_3 ; area DATA FSR_ 0x0180:0x01A0 ; area BSS RESERVED 0x01A0:0x01F0 ; area DATA Gen_Purp_BANK0 0x01F0:0x0200 accesses 70h-7Fh ; area DATA MEM_Program 0x0200:0x0800 On-chip Program Memory ; Interrupt and reset vector assignments interrupt RESET 0x0000 RESET ; INPUT/OUTPUT PORTS ; BANK0 (0x0000:0x0080) BANK0:INDF 0x0000 INDF (not a physical register) BANK0:TMR0 0x0001 Timer0 module's register BANK0:PCL 0x0002 Program Counter's (PC) Least Significant Byte BANK0:STATUS 0x0003 STATUS REGISTER BANK0:STATUS.IRP 7 Register Bank Select bit BANK0:STATUS.RP1 6 Register Bank Select bit 1 BANK0:STATUS.RP0 5 Register Bank Select bit 0 BANK0:STATUS.TO 4 Time-out bit BANK0:STATUS.PD 3 Power-down bit BANK0:STATUS.Z 2 Zero bit BANK0:STATUS.DC 1 Digit carry/borrow bit BANK0:STATUS.C 0 Carry/borrow bit BANK0:FSR 0x0004 Indirect data memory address pointer BANK0:PORTA 0x0005 PORTA REGISTER BANK0:PORTA.RA7 7 PORTA bit 7 BANK0:PORTA.RA6 6 PORTA bit 6 BANK0:PORTA.RA5 5 PORTA bit 5 BANK0:PORTA.RA4 4 PORTA bit 4 BANK0:PORTA.RA3 3 PORTA bit 3 BANK0:PORTA.RA2 2 PORTA bit 2 BANK0:PORTA.RA1 1 PORTA bit 1 BANK0:PORTA.RA0 0 PORTA bit 0 BANK0:PORTB 0x0006 PORTB REGISTER BANK0:PORTB.RB7 7 PORTB bit 7 BANK0:PORTB.RB6 6 PORTB bit 6 BANK0:PORTB.RB5 5 PORTB bit 5 BANK0:PORTB.RB4 4 PORTB bit 4 BANK0:PORTB.RB3 3 PORTB bit 3 BANK0:PORTB.RB2 2 PORTB bit 2 BANK0:PORTB.RB1 1 PORTB bit 1 BANK0:PORTB.RB0 0 PORTB bit 0 BANK0:RESERVED0007 0x0007 RESERVED BANK0:RESERVED0008 0x0008 RESERVED BANK0:RESERVED0009 0x0009 RESERVED BANK0:PCLATH 0x000A Write Buffer for the upper 5 bits of the Program Counter BANK0:INTCON 0x000B INTCON REGISTER BANK0:INTCON.GIE 7 Global Interrupt Enable bit BANK0:INTCON.PEIE 6 Peripheral Interrupt Enable bit BANK0:INTCON.T0IE 5 TMR0 Overflow Interrupt Enable bit BANK0:INTCON.INTE 4 RB0/INT External Interrupt Enable bit BANK0:INTCON.RBIE 3 RB Port Change Interrupt Enable bit BANK0:INTCON.T0IF 2 TMR0 Overflow Interrupt Flag bit BANK0:INTCON.INTF 1 RB0/INT External Interrupt Flag bit BANK0:INTCON.RBIF 0 RB Port Change Interrupt Flag bit BANK0:PIR1 0x000C PIR1 REGISTER BANK0:PIR1.LVDIF 7 Low Voltage Detect Interrupt Flag bit BANK0:PIR1.ADIF 6 A/D Converter Interrupt Flag bit BANK0:PIR1.C2IF 5 Comparator C2 Interrupt Flag bit BANK0:PIR1.C1IF 4 Comparator C1 Interrupt Flag bit BANK0:PIR1.TMR1IF 0 TMR1 Overflow Interrupt Flag bit BANK0:RESERVED000D 0x000D RESERVED BANK0:TMR1L 0x000E Holding register for the Least Significant Byte of the 16-bit TMR1 register BANK0:TMR1H 0x000F Holding register for the Most Significant Byte of the 16-bit TMR1 register BANK0:T1CON 0x0010 TIMER1 CONTROL REGISTER BANK0:T1CON.TMR1GE 6 Timer1 Gate Enable bit BANK0:T1CON.T1CKPS1 5 Timer1 Input Clock Prescale Select bit 1 BANK0:T1CON.T1CKPS0 4 Timer1 Input Clock Prescale Select bit 0 BANK0:T1CON.T1OSCEN 3 Timer1 Oscillator Enable Control bit BANK0:T1CON.T1SYNC 2 Timer1 External Clock Input Synchronization Control bit BANK0:T1CON.TMR1CS 1 Timer1 Clock Source Select bit BANK0:T1CON.TMR1ON 0 Timer1 On bit BANK0:RESERVED0011 0x0011 RESERVED BANK0:RESERVED0012 0x0012 RESERVED BANK0:RESERVED0013 0x0013 RESERVED BANK0:RESERVED0014 0x0014 RESERVED BANK0:RESERVED0015 0x0015 RESERVED BANK0:RESERVED0016 0x0016 RESERVED BANK0:RESERVED0017 0x0017 RESERVED BANK0:RESERVED0018 0x0018 RESERVED BANK0:RESERVED0019 0x0019 RESERVED BANK0:RESERVED001A 0x001A RESERVED BANK0:RESERVED001B 0x001B RESERVED BANK0:RESERVED001C 0x001C RESERVED BANK0:RESERVED001D 0x001D RESERVED BANK0:ADRES 0x001E ADC Result Register BANK0:ADCON0 0x001F ADCON0 REGISTER BANK0:ADCON0.ADCS1 7 A/D Conversion Clock Select bit 1 BANK0:ADCON0.ADCS0 6 A/D Conversion Clock Select bit 0 BANK0:ADCON0.CHS2 5 Analog Channel Select bit 2 BANK0:ADCON0.CHS1 4 Analog Channel Select bit 1 BANK0:ADCON0.CHS0 3 Analog Channel Select bit 0 BANK0:ADCON0.GO_DONE 2 A/D Conversion Status bit BANK0:ADCON0.CHS3 1 Analog Channel Select bit 3 BANK0:ADCON0.ADON 0 A/D On bit ; BANK1 (0x0080:0x0100) BANK1:INDF 0x0080 INDF (not a physical register) BANK1:OPTION 0x0081 OPTION REGISTER BANK1:OPTION.RBPU 7 PORTB Pull-up Enable bit BANK1:OPTION.INTEDG 6 Interrupt Edge Select bit BANK1:OPTION.T0CS 5 TMR0 Clock Source Select bit BANK1:OPTION.T0SE 4 TMR0 Source Edge Select bit BANK1:OPTION.PSA 3 Prescaler Assignment bit BANK1:OPTION.PS2 2 Prescaler Rate Select bit 2 BANK1:OPTION.PS1 1 Prescaler Rate Select bit 1 BANK1:OPTION.PS0 0 Prescaler Rate Select bit 0 BANK1:PCL 0x0082 Program Counter's (PC) Least Significant Byte BANK1:STATUS 0x0083 STATUS REGISTER BANK1:STATUS.IRP 7 Register Bank Select bit BANK1:STATUS.RP1 6 Register Bank Select bit 1 BANK1:STATUS.RP0 5 Register Bank Select bit 0 BANK1:STATUS.TO 4 Time-out bit BANK1:STATUS.PD 3 Power-down bit BANK1:STATUS.Z 2 Zero bit BANK1:STATUS.DC 1 Digit carry/borrow bit BANK1:STATUS.C 0 Carry/borrow bit BANK1:FSR 0x0084 Indirect data memory address pointer BANK1:TRISA 0x0085 PORTA Data Direction Register BANK1:TRISA.TRISA7 7 PORTA Data Direction Register bit 7 BANK1:TRISA.TRISA6 6 PORTA Data Direction Register bit 6 BANK1:TRISA.TRISA5 5 PORTA Data Direction Register bit 5 BANK1:TRISA.TRISA4 4 PORTA Data Direction Register bit 4 BANK1:TRISA.TRISA3 3 PORTA Data Direction Register bit 3 BANK1:TRISA.TRISA2 2 PORTA Data Direction Register bit 2 BANK1:TRISA.TRISA1 1 PORTA Data Direction Register bit 1 BANK1:TRISA.TRISA0 0 PORTA Data Direction Register bit 0 BANK1:TRISB 0x0086 PORTB Data Direction Register BANK1:TRISB.TRISB7 7 PORTB Data Direction Register bit 7 BANK1:TRISB.TRISB6 6 PORTB Data Direction Register bit 6 BANK1:TRISB.TRISB5 5 PORTB Data Direction Register bit 5 BANK1:TRISB.TRISB4 4 PORTB Data Direction Register bit 4 BANK1:TRISB.TRISB3 3 PORTB Data Direction Register bit 3 BANK1:TRISB.TRISB2 2 PORTB Data Direction Register bit 2 BANK1:TRISB.TRISB1 1 PORTB Data Direction Register bit 1 BANK1:TRISB.TRISB0 0 PORTB Data Direction Register bit 0 BANK1:RESERVED0087 0x0087 RESERVED BANK1:RESERVED0088 0x0088 RESERVED BANK1:RESERVED0089 0x0089 RESERVED BANK1:PCLATH 0x008A Write Buffer for the upper 5 bits of the Program Counter BANK1:INTCON 0x008B INTCON REGISTER BANK1:INTCON.GIE 7 Global Interrupt Enable bit BANK1:INTCON.PEIE 6 Peripheral Interrupt Enable bit BANK1:INTCON.T0IE 5 TMR0 Overflow Interrupt Enable bit BANK1:INTCON.INTE 4 RB0/INT External Interrupt Enable bit BANK1:INTCON.RBIE 3 RB Port Change Interrupt Enable bit BANK1:INTCON.T0IF 2 TMR0 Overflow Interrupt Flag bit BANK1:INTCON.INTF 1 RB0/INT External Interrupt Flag bit BANK1:INTCON.RBIF 0 RB Port Change Interrupt Flag bit BANK1:PIE1 0x008C PIE1 REGISTER BANK1:PIE1.LVDIE 7 Low Voltage Detect Interrupt Enable bit BANK1:PIE1.ADIE 6 A/D Converter Interrupt Enable bit BANK1:PIE1.C2IE 5 Comparator C2 Interrupt Enable bit BANK1:PIE1.C1IE 4 Comparator C1 Interrupt Enable bit BANK1:PIE1.TMR1IE 0 TMR1 Overflow Interrupt Enable bit BANK1:RESERVED008D 0x008D RESERVED BANK1:PCON 0x008E PCON REGISTER BANK1:PCON.WDTON 4 WDT Software Enable bit BANK1:PCON.OSCF 3 Oscillator Speed INTRC Mode bit BANK1:PCON.POR 1 Power-on Reset Status bit BANK1:PCON.BOR 0 Brown-out Reset Status bit BANK1:RESERVED008F 0x008F RESERVED BANK1:RESERVED0090 0x0090 RESERVED BANK1:RESERVED0091 0x0091 RESERVED BANK1:RESERVED0092 0x0092 RESERVED BANK1:RESERVED0093 0x0093 RESERVED BANK1:RESERVED0094 0x0094 RESERVED BANK1:WPUB 0x0095 PORTB Weak Pull-up Control BANK1:IOCB 0x0096 PORTB Interrupt-on-Change Control BANK1:RESERVED0097 0x0097 RESERVED BANK1:RESERVED0098 0x0098 RESERVED BANK1:RESERVED0099 0x0099 RESERVED BANK1:RESERVED009A 0x009A RESERVED BANK1:REFCON 0x009B VOLTAGE REFERENCE CONTROL REGISTER BANK1:REFCON.VREN 3 Voltage Reference Enable bit BANK1:REFCON.VROE 2 Voltage Reference Output Enable bit BANK1:LVDCON 0x009C PROGRAMMABLE LOW VOLTAGE DETECT REGISTER BANK1:LVDCON.BGST 5 Internal Reference Voltage Stable Flag bit BANK1:LVDCON.LVDEN 4 Low Voltage Detect Power Enable bit BANK1:LVDCON.LV3 3 Low Voltage Detection Limit bit 3 BANK1:LVDCON.LV2 2 Low Voltage Detection Limit bit 2 BANK1:LVDCON.LV1 1 Low Voltage Detection Limit bit 1 BANK1:LVDCON.LV0 0 Low Voltage Detection Limit bit 0 BANK1:ANSEL 0x009D Analog Channel Select BANK1:RESERVED009E 0x009E RESERVED BANK1:ADCON1 0x009F ADCON1 REGISTER BANK1:ADCON1.VCFG1 5 Voltage reference configuration bit 1 BANK1:ADCON1.VCFG0 4 Voltage reference configuration bit 0 ; BANK2 (0x0100:0x0180) BANK2:INDF 0x0100 INDF (not a physical register) BANK2:TMR0 0x0101 Timer0 module's register BANK2:PCL 0x0102 Program Counter's (PC) Least Significant Byte BANK2:STATUS 0x0103 STATUS REGISTER BANK2:STATUS.IRP 7 Register Bank Select bit BANK2:STATUS.RP1 6 Register Bank Select bit 1 BANK2:STATUS.RP0 5 Register Bank Select bit 0 BANK2:STATUS.TO 4 Time-out bit BANK2:STATUS.PD 3 Power-down bit BANK2:STATUS.Z 2 Zero bit BANK2:STATUS.DC 1 Digit carry/borrow bit BANK2:STATUS.C 0 Carry/borrow bit BANK2:FSR 0x0104 Indirect data memory address pointer BANK2:RESERVED0105 0x0105 RESERVED BANK2:PORTB 0x0106 PORTB REGISTER BANK2:PORTB.RB7 7 PORTB bit 7 BANK2:PORTB.RB6 6 PORTB bit 6 BANK2:PORTB.RB5 5 PORTB bit 5 BANK2:PORTB.RB4 4 PORTB bit 4 BANK2:PORTB.RB3 3 PORTB bit 3 BANK2:PORTB.RB2 2 PORTB bit 2 BANK2:PORTB.RB1 1 PORTB bit 1 BANK2:PORTB.RB0 0 PORTB bit 0 BANK2:RESERVED0107 0x0107 RESERVED BANK2:RESERVED0108 0x0108 RESERVED BANK2:RESERVED0109 0x0109 RESERVED BANK2:PCLATH 0x010A Write Buffer for the upper 5 bits of the Program Counter BANK2:INTCON 0x010B INTCON REGISTER BANK2:INTCON.GIE 7 Global Interrupt Enable bit BANK2:INTCON.PEIE 6 Peripheral Interrupt Enable bit BANK2:INTCON.T0IE 5 TMR0 Overflow Interrupt Enable bit BANK2:INTCON.INTE 4 RB0/INT External Interrupt Enable bit BANK2:INTCON.RBIE 3 RB Port Change Interrupt Enable bit BANK2:INTCON.T0IF 2 TMR0 Overflow Interrupt Flag bit BANK2:INTCON.INTF 1 RB0/INT External Interrupt Flag bit BANK2:INTCON.RBIF 0 RB Port Change Interrupt Flag bit BANK2:PMDATL 0x010C PROGRAM MEMORY DATA LOW BANK2:PMDATL.PMD7 7 Program Memory Data bit 7 BANK2:PMDATL.PMD6 6 Program Memory Data bit 6 BANK2:PMDATL.PMD5 5 Program Memory Data bit 5 BANK2:PMDATL.PMD4 4 Program Memory Data bit 4 BANK2:PMDATL.PMD3 3 Program Memory Data bit 3 BANK2:PMDATL.PMD2 2 Program Memory Data bit 2 BANK2:PMDATL.PMD1 1 Program Memory Data bit 1 BANK2:PMDATL.PMD0 0 Program Memory Data bit 0 BANK2:PMADRL 0x010D PROGRAM MEMORY ADDRESS LOW BANK2:PMADRL.PMA7 7 PMR Address bit 7 BANK2:PMADRL.PMA6 6 PMR Address bit 6 BANK2:PMADRL.PMA5 5 PMR Address bit 5 BANK2:PMADRL.PMA4 4 PMR Address bit 4 BANK2:PMADRL.PMA3 3 PMR Address bit 3 BANK2:PMADRL.PMA2 2 PMR Address bit 2 BANK2:PMADRL.PMA1 1 PMR Address bit 1 BANK2:PMADRL.PMA0 0 PMR Address bit 0 BANK2:PMDATH 0x010E PROGRAM MEMORY DATA HIGH BANK2:PMDATH.PMD13 5 Program Memory Data bit 13 BANK2:PMDATH.PMD12 4 Program Memory Data bit 12 BANK2:PMDATH.PMD11 3 Program Memory Data bit 11 BANK2:PMDATH.PMD10 2 Program Memory Data bit 10 BANK2:PMDATH.PMD9 1 Program Memory Data bit 9 BANK2:PMDATH.PMD8 0 Program Memory Data bit 8 BANK2:PMADRH 0x010F PROGRAM MEMORY ADDRESS HIGH BANK2:PMADRH.PMA10 2 PMR Address bit 10 BANK2:PMADRH.PMA9 1 PMR Address bit 9 BANK2:PMADRH.PMA8 0 PMR Address bit 8 BANK2:CALCON 0x0110 CALIBRATION CONTROL REGISTER BANK2:CALCON.CAL 7 Start and Status bit BANK2:CALCON.CALERR 6 Calibration Error Indicator bit BANK2:CALCON.CALREF 5 Calibration Voltage Select bit BANK2:PSMCCON0 0x0111 PSMC CONTROL REGISTER0 BANK2:PSMCCON0.SMCCL1 7 Clock Frequency Select bit 1 BANK2:PSMCCON0.SMCCL0 6 Clock Frequency Select bit 0 BANK2:PSMCCON0.MINDC1 5 Minimum Duty Cycle Select bit 1 for PWM Mode BANK2:PSMCCON0.MINDC0 4 Minimum Duty Cycle Select bit 0 for PWM Mode BANK2:PSMCCON0.MAXDC1 3 Maximum Duty Cycle Select bit 1 for PWM Mode BANK2:PSMCCON0.MAXDC0 2 Maximum Duty Cycle Select bit 0 for PWM Mode BANK2:PSMCCON0.DC1 1 Duty Cycle Select bit 1 for PSM Mode BANK2:PSMCCON0.DC0 0 Duty Cycle Select bit 0 for PSM Mode BANK2:PSMCCON1 0x0112 PSMC CONTROL REGISTER1 BANK2:PSMCCON1.SMCON 7 PSMC Module Enable bit BANK2:PSMCCON1.S1APOL 6 PSMC1A Output Polarity Control bit BANK2:PSMCCON1.S1BPOL 5 PSMC1B Output Polarity Control bit BANK2:PSMCCON1.SCEN 3 Slope Compensation Output Enable bit BANK2:PSMCCON1.SMCOM 2 PSMC Output Mode bit BANK2:PSMCCON1.PWM_PSM 1 PSMC Modulation Mode Select bit BANK2:PSMCCON1.SMCCS 0 PSMC Comparator Select bit BANK2:RESERVED0113 0x0113 RESERVED BANK2:RESERVED0114 0x0114 RESERVED BANK2:RESERVED0115 0x0115 RESERVED BANK2:RESERVED0116 0x0116 RESERVED BANK2:RESERVED0117 0x0117 RESERVED BANK2:RESERVED0118 0x0118 RESERVED BANK2:CM1CON0 0x0119 COMPARATOR C1 CONTROL REGISTER0 BANK2:CM1CON0.C1ON 7 Comparator C1 Enable bit BANK2:CM1CON0.C1OUT 6 Comparator C1 Output bit BANK2:CM1CON0.C1OE 5 Comparator C1 Output Enable bit BANK2:CM1CON0.C1POL 4 Comparator C1 Output Polarity Select bit BANK2:CM1CON0.C1SP 3 Comparator C1 Speed Select bit BANK2:CM1CON0.C1R 2 Comparator C1 Reference Select bits (non-inverting input) BANK2:CM1CON0.C1CH1 1 Comparator C1 Channel Select bit 1 BANK2:CM1CON0.C1CH0 0 Comparator C1 Channel Select bit 0 BANK2:CM2CON0 0x011A COMPARATOR C2 CONTROL REGISTER0 BANK2:CM2CON0.C2ON 7 Comparator C2 Enable bit BANK2:CM2CON0.C2OUT 6 Comparator C2 Output bit BANK2:CM2CON0.C2OE 5 Comparator C2 Output Enable bit BANK2:CM2CON0.C2POL 4 Comparator C2 Output Polarity Select bit BANK2:CM2CON0.C2SP 3 Comparator C2 Speed Select bit BANK2:CM2CON0.C2R 2 Comparator C2 Reference Select bits (non-inverting input) BANK2:CM2CON0.C2CH1 1 Comparator C2 Channel Select bit 1 BANK2:CM2CON0.C2CH0 0 Comparator C2 Channel Select bit 0 BANK2:CM2CON1 0x011B COMPARATOR C2 CONTROL REGISTER1 BANK2:CM2CON1.MC1OUT 7 Mirror Copy of C1OUT (CM1CON0<6>) BANK2:CM2CON1.MC2OUT 6 Copy of C2OUT (CM2CON0<6>) BANK2:CM2CON1.C2SYNC 0 C2 Output Synchronous Mode bit BANK2:OPACON 0x011C OPAMP CONTROL REGISTER BANK2:OPACON.OPAON 7 OPAMP Enable bit BANK2:OPACON.CMPEN 6 Comparator Mode Enable bit BANK2:OPACON.GBWP 0 Gain Bandwidth Product Select bits BANK2:RESERVED011D 0x011D RESERVED BANK2:DAC 0x011E DIGITAL-TO-ANALOG CONVERTER REGISTER BANK2:DAC.DA7 7 Digital-to-Analog Converter Digital Input bit 7 BANK2:DAC.DA6 6 Digital-to-Analog Converter Digital Input bit 6 BANK2:DAC.DA5 5 Digital-to-Analog Converter Digital Input bit 5 BANK2:DAC.DA4 4 Digital-to-Analog Converter Digital Input bit 4 BANK2:DAC.DA3 3 Digital-to-Analog Converter Digital Input bit 3 BANK2:DAC.DA2 2 Digital-to-Analog Converter Digital Input bit 2 BANK2:DAC.DA1 1 Digital-to-Analog Converter Digital Input bit 1 BANK2:DAC.DA0 0 Digital-to-Analog Converter Digital Input bit 0 BANK2:DACON0 0x011F DIGITAL-TO-ANALOG CONVERTER CONTROL REGISTER0 BANK2:DACON0.DAON 7 Digital-to-Analog Converter Enable bit BANK2:DACON0.DAOE 6 Digital-to-Analog Converter Output Enable bit BANK2:DACON0.DARS1 1 Digital-to-Analog Converter Voltage Reference Select bit 1 BANK2:DACON0.DARS0 0 Digital-to-Analog Converter Voltage Reference Select bit 0 ; BANK3 (0x0180:0x0200) BANK3:INDF 0x0180 INDF (not a physical register) BANK3:OPTION 0x0181 OPTION REGISTER BANK3:OPTION.RBPU 7 PORTB Pull-up Enable bit BANK3:OPTION.INTEDG 6 Interrupt Edge Select bit BANK3:OPTION.T0CS 5 TMR0 Clock Source Select bit BANK3:OPTION.T0SE 4 TMR0 Source Edge Select bit BANK3:OPTION.PSA 3 Prescaler Assignment bit BANK3:OPTION.PS2 2 Prescaler Rate Select bit 2 BANK3:OPTION.PS1 1 Prescaler Rate Select bit 1 BANK3:OPTION.PS0 0 Prescaler Rate Select bit 0 BANK3:PCL 0x0182 Program Counter's (PC) Least Significant Byte BANK3:STATUS 0x0183 STATUS REGISTER BANK3:STATUS.IRP 7 Register Bank Select bit BANK3:STATUS.RP1 6 Register Bank Select bit 1 BANK3:STATUS.RP0 5 Register Bank Select bit 0 BANK3:STATUS.TO 4 Time-out bit BANK3:STATUS.PD 3 Power-down bit BANK3:STATUS.Z 2 Zero bit BANK3:STATUS.DC 1 Digit carry/borrow bit BANK3:STATUS.C 0 Carry/borrow bit BANK3:FSR 0x0184 Indirect data memory address pointer BANK3:RESERVED 0x0185 RESERVED BANK3:TRISB 0x0186 PORTB Data Direction Register BANK3:TRISB.TRISB7 7 PORTB Data Direction Register bit 7 BANK3:TRISB.TRISB6 6 PORTB Data Direction Register bit 6 BANK3:TRISB.TRISB5 5 PORTB Data Direction Register bit 5 BANK3:TRISB.TRISB4 4 PORTB Data Direction Register bit 4 BANK3:TRISB.TRISB3 3 PORTB Data Direction Register bit 3 BANK3:TRISB.TRISB2 2 PORTB Data Direction Register bit 2 BANK3:TRISB.TRISB1 1 PORTB Data Direction Register bit 1 BANK3:TRISB.TRISB0 0 PORTB Data Direction Register bit 0 BANK3:RESERVED0187 0x0187 RESERVED BANK3:RESERVED0188 0x0188 RESERVED BANK3:RESERVED0189 0x0189 RESERVED BANK3:PCLATH 0x018A Write Buffer for the upper 5 bits of the Program Counter BANK3:INTCON 0x018B INTCON REGISTER BANK3:INTCON.GIE 7 Global Interrupt Enable bit BANK3:INTCON.PEIE 6 Peripheral Interrupt Enable bit BANK3:INTCON.T0IE 5 TMR0 Overflow Interrupt Enable bit BANK3:INTCON.INTE 4 RB0/INT External Interrupt Enable bit BANK3:INTCON.RBIE 3 RB Port Change Interrupt Enable bit BANK3:INTCON.T0IF 2 TMR0 Overflow Interrupt Flag bit BANK3:INTCON.INTF 1 RB0/INT External Interrupt Flag bit BANK3:INTCON.RBIF 0 RB Port Change Interrupt Flag bit BANK3:PMCON1 0x018C PROGRAM MEMORY READ CONTROL REGISTER 1 BANK3:PMCON1.RD 0 Read Control bit BANK3:RESERVED018D 0x018D RESERVED BANK3:RESERVED018E 0x018E RESERVED BANK3:RESERVED018F 0x018F RESERVED BANK3:RESERVED0190 0x0190 RESERVED BANK3:RESERVED0191 0x0191 RESERVED BANK3:RESERVED0192 0x0192 RESERVED BANK3:RESERVED0193 0x0193 RESERVED BANK3:RESERVED0194 0x0194 RESERVED BANK3:RESERVED0195 0x0195 RESERVED BANK3:RESERVED0196 0x0196 RESERVED BANK3:RESERVED0197 0x0197 RESERVED BANK3:RESERVED0198 0x0198 RESERVED BANK3:RESERVED0199 0x0199 RESERVED BANK3:RESERVED019A 0x019A RESERVED BANK3:RESERVED019B 0x019B RESERVED BANK3:RESERVED019C 0x019C RESERVED BANK3:RESERVED019D 0x019D RESERVED BANK3:RESERVED019E 0x019E RESERVED BANK3:RESERVED019F 0x019F RESERVED .16C73 ; http://www.microchip.com/download/lit/pline/picmicro/families/16c7x/30390e.pdf ; PIC16C7X.pdf ; MEMORY MAP ; BANK_0 area DATA FSR_ 0x0000:0x0020 area DATA Gen_Purp 0x0020:0x0080 General Purpose Register area DATA MEM_Program0 0x0080:0x0800 On-chip Program Memory (Page 0) area DATA MEM_Program1 0x0800:0x1000 On-chip Program Memory (Page 1) ; BANK_1 ; area DATA FSR_ 0x0080:0x00A0 ; area DATA Gen_Purp 0x00A0:0x0100 General Purpose Register ; area DATA MEM_Program0 0x0100:0x0800 On-chip Program Memory (Page 0) ; area DATA MEM_Program1 0x0800:0x1000 On-chip Program Memory (Page 1) ; Interrupt and reset vector assignments interrupt RESET 0x0000 RESET ; INPUT/OUTPUT PORTS ; BANK0 (0x0000:0x0080) BANK0:INDF 0x0000 INDF (not a physical register) BANK0:TMR0 0x0001 Timer0 module's register BANK0:PCL 0x0002 Program Counter's (PC) Least Significant Byte BANK0:STATUS 0x0003 STATUS REGISTER BANK0:STATUS.RP0 5 Register Bank Select bit 0 BANK0:STATUS.TO 4 Time-out bit BANK0:STATUS.PD 3 Power-down bit BANK0:STATUS.Z 2 Zero bit BANK0:STATUS.DC 1 Digit carry/borrow bit BANK0:STATUS.C 0 Carry/borrow bit BANK0:FSR 0x0004 Indirect data memory address pointer BANK0:PORTA 0x0005 PORTA REGISTER BANK0:PORTA.RA5 5 PORTA bit 5 BANK0:PORTA.RA4 4 PORTA bit 4 BANK0:PORTA.RA3 3 PORTA bit 3 BANK0:PORTA.RA2 2 PORTA bit 2 BANK0:PORTA.RA1 1 PORTA bit 1 BANK0:PORTA.RA0 0 PORTA bit 0 BANK0:PORTB 0x0006 PORTB REGISTER BANK0:PORTB.RB7 7 PORTB bit 7 BANK0:PORTB.RB6 6 PORTB bit 6 BANK0:PORTB.RB5 5 PORTB bit 5 BANK0:PORTB.RB4 4 PORTB bit 4 BANK0:PORTB.RB3 3 PORTB bit 3 BANK0:PORTB.RB2 2 PORTB bit 2 BANK0:PORTB.RB1 1 PORTB bit 1 BANK0:PORTB.RB0 0 PORTB bit 0 BANK0:PORTC 0x0007 PORTC REGISTER BANK0:PORTC.RC7 7 PORTC bit 7 BANK0:PORTC.RC6 6 PORTC bit 6 BANK0:PORTC.RC5 5 PORTC bit 5 BANK0:PORTC.RC4 4 PORTC bit 4 BANK0:PORTC.RC3 3 PORTC bit 3 BANK0:PORTC.RC2 2 PORTC bit 2 BANK0:PORTC.RC1 1 PORTC bit 1 BANK0:PORTC.RC0 0 PORTC bit 0 BANK0:RESERVED0008 0x0008 RESERVED BANK0:RESERVED0009 0x0009 RESERVED BANK0:PCLATH 0x000A Write Buffer for the upper 5 bits of the Program Counter BANK0:INTCON 0x000B INTCON REGISTER BANK0:INTCON.GIE 7 Global Interrupt Enable bit BANK0:INTCON.PEIE 6 Peripheral Interrupt Enable bit BANK0:INTCON.T0IE 5 TMR0 Overflow Interrupt Enable bit BANK0:INTCON.INTE 4 RB0/INT External Interrupt Enable bit BANK0:INTCON.RBIE 3 RB Port Change Interrupt Enable bit BANK0:INTCON.T0IF 2 TMR0 Overflow Interrupt Flag bit BANK0:INTCON.INTF 1 RB0/INT External Interrupt Flag bit BANK0:INTCON.RBIF 0 RB Port Change Interrupt Flag bit BANK0:PIR1 0x000C PIR1 REGISTER BANK0:PIR1.ADIF 6 A/D Converter Interrupt Flag bit BANK0:PIR1.RCIF 5 USART Receive Interrupt Flag bit BANK0:PIR1.TXIF 4 USART Transmit Interrupt Flag bit BANK0:PIR1.SSPIF 3 Synchronous Serial Port Interrupt Flag bit BANK0:PIR1.CCP1IF 2 CCP1 Interrupt Flag bit BANK0:PIR1.TMR2IF 1 TMR2 to PR2 Match Interrupt Flag bit BANK0:PIR1.TMR1IF 0 TMR1 Overflow Interrupt Flag bit BANK0:PIR2 0x000D PIR2 REGISTER BANK0:PIR2.CCP2IF 0 CCP2 Interrupt Flag bit BANK0:TMR1L 0x000E Holding register for the Least Significant Byte of the 16-bit TMR1 register BANK0:TMR1H 0x000F Holding register for the Most Significant Byte of the 16-bit TMR1 register BANK0:T1CON 0x0010 TIMER1 CONTROL REGISTER BANK0:T1CON.T1CKPS1 5 Timer1 Input Clock Prescale Select bit 1 BANK0:T1CON.T1CKPS0 4 Timer1 Input Clock Prescale Select bit 0 BANK0:T1CON.T1OSCEN 3 Timer1 Oscillator Enable Control bit BANK0:T1CON.T1SYNC 2 Timer1 External Clock Input Synchronization Control bit BANK0:T1CON.TMR1CS 1 Timer1 Clock Source Select bit BANK0:T1CON.TMR1ON 0 Timer1 On bit BANK0:TMR2 0x0011 Timer2 module's register BANK0:T2CON 0x0012 TIMER2 CONTROL REGISTER BANK0:T2CON.TOUTPS3 6 Timer2 Output Postscale Select bit 3 BANK0:T2CON.TOUTPS2 5 Timer2 Output Postscale Select bit 2 BANK0:T2CON.TOUTPS1 4 Timer2 Output Postscale Select bit 1 BANK0:T2CON.TOUTPS0 3 Timer2 Output Postscale Select bit 0 BANK0:T2CON.TMR2ON 2 Timer2 On bit BANK0:T2CON.T2CKPS1 1 Timer2 Clock Prescale Select bit 1 BANK0:T2CON.T2CKPS0 0 Timer2 Clock Prescale Select bit 0 BANK0:SSPBUF 0x0013 Synchronous Serial Port Receive Buffer/Transmit Register BANK0:SSPCON 0x0014 SYNC SERIAL PORT CONTROL REGISTER BANK0:SSPCON.WCOL 7 Write Collision Detect bit BANK0:SSPCON.SSPOV 6 Receive Overflow Indicator bit BANK0:SSPCON.SSPEN 5 Synchronous Serial Port Enable bit BANK0:SSPCON.CKP 4 Clock Polarity Select bit BANK0:SSPCON.SSPM3 3 Synchronous Serial Port Mode Select bit 3 BANK0:SSPCON.SSPM2 2 Synchronous Serial Port Mode Select bit 2 BANK0:SSPCON.SSPM1 1 Synchronous Serial Port Mode Select bit 1 BANK0:SSPCON.SSPM0 0 Synchronous Serial Port Mode Select bit 0 BANK0:CCPR1L 0x0015 Capture/Compare/PWM Register1 (LSB) BANK0:CCPR1H 0x0016 Capture/Compare/PWM Register1 (MSB) BANK0:CCP1CON 0x0017 CCP1CON REGISTER BANK0:CCP1CON.CCP1X 5 PWM Least Significant bit BANK0:CCP1CON.CCP1Y 4 PWM Least Significant bit BANK0:CCP1CON.CCP1M3 3 CCP1 Mode Select bit 3 BANK0:CCP1CON.CCP1M2 2 CCP1 Mode Select bit 2 BANK0:CCP1CON.CCP1M1 1 CCP1 Mode Select bit 1 BANK0:CCP1CON.CCP1M0 0 CCP1 Mode Select bit 0 BANK0:RCSTA 0x0018 RECEIVE STATUS AND CONTROL REGISTER BANK0:RCSTA.SPEN 7 Serial Port Enable bit BANK0:RCSTA.RX9 6 9-bit Receive Enable bit BANK0:RCSTA.SREN 5 Single Receive Enable bit BANK0:RCSTA.CREN 4 Continuous Receive Enable bit BANK0:RCSTA.FERR 2 Framing Error bit BANK0:RCSTA.OERR 1 Overrun Error bit BANK0:RCSTA.RX9D 0 9th bit of received data BANK0:TXREG 0x0019 USART Transmit Data Register BANK0:RCREG 0x001A USART Receive Data Register BANK0:CCPR2L 0x001B Capture/Compare/PWM Register2 (LSB) BANK0:CCPR2H 0x001C Capture/Compare/PWM Register2 (MSB) BANK0:CCP2CON 0x001D CCP2CON REGISTER BANK0:CCP2CON.CCP2X 5 PWM Least Significant bit BANK0:CCP2CON.CCP2Y 4 PWM Least Significant bit BANK0:CCP2CON.CCP2M3 3 CCP2 Mode Select bit 3 BANK0:CCP2CON.CCP2M2 2 CCP2 Mode Select bit 2 BANK0:CCP2CON.CCP2M1 1 CCP2 Mode Select bit 1 BANK0:CCP2CON.CCP2M0 0 CCP2 Mode Select bit 0 BANK0:ADRES 0x001E A/D Result Register BANK0:ADCON0 0x001F ADCON0 REGISTER BANK0:ADCON0.ADCS1 7 A/D Conversion Clock Select bit 1 BANK0:ADCON0.ADCS0 6 A/D Conversion Clock Select bit 0 BANK0:ADCON0.CHS2 5 Analog Channel Select bit 2 BANK0:ADCON0.CHS1 4 Analog Channel Select bit 1 BANK0:ADCON0.CHS0 3 Analog Channel Select bit 0 BANK0:ADCON0.GO_DONE 2 A/D Conversion Status bit BANK0:ADCON0.ADON 0 A/D On bit ; BANK1 (0x0080:0x0100) BANK1:INDF 0x0080 INDF (not a physical register) BANK1:OPTION 0x0081 OPTION REGISTER BANK1:OPTION.RBPU 7 PORTB Pull-up Enable bit BANK1:OPTION.INTEDG 6 Interrupt Edge Select bit BANK1:OPTION.T0CS 5 TMR0 Clock Source Select bit BANK1:OPTION.T0SE 4 TMR0 Source Edge Select bit BANK1:OPTION.PSA 3 Prescaler Assignment bit BANK1:OPTION.PS2 2 Prescaler Rate Select bit 2 BANK1:OPTION.PS1 1 Prescaler Rate Select bit 1 BANK1:OPTION.PS0 0 Prescaler Rate Select bit 0 BANK1:PCL 0x0082 Program Counter's (PC) Least Significant Byte BANK1:STATUS 0x0083 STATUS REGISTER BANK1:STATUS.RP0 5 Register Bank Select bit 0 BANK1:STATUS.TO 4 Time-out bit BANK1:STATUS.PD 3 Power-down bit BANK1:STATUS.Z 2 Zero bit BANK1:STATUS.DC 1 Digit carry/borrow bit BANK1:STATUS.C 0 Carry/borrow bit BANK1:FSR 0x0084 Indirect data memory address pointer BANK1:TRISA 0x0085 PORTA Data Direction Register BANK1:TRISA.TRISA5 5 PORTA Data Direction Register bit 5 BANK1:TRISA.TRISA4 4 PORTA Data Direction Register bit 4 BANK1:TRISA.TRISA3 3 PORTA Data Direction Register bit 3 BANK1:TRISA.TRISA2 2 PORTA Data Direction Register bit 2 BANK1:TRISA.TRISA1 1 PORTA Data Direction Register bit 1 BANK1:TRISA.TRISA0 0 PORTA Data Direction Register bit 0 BANK1:TRISB 0x0086 PORTB Data Direction Register BANK1:TRISB.TRISB7 7 PORTB Data Direction Register bit 7 BANK1:TRISB.TRISB6 6 PORTB Data Direction Register bit 6 BANK1:TRISB.TRISB5 5 PORTB Data Direction Register bit 5 BANK1:TRISB.TRISB4 4 PORTB Data Direction Register bit 4 BANK1:TRISB.TRISB3 3 PORTB Data Direction Register bit 3 BANK1:TRISB.TRISB2 2 PORTB Data Direction Register bit 2 BANK1:TRISB.TRISB1 1 PORTB Data Direction Register bit 1 BANK1:TRISB.TRISB0 0 PORTB Data Direction Register bit 0 BANK1:TRISC 0x0087 PORTC Data Direction Register BANK1:TRISC.TRISC7 7 PORTC Data Direction Register bit 7 BANK1:TRISC.TRISC6 6 PORTC Data Direction Register bit 6 BANK1:TRISC.TRISC5 5 PORTC Data Direction Register bit 5 BANK1:TRISC.TRISC4 4 PORTC Data Direction Register bit 4 BANK1:TRISC.TRISC3 3 PORTC Data Direction Register bit 3 BANK1:TRISC.TRISC2 2 PORTC Data Direction Register bit 2 BANK1:TRISC.TRISC1 1 PORTC Data Direction Register bit 1 BANK1:TRISC.TRISC0 0 PORTC Data Direction Register bit 0 BANK1:RESERVED0088 0x0088 RESERVED BANK1:RESERVED0089 0x0089 RESERVED BANK1:PCLATH 0x008A Write Buffer for the upper 5 bits of the Program Counter BANK1:INTCON 0x008B INTCON REGISTER BANK1:INTCON.GIE 7 Global Interrupt Enable bit BANK1:INTCON.PEIE 6 Peripheral Interrupt Enable bit BANK1:INTCON.T0IE 5 TMR0 Overflow Interrupt Enable bit BANK1:INTCON.INTE 4 RB0/INT External Interrupt Enable bit BANK1:INTCON.RBIE 3 RB Port Change Interrupt Enable bit BANK1:INTCON.T0IF 2 TMR0 Overflow Interrupt Flag bit BANK1:INTCON.INTF 1 RB0/INT External Interrupt Flag bit BANK1:INTCON.RBIF 0 RB Port Change Interrupt Flag bit BANK1:PIE1 0x008C PIE1 REGISTER BANK1:PIE1.ADIE 6 A/D Converter Interrupt Enable bit BANK1:PIE1.RCIE 5 USART Receive Interrupt Enable bit BANK1:PIE1.TXIE 4 USART Transmit Interrupt Enable bit BANK1:PIE1.SSPIE 3 Synchronous Serial Port Interrupt Enable bit BANK1:PIE1.CCP1IE 2 CCP1 Interrupt Enable bit BANK1:PIE1.TMR2IE 1 TMR2 to PR2 Match Interrupt Enable bit BANK1:PIE1.TMR1IE 0 TMR1 Overflow Interrupt Enable bit BANK1:PIE2 0x008D PIE2 REGISTER BANK1:PIE2.CCP2IE 0 CCP2 Interrupt Enable bit BANK1:PCON 0x008E PCON REGISTER BANK1:PCON.POR 1 Power-on Reset Status bit BANK1:RESERVED008F 0x008F RESERVED BANK1:RESERVED0090 0x0090 RESERVED BANK1:RESERVED0091 0x0091 RESERVED BANK1:PR2 0x0092 Timer2 Period Register BANK1:SSPADD 0x0093 Synchronous Serial Port (I2C mode) Address Register BANK1:SSPSTAT 0x0094 SYNC SERIAL PORT STATUS REGISTER BANK1:SSPSTAT.D_A 5 Data/Address bit (I2C mode only) BANK1:SSPSTAT.P 4 Stop bit (I2C mode only) BANK1:SSPSTAT.S 3 Start bit (I2C mode only) BANK1:SSPSTAT.R_W 2 Read/Write bit information (I2C mode only) BANK1:SSPSTAT.UA 1 Update Address (I2C mode only) BANK1:SSPSTAT.BF 0 Buffer Full Status bit BANK1:RESERVED0095 0x0095 RESERVED BANK1:RESERVED0096 0x0096 RESERVED BANK1:RESERVED0097 0x0097 RESERVED BANK1:TXSTA 0x0098 TRANSMIT STATUS AND CONTROL REGISTER BANK1:TXSTA.CSRC 7 Clock Source Select bit BANK1:TXSTA.TX9 6 9-bit Transmit Enable bit BANK1:TXSTA.TXEN 5 Transmit Enable bit BANK1:TXSTA.SYNC 4 USART Mode Select bit BANK1:TXSTA.BRGH 2 High Baud Rate Select bit BANK1:TXSTA.TRMT 1 Transmit Shift Register Status bit BANK1:TXSTA.TX9D 0 9th bit of transmit data. Can be parity bit BANK1:SPBRG 0x0099 Baud Rate Generator Register BANK1:RESERVED009A 0x009A RESERVED BANK1:RESERVED009B 0x009B RESERVED BANK1:RESERVED009C 0x009C RESERVED BANK1:RESERVED009D 0x009D RESERVED BANK1:RESERVED009E 0x009E RESERVED BANK1:ADCON1 0x009F ADCON1 REGISTER BANK1:ADCON1.PCFG2 2 A/D Port Configuration Control bit 2 BANK1:ADCON1.PCFG1 1 A/D Port Configuration Control bit 1 BANK1:ADCON1.PCFG0 0 A/D Port Configuration Control bit 0 .16C73A ; http://www.microchip.com/download/lit/pline/picmicro/families/16c7x/30390e.pdf ; PIC16C7X.pdf ; MEMORY MAP ; BANK_0 area DATA FSR_ 0x0000:0x0020 area DATA Gen_Purp 0x0020:0x0080 General Purpose Register area DATA MEM_Program0 0x0080:0x0800 On-chip Program Memory (Page 0) area DATA MEM_Program1 0x0800:0x1000 On-chip Program Memory (Page 1) ; BANK_1 ; area DATA FSR_ 0x0080:0x00A0 ; area DATA Gen_Purp 0x00A0:0x0100 General Purpose Register ; area DATA MEM_Program0 0x0100:0x0800 On-chip Program Memory (Page 0) ; area DATA MEM_Program1 0x0800:0x1000 On-chip Program Memory (Page 1) ; Interrupt and reset vector assignments interrupt RESET 0x0000 RESET ; INPUT/OUTPUT PORTS ; BANK0 (0x0000:0x0080) BANK0:INDF 0x0000 INDF (not a physical register) BANK0:TMR0 0x0001 Timer0 module's register BANK0:PCL 0x0002 Program Counter's (PC) Least Significant Byte BANK0:STATUS 0x0003 STATUS REGISTER BANK0:STATUS.RP0 5 Register Bank Select bit 0 BANK0:STATUS.TO 4 Time-out bit BANK0:STATUS.PD 3 Power-down bit BANK0:STATUS.Z 2 Zero bit BANK0:STATUS.DC 1 Digit carry/borrow bit BANK0:STATUS.C 0 Carry/borrow bit BANK0:FSR 0x0004 Indirect data memory address pointer BANK0:PORTA 0x0005 PORTA REGISTER BANK0:PORTA.RA5 5 PORTA bit 5 BANK0:PORTA.RA4 4 PORTA bit 4 BANK0:PORTA.RA3 3 PORTA bit 3 BANK0:PORTA.RA2 2 PORTA bit 2 BANK0:PORTA.RA1 1 PORTA bit 1 BANK0:PORTA.RA0 0 PORTA bit 0 BANK0:PORTB 0x0006 PORTB REGISTER BANK0:PORTB.RB7 7 PORTB bit 7 BANK0:PORTB.RB6 6 PORTB bit 6 BANK0:PORTB.RB5 5 PORTB bit 5 BANK0:PORTB.RB4 4 PORTB bit 4 BANK0:PORTB.RB3 3 PORTB bit 3 BANK0:PORTB.RB2 2 PORTB bit 2 BANK0:PORTB.RB1 1 PORTB bit 1 BANK0:PORTB.RB0 0 PORTB bit 0 BANK0:PORTC 0x0007 PORTC REGISTER BANK0:PORTC.RC7 7 PORTC bit 7 BANK0:PORTC.RC6 6 PORTC bit 6 BANK0:PORTC.RC5 5 PORTC bit 5 BANK0:PORTC.RC4 4 PORTC bit 4 BANK0:PORTC.RC3 3 PORTC bit 3 BANK0:PORTC.RC2 2 PORTC bit 2 BANK0:PORTC.RC1 1 PORTC bit 1 BANK0:PORTC.RC0 0 PORTC bit 0 BANK0:RESERVED0008 0x0008 RESERVED BANK0:RESERVED0009 0x0009 RESERVED BANK0:PCLATH 0x000A Write Buffer for the upper 5 bits of the Program Counter BANK0:INTCON 0x000B INTCON REGISTER BANK0:INTCON.GIE 7 Global Interrupt Enable bit BANK0:INTCON.PEIE 6 Peripheral Interrupt Enable bit BANK0:INTCON.T0IE 5 TMR0 Overflow Interrupt Enable bit BANK0:INTCON.INTE 4 RB0/INT External Interrupt Enable bit BANK0:INTCON.RBIE 3 RB Port Change Interrupt Enable bit BANK0:INTCON.T0IF 2 TMR0 Overflow Interrupt Flag bit BANK0:INTCON.INTF 1 RB0/INT External Interrupt Flag bit BANK0:INTCON.RBIF 0 RB Port Change Interrupt Flag bit BANK0:PIR1 0x000C PIR1 REGISTER BANK0:PIR1.ADIF 6 A/D Converter Interrupt Flag bit BANK0:PIR1.RCIF 5 USART Receive Interrupt Flag bit BANK0:PIR1.TXIF 4 USART Transmit Interrupt Flag bit BANK0:PIR1.SSPIF 3 Synchronous Serial Port Interrupt Flag bit BANK0:PIR1.CCP1IF 2 CCP1 Interrupt Flag bit BANK0:PIR1.TMR2IF 1 TMR2 to PR2 Match Interrupt Flag bit BANK0:PIR1.TMR1IF 0 TMR1 Overflow Interrupt Flag bit BANK0:PIR2 0x000D PIR2 REGISTER BANK0:PIR2.CCP2IF 0 CCP2 Interrupt Flag bit BANK0:TMR1L 0x000E Holding register for the Least Significant Byte of the 16-bit TMR1 register BANK0:TMR1H 0x000F Holding register for the Most Significant Byte of the 16-bit TMR1 register BANK0:T1CON 0x0010 TIMER1 CONTROL REGISTER BANK0:T1CON.T1CKPS1 5 Timer1 Input Clock Prescale Select bit 1 BANK0:T1CON.T1CKPS0 4 Timer1 Input Clock Prescale Select bit 0 BANK0:T1CON.T1OSCEN 3 Timer1 Oscillator Enable Control bit BANK0:T1CON.T1SYNC 2 Timer1 External Clock Input Synchronization Control bit BANK0:T1CON.TMR1CS 1 Timer1 Clock Source Select bit BANK0:T1CON.TMR1ON 0 Timer1 On bit BANK0:TMR2 0x0011 Timer2 module's register BANK0:T2CON 0x0012 TIMER2 CONTROL REGISTER BANK0:T2CON.TOUTPS3 6 Timer2 Output Postscale Select bit 3 BANK0:T2CON.TOUTPS2 5 Timer2 Output Postscale Select bit 2 BANK0:T2CON.TOUTPS1 4 Timer2 Output Postscale Select bit 1 BANK0:T2CON.TOUTPS0 3 Timer2 Output Postscale Select bit 0 BANK0:T2CON.TMR2ON 2 Timer2 On bit BANK0:T2CON.T2CKPS1 1 Timer2 Clock Prescale Select bit 1 BANK0:T2CON.T2CKPS0 0 Timer2 Clock Prescale Select bit 0 BANK0:SSPBUF 0x0013 Synchronous Serial Port Receive Buffer/Transmit Register BANK0:SSPCON 0x0014 SYNC SERIAL PORT CONTROL REGISTER BANK0:SSPCON.WCOL 7 Write Collision Detect bit BANK0:SSPCON.SSPOV 6 Receive Overflow Indicator bit BANK0:SSPCON.SSPEN 5 Synchronous Serial Port Enable bit BANK0:SSPCON.CKP 4 Clock Polarity Select bit BANK0:SSPCON.SSPM3 3 Synchronous Serial Port Mode Select bit 3 BANK0:SSPCON.SSPM2 2 Synchronous Serial Port Mode Select bit 2 BANK0:SSPCON.SSPM1 1 Synchronous Serial Port Mode Select bit 1 BANK0:SSPCON.SSPM0 0 Synchronous Serial Port Mode Select bit 0 BANK0:CCPR1L 0x0015 Capture/Compare/PWM Register1 (LSB) BANK0:CCPR1H 0x0016 Capture/Compare/PWM Register1 (MSB) BANK0:CCP1CON 0x0017 CCP1CON REGISTER BANK0:CCP1CON.CCP1X 5 PWM Least Significant bit BANK0:CCP1CON.CCP1Y 4 PWM Least Significant bit BANK0:CCP1CON.CCP1M3 3 CCP1 Mode Select bit 3 BANK0:CCP1CON.CCP1M2 2 CCP1 Mode Select bit 2 BANK0:CCP1CON.CCP1M1 1 CCP1 Mode Select bit 1 BANK0:CCP1CON.CCP1M0 0 CCP1 Mode Select bit 0 BANK0:RCSTA 0x0018 RECEIVE STATUS AND CONTROL REGISTER BANK0:RCSTA.SPEN 7 Serial Port Enable bit BANK0:RCSTA.RX9 6 9-bit Receive Enable bit BANK0:RCSTA.SREN 5 Single Receive Enable bit BANK0:RCSTA.CREN 4 Continuous Receive Enable bit BANK0:RCSTA.FERR 2 Framing Error bit BANK0:RCSTA.OERR 1 Overrun Error bit BANK0:RCSTA.RX9D 0 9th bit of received data BANK0:TXREG 0x0019 USART Transmit Data Register BANK0:RCREG 0x001A USART Receive Data Register BANK0:CCPR2L 0x001B Capture/Compare/PWM Register2 (LSB) BANK0:CCPR2H 0x001C Capture/Compare/PWM Register2 (MSB) BANK0:CCP2CON 0x001D CCP2CON REGISTER BANK0:CCP2CON.CCP2X 5 PWM Least Significant bit BANK0:CCP2CON.CCP2Y 4 PWM Least Significant bit BANK0:CCP2CON.CCP2M3 3 CCP2 Mode Select bit 3 BANK0:CCP2CON.CCP2M2 2 CCP2 Mode Select bit 2 BANK0:CCP2CON.CCP2M1 1 CCP2 Mode Select bit 1 BANK0:CCP2CON.CCP2M0 0 CCP2 Mode Select bit 0 BANK0:ADRES 0x001E A/D Result Register BANK0:ADCON0 0x001F ADCON0 REGISTER BANK0:ADCON0.ADCS1 7 A/D Conversion Clock Select bit 1 BANK0:ADCON0.ADCS0 6 A/D Conversion Clock Select bit 0 BANK0:ADCON0.CHS2 5 Analog Channel Select bit 2 BANK0:ADCON0.CHS1 4 Analog Channel Select bit 1 BANK0:ADCON0.CHS0 3 Analog Channel Select bit 0 BANK0:ADCON0.GO_DONE 2 A/D Conversion Status bit BANK0:ADCON0.ADON 0 A/D On bit ; BANK1 (0x0080:0x0100) BANK1:INDF 0x0080 INDF (not a physical register) BANK1:OPTION 0x0081 OPTION REGISTER BANK1:OPTION.RBPU 7 PORTB Pull-up Enable bit BANK1:OPTION.INTEDG 6 Interrupt Edge Select bit BANK1:OPTION.T0CS 5 TMR0 Clock Source Select bit BANK1:OPTION.T0SE 4 TMR0 Source Edge Select bit BANK1:OPTION.PSA 3 Prescaler Assignment bit BANK1:OPTION.PS2 2 Prescaler Rate Select bit 2 BANK1:OPTION.PS1 1 Prescaler Rate Select bit 1 BANK1:OPTION.PS0 0 Prescaler Rate Select bit 0 BANK1:PCL 0x0082 Program Counter's (PC) Least Significant Byte BANK1:STATUS 0x0083 STATUS REGISTER BANK1:STATUS.RP0 5 Register Bank Select bit 0 BANK1:STATUS.TO 4 Time-out bit BANK1:STATUS.PD 3 Power-down bit BANK1:STATUS.Z 2 Zero bit BANK1:STATUS.DC 1 Digit carry/borrow bit BANK1:STATUS.C 0 Carry/borrow bit BANK1:FSR 0x0084 Indirect data memory address pointer BANK1:TRISA 0x0085 PORTA Data Direction Register BANK1:TRISA.TRISA5 5 PORTA Data Direction Register bit 5 BANK1:TRISA.TRISA4 4 PORTA Data Direction Register bit 4 BANK1:TRISA.TRISA3 3 PORTA Data Direction Register bit 3 BANK1:TRISA.TRISA2 2 PORTA Data Direction Register bit 2 BANK1:TRISA.TRISA1 1 PORTA Data Direction Register bit 1 BANK1:TRISA.TRISA0 0 PORTA Data Direction Register bit 0 BANK1:TRISB 0x0086 PORTB Data Direction Register BANK1:TRISB.TRISB7 7 PORTB Data Direction Register bit 7 BANK1:TRISB.TRISB6 6 PORTB Data Direction Register bit 6 BANK1:TRISB.TRISB5 5 PORTB Data Direction Register bit 5 BANK1:TRISB.TRISB4 4 PORTB Data Direction Register bit 4 BANK1:TRISB.TRISB3 3 PORTB Data Direction Register bit 3 BANK1:TRISB.TRISB2 2 PORTB Data Direction Register bit 2 BANK1:TRISB.TRISB1 1 PORTB Data Direction Register bit 1 BANK1:TRISB.TRISB0 0 PORTB Data Direction Register bit 0 BANK1:TRISC 0x0087 PORTC Data Direction Register BANK1:TRISC.TRISC7 7 PORTC Data Direction Register bit 7 BANK1:TRISC.TRISC6 6 PORTC Data Direction Register bit 6 BANK1:TRISC.TRISC5 5 PORTC Data Direction Register bit 5 BANK1:TRISC.TRISC4 4 PORTC Data Direction Register bit 4 BANK1:TRISC.TRISC3 3 PORTC Data Direction Register bit 3 BANK1:TRISC.TRISC2 2 PORTC Data Direction Register bit 2 BANK1:TRISC.TRISC1 1 PORTC Data Direction Register bit 1 BANK1:TRISC.TRISC0 0 PORTC Data Direction Register bit 0 BANK1:RESERVED0088 0x0088 RESERVED BANK1:RESERVED0089 0x0089 RESERVED BANK1:PCLATH 0x008A Write Buffer for the upper 5 bits of the Program Counter BANK1:INTCON 0x008B INTCON REGISTER BANK1:INTCON.GIE 7 Global Interrupt Enable bit BANK1:INTCON.PEIE 6 Peripheral Interrupt Enable bit BANK1:INTCON.T0IE 5 TMR0 Overflow Interrupt Enable bit BANK1:INTCON.INTE 4 RB0/INT External Interrupt Enable bit BANK1:INTCON.RBIE 3 RB Port Change Interrupt Enable bit BANK1:INTCON.T0IF 2 TMR0 Overflow Interrupt Flag bit BANK1:INTCON.INTF 1 RB0/INT External Interrupt Flag bit BANK1:INTCON.RBIF 0 RB Port Change Interrupt Flag bit BANK1:PIE1 0x008C PIE1 REGISTER BANK1:PIE1.ADIE 6 A/D Converter Interrupt Enable bit BANK1:PIE1.RCIE 5 USART Receive Interrupt Enable bit BANK1:PIE1.TXIE 4 USART Transmit Interrupt Enable bit BANK1:PIE1.SSPIE 3 Synchronous Serial Port Interrupt Enable bit BANK1:PIE1.CCP1IE 2 CCP1 Interrupt Enable bit BANK1:PIE1.TMR2IE 1 TMR2 to PR2 Match Interrupt Enable bit BANK1:PIE1.TMR1IE 0 TMR1 Overflow Interrupt Enable bit BANK1:PIE2 0x008D PIE2 REGISTER BANK1:PIE2.CCP2IE 0 CCP2 Interrupt Enable bit BANK1:PCON 0x008E PCON REGISTER BANK1:PCON.POR 1 Power-on Reset Status bit BANK1:PCON.BOR 0 Brown-out Reset Status bit BANK1:RESERVED008F 0x008F RESERVED BANK1:RESERVED0090 0x0090 RESERVED BANK1:RESERVED0091 0x0091 RESERVED BANK1:PR2 0x0092 Timer2 Period Register BANK1:SSPADD 0x0093 Synchronous Serial Port (I2C mode) Address Register BANK1:SSPSTAT 0x0094 SYNC SERIAL PORT STATUS REGISTER BANK1:SSPSTAT.D_A 5 Data/Address bit (I2C mode only) BANK1:SSPSTAT.P 4 Stop bit (I2C mode only) BANK1:SSPSTAT.S 3 Start bit (I2C mode only) BANK1:SSPSTAT.R_W 2 Read/Write bit information (I2C mode only) BANK1:SSPSTAT.UA 1 Update Address (I2C mode only) BANK1:SSPSTAT.BF 0 Buffer Full Status bit BANK1:RESERVED0095 0x0095 RESERVED BANK1:RESERVED0096 0x0096 RESERVED BANK1:RESERVED0097 0x0097 RESERVED BANK1:TXSTA 0x0098 TRANSMIT STATUS AND CONTROL REGISTER BANK1:TXSTA.CSRC 7 Clock Source Select bit BANK1:TXSTA.TX9 6 9-bit Transmit Enable bit BANK1:TXSTA.TXEN 5 Transmit Enable bit BANK1:TXSTA.SYNC 4 USART Mode Select bit BANK1:TXSTA.BRGH 2 High Baud Rate Select bit BANK1:TXSTA.TRMT 1 Transmit Shift Register Status bit BANK1:TXSTA.TX9D 0 9th bit of transmit data. Can be parity bit BANK1:SPBRG 0x0099 Baud Rate Generator Register BANK1:RESERVED009A 0x009A RESERVED BANK1:RESERVED009B 0x009B RESERVED BANK1:RESERVED009C 0x009C RESERVED BANK1:RESERVED009D 0x009D RESERVED BANK1:RESERVED009E 0x009E RESERVED BANK1:ADCON1 0x009F ADCON1 REGISTER BANK1:ADCON1.PCFG2 2 A/D Port Configuration Control bit 2 BANK1:ADCON1.PCFG1 1 A/D Port Configuration Control bit 1 BANK1:ADCON1.PCFG0 0 A/D Port Configuration Control bit 0 .16C74 ; http://www.microchip.com/download/lit/pline/picmicro/families/16c7x/30390e.pdf ; PIC16C7X.pdf ; MEMORY MAP ; BANK_0 area DATA FSR_ 0x0000:0x0020 area DATA Gen_Purp 0x0020:0x0080 General Purpose Register area DATA MEM_Program0 0x0080:0x0800 On-chip Program Memory (Page 0) area DATA MEM_Program1 0x0800:0x1000 On-chip Program Memory (Page 1) ; BANK_1 ; area DATA FSR_ 0x0080:0x00A0 ; area DATA Gen_Purp 0x00A0:0x0100 General Purpose Register ; area DATA MEM_Program0 0x0100:0x0800 On-chip Program Memory (Page 0) ; area DATA MEM_Program1 0x0800:0x1000 On-chip Program Memory (Page 1) ; Interrupt and reset vector assignments interrupt RESET 0x0000 RESET ; INPUT/OUTPUT PORTS ; BANK0 (0x0000:0x0080) BANK0:INDF 0x0000 INDF (not a physical register) BANK0:TMR0 0x0001 Timer0 module's register BANK0:PCL 0x0002 Program Counter's (PC) Least Significant Byte BANK0:STATUS 0x0003 STATUS REGISTER BANK0:STATUS.RP0 5 Register Bank Select bit 0 BANK0:STATUS.TO 4 Time-out bit BANK0:STATUS.PD 3 Power-down bit BANK0:STATUS.Z 2 Zero bit BANK0:STATUS.DC 1 Digit carry/borrow bit BANK0:STATUS.C 0 Carry/borrow bit BANK0:FSR 0x0004 Indirect data memory address pointer BANK0:PORTA 0x0005 PORTA REGISTER BANK0:PORTA.RA5 5 PORTA bit 5 BANK0:PORTA.RA4 4 PORTA bit 4 BANK0:PORTA.RA3 3 PORTA bit 3 BANK0:PORTA.RA2 2 PORTA bit 2 BANK0:PORTA.RA1 1 PORTA bit 1 BANK0:PORTA.RA0 0 PORTA bit 0 BANK0:PORTB 0x0006 PORTB REGISTER BANK0:PORTB.RB7 7 PORTB bit 7 BANK0:PORTB.RB6 6 PORTB bit 6 BANK0:PORTB.RB5 5 PORTB bit 5 BANK0:PORTB.RB4 4 PORTB bit 4 BANK0:PORTB.RB3 3 PORTB bit 3 BANK0:PORTB.RB2 2 PORTB bit 2 BANK0:PORTB.RB1 1 PORTB bit 1 BANK0:PORTB.RB0 0 PORTB bit 0 BANK0:PORTC 0x0007 PORTC REGISTER BANK0:PORTC.RC7 7 PORTC bit 7 BANK0:PORTC.RC6 6 PORTC bit 6 BANK0:PORTC.RC5 5 PORTC bit 5 BANK0:PORTC.RC4 4 PORTC bit 4 BANK0:PORTC.RC3 3 PORTC bit 3 BANK0:PORTC.RC2 2 PORTC bit 2 BANK0:PORTC.RC1 1 PORTC bit 1 BANK0:PORTC.RC0 0 PORTC bit 0 BANK0:PORTD 0x0008 PORTD REGISTER BANK0:PORTD.RD7 7 PORTD bit 7 BANK0:PORTD.RD6 6 PORTD bit 6 BANK0:PORTD.RD5 5 PORTD bit 5 BANK0:PORTD.RD4 4 PORTD bit 4 BANK0:PORTD.RD3 3 PORTD bit 3 BANK0:PORTD.RD2 2 PORTD bit 2 BANK0:PORTD.RD1 1 PORTD bit 1 BANK0:PORTD.RD0 0 PORTD bit 0 BANK0:PORTE 0x0009 PORTE REGISTER BANK0:PORTE.RE2 2 PORTE bit 2 BANK0:PORTE.RE1 1 PORTE bit 1 BANK0:PORTE.RE0 0 PORTE bit 0 BANK0:PCLATH 0x000A Write Buffer for the upper 5 bits of the Program Counter BANK0:INTCON 0x000B INTCON REGISTER BANK0:INTCON.GIE 7 Global Interrupt Enable bit BANK0:INTCON.PEIE 6 Peripheral Interrupt Enable bit BANK0:INTCON.T0IE 5 TMR0 Overflow Interrupt Enable bit BANK0:INTCON.INTE 4 RB0/INT External Interrupt Enable bit BANK0:INTCON.RBIE 3 RB Port Change Interrupt Enable bit BANK0:INTCON.T0IF 2 TMR0 Overflow Interrupt Flag bit BANK0:INTCON.INTF 1 RB0/INT External Interrupt Flag bit BANK0:INTCON.RBIF 0 RB Port Change Interrupt Flag bit BANK0:PIR1 0x000C PIR1 REGISTER BANK0:PIR1.PSPIF 7 Parallel Slave Port Read/Write Interrupt Flag bit BANK0:PIR1.ADIF 6 A/D Converter Interrupt Flag bit BANK0:PIR1.RCIF 5 USART Receive Interrupt Flag bit BANK0:PIR1.TXIF 4 USART Transmit Interrupt Flag bit BANK0:PIR1.SSPIF 3 Synchronous Serial Port Interrupt Flag bit BANK0:PIR1.CCP1IF 2 CCP1 Interrupt Flag bit BANK0:PIR1.TMR2IF 1 TMR2 to PR2 Match Interrupt Flag bit BANK0:PIR1.TMR1IF 0 TMR1 Overflow Interrupt Flag bit BANK0:PIR2 0x000D PIR2 REGISTER BANK0:PIR2.CCP2IF 0 CCP2 Interrupt Flag bit BANK0:TMR1L 0x000E Holding register for the Least Significant Byte of the 16-bit TMR1 register BANK0:TMR1H 0x000F Holding register for the Most Significant Byte of the 16-bit TMR1 register BANK0:T1CON 0x0010 TIMER1 CONTROL REGISTER BANK0:T1CON.T1CKPS1 5 Timer1 Input Clock Prescale Select bit 1 BANK0:T1CON.T1CKPS0 4 Timer1 Input Clock Prescale Select bit 0 BANK0:T1CON.T1OSCEN 3 Timer1 Oscillator Enable Control bit BANK0:T1CON.T1SYNC 2 Timer1 External Clock Input Synchronization Control bit BANK0:T1CON.TMR1CS 1 Timer1 Clock Source Select bit BANK0:T1CON.TMR1ON 0 Timer1 On bit BANK0:TMR2 0x0011 Timer2 module's register BANK0:T2CON 0x0012 TIMER2 CONTROL REGISTER BANK0:T2CON.TOUTPS3 6 Timer2 Output Postscale Select bit 3 BANK0:T2CON.TOUTPS2 5 Timer2 Output Postscale Select bit 2 BANK0:T2CON.TOUTPS1 4 Timer2 Output Postscale Select bit 1 BANK0:T2CON.TOUTPS0 3 Timer2 Output Postscale Select bit 0 BANK0:T2CON.TMR2ON 2 Timer2 On bit BANK0:T2CON.T2CKPS1 1 Timer2 Clock Prescale Select bit 1 BANK0:T2CON.T2CKPS0 0 Timer2 Clock Prescale Select bit 0 BANK0:SSPBUF 0x0013 Synchronous Serial Port Receive Buffer/Transmit Register BANK0:SSPCON 0x0014 SYNC SERIAL PORT CONTROL REGISTER BANK0:SSPCON.WCOL 7 Write Collision Detect bit BANK0:SSPCON.SSPOV 6 Receive Overflow Indicator bit BANK0:SSPCON.SSPEN 5 Synchronous Serial Port Enable bit BANK0:SSPCON.CKP 4 Clock Polarity Select bit BANK0:SSPCON.SSPM3 3 Synchronous Serial Port Mode Select bit 3 BANK0:SSPCON.SSPM2 2 Synchronous Serial Port Mode Select bit 2 BANK0:SSPCON.SSPM1 1 Synchronous Serial Port Mode Select bit 1 BANK0:SSPCON.SSPM0 0 Synchronous Serial Port Mode Select bit 0 BANK0:CCPR1L 0x0015 Capture/Compare/PWM Register1 (LSB) BANK0:CCPR1H 0x0016 Capture/Compare/PWM Register1 (MSB) BANK0:CCP1CON 0x0017 CCP1CON REGISTER BANK0:CCP1CON.CCP1X 5 PWM Least Significant bit BANK0:CCP1CON.CCP1Y 4 PWM Least Significant bit BANK0:CCP1CON.CCP1M3 3 CCP1 Mode Select bit 3 BANK0:CCP1CON.CCP1M2 2 CCP1 Mode Select bit 2 BANK0:CCP1CON.CCP1M1 1 CCP1 Mode Select bit 1 BANK0:CCP1CON.CCP1M0 0 CCP1 Mode Select bit 0 BANK0:RCSTA 0x0018 RECEIVE STATUS AND CONTROL REGISTER BANK0:RCSTA.SPEN 7 Serial Port Enable bit BANK0:RCSTA.RX9 6 9-bit Receive Enable bit BANK0:RCSTA.SREN 5 Single Receive Enable bit BANK0:RCSTA.CREN 4 Continuous Receive Enable bit BANK0:RCSTA.FERR 2 Framing Error bit BANK0:RCSTA.OERR 1 Overrun Error bit BANK0:RCSTA.RX9D 0 9th bit of received data BANK0:TXREG 0x0019 USART Transmit Data Register BANK0:RCREG 0x001A USART Receive Data Register BANK0:CCPR2L 0x001B Capture/Compare/PWM Register2 (LSB) BANK0:CCPR2H 0x001C Capture/Compare/PWM Register2 (MSB) BANK0:CCP2CON 0x001D CCP2CON REGISTER BANK0:CCP2CON.CCP2X 5 PWM Least Significant bit BANK0:CCP2CON.CCP2Y 4 PWM Least Significant bit BANK0:CCP2CON.CCP2M3 3 CCP2 Mode Select bit 3 BANK0:CCP2CON.CCP2M2 2 CCP2 Mode Select bit 2 BANK0:CCP2CON.CCP2M1 1 CCP2 Mode Select bit 1 BANK0:CCP2CON.CCP2M0 0 CCP2 Mode Select bit 0 BANK0:ADRES 0x001E A/D Result Register BANK0:ADCON0 0x001F ADCON0 REGISTER BANK0:ADCON0.ADCS1 7 A/D Conversion Clock Select bit 1 BANK0:ADCON0.ADCS0 6 A/D Conversion Clock Select bit 0 BANK0:ADCON0.CHS2 5 Analog Channel Select bit 2 BANK0:ADCON0.CHS1 4 Analog Channel Select bit 1 BANK0:ADCON0.CHS0 3 Analog Channel Select bit 0 BANK0:ADCON0.GO_DONE 2 A/D Conversion Status bit BANK0:ADCON0.ADON 0 A/D On bit ; BANK1 (0x0080:0x0100) BANK1:INDF 0x0080 INDF (not a physical register) BANK1:OPTION 0x0081 OPTION REGISTER BANK1:OPTION.RBPU 7 PORTB Pull-up Enable bit BANK1:OPTION.INTEDG 6 Interrupt Edge Select bit BANK1:OPTION.T0CS 5 TMR0 Clock Source Select bit BANK1:OPTION.T0SE 4 TMR0 Source Edge Select bit BANK1:OPTION.PSA 3 Prescaler Assignment bit BANK1:OPTION.PS2 2 Prescaler Rate Select bit 2 BANK1:OPTION.PS1 1 Prescaler Rate Select bit 1 BANK1:OPTION.PS0 0 Prescaler Rate Select bit 0 BANK1:PCL 0x0082 Program Counter's (PC) Least Significant Byte BANK1:STATUS 0x0083 STATUS REGISTER BANK1:STATUS.RP0 5 Register Bank Select bit 0 BANK1:STATUS.TO 4 Time-out bit BANK1:STATUS.PD 3 Power-down bit BANK1:STATUS.Z 2 Zero bit BANK1:STATUS.DC 1 Digit carry/borrow bit BANK1:STATUS.C 0 Carry/borrow bit BANK1:FSR 0x0084 Indirect data memory address pointer BANK1:TRISA 0x0085 PORTA Data Direction Register BANK1:TRISA.TRISA5 5 PORTA Data Direction Register bit 5 BANK1:TRISA.TRISA4 4 PORTA Data Direction Register bit 4 BANK1:TRISA.TRISA3 3 PORTA Data Direction Register bit 3 BANK1:TRISA.TRISA2 2 PORTA Data Direction Register bit 2 BANK1:TRISA.TRISA1 1 PORTA Data Direction Register bit 1 BANK1:TRISA.TRISA0 0 PORTA Data Direction Register bit 0 BANK1:TRISB 0x0086 PORTB Data Direction Register BANK1:TRISB.TRISB7 7 PORTB Data Direction Register bit 7 BANK1:TRISB.TRISB6 6 PORTB Data Direction Register bit 6 BANK1:TRISB.TRISB5 5 PORTB Data Direction Register bit 5 BANK1:TRISB.TRISB4 4 PORTB Data Direction Register bit 4 BANK1:TRISB.TRISB3 3 PORTB Data Direction Register bit 3 BANK1:TRISB.TRISB2 2 PORTB Data Direction Register bit 2 BANK1:TRISB.TRISB1 1 PORTB Data Direction Register bit 1 BANK1:TRISB.TRISB0 0 PORTB Data Direction Register bit 0 BANK1:TRISC 0x0087 PORTC Data Direction Register BANK1:TRISC.TRISC7 7 PORTC Data Direction Register bit 7 BANK1:TRISC.TRISC6 6 PORTC Data Direction Register bit 6 BANK1:TRISC.TRISC5 5 PORTC Data Direction Register bit 5 BANK1:TRISC.TRISC4 4 PORTC Data Direction Register bit 4 BANK1:TRISC.TRISC3 3 PORTC Data Direction Register bit 3 BANK1:TRISC.TRISC2 2 PORTC Data Direction Register bit 2 BANK1:TRISC.TRISC1 1 PORTC Data Direction Register bit 1 BANK1:TRISC.TRISC0 0 PORTC Data Direction Register bit 0 BANK1:TRISD 0x0088 PORTD Data Direction Register BANK1:TRISD.TRISD7 7 PORTD Data Direction Register bit 7 BANK1:TRISD.TRISD6 6 PORTD Data Direction Register bit 6 BANK1:TRISD.TRISD5 5 PORTD Data Direction Register bit 5 BANK1:TRISD.TRISD4 4 PORTD Data Direction Register bit 4 BANK1:TRISD.TRISD3 3 PORTD Data Direction Register bit 3 BANK1:TRISD.TRISD2 2 PORTD Data Direction Register bit 2 BANK1:TRISD.TRISD1 1 PORTD Data Direction Register bit 1 BANK1:TRISD.TRISD0 0 PORTD Data Direction Register bit 0 BANK1:TRISE 0x0089 TRISE REGISTER BANK1:TRISE.IBF 7 Input Buffer Full Status bit BANK1:TRISE.OBF 6 Output Buffer Full Status bit BANK1:TRISE.IBOV 5 Input Buffer Overflow Detect bit BANK1:TRISE.PSPMODE 4 Parallel Slave Port Mode Select bit BANK1:TRISE.TRISE2 2 Direction Control bit for pin RE2/CS/AN7 BANK1:TRISE.TRISE1 1 Direction Control bit for pin RE1/WR/AN6 BANK1:TRISE.TRISE0 0 Direction Control bit for pin RE0/RD/AN5 BANK1:PCLATH 0x008A Write Buffer for the upper 5 bits of the Program Counter BANK1:INTCON 0x008B INTCON REGISTER BANK1:INTCON.GIE 7 Global Interrupt Enable bit BANK1:INTCON.PEIE 6 Peripheral Interrupt Enable bit BANK1:INTCON.T0IE 5 TMR0 Overflow Interrupt Enable bit BANK1:INTCON.INTE 4 RB0/INT External Interrupt Enable bit BANK1:INTCON.RBIE 3 RB Port Change Interrupt Enable bit BANK1:INTCON.T0IF 2 TMR0 Overflow Interrupt Flag bit BANK1:INTCON.INTF 1 RB0/INT External Interrupt Flag bit BANK1:INTCON.RBIF 0 RB Port Change Interrupt Flag bit BANK1:PIE1 0x008C PIE1 REGISTER BANK1:PIE1.PSPIE 7 Parallel Slave Port Read/Write Interrupt Enable bit BANK1:PIE1.ADIE 6 A/D Converter Interrupt Enable bit BANK1:PIE1.RCIE 5 USART Receive Interrupt Enable bit BANK1:PIE1.TXIE 4 USART Transmit Interrupt Enable bit BANK1:PIE1.SSPIE 3 Synchronous Serial Port Interrupt Enable bit BANK1:PIE1.CCP1IE 2 CCP1 Interrupt Enable bit BANK1:PIE1.TMR2IE 1 TMR2 to PR2 Match Interrupt Enable bit BANK1:PIE1.TMR1IE 0 TMR1 Overflow Interrupt Enable bit BANK1:PIE2 0x008D PIE2 REGISTER BANK1:PIE2.CCP2IE 0 CCP2 Interrupt Enable bit BANK1:PCON 0x008E PCON REGISTER BANK1:PCON.POR 1 Power-on Reset Status bit BANK1:RESERVED008F 0x008F RESERVED BANK1:RESERVED0090 0x0090 RESERVED BANK1:RESERVED0091 0x0091 RESERVED BANK1:PR2 0x0092 Timer2 Period Register BANK1:SSPADD 0x0093 Synchronous Serial Port (I2C mode) Address Register BANK1:SSPSTAT 0x0094 SYNC SERIAL PORT STATUS REGISTER BANK1:SSPSTAT.D_A 5 Data/Address bit (I2C mode only) BANK1:SSPSTAT.P 4 Stop bit (I2C mode only) BANK1:SSPSTAT.S 3 Start bit (I2C mode only) BANK1:SSPSTAT.R_W 2 Read/Write bit information (I2C mode only) BANK1:SSPSTAT.UA 1 Update Address (I2C mode only) BANK1:SSPSTAT.BF 0 Buffer Full Status bit BANK1:RESERVED0095 0x0095 RESERVED BANK1:RESERVED0096 0x0096 RESERVED BANK1:RESERVED0097 0x0097 RESERVED BANK1:TXSTA 0x0098 TRANSMIT STATUS AND CONTROL REGISTER BANK1:TXSTA.CSRC 7 Clock Source Select bit BANK1:TXSTA.TX9 6 9-bit Transmit Enable bit BANK1:TXSTA.TXEN 5 Transmit Enable bit BANK1:TXSTA.SYNC 4 USART Mode Select bit BANK1:TXSTA.BRGH 2 High Baud Rate Select bit BANK1:TXSTA.TRMT 1 Transmit Shift Register Status bit BANK1:TXSTA.TX9D 0 9th bit of transmit data. Can be parity bit BANK1:SPBRG 0x0099 Baud Rate Generator Register BANK1:RESERVED009A 0x009A RESERVED BANK1:RESERVED009B 0x009B RESERVED BANK1:RESERVED009C 0x009C RESERVED BANK1:RESERVED009D 0x009D RESERVED BANK1:RESERVED009E 0x009E RESERVED BANK1:ADCON1 0x009F ADCON1 REGISTER BANK1:ADCON1.PCFG2 2 A/D Port Configuration Control bit 2 BANK1:ADCON1.PCFG1 1 A/D Port Configuration Control bit 1 BANK1:ADCON1.PCFG0 0 A/D Port Configuration Control bit 0 .16C74A ; http://www.microchip.com/download/lit/pline/picmicro/families/16c7x/30390e.pdf ; PIC16C7X.pdf ; MEMORY MAP ; BANK_0 area DATA FSR_ 0x0000:0x0020 area DATA Gen_Purp 0x0020:0x0080 General Purpose Register area DATA MEM_Program0 0x0080:0x0800 On-chip Program Memory (Page 0) area DATA MEM_Program1 0x0800:0x1000 On-chip Program Memory (Page 1) ; BANK_1 ; area DATA FSR_ 0x0080:0x00A0 ; area DATA Gen_Purp 0x00A0:0x0100 General Purpose Register ; area DATA MEM_Program0 0x0100:0x0800 On-chip Program Memory (Page 0) ; area DATA MEM_Program1 0x0800:0x1000 On-chip Program Memory (Page 1) ; Interrupt and reset vector assignments interrupt RESET 0x0000 RESET ; INPUT/OUTPUT PORTS ; BANK0 (0x0000:0x0080) BANK0:INDF 0x0000 INDF (not a physical register) BANK0:TMR0 0x0001 Timer0 module's register BANK0:PCL 0x0002 Program Counter's (PC) Least Significant Byte BANK0:STATUS 0x0003 STATUS REGISTER BANK0:STATUS.RP0 5 Register Bank Select bit 0 BANK0:STATUS.TO 4 Time-out bit BANK0:STATUS.PD 3 Power-down bit BANK0:STATUS.Z 2 Zero bit BANK0:STATUS.DC 1 Digit carry/borrow bit BANK0:STATUS.C 0 Carry/borrow bit BANK0:FSR 0x0004 Indirect data memory address pointer BANK0:PORTA 0x0005 PORTA REGISTER BANK0:PORTA.RA5 5 PORTA bit 5 BANK0:PORTA.RA4 4 PORTA bit 4 BANK0:PORTA.RA3 3 PORTA bit 3 BANK0:PORTA.RA2 2 PORTA bit 2 BANK0:PORTA.RA1 1 PORTA bit 1 BANK0:PORTA.RA0 0 PORTA bit 0 BANK0:PORTB 0x0006 PORTB REGISTER BANK0:PORTB.RB7 7 PORTB bit 7 BANK0:PORTB.RB6 6 PORTB bit 6 BANK0:PORTB.RB5 5 PORTB bit 5 BANK0:PORTB.RB4 4 PORTB bit 4 BANK0:PORTB.RB3 3 PORTB bit 3 BANK0:PORTB.RB2 2 PORTB bit 2 BANK0:PORTB.RB1 1 PORTB bit 1 BANK0:PORTB.RB0 0 PORTB bit 0 BANK0:PORTC 0x0007 PORTC REGISTER BANK0:PORTC.RC7 7 PORTC bit 7 BANK0:PORTC.RC6 6 PORTC bit 6 BANK0:PORTC.RC5 5 PORTC bit 5 BANK0:PORTC.RC4 4 PORTC bit 4 BANK0:PORTC.RC3 3 PORTC bit 3 BANK0:PORTC.RC2 2 PORTC bit 2 BANK0:PORTC.RC1 1 PORTC bit 1 BANK0:PORTC.RC0 0 PORTC bit 0 BANK0:PORTD 0x0008 PORTD REGISTER BANK0:PORTD.RD7 7 PORTD bit 7 BANK0:PORTD.RD6 6 PORTD bit 6 BANK0:PORTD.RD5 5 PORTD bit 5 BANK0:PORTD.RD4 4 PORTD bit 4 BANK0:PORTD.RD3 3 PORTD bit 3 BANK0:PORTD.RD2 2 PORTD bit 2 BANK0:PORTD.RD1 1 PORTD bit 1 BANK0:PORTD.RD0 0 PORTD bit 0 BANK0:PORTE 0x0009 PORTE REGISTER BANK0:PORTE.RE2 2 PORTE bit 2 BANK0:PORTE.RE1 1 PORTE bit 1 BANK0:PORTE.RE0 0 PORTE bit 0 BANK0:PCLATH 0x000A Write Buffer for the upper 5 bits of the Program Counter BANK0:INTCON 0x000B INTCON REGISTER BANK0:INTCON.GIE 7 Global Interrupt Enable bit BANK0:INTCON.PEIE 6 Peripheral Interrupt Enable bit BANK0:INTCON.T0IE 5 TMR0 Overflow Interrupt Enable bit BANK0:INTCON.INTE 4 RB0/INT External Interrupt Enable bit BANK0:INTCON.RBIE 3 RB Port Change Interrupt Enable bit BANK0:INTCON.T0IF 2 TMR0 Overflow Interrupt Flag bit BANK0:INTCON.INTF 1 RB0/INT External Interrupt Flag bit BANK0:INTCON.RBIF 0 RB Port Change Interrupt Flag bit BANK0:PIR1 0x000C PIR1 REGISTER BANK0:PIR1.PSPIF 7 Parallel Slave Port Read/Write Interrupt Flag bit BANK0:PIR1.ADIF 6 A/D Converter Interrupt Flag bit BANK0:PIR1.RCIF 5 USART Receive Interrupt Flag bit BANK0:PIR1.TXIF 4 USART Transmit Interrupt Flag bit BANK0:PIR1.SSPIF 3 Synchronous Serial Port Interrupt Flag bit BANK0:PIR1.CCP1IF 2 CCP1 Interrupt Flag bit BANK0:PIR1.TMR2IF 1 TMR2 to PR2 Match Interrupt Flag bit BANK0:PIR1.TMR1IF 0 TMR1 Overflow Interrupt Flag bit BANK0:PIR2 0x000D PIR2 REGISTER BANK0:PIR2.CCP2IF 0 CCP2 Interrupt Flag bit BANK0:TMR1L 0x000E Holding register for the Least Significant Byte of the 16-bit TMR1 register BANK0:TMR1H 0x000F Holding register for the Most Significant Byte of the 16-bit TMR1 register BANK0:T1CON 0x0010 TIMER1 CONTROL REGISTER BANK0:T1CON.T1CKPS1 5 Timer1 Input Clock Prescale Select bit 1 BANK0:T1CON.T1CKPS0 4 Timer1 Input Clock Prescale Select bit 0 BANK0:T1CON.T1OSCEN 3 Timer1 Oscillator Enable Control bit BANK0:T1CON.T1SYNC 2 Timer1 External Clock Input Synchronization Control bit BANK0:T1CON.TMR1CS 1 Timer1 Clock Source Select bit BANK0:T1CON.TMR1ON 0 Timer1 On bit BANK0:TMR2 0x0011 Timer2 module's register BANK0:T2CON 0x0012 TIMER2 CONTROL REGISTER BANK0:T2CON.TOUTPS3 6 Timer2 Output Postscale Select bit 3 BANK0:T2CON.TOUTPS2 5 Timer2 Output Postscale Select bit 2 BANK0:T2CON.TOUTPS1 4 Timer2 Output Postscale Select bit 1 BANK0:T2CON.TOUTPS0 3 Timer2 Output Postscale Select bit 0 BANK0:T2CON.TMR2ON 2 Timer2 On bit BANK0:T2CON.T2CKPS1 1 Timer2 Clock Prescale Select bit 1 BANK0:T2CON.T2CKPS0 0 Timer2 Clock Prescale Select bit 0 BANK0:SSPBUF 0x0013 Synchronous Serial Port Receive Buffer/Transmit Register BANK0:SSPCON 0x0014 SYNC SERIAL PORT CONTROL REGISTER BANK0:SSPCON.WCOL 7 Write Collision Detect bit BANK0:SSPCON.SSPOV 6 Receive Overflow Indicator bit BANK0:SSPCON.SSPEN 5 Synchronous Serial Port Enable bit BANK0:SSPCON.CKP 4 Clock Polarity Select bit BANK0:SSPCON.SSPM3 3 Synchronous Serial Port Mode Select bit 3 BANK0:SSPCON.SSPM2 2 Synchronous Serial Port Mode Select bit 2 BANK0:SSPCON.SSPM1 1 Synchronous Serial Port Mode Select bit 1 BANK0:SSPCON.SSPM0 0 Synchronous Serial Port Mode Select bit 0 BANK0:CCPR1L 0x0015 Capture/Compare/PWM Register1 (LSB) BANK0:CCPR1H 0x0016 Capture/Compare/PWM Register1 (MSB) BANK0:CCP1CON 0x0017 CCP1CON REGISTER BANK0:CCP1CON.CCP1X 5 PWM Least Significant bit BANK0:CCP1CON.CCP1Y 4 PWM Least Significant bit BANK0:CCP1CON.CCP1M3 3 CCP1 Mode Select bit 3 BANK0:CCP1CON.CCP1M2 2 CCP1 Mode Select bit 2 BANK0:CCP1CON.CCP1M1 1 CCP1 Mode Select bit 1 BANK0:CCP1CON.CCP1M0 0 CCP1 Mode Select bit 0 BANK0:RCSTA 0x0018 RECEIVE STATUS AND CONTROL REGISTER BANK0:RCSTA.SPEN 7 Serial Port Enable bit BANK0:RCSTA.RX9 6 9-bit Receive Enable bit BANK0:RCSTA.SREN 5 Single Receive Enable bit BANK0:RCSTA.CREN 4 Continuous Receive Enable bit BANK0:RCSTA.FERR 2 Framing Error bit BANK0:RCSTA.OERR 1 Overrun Error bit BANK0:RCSTA.RX9D 0 9th bit of received data BANK0:TXREG 0x0019 USART Transmit Data Register BANK0:RCREG 0x001A USART Receive Data Register BANK0:CCPR2L 0x001B Capture/Compare/PWM Register2 (LSB) BANK0:CCPR2H 0x001C Capture/Compare/PWM Register2 (MSB) BANK0:CCP2CON 0x001D CCP2CON REGISTER BANK0:CCP2CON.CCP2X 5 PWM Least Significant bit BANK0:CCP2CON.CCP2Y 4 PWM Least Significant bit BANK0:CCP2CON.CCP2M3 3 CCP2 Mode Select bit 3 BANK0:CCP2CON.CCP2M2 2 CCP2 Mode Select bit 2 BANK0:CCP2CON.CCP2M1 1 CCP2 Mode Select bit 1 BANK0:CCP2CON.CCP2M0 0 CCP2 Mode Select bit 0 BANK0:ADRES 0x001E A/D Result Register BANK0:ADCON0 0x001F ADCON0 REGISTER BANK0:ADCON0.ADCS1 7 A/D Conversion Clock Select bit 1 BANK0:ADCON0.ADCS0 6 A/D Conversion Clock Select bit 0 BANK0:ADCON0.CHS2 5 Analog Channel Select bit 2 BANK0:ADCON0.CHS1 4 Analog Channel Select bit 1 BANK0:ADCON0.CHS0 3 Analog Channel Select bit 0 BANK0:ADCON0.GO_DONE 2 A/D Conversion Status bit BANK0:ADCON0.ADON 0 A/D On bit ; BANK1 (0x0080:0x0100) BANK1:INDF 0x0080 INDF (not a physical register) BANK1:OPTION 0x0081 OPTION REGISTER BANK1:OPTION.RBPU 7 PORTB Pull-up Enable bit BANK1:OPTION.INTEDG 6 Interrupt Edge Select bit BANK1:OPTION.T0CS 5 TMR0 Clock Source Select bit BANK1:OPTION.T0SE 4 TMR0 Source Edge Select bit BANK1:OPTION.PSA 3 Prescaler Assignment bit BANK1:OPTION.PS2 2 Prescaler Rate Select bit 2 BANK1:OPTION.PS1 1 Prescaler Rate Select bit 1 BANK1:OPTION.PS0 0 Prescaler Rate Select bit 0 BANK1:PCL 0x0082 Program Counter's (PC) Least Significant Byte BANK1:STATUS 0x0083 STATUS REGISTER BANK1:STATUS.RP0 5 Register Bank Select bit 0 BANK1:STATUS.TO 4 Time-out bit BANK1:STATUS.PD 3 Power-down bit BANK1:STATUS.Z 2 Zero bit BANK1:STATUS.DC 1 Digit carry/borrow bit BANK1:STATUS.C 0 Carry/borrow bit BANK1:FSR 0x0084 Indirect data memory address pointer BANK1:TRISA 0x0085 PORTA Data Direction Register BANK1:TRISA.TRISA5 5 PORTA Data Direction Register bit 5 BANK1:TRISA.TRISA4 4 PORTA Data Direction Register bit 4 BANK1:TRISA.TRISA3 3 PORTA Data Direction Register bit 3 BANK1:TRISA.TRISA2 2 PORTA Data Direction Register bit 2 BANK1:TRISA.TRISA1 1 PORTA Data Direction Register bit 1 BANK1:TRISA.TRISA0 0 PORTA Data Direction Register bit 0 BANK1:TRISB 0x0086 PORTB Data Direction Register BANK1:TRISB.TRISB7 7 PORTB Data Direction Register bit 7 BANK1:TRISB.TRISB6 6 PORTB Data Direction Register bit 6 BANK1:TRISB.TRISB5 5 PORTB Data Direction Register bit 5 BANK1:TRISB.TRISB4 4 PORTB Data Direction Register bit 4 BANK1:TRISB.TRISB3 3 PORTB Data Direction Register bit 3 BANK1:TRISB.TRISB2 2 PORTB Data Direction Register bit 2 BANK1:TRISB.TRISB1 1 PORTB Data Direction Register bit 1 BANK1:TRISB.TRISB0 0 PORTB Data Direction Register bit 0 BANK1:TRISC 0x0087 PORTC Data Direction Register BANK1:TRISC.TRISC7 7 PORTC Data Direction Register bit 7 BANK1:TRISC.TRISC6 6 PORTC Data Direction Register bit 6 BANK1:TRISC.TRISC5 5 PORTC Data Direction Register bit 5 BANK1:TRISC.TRISC4 4 PORTC Data Direction Register bit 4 BANK1:TRISC.TRISC3 3 PORTC Data Direction Register bit 3 BANK1:TRISC.TRISC2 2 PORTC Data Direction Register bit 2 BANK1:TRISC.TRISC1 1 PORTC Data Direction Register bit 1 BANK1:TRISC.TRISC0 0 PORTC Data Direction Register bit 0 BANK1:TRISD 0x0088 PORTD Data Direction Register BANK1:TRISD.TRISD7 7 PORTD Data Direction Register bit 7 BANK1:TRISD.TRISD6 6 PORTD Data Direction Register bit 6 BANK1:TRISD.TRISD5 5 PORTD Data Direction Register bit 5 BANK1:TRISD.TRISD4 4 PORTD Data Direction Register bit 4 BANK1:TRISD.TRISD3 3 PORTD Data Direction Register bit 3 BANK1:TRISD.TRISD2 2 PORTD Data Direction Register bit 2 BANK1:TRISD.TRISD1 1 PORTD Data Direction Register bit 1 BANK1:TRISD.TRISD0 0 PORTD Data Direction Register bit 0 BANK1:TRISE 0x0089 TRISE REGISTER BANK1:TRISE.IBF 7 Input Buffer Full Status bit BANK1:TRISE.OBF 6 Output Buffer Full Status bit BANK1:TRISE.IBOV 5 Input Buffer Overflow Detect bit BANK1:TRISE.PSPMODE 4 Parallel Slave Port Mode Select bit BANK1:TRISE.TRISE2 2 Direction Control bit for pin RE2/CS/AN7 BANK1:TRISE.TRISE1 1 Direction Control bit for pin RE1/WR/AN6 BANK1:TRISE.TRISE0 0 Direction Control bit for pin RE0/RD/AN5 BANK1:PCLATH 0x008A Write Buffer for the upper 5 bits of the Program Counter BANK1:INTCON 0x008B INTCON REGISTER BANK1:INTCON.GIE 7 Global Interrupt Enable bit BANK1:INTCON.PEIE 6 Peripheral Interrupt Enable bit BANK1:INTCON.T0IE 5 TMR0 Overflow Interrupt Enable bit BANK1:INTCON.INTE 4 RB0/INT External Interrupt Enable bit BANK1:INTCON.RBIE 3 RB Port Change Interrupt Enable bit BANK1:INTCON.T0IF 2 TMR0 Overflow Interrupt Flag bit BANK1:INTCON.INTF 1 RB0/INT External Interrupt Flag bit BANK1:INTCON.RBIF 0 RB Port Change Interrupt Flag bit BANK1:PIE1 0x008C PIE1 REGISTER BANK1:PIE1.PSPIE 7 Parallel Slave Port Read/Write Interrupt Enable bit BANK1:PIE1.ADIE 6 A/D Converter Interrupt Enable bit BANK1:PIE1.RCIE 5 USART Receive Interrupt Enable bit BANK1:PIE1.TXIE 4 USART Transmit Interrupt Enable bit BANK1:PIE1.SSPIE 3 Synchronous Serial Port Interrupt Enable bit BANK1:PIE1.CCP1IE 2 CCP1 Interrupt Enable bit BANK1:PIE1.TMR2IE 1 TMR2 to PR2 Match Interrupt Enable bit BANK1:PIE1.TMR1IE 0 TMR1 Overflow Interrupt Enable bit BANK1:PIE2 0x008D PIE2 REGISTER BANK1:PIE2.CCP2IE 0 CCP2 Interrupt Enable bit BANK1:PCON 0x008E PCON REGISTER BANK1:PCON.POR 1 Power-on Reset Status bit BANK1:PCON.BOR 0 Brown-out Reset Status bit BANK1:RESERVED008F 0x008F RESERVED BANK1:RESERVED0090 0x0090 RESERVED BANK1:RESERVED0091 0x0091 RESERVED BANK1:PR2 0x0092 Timer2 Period Register BANK1:SSPADD 0x0093 Synchronous Serial Port (I2C mode) Address Register BANK1:SSPSTAT 0x0094 SYNC SERIAL PORT STATUS REGISTER BANK1:SSPSTAT.D_A 5 Data/Address bit (I2C mode only) BANK1:SSPSTAT.P 4 Stop bit (I2C mode only) BANK1:SSPSTAT.S 3 Start bit (I2C mode only) BANK1:SSPSTAT.R_W 2 Read/Write bit information (I2C mode only) BANK1:SSPSTAT.UA 1 Update Address (I2C mode only) BANK1:SSPSTAT.BF 0 Buffer Full Status bit BANK1:RESERVED0095 0x0095 RESERVED BANK1:RESERVED0096 0x0096 RESERVED BANK1:RESERVED0097 0x0097 RESERVED BANK1:TXSTA 0x0098 TRANSMIT STATUS AND CONTROL REGISTER BANK1:TXSTA.CSRC 7 Clock Source Select bit BANK1:TXSTA.TX9 6 9-bit Transmit Enable bit BANK1:TXSTA.TXEN 5 Transmit Enable bit BANK1:TXSTA.SYNC 4 USART Mode Select bit BANK1:TXSTA.BRGH 2 High Baud Rate Select bit BANK1:TXSTA.TRMT 1 Transmit Shift Register Status bit BANK1:TXSTA.TX9D 0 9th bit of transmit data. Can be parity bit BANK1:SPBRG 0x0099 Baud Rate Generator Register BANK1:RESERVED009A 0x009A RESERVED BANK1:RESERVED009B 0x009B RESERVED BANK1:RESERVED009C 0x009C RESERVED BANK1:RESERVED009D 0x009D RESERVED BANK1:RESERVED009E 0x009E RESERVED BANK1:ADCON1 0x009F ADCON1 REGISTER BANK1:ADCON1.PCFG2 2 A/D Port Configuration Control bit 2 BANK1:ADCON1.PCFG1 1 A/D Port Configuration Control bit 1 BANK1:ADCON1.PCFG0 0 A/D Port Configuration Control bit 0 .16C76 ; http://www.microchip.com/download/lit/pline/picmicro/families/16c7x/30390e.pdf ; PIC16C7X.pdf ; MEMORY MAP ; BANK_0 area DATA FSR_ 0x0000:0x0020 area DATA Gen_Purp 0x0020:0x0080 General Purpose Register area DATA MEM_Program0 0x0080:0x0800 On-chip Program Memory (Page 0) area DATA MEM_Program1 0x0800:0x1000 On-chip Program Memory (Page 1) area DATA MEM_Program2 0x1000:0x1800 On-chip Program Memory (Page 2) area DATA MEM_Program3 0x1800:0x2000 On-chip Program Memory (Page 3) ; BANK_1 ; area DATA FSR_ 0x0080:0x00A0 ; area DATA Gen_Purp 0x00A0:0x00F0 General Purpose Register ; area DATA Gen_Purp_BANK0 0x00F0:0x0100 accesses 70h-7Fh ; area DATA MEM_Program0 0x0100:0x0800 On-chip Program Memory (Page 0) ; area DATA MEM_Program1 0x0800:0x1000 On-chip Program Memory (Page 1) ; area DATA MEM_Program2 0x1000:0x1800 On-chip Program Memory (Page 2) ; area DATA MEM_Program3 0x1800:0x2000 On-chip Program Memory (Page 3) ; BANK_2 ; area DATA FSR_ 0x0100:0x0110 ; area DATA Gen_Purp0 0x0110:0x0120 General Purpose Register 0 ; area DATA Gen_Purp1 0x0120:0x0170 General Purpose Register 1 ; area DATA Gen_Purp_BANK0 0x0170:0x0180 accesses 70h-7Fh ; area DATA MEM_Program0 0x0180:0x0800 On-chip Program Memory (Page 0) ; area DATA MEM_Program1 0x0800:0x1000 On-chip Program Memory (Page 1) ; area DATA MEM_Program2 0x1000:0x1800 On-chip Program Memory (Page 2) ; area DATA MEM_Program3 0x1800:0x2000 On-chip Program Memory (Page 3) ; BANK_3 ; area DATA FSR_ 0x0180:0x0190 ; area DATA Gen_Purp0 0x0190:0x01A0 General Purpose Register 0 ; area DATA Gen_Purp1 0x01A0:0x01F0 General Purpose Register 1 ; area DATA Gen_Purp_BANK0 0x01F0:0x0200 accesses 70h-7Fh ; area DATA MEM_Program0 0x0200:0x0800 On-chip Program Memory (Page 0) ; area DATA MEM_Program1 0x0800:0x1000 On-chip Program Memory (Page 1) ; area DATA MEM_Program2 0x1000:0x1800 On-chip Program Memory (Page 2) ; area DATA MEM_Program3 0x1800:0x2000 On-chip Program Memory (Page 3) ; Interrupt and reset vector assignments interrupt RESET 0x0000 RESET ; INPUT/OUTPUT PORTS ; BANK0 (0x0000:0x0080) BANK0:INDF 0x0000 INDF (not a physical register) BANK0:TMR0 0x0001 Timer0 module's register BANK0:PCL 0x0002 Program Counter's (PC) Least Significant Byte BANK0:STATUS 0x0003 STATUS REGISTER BANK0:STATUS.IRP 7 Register Bank Select bit BANK0:STATUS.RP1 6 Register Bank Select bit 1 BANK0:STATUS.RP0 5 Register Bank Select bit 0 BANK0:STATUS.TO 4 Time-out bit BANK0:STATUS.PD 3 Power-down bit BANK0:STATUS.Z 2 Zero bit BANK0:STATUS.DC 1 Digit carry/borrow bit BANK0:STATUS.C 0 Carry/borrow bit BANK0:FSR 0x0004 Indirect data memory address pointer BANK0:PORTA 0x0005 PORTA REGISTER BANK0:PORTA.RA5 5 PORTA bit 5 BANK0:PORTA.RA4 4 PORTA bit 4 BANK0:PORTA.RA3 3 PORTA bit 3 BANK0:PORTA.RA2 2 PORTA bit 2 BANK0:PORTA.RA1 1 PORTA bit 1 BANK0:PORTA.RA0 0 PORTA bit 0 BANK0:PORTB 0x0006 PORTB REGISTER BANK0:PORTB.RB7 7 PORTB bit 7 BANK0:PORTB.RB6 6 PORTB bit 6 BANK0:PORTB.RB5 5 PORTB bit 5 BANK0:PORTB.RB4 4 PORTB bit 4 BANK0:PORTB.RB3 3 PORTB bit 3 BANK0:PORTB.RB2 2 PORTB bit 2 BANK0:PORTB.RB1 1 PORTB bit 1 BANK0:PORTB.RB0 0 PORTB bit 0 BANK0:PORTC 0x0007 PORTC REGISTER BANK0:PORTC.RC7 7 PORTC bit 7 BANK0:PORTC.RC6 6 PORTC bit 6 BANK0:PORTC.RC5 5 PORTC bit 5 BANK0:PORTC.RC4 4 PORTC bit 4 BANK0:PORTC.RC3 3 PORTC bit 3 BANK0:PORTC.RC2 2 PORTC bit 2 BANK0:PORTC.RC1 1 PORTC bit 1 BANK0:PORTC.RC0 0 PORTC bit 0 BANK0:RESERVED0008 0x0008 RESERVED BANK0:RESERVED0009 0x0009 RESERVED BANK0:PCLATH 0x000A Write Buffer for the upper 5 bits of the Program Counter BANK0:INTCON 0x000B INTCON REGISTER BANK0:INTCON.GIE 7 Global Interrupt Enable bit BANK0:INTCON.PEIE 6 Peripheral Interrupt Enable bit BANK0:INTCON.T0IE 5 TMR0 Overflow Interrupt Enable bit BANK0:INTCON.INTE 4 RB0/INT External Interrupt Enable bit BANK0:INTCON.RBIE 3 RB Port Change Interrupt Enable bit BANK0:INTCON.T0IF 2 TMR0 Overflow Interrupt Flag bit BANK0:INTCON.INTF 1 RB0/INT External Interrupt Flag bit BANK0:INTCON.RBIF 0 RB Port Change Interrupt Flag bit BANK0:PIR1 0x000C PIR1 REGISTER BANK0:PIR1.ADIF 6 A/D Converter Interrupt Flag bit BANK0:PIR1.RCIF 5 USART Receive Interrupt Flag bit BANK0:PIR1.TXIF 4 USART Transmit Interrupt Flag bit BANK0:PIR1.SSPIF 3 Synchronous Serial Port Interrupt Flag bit BANK0:PIR1.CCP1IF 2 CCP1 Interrupt Flag bit BANK0:PIR1.TMR2IF 1 TMR2 to PR2 Match Interrupt Flag bit BANK0:PIR1.TMR1IF 0 TMR1 Overflow Interrupt Flag bit BANK0:PIR2 0x000D PIR2 REGISTER BANK0:PIR2.CCP2IF 0 CCP2 Interrupt Flag bit BANK0:TMR1L 0x000E Holding register for the Least Significant Byte of the 16-bit TMR1 register BANK0:TMR1H 0x000F Holding register for the Most Significant Byte of the 16-bit TMR1 register BANK0:T1CON 0x0010 TIMER1 CONTROL REGISTER BANK0:T1CON.T1CKPS1 5 Timer1 Input Clock Prescale Select bit 1 BANK0:T1CON.T1CKPS0 4 Timer1 Input Clock Prescale Select bit 0 BANK0:T1CON.T1OSCEN 3 Timer1 Oscillator Enable Control bit BANK0:T1CON.T1SYNC 2 Timer1 External Clock Input Synchronization Control bit BANK0:T1CON.TMR1CS 1 Timer1 Clock Source Select bit BANK0:T1CON.TMR1ON 0 Timer1 On bit BANK0:TMR2 0x0011 Timer2 module's register BANK0:T2CON 0x0012 TIMER2 CONTROL REGISTER BANK0:T2CON.TOUTPS3 6 Timer2 Output Postscale Select bit 3 BANK0:T2CON.TOUTPS2 5 Timer2 Output Postscale Select bit 2 BANK0:T2CON.TOUTPS1 4 Timer2 Output Postscale Select bit 1 BANK0:T2CON.TOUTPS0 3 Timer2 Output Postscale Select bit 0 BANK0:T2CON.TMR2ON 2 Timer2 On bit BANK0:T2CON.T2CKPS1 1 Timer2 Clock Prescale Select bit 1 BANK0:T2CON.T2CKPS0 0 Timer2 Clock Prescale Select bit 0 BANK0:SSPBUF 0x0013 Synchronous Serial Port Receive Buffer/Transmit Register BANK0:SSPCON 0x0014 SYNC SERIAL PORT CONTROL REGISTER BANK0:SSPCON.WCOL 7 Write Collision Detect bit BANK0:SSPCON.SSPOV 6 Receive Overflow Indicator bit BANK0:SSPCON.SSPEN 5 Synchronous Serial Port Enable bit BANK0:SSPCON.CKP 4 Clock Polarity Select bit BANK0:SSPCON.SSPM3 3 Synchronous Serial Port Mode Select bit 3 BANK0:SSPCON.SSPM2 2 Synchronous Serial Port Mode Select bit 2 BANK0:SSPCON.SSPM1 1 Synchronous Serial Port Mode Select bit 1 BANK0:SSPCON.SSPM0 0 Synchronous Serial Port Mode Select bit 0 BANK0:CCPR1L 0x0015 Capture/Compare/PWM Register1 (LSB) BANK0:CCPR1H 0x0016 Capture/Compare/PWM Register1 (MSB) BANK0:CCP1CON 0x0017 CCP1CON REGISTER BANK0:CCP1CON.CCP1X 5 PWM Least Significant bit BANK0:CCP1CON.CCP1Y 4 PWM Least Significant bit BANK0:CCP1CON.CCP1M3 3 CCP1 Mode Select bit 3 BANK0:CCP1CON.CCP1M2 2 CCP1 Mode Select bit 2 BANK0:CCP1CON.CCP1M1 1 CCP1 Mode Select bit 1 BANK0:CCP1CON.CCP1M0 0 CCP1 Mode Select bit 0 BANK0:RCSTA 0x0018 RECEIVE STATUS AND CONTROL REGISTER BANK0:RCSTA.SPEN 7 Serial Port Enable bit BANK0:RCSTA.RX9 6 9-bit Receive Enable bit BANK0:RCSTA.SREN 5 Single Receive Enable bit BANK0:RCSTA.CREN 4 Continuous Receive Enable bit BANK0:RCSTA.FERR 2 Framing Error bit BANK0:RCSTA.OERR 1 Overrun Error bit BANK0:RCSTA.RX9D 0 9th bit of received data BANK0:TXREG 0x0019 USART Transmit Data Register BANK0:RCREG 0x001A USART Receive Data Register BANK0:CCPR2L 0x001B Capture/Compare/PWM Register2 (LSB) BANK0:CCPR2H 0x001C Capture/Compare/PWM Register2 (MSB) BANK0:CCP2CON 0x001D CCP2CON REGISTER BANK0:CCP2CON.CCP2X 5 PWM Least Significant bit BANK0:CCP2CON.CCP2Y 4 PWM Least Significant bit BANK0:CCP2CON.CCP2M3 3 CCP2 Mode Select bit 3 BANK0:CCP2CON.CCP2M2 2 CCP2 Mode Select bit 2 BANK0:CCP2CON.CCP2M1 1 CCP2 Mode Select bit 1 BANK0:CCP2CON.CCP2M0 0 CCP2 Mode Select bit 0 BANK0:ADRES 0x001E A/D Result Register BANK0:ADCON0 0x001F ADCON0 REGISTER BANK0:ADCON0.ADCS1 7 A/D Conversion Clock Select bit 1 BANK0:ADCON0.ADCS0 6 A/D Conversion Clock Select bit 0 BANK0:ADCON0.CHS2 5 Analog Channel Select bit 2 BANK0:ADCON0.CHS1 4 Analog Channel Select bit 1 BANK0:ADCON0.CHS0 3 Analog Channel Select bit 0 BANK0:ADCON0.GO_DONE 2 A/D Conversion Status bit BANK0:ADCON0.ADON 0 A/D On bit ; BANK1 (0x0080:0x0100) BANK1:INDF 0x0080 INDF (not a physical register) BANK1:OPTION 0x0081 OPTION REGISTER BANK1:OPTION.RBPU 7 PORTB Pull-up Enable bit BANK1:OPTION.INTEDG 6 Interrupt Edge Select bit BANK1:OPTION.T0CS 5 TMR0 Clock Source Select bit BANK1:OPTION.T0SE 4 TMR0 Source Edge Select bit BANK1:OPTION.PSA 3 Prescaler Assignment bit BANK1:OPTION.PS2 2 Prescaler Rate Select bit 2 BANK1:OPTION.PS1 1 Prescaler Rate Select bit 1 BANK1:OPTION.PS0 0 Prescaler Rate Select bit 0 BANK1:PCL 0x0082 Program Counter's (PC) Least Significant Byte BANK1:STATUS 0x0083 STATUS REGISTER BANK1:STATUS.IRP 7 Register Bank Select bit BANK1:STATUS.RP1 6 Register Bank Select bit 1 BANK1:STATUS.RP0 5 Register Bank Select bit 0 BANK1:STATUS.TO 4 Time-out bit BANK1:STATUS.PD 3 Power-down bit BANK1:STATUS.Z 2 Zero bit BANK1:STATUS.DC 1 Digit carry/borrow bit BANK1:STATUS.C 0 Carry/borrow bit BANK1:FSR 0x0084 Indirect data memory address pointer BANK1:TRISA 0x0085 PORTA Data Direction Register BANK1:TRISA.TRISA5 5 PORTA Data Direction Register bit 5 BANK1:TRISA.TRISA4 4 PORTA Data Direction Register bit 4 BANK1:TRISA.TRISA3 3 PORTA Data Direction Register bit 3 BANK1:TRISA.TRISA2 2 PORTA Data Direction Register bit 2 BANK1:TRISA.TRISA1 1 PORTA Data Direction Register bit 1 BANK1:TRISA.TRISA0 0 PORTA Data Direction Register bit 0 BANK1:TRISB 0x0086 PORTB Data Direction Register BANK1:TRISB.TRISB7 7 PORTB Data Direction Register bit 7 BANK1:TRISB.TRISB6 6 PORTB Data Direction Register bit 6 BANK1:TRISB.TRISB5 5 PORTB Data Direction Register bit 5 BANK1:TRISB.TRISB4 4 PORTB Data Direction Register bit 4 BANK1:TRISB.TRISB3 3 PORTB Data Direction Register bit 3 BANK1:TRISB.TRISB2 2 PORTB Data Direction Register bit 2 BANK1:TRISB.TRISB1 1 PORTB Data Direction Register bit 1 BANK1:TRISB.TRISB0 0 PORTB Data Direction Register bit 0 BANK1:TRISC 0x0087 PORTC Data Direction Register BANK1:TRISC.TRISC7 7 PORTC Data Direction Register bit 7 BANK1:TRISC.TRISC6 6 PORTC Data Direction Register bit 6 BANK1:TRISC.TRISC5 5 PORTC Data Direction Register bit 5 BANK1:TRISC.TRISC4 4 PORTC Data Direction Register bit 4 BANK1:TRISC.TRISC3 3 PORTC Data Direction Register bit 3 BANK1:TRISC.TRISC2 2 PORTC Data Direction Register bit 2 BANK1:TRISC.TRISC1 1 PORTC Data Direction Register bit 1 BANK1:TRISC.TRISC0 0 PORTC Data Direction Register bit 0 BANK1:RESERVED0088 0x0088 RESERVED BANK1:RESERVED0089 0x0089 RESERVED BANK1:PCLATH 0x008A Write Buffer for the upper 5 bits of the Program Counter BANK1:INTCON 0x008B INTCON REGISTER BANK1:INTCON.GIE 7 Global Interrupt Enable bit BANK1:INTCON.PEIE 6 Peripheral Interrupt Enable bit BANK1:INTCON.T0IE 5 TMR0 Overflow Interrupt Enable bit BANK1:INTCON.INTE 4 RB0/INT External Interrupt Enable bit BANK1:INTCON.RBIE 3 RB Port Change Interrupt Enable bit BANK1:INTCON.T0IF 2 TMR0 Overflow Interrupt Flag bit BANK1:INTCON.INTF 1 RB0/INT External Interrupt Flag bit BANK1:INTCON.RBIF 0 RB Port Change Interrupt Flag bit BANK1:PIE1 0x008C PIE1 REGISTER BANK1:PIE1.ADIE 6 A/D Converter Interrupt Enable bit BANK1:PIE1.RCIE 5 USART Receive Interrupt Enable bit BANK1:PIE1.TXIE 4 USART Transmit Interrupt Enable bit BANK1:PIE1.SSPIE 3 Synchronous Serial Port Interrupt Enable bit BANK1:PIE1.CCP1IE 2 CCP1 Interrupt Enable bit BANK1:PIE1.TMR2IE 1 TMR2 to PR2 Match Interrupt Enable bit BANK1:PIE1.TMR1IE 0 TMR1 Overflow Interrupt Enable bit BANK1:PIE2 0x008D PIE2 REGISTER BANK1:PIE2.CCP2IE 0 CCP2 Interrupt Enable bit BANK1:PCON 0x008E PCON REGISTER BANK1:PCON.POR 1 Power-on Reset Status bit BANK1:PCON.BOR 0 Brown-out Reset Status bit BANK1:RESERVED008F 0x008F RESERVED BANK1:RESERVED0090 0x0090 RESERVED BANK1:RESERVED0091 0x0091 RESERVED BANK1:PR2 0x0092 Timer2 Period Register BANK1:SSPADD 0x0093 Synchronous Serial Port (I2C mode) Address Register BANK1:SSPSTAT 0x0094 SYNC SERIAL PORT STATUS REGISTER BANK1:SSPSTAT.SMP 7 SPI data input sample phase BANK1:SSPSTAT.CKE 6 SPI Clock Edge Select BANK1:SSPSTAT.D_A 5 Data/Address bit (I2C mode only) BANK1:SSPSTAT.P 4 Stop bit (I2C mode only) BANK1:SSPSTAT.S 3 Start bit (I2C mode only) BANK1:SSPSTAT.R_W 2 Read/Write bit information (I2C mode only) BANK1:SSPSTAT.UA 1 Update Address (I2C mode only) BANK1:SSPSTAT.BF 0 Buffer Full Status bit BANK1:RESERVED0095 0x0095 RESERVED BANK1:RESERVED0096 0x0096 RESERVED BANK1:RESERVED0097 0x0097 RESERVED BANK1:TXSTA 0x0098 TRANSMIT STATUS AND CONTROL REGISTER BANK1:TXSTA.CSRC 7 Clock Source Select bit BANK1:TXSTA.TX9 6 9-bit Transmit Enable bit BANK1:TXSTA.TXEN 5 Transmit Enable bit BANK1:TXSTA.SYNC 4 USART Mode Select bit BANK1:TXSTA.BRGH 2 High Baud Rate Select bit BANK1:TXSTA.TRMT 1 Transmit Shift Register Status bit BANK1:TXSTA.TX9D 0 9th bit of transmit data. Can be parity bit BANK1:SPBRG 0x0099 Baud Rate Generator Register BANK1:RESERVED009A 0x009A RESERVED BANK1:RESERVED009B 0x009B RESERVED BANK1:RESERVED009C 0x009C RESERVED BANK1:RESERVED009D 0x009D RESERVED BANK1:RESERVED009E 0x009E RESERVED BANK1:ADCON1 0x009F ADCON1 REGISTER BANK1:ADCON1.PCFG2 2 A/D Port Configuration Control bit 2 BANK1:ADCON1.PCFG1 1 A/D Port Configuration Control bit 1 BANK1:ADCON1.PCFG0 0 A/D Port Configuration Control bit 0 ; BANK2 (0x0100:0x0180) BANK2:INDF 0x0100 INDF (not a physical register) BANK2:TMR0 0x0101 Timer0 module's register BANK2:PCL 0x0102 Program Counter's (PC) Least Significant Byte BANK2:STATUS 0x0103 STATUS REGISTER BANK2:STATUS.IRP 7 Register Bank Select bit BANK2:STATUS.RP1 6 Register Bank Select bit 1 BANK2:STATUS.RP0 5 Register Bank Select bit 0 BANK2:STATUS.TO 4 Time-out bit BANK2:STATUS.PD 3 Power-down bit BANK2:STATUS.Z 2 Zero bit BANK2:STATUS.DC 1 Digit carry/borrow bit BANK2:STATUS.C 0 Carry/borrow bit BANK2:FSR 0x0104 Indirect data memory address pointer BANK2:RESERVED0105 0x0105 RESERVED BANK2:PORTB 0x0106 PORTB REGISTER BANK2:PORTB.RB7 7 PORTB bit 7 BANK2:PORTB.RB6 6 PORTB bit 6 BANK2:PORTB.RB5 5 PORTB bit 5 BANK2:PORTB.RB4 4 PORTB bit 4 BANK2:PORTB.RB3 3 PORTB bit 3 BANK2:PORTB.RB2 2 PORTB bit 2 BANK2:PORTB.RB1 1 PORTB bit 1 BANK2:PORTB.RB0 0 PORTB bit 0 BANK2:RESERVED0107 0x0107 RESERVED BANK2:RESERVED0108 0x0108 RESERVED BANK2:RESERVED0109 0x0109 RESERVED BANK2:PCLATH 0x010A Write Buffer for the upper 5 bits of the Program Counter BANK2:INTCON 0x010B INTCON REGISTER BANK2:INTCON.GIE 7 Global Interrupt Enable bit BANK2:INTCON.PEIE 6 Peripheral Interrupt Enable bit BANK2:INTCON.T0IE 5 TMR0 Overflow Interrupt Enable bit BANK2:INTCON.INTE 4 RB0/INT External Interrupt Enable bit BANK2:INTCON.RBIE 3 RB Port Change Interrupt Enable bit BANK2:INTCON.T0IF 2 TMR0 Overflow Interrupt Flag bit BANK2:INTCON.INTF 1 RB0/INT External Interrupt Flag bit BANK2:INTCON.RBIF 0 RB Port Change Interrupt Flag bit BANK2:RESERVED010C 0x010C RESERVED BANK2:RESERVED010D 0x010D RESERVED BANK2:RESERVED010E 0x010E RESERVED BANK2:RESERVED010F 0x010F RESERVED ; BANK3 (0x0180:0x0200) BANK3:INDF 0x0180 INDF (not a physical register) BANK3:OPTION 0x0181 OPTION REGISTER BANK3:OPTION.RBPU 7 PORTB Pull-up Enable bit BANK3:OPTION.INTEDG 6 Interrupt Edge Select bit BANK3:OPTION.T0CS 5 TMR0 Clock Source Select bit BANK3:OPTION.T0SE 4 TMR0 Source Edge Select bit BANK3:OPTION.PSA 3 Prescaler Assignment bit BANK3:OPTION.PS2 2 Prescaler Rate Select bit 2 BANK3:OPTION.PS1 1 Prescaler Rate Select bit 1 BANK3:OPTION.PS0 0 Prescaler Rate Select bit 0 BANK3:PCL 0x0182 Program Counter's (PC) Least Significant Byte BANK3:STATUS 0x0183 STATUS REGISTER BANK3:STATUS.IRP 7 Register Bank Select bit BANK3:STATUS.RP1 6 Register Bank Select bit 1 BANK3:STATUS.RP0 5 Register Bank Select bit 0 BANK3:STATUS.TO 4 Time-out bit BANK3:STATUS.PD 3 Power-down bit BANK3:STATUS.Z 2 Zero bit BANK3:STATUS.DC 1 Digit carry/borrow bit BANK3:STATUS.C 0 Carry/borrow bit BANK3:FSR 0x0184 Indirect data memory address pointer BANK3:RESERVED0185 0x0185 RESERVED BANK3:TRISB 0x0186 PORTB Data Direction Register BANK3:TRISB.TRISB7 7 PORTB Data Direction Register bit 7 BANK3:TRISB.TRISB6 6 PORTB Data Direction Register bit 6 BANK3:TRISB.TRISB5 5 PORTB Data Direction Register bit 5 BANK3:TRISB.TRISB4 4 PORTB Data Direction Register bit 4 BANK3:TRISB.TRISB3 3 PORTB Data Direction Register bit 3 BANK3:TRISB.TRISB2 2 PORTB Data Direction Register bit 2 BANK3:TRISB.TRISB1 1 PORTB Data Direction Register bit 1 BANK3:TRISB.TRISB0 0 PORTB Data Direction Register bit 0 BANK3:RESERVED0187 0x0187 RESERVED BANK3:RESERVED0188 0x0188 RESERVED BANK3:RESERVED0189 0x0189 RESERVED BANK3:PCLATH 0x018A Write Buffer for the upper 5 bits of the Program Counter BANK3:INTCON 0x018B INTCON REGISTER BANK3:INTCON.GIE 7 Global Interrupt Enable bit BANK3:INTCON.PEIE 6 Peripheral Interrupt Enable bit BANK3:INTCON.T0IE 5 TMR0 Overflow Interrupt Enable bit BANK3:INTCON.INTE 4 RB0/INT External Interrupt Enable bit BANK3:INTCON.RBIE 3 RB Port Change Interrupt Enable bit BANK3:INTCON.T0IF 2 TMR0 Overflow Interrupt Flag bit BANK3:INTCON.INTF 1 RB0/INT External Interrupt Flag bit BANK3:INTCON.RBIF 0 RB Port Change Interrupt Flag bit BANK3:RESERVED018C 0x018C RESERVED BANK3:RESERVED018D 0x018D RESERVED BANK3:RESERVED018E 0x018E RESERVED BANK3:RESERVED018F 0x018F RESERVED .16C77 ; http://www.microchip.com/download/lit/pline/picmicro/families/16c7x/30390e.pdf ; PIC16C7X.pdf ; MEMORY MAP ; BANK_0 area DATA FSR_ 0x0000:0x0020 area DATA Gen_Purp 0x0020:0x0080 General Purpose Register area DATA MEM_Program0 0x0080:0x0800 On-chip Program Memory (Page 0) area DATA MEM_Program1 0x0800:0x1000 On-chip Program Memory (Page 1) area DATA MEM_Program2 0x1000:0x1800 On-chip Program Memory (Page 2) area DATA MEM_Program3 0x1800:0x2000 On-chip Program Memory (Page 3) ; BANK_1 ; area DATA FSR_ 0x0080:0x00A0 ; area DATA Gen_Purp 0x00A0:0x00F0 General Purpose Register ; area DATA Gen_Purp_BANK0 0x00F0:0x0100 accesses 70h-7Fh ; area DATA MEM_Program0 0x0100:0x0800 On-chip Program Memory (Page 0) ; area DATA MEM_Program1 0x0800:0x1000 On-chip Program Memory (Page 1) ; area DATA MEM_Program2 0x1000:0x1800 On-chip Program Memory (Page 2) ; area DATA MEM_Program3 0x1800:0x2000 On-chip Program Memory (Page 3) ; BANK_2 ; area DATA FSR_ 0x0100:0x0110 ; area DATA Gen_Purp0 0x0110:0x0120 General Purpose Register 0 ; area DATA Gen_Purp1 0x0120:0x0170 General Purpose Register 1 ; area DATA Gen_Purp_BANK0 0x0170:0x0180 accesses 70h-7Fh ; area DATA MEM_Program0 0x0180:0x0800 On-chip Program Memory (Page 0) ; area DATA MEM_Program1 0x0800:0x1000 On-chip Program Memory (Page 1) ; area DATA MEM_Program2 0x1000:0x1800 On-chip Program Memory (Page 2) ; area DATA MEM_Program3 0x1800:0x2000 On-chip Program Memory (Page 3) ; BANK_3 ; area DATA FSR_ 0x0180:0x0190 ; area DATA Gen_Purp0 0x0190:0x01A0 General Purpose Register 0 ; area DATA Gen_Purp1 0x01A0:0x01F0 General Purpose Register 1 ; area DATA Gen_Purp_BANK0 0x01F0:0x0200 accesses 70h-7Fh ; area DATA MEM_Program0 0x0200:0x0800 On-chip Program Memory (Page 0) ; area DATA MEM_Program1 0x0800:0x1000 On-chip Program Memory (Page 1) ; area DATA MEM_Program2 0x1000:0x1800 On-chip Program Memory (Page 2) ; area DATA MEM_Program3 0x1800:0x2000 On-chip Program Memory (Page 3) ; Interrupt and reset vector assignments interrupt RESET 0x0000 RESET ; INPUT/OUTPUT PORTS ; BANK0 (0x0000:0x0080) BANK0:INDF 0x0000 INDF (not a physical register) BANK0:TMR0 0x0001 Timer0 module's register BANK0:PCL 0x0002 Program Counter's (PC) Least Significant Byte BANK0:STATUS 0x0003 STATUS REGISTER BANK0:STATUS.IRP 7 Register Bank Select bit BANK0:STATUS.RP1 6 Register Bank Select bit 1 BANK0:STATUS.RP0 5 Register Bank Select bit 0 BANK0:STATUS.TO 4 Time-out bit BANK0:STATUS.PD 3 Power-down bit BANK0:STATUS.Z 2 Zero bit BANK0:STATUS.DC 1 Digit carry/borrow bit BANK0:STATUS.C 0 Carry/borrow bit BANK0:FSR 0x0004 Indirect data memory address pointer BANK0:PORTA 0x0005 PORTA REGISTER BANK0:PORTA.RA5 5 PORTA bit 5 BANK0:PORTA.RA4 4 PORTA bit 4 BANK0:PORTA.RA3 3 PORTA bit 3 BANK0:PORTA.RA2 2 PORTA bit 2 BANK0:PORTA.RA1 1 PORTA bit 1 BANK0:PORTA.RA0 0 PORTA bit 0 BANK0:PORTB 0x0006 PORTB REGISTER BANK0:PORTB.RB7 7 PORTB bit 7 BANK0:PORTB.RB6 6 PORTB bit 6 BANK0:PORTB.RB5 5 PORTB bit 5 BANK0:PORTB.RB4 4 PORTB bit 4 BANK0:PORTB.RB3 3 PORTB bit 3 BANK0:PORTB.RB2 2 PORTB bit 2 BANK0:PORTB.RB1 1 PORTB bit 1 BANK0:PORTB.RB0 0 PORTB bit 0 BANK0:PORTC 0x0007 PORTC REGISTER BANK0:PORTC.RC7 7 PORTC bit 7 BANK0:PORTC.RC6 6 PORTC bit 6 BANK0:PORTC.RC5 5 PORTC bit 5 BANK0:PORTC.RC4 4 PORTC bit 4 BANK0:PORTC.RC3 3 PORTC bit 3 BANK0:PORTC.RC2 2 PORTC bit 2 BANK0:PORTC.RC1 1 PORTC bit 1 BANK0:PORTC.RC0 0 PORTC bit 0 BANK0:PORTD 0x0008 PORTD REGISTER BANK0:PORTD.RD7 7 PORTD bit 7 BANK0:PORTD.RD6 6 PORTD bit 6 BANK0:PORTD.RD5 5 PORTD bit 5 BANK0:PORTD.RD4 4 PORTD bit 4 BANK0:PORTD.RD3 3 PORTD bit 3 BANK0:PORTD.RD2 2 PORTD bit 2 BANK0:PORTD.RD1 1 PORTD bit 1 BANK0:PORTD.RD0 0 PORTD bit 0 BANK0:PORTE 0x0009 PORTE REGISTER BANK0:PORTE.RE2 2 PORTE bit 2 BANK0:PORTE.RE1 1 PORTE bit 1 BANK0:PORTE.RE0 0 PORTE bit 0 BANK0:PCLATH 0x000A Write Buffer for the upper 5 bits of the Program Counter BANK0:INTCON 0x000B INTCON REGISTER BANK0:INTCON.GIE 7 Global Interrupt Enable bit BANK0:INTCON.PEIE 6 Peripheral Interrupt Enable bit BANK0:INTCON.T0IE 5 TMR0 Overflow Interrupt Enable bit BANK0:INTCON.INTE 4 RB0/INT External Interrupt Enable bit BANK0:INTCON.RBIE 3 RB Port Change Interrupt Enable bit BANK0:INTCON.T0IF 2 TMR0 Overflow Interrupt Flag bit BANK0:INTCON.INTF 1 RB0/INT External Interrupt Flag bit BANK0:INTCON.RBIF 0 RB Port Change Interrupt Flag bit BANK0:PIR1 0x000C PIR1 REGISTER BANK0:PIR1.PSPIF 7 Parallel Slave Port Read/Write Interrupt Flag bit BANK0:PIR1.ADIF 6 A/D Converter Interrupt Flag bit BANK0:PIR1.RCIF 5 USART Receive Interrupt Flag bit BANK0:PIR1.TXIF 4 USART Transmit Interrupt Flag bit BANK0:PIR1.SSPIF 3 Synchronous Serial Port Interrupt Flag bit BANK0:PIR1.CCP1IF 2 CCP1 Interrupt Flag bit BANK0:PIR1.TMR2IF 1 TMR2 to PR2 Match Interrupt Flag bit BANK0:PIR1.TMR1IF 0 TMR1 Overflow Interrupt Flag bit BANK0:PIR2 0x000D PIR2 REGISTER BANK0:PIR2.CCP2IF 0 CCP2 Interrupt Flag bit BANK0:TMR1L 0x000E Holding register for the Least Significant Byte of the 16-bit TMR1 register BANK0:TMR1H 0x000F Holding register for the Most Significant Byte of the 16-bit TMR1 register BANK0:T1CON 0x0010 TIMER1 CONTROL REGISTER BANK0:T1CON.T1CKPS1 5 Timer1 Input Clock Prescale Select bit 1 BANK0:T1CON.T1CKPS0 4 Timer1 Input Clock Prescale Select bit 0 BANK0:T1CON.T1OSCEN 3 Timer1 Oscillator Enable Control bit BANK0:T1CON.T1SYNC 2 Timer1 External Clock Input Synchronization Control bit BANK0:T1CON.TMR1CS 1 Timer1 Clock Source Select bit BANK0:T1CON.TMR1ON 0 Timer1 On bit BANK0:TMR2 0x0011 Timer2 module's register BANK0:T2CON 0x0012 TIMER2 CONTROL REGISTER BANK0:T2CON.TOUTPS3 6 Timer2 Output Postscale Select bit 3 BANK0:T2CON.TOUTPS2 5 Timer2 Output Postscale Select bit 2 BANK0:T2CON.TOUTPS1 4 Timer2 Output Postscale Select bit 1 BANK0:T2CON.TOUTPS0 3 Timer2 Output Postscale Select bit 0 BANK0:T2CON.TMR2ON 2 Timer2 On bit BANK0:T2CON.T2CKPS1 1 Timer2 Clock Prescale Select bit 1 BANK0:T2CON.T2CKPS0 0 Timer2 Clock Prescale Select bit 0 BANK0:SSPBUF 0x0013 Synchronous Serial Port Receive Buffer/Transmit Register BANK0:SSPCON 0x0014 SYNC SERIAL PORT CONTROL REGISTER BANK0:SSPCON.WCOL 7 Write Collision Detect bit BANK0:SSPCON.SSPOV 6 Receive Overflow Indicator bit BANK0:SSPCON.SSPEN 5 Synchronous Serial Port Enable bit BANK0:SSPCON.CKP 4 Clock Polarity Select bit BANK0:SSPCON.SSPM3 3 Synchronous Serial Port Mode Select bit 3 BANK0:SSPCON.SSPM2 2 Synchronous Serial Port Mode Select bit 2 BANK0:SSPCON.SSPM1 1 Synchronous Serial Port Mode Select bit 1 BANK0:SSPCON.SSPM0 0 Synchronous Serial Port Mode Select bit 0 BANK0:CCPR1L 0x0015 Capture/Compare/PWM Register1 (LSB) BANK0:CCPR1H 0x0016 Capture/Compare/PWM Register1 (MSB) BANK0:CCP1CON 0x0017 CCP1CON REGISTER BANK0:CCP1CON.CCP1X 5 PWM Least Significant bit BANK0:CCP1CON.CCP1Y 4 PWM Least Significant bit BANK0:CCP1CON.CCP1M3 3 CCP1 Mode Select bit 3 BANK0:CCP1CON.CCP1M2 2 CCP1 Mode Select bit 2 BANK0:CCP1CON.CCP1M1 1 CCP1 Mode Select bit 1 BANK0:CCP1CON.CCP1M0 0 CCP1 Mode Select bit 0 BANK0:RCSTA 0x0018 RECEIVE STATUS AND CONTROL REGISTER BANK0:RCSTA.SPEN 7 Serial Port Enable bit BANK0:RCSTA.RX9 6 9-bit Receive Enable bit BANK0:RCSTA.SREN 5 Single Receive Enable bit BANK0:RCSTA.CREN 4 Continuous Receive Enable bit BANK0:RCSTA.FERR 2 Framing Error bit BANK0:RCSTA.OERR 1 Overrun Error bit BANK0:RCSTA.RX9D 0 9th bit of received data BANK0:TXREG 0x0019 USART Transmit Data Register BANK0:RCREG 0x001A USART Receive Data Register BANK0:CCPR2L 0x001B Capture/Compare/PWM Register2 (LSB) BANK0:CCPR2H 0x001C Capture/Compare/PWM Register2 (MSB) BANK0:CCP2CON 0x001D CCP2CON REGISTER BANK0:CCP2CON.CCP2X 5 PWM Least Significant bit BANK0:CCP2CON.CCP2Y 4 PWM Least Significant bit BANK0:CCP2CON.CCP2M3 3 CCP2 Mode Select bit 3 BANK0:CCP2CON.CCP2M2 2 CCP2 Mode Select bit 2 BANK0:CCP2CON.CCP2M1 1 CCP2 Mode Select bit 1 BANK0:CCP2CON.CCP2M0 0 CCP2 Mode Select bit 0 BANK0:ADRES 0x001E A/D Result Register BANK0:ADCON0 0x001F ADCON0 REGISTER BANK0:ADCON0.ADCS1 7 A/D Conversion Clock Select bit 1 BANK0:ADCON0.ADCS0 6 A/D Conversion Clock Select bit 0 BANK0:ADCON0.CHS2 5 Analog Channel Select bit 2 BANK0:ADCON0.CHS1 4 Analog Channel Select bit 1 BANK0:ADCON0.CHS0 3 Analog Channel Select bit 0 BANK0:ADCON0.GO_DONE 2 A/D Conversion Status bit BANK0:ADCON0.ADON 0 A/D On bit ; BANK1 (0x0080:0x0100) BANK1:INDF 0x0080 INDF (not a physical register) BANK1:OPTION 0x0081 OPTION REGISTER BANK1:OPTION.RBPU 7 PORTB Pull-up Enable bit BANK1:OPTION.INTEDG 6 Interrupt Edge Select bit BANK1:OPTION.T0CS 5 TMR0 Clock Source Select bit BANK1:OPTION.T0SE 4 TMR0 Source Edge Select bit BANK1:OPTION.PSA 3 Prescaler Assignment bit BANK1:OPTION.PS2 2 Prescaler Rate Select bit 2 BANK1:OPTION.PS1 1 Prescaler Rate Select bit 1 BANK1:OPTION.PS0 0 Prescaler Rate Select bit 0 BANK1:PCL 0x0082 Program Counter's (PC) Least Significant Byte BANK1:STATUS 0x0083 STATUS REGISTER BANK1:STATUS.IRP 7 Register Bank Select bit BANK1:STATUS.RP1 6 Register Bank Select bit 1 BANK1:STATUS.RP0 5 Register Bank Select bit 0 BANK1:STATUS.TO 4 Time-out bit BANK1:STATUS.PD 3 Power-down bit BANK1:STATUS.Z 2 Zero bit BANK1:STATUS.DC 1 Digit carry/borrow bit BANK1:STATUS.C 0 Carry/borrow bit BANK1:FSR 0x0084 Indirect data memory address pointer BANK1:TRISA 0x0085 PORTA Data Direction Register BANK1:TRISA.TRISA5 5 PORTA Data Direction Register bit 5 BANK1:TRISA.TRISA4 4 PORTA Data Direction Register bit 4 BANK1:TRISA.TRISA3 3 PORTA Data Direction Register bit 3 BANK1:TRISA.TRISA2 2 PORTA Data Direction Register bit 2 BANK1:TRISA.TRISA1 1 PORTA Data Direction Register bit 1 BANK1:TRISA.TRISA0 0 PORTA Data Direction Register bit 0 BANK1:TRISB 0x0086 PORTB Data Direction Register BANK1:TRISB.TRISB7 7 PORTB Data Direction Register bit 7 BANK1:TRISB.TRISB6 6 PORTB Data Direction Register bit 6 BANK1:TRISB.TRISB5 5 PORTB Data Direction Register bit 5 BANK1:TRISB.TRISB4 4 PORTB Data Direction Register bit 4 BANK1:TRISB.TRISB3 3 PORTB Data Direction Register bit 3 BANK1:TRISB.TRISB2 2 PORTB Data Direction Register bit 2 BANK1:TRISB.TRISB1 1 PORTB Data Direction Register bit 1 BANK1:TRISB.TRISB0 0 PORTB Data Direction Register bit 0 BANK1:TRISC 0x0087 PORTC Data Direction Register BANK1:TRISC.TRISC7 7 PORTC Data Direction Register bit 7 BANK1:TRISC.TRISC6 6 PORTC Data Direction Register bit 6 BANK1:TRISC.TRISC5 5 PORTC Data Direction Register bit 5 BANK1:TRISC.TRISC4 4 PORTC Data Direction Register bit 4 BANK1:TRISC.TRISC3 3 PORTC Data Direction Register bit 3 BANK1:TRISC.TRISC2 2 PORTC Data Direction Register bit 2 BANK1:TRISC.TRISC1 1 PORTC Data Direction Register bit 1 BANK1:TRISC.TRISC0 0 PORTC Data Direction Register bit 0 BANK1:TRISD 0x0088 PORTD Data Direction Register BANK1:TRISD.TRISD7 7 PORTD Data Direction Register bit 7 BANK1:TRISD.TRISD6 6 PORTD Data Direction Register bit 6 BANK1:TRISD.TRISD5 5 PORTD Data Direction Register bit 5 BANK1:TRISD.TRISD4 4 PORTD Data Direction Register bit 4 BANK1:TRISD.TRISD3 3 PORTD Data Direction Register bit 3 BANK1:TRISD.TRISD2 2 PORTD Data Direction Register bit 2 BANK1:TRISD.TRISD1 1 PORTD Data Direction Register bit 1 BANK1:TRISD.TRISD0 0 PORTD Data Direction Register bit 0 BANK1:TRISE 0x0089 TRISE REGISTER BANK1:TRISE.IBF 7 Input Buffer Full Status bit BANK1:TRISE.OBF 6 Output Buffer Full Status bit BANK1:TRISE.IBOV 5 Input Buffer Overflow Detect bit BANK1:TRISE.PSPMODE 4 Parallel Slave Port Mode Select bit BANK1:TRISE.TRISE2 2 Direction Control bit for pin RE2/CS/AN7 BANK1:TRISE.TRISE1 1 Direction Control bit for pin RE1/WR/AN6 BANK1:TRISE.TRISE0 0 Direction Control bit for pin RE0/RD/AN5 BANK1:PCLATH 0x008A Write Buffer for the upper 5 bits of the Program Counter BANK1:INTCON 0x008B INTCON REGISTER BANK1:INTCON.GIE 7 Global Interrupt Enable bit BANK1:INTCON.PEIE 6 Peripheral Interrupt Enable bit BANK1:INTCON.T0IE 5 TMR0 Overflow Interrupt Enable bit BANK1:INTCON.INTE 4 RB0/INT External Interrupt Enable bit BANK1:INTCON.RBIE 3 RB Port Change Interrupt Enable bit BANK1:INTCON.T0IF 2 TMR0 Overflow Interrupt Flag bit BANK1:INTCON.INTF 1 RB0/INT External Interrupt Flag bit BANK1:INTCON.RBIF 0 RB Port Change Interrupt Flag bit BANK1:PIE1 0x008C PIE1 REGISTER BANK1:PIE1.PSPIE 7 Parallel Slave Port Read/Write Interrupt Enable bit BANK1:PIE1.ADIE 6 A/D Converter Interrupt Enable bit BANK1:PIE1.RCIE 5 USART Receive Interrupt Enable bit BANK1:PIE1.TXIE 4 USART Transmit Interrupt Enable bit BANK1:PIE1.SSPIE 3 Synchronous Serial Port Interrupt Enable bit BANK1:PIE1.CCP1IE 2 CCP1 Interrupt Enable bit BANK1:PIE1.TMR2IE 1 TMR2 to PR2 Match Interrupt Enable bit BANK1:PIE1.TMR1IE 0 TMR1 Overflow Interrupt Enable bit BANK1:PIE2 0x008D PIE2 REGISTER BANK1:PIE2.CCP2IE 0 CCP2 Interrupt Enable bit BANK1:PCON 0x008E PCON REGISTER BANK1:PCON.POR 1 Power-on Reset Status bit BANK1:PCON.BOR 0 Brown-out Reset Status bit BANK1:RESERVED008F 0x008F RESERVED BANK1:RESERVED0090 0x0090 RESERVED BANK1:RESERVED0091 0x0091 RESERVED BANK1:PR2 0x0092 Timer2 Period Register BANK1:SSPADD 0x0093 Synchronous Serial Port (I2C mode) Address Register BANK1:SSPSTAT 0x0094 SYNC SERIAL PORT STATUS REGISTER BANK1:SSPSTAT.SMP 7 SPI data input sample phase BANK1:SSPSTAT.CKE 6 SPI Clock Edge Select BANK1:SSPSTAT.D_A 5 Data/Address bit (I2C mode only) BANK1:SSPSTAT.P 4 Stop bit (I2C mode only) BANK1:SSPSTAT.S 3 Start bit (I2C mode only) BANK1:SSPSTAT.R_W 2 Read/Write bit information (I2C mode only) BANK1:SSPSTAT.UA 1 Update Address (I2C mode only) BANK1:SSPSTAT.BF 0 Buffer Full Status bit BANK1:RESERVED0095 0x0095 RESERVED BANK1:RESERVED0096 0x0096 RESERVED BANK1:RESERVED0097 0x0097 RESERVED BANK1:TXSTA 0x0098 TRANSMIT STATUS AND CONTROL REGISTER BANK1:TXSTA.CSRC 7 Clock Source Select bit BANK1:TXSTA.TX9 6 9-bit Transmit Enable bit BANK1:TXSTA.TXEN 5 Transmit Enable bit BANK1:TXSTA.SYNC 4 USART Mode Select bit BANK1:TXSTA.BRGH 2 High Baud Rate Select bit BANK1:TXSTA.TRMT 1 Transmit Shift Register Status bit BANK1:TXSTA.TX9D 0 9th bit of transmit data. Can be parity bit BANK1:SPBRG 0x0099 Baud Rate Generator Register BANK1:RESERVED009A 0x009A RESERVED BANK1:RESERVED009B 0x009B RESERVED BANK1:RESERVED009C 0x009C RESERVED BANK1:RESERVED009D 0x009D RESERVED BANK1:RESERVED009E 0x009E RESERVED BANK1:ADCON1 0x009F ADCON1 REGISTER BANK1:ADCON1.PCFG2 2 A/D Port Configuration Control bit 2 BANK1:ADCON1.PCFG1 1 A/D Port Configuration Control bit 1 BANK1:ADCON1.PCFG0 0 A/D Port Configuration Control bit 0 ; BANK2 (0x0100:0x0180) BANK2:INDF 0x0100 INDF (not a physical register) BANK2:TMR0 0x0101 Timer0 module's register BANK2:PCL 0x0102 Program Counter's (PC) Least Significant Byte BANK2:STATUS 0x0103 STATUS REGISTER BANK2:STATUS.IRP 7 Register Bank Select bit BANK2:STATUS.RP1 6 Register Bank Select bit 1 BANK2:STATUS.RP0 5 Register Bank Select bit 0 BANK2:STATUS.TO 4 Time-out bit BANK2:STATUS.PD 3 Power-down bit BANK2:STATUS.Z 2 Zero bit BANK2:STATUS.DC 1 Digit carry/borrow bit BANK2:STATUS.C 0 Carry/borrow bit BANK2:FSR 0x0104 Indirect data memory address pointer BANK2:RESERVED0105 0x0105 RESERVED BANK2:PORTB 0x0106 PORTB REGISTER BANK2:PORTB.RB7 7 PORTB bit 7 BANK2:PORTB.RB6 6 PORTB bit 6 BANK2:PORTB.RB5 5 PORTB bit 5 BANK2:PORTB.RB4 4 PORTB bit 4 BANK2:PORTB.RB3 3 PORTB bit 3 BANK2:PORTB.RB2 2 PORTB bit 2 BANK2:PORTB.RB1 1 PORTB bit 1 BANK2:PORTB.RB0 0 PORTB bit 0 BANK2:RESERVED0107 0x0107 RESERVED BANK2:RESERVED0108 0x0108 RESERVED BANK2:RESERVED0109 0x0109 RESERVED BANK2:PCLATH 0x010A Write Buffer for the upper 5 bits of the Program Counter BANK2:INTCON 0x010B INTCON REGISTER BANK2:INTCON.GIE 7 Global Interrupt Enable bit BANK2:INTCON.PEIE 6 Peripheral Interrupt Enable bit BANK2:INTCON.T0IE 5 TMR0 Overflow Interrupt Enable bit BANK2:INTCON.INTE 4 RB0/INT External Interrupt Enable bit BANK2:INTCON.RBIE 3 RB Port Change Interrupt Enable bit BANK2:INTCON.T0IF 2 TMR0 Overflow Interrupt Flag bit BANK2:INTCON.INTF 1 RB0/INT External Interrupt Flag bit BANK2:INTCON.RBIF 0 RB Port Change Interrupt Flag bit BANK2:RESERVED010C 0x010C RESERVED BANK2:RESERVED010D 0x010D RESERVED BANK2:RESERVED010E 0x010E RESERVED BANK2:RESERVED010F 0x010F RESERVED ; BANK3 (0x0180:0x0200) BANK3:INDF 0x0180 INDF (not a physical register) BANK3:OPTION 0x0181 OPTION REGISTER BANK3:OPTION.RBPU 7 PORTB Pull-up Enable bit BANK3:OPTION.INTEDG 6 Interrupt Edge Select bit BANK3:OPTION.T0CS 5 TMR0 Clock Source Select bit BANK3:OPTION.T0SE 4 TMR0 Source Edge Select bit BANK3:OPTION.PSA 3 Prescaler Assignment bit BANK3:OPTION.PS2 2 Prescaler Rate Select bit 2 BANK3:OPTION.PS1 1 Prescaler Rate Select bit 1 BANK3:OPTION.PS0 0 Prescaler Rate Select bit 0 BANK3:PCL 0x0182 Program Counter's (PC) Least Significant Byte BANK3:STATUS 0x0183 STATUS REGISTER BANK3:STATUS.IRP 7 Register Bank Select bit BANK3:STATUS.RP1 6 Register Bank Select bit 1 BANK3:STATUS.RP0 5 Register Bank Select bit 0 BANK3:STATUS.TO 4 Time-out bit BANK3:STATUS.PD 3 Power-down bit BANK3:STATUS.Z 2 Zero bit BANK3:STATUS.DC 1 Digit carry/borrow bit BANK3:STATUS.C 0 Carry/borrow bit BANK3:FSR 0x0184 Indirect data memory address pointer BANK3:RESERVED0185 0x0185 RESERVED BANK3:TRISB 0x0186 PORTB Data Direction Register BANK3:TRISB.TRISB7 7 PORTB Data Direction Register bit 7 BANK3:TRISB.TRISB6 6 PORTB Data Direction Register bit 6 BANK3:TRISB.TRISB5 5 PORTB Data Direction Register bit 5 BANK3:TRISB.TRISB4 4 PORTB Data Direction Register bit 4 BANK3:TRISB.TRISB3 3 PORTB Data Direction Register bit 3 BANK3:TRISB.TRISB2 2 PORTB Data Direction Register bit 2 BANK3:TRISB.TRISB1 1 PORTB Data Direction Register bit 1 BANK3:TRISB.TRISB0 0 PORTB Data Direction Register bit 0 BANK3:RESERVED0187 0x0187 RESERVED BANK3:RESERVED0188 0x0188 RESERVED BANK3:RESERVED0189 0x0189 RESERVED BANK3:PCLATH 0x018A Write Buffer for the upper 5 bits of the Program Counter BANK3:INTCON 0x018B INTCON REGISTER BANK3:INTCON.GIE 7 Global Interrupt Enable bit BANK3:INTCON.PEIE 6 Peripheral Interrupt Enable bit BANK3:INTCON.T0IE 5 TMR0 Overflow Interrupt Enable bit BANK3:INTCON.INTE 4 RB0/INT External Interrupt Enable bit BANK3:INTCON.RBIE 3 RB Port Change Interrupt Enable bit BANK3:INTCON.T0IF 2 TMR0 Overflow Interrupt Flag bit BANK3:INTCON.INTF 1 RB0/INT External Interrupt Flag bit BANK3:INTCON.RBIF 0 RB Port Change Interrupt Flag bit BANK3:RESERVED018C 0x018C RESERVED BANK3:RESERVED018D 0x018D RESERVED BANK3:RESERVED018E 0x018E RESERVED BANK3:RESERVED018F 0x018F RESERVED .16C923 ; http://www.microchip.com/download/lit/pline/picmicro/families/16c9xx/30444e.pdf ; PIC16C923_4.pdf ; MEMORY MAP ; BANK_0 area DATA FSR_ 0x0000:0x0020 area DATA Gen_Purp 0x0020:0x0080 General Purpose Register area DATA MEM_Program0 0x0080:0x0800 On-chip Program Memory (Page 0) area DATA MEM_Program1 0x0800:0x1000 On-chip Program Memory (Page 1) ; BANK_1 ; area DATA FSR_ 0x0080:0x00A0 ; area DATA Gen_Purp 0x00A0:0x00F0 General Purpose Register ; area DATA Gen_Purp_BANK0 0x00F0:0x0100 Mapped in Bank 0 70h-7Fh ; area DATA MEM_Program0 0x0100:0x0800 On-chip Program Memory (Page 0) ; area DATA MEM_Program1 0x0800:0x1000 On-chip Program Memory (Page 1) ; BANK_2 ; area DATA FSR_ 0x0100:0x0120 ; area BSS RESERVED 0x0120:0x0170 ; area DATA Gen_Purp_BANK0 0x0170:0x0180 Mapped in Bank 0 70h-7Fh ; area DATA MEM_Program0 0x0180:0x0800 On-chip Program Memory (Page 0) ; area DATA MEM_Program1 0x0800:0x1000 On-chip Program Memory (Page 1) ; BANK_3 ; area DATA FSR_ 0x0180:0x018B ; area BSS RESERVED 0x018B:0x01F0 ; area DATA Gen_Purp_BANK0 0x01F0:0x0200 Mapped in Bank 0 70h-7Fh ; area DATA MEM_Program0 0x0200:0x0800 On-chip Program Memory (Page 0) ; area DATA MEM_Program1 0x0800:0x1000 On-chip Program Memory (Page 1) ; Interrupt and reset vector assignments interrupt RESET 0x0000 RESET ; INPUT/OUTPUT PORTS ; BANK0 (0x0000:0x0080) BANK0:INDF 0x0000 INDF (not a physical register) BANK0:TMR0 0x0001 Timer0 module's register BANK0:PCL 0x0002 Program Counter's (PC) Least Significant Byte BANK0:STATUS 0x0003 STATUS REGISTER BANK0:STATUS.IRP 7 Register Bank Select bit BANK0:STATUS.RP1 6 Register Bank Select bit 1 BANK0:STATUS.RP0 5 Register Bank Select bit 0 BANK0:STATUS.TO 4 Time-out bit BANK0:STATUS.PD 3 Power-down bit BANK0:STATUS.Z 2 Zero bit BANK0:STATUS.DC 1 Digit carry/borrow bit BANK0:STATUS.C 0 Carry/borrow bit BANK0:FSR 0x0004 Indirect data memory address pointer BANK0:PORTA 0x0005 PORTA REGISTER BANK0:PORTA.RA5 5 PORTA bit 5 BANK0:PORTA.RA4 4 PORTA bit 4 BANK0:PORTA.RA3 3 PORTA bit 3 BANK0:PORTA.RA2 2 PORTA bit 2 BANK0:PORTA.RA1 1 PORTA bit 1 BANK0:PORTA.RA0 0 PORTA bit 0 BANK0:PORTB 0x0006 PORTB REGISTER BANK0:PORTB.RB7 7 PORTB bit 7 BANK0:PORTB.RB6 6 PORTB bit 6 BANK0:PORTB.RB5 5 PORTB bit 5 BANK0:PORTB.RB4 4 PORTB bit 4 BANK0:PORTB.RB3 3 PORTB bit 3 BANK0:PORTB.RB2 2 PORTB bit 2 BANK0:PORTB.RB1 1 PORTB bit 1 BANK0:PORTB.RB0 0 PORTB bit 0 BANK0:PORTC 0x0007 PORTC REGISTER BANK0:PORTC.RC5 5 PORTC bit 5 BANK0:PORTC.RC4 4 PORTC bit 4 BANK0:PORTC.RC3 3 PORTC bit 3 BANK0:PORTC.RC2 2 PORTC bit 2 BANK0:PORTC.RC1 1 PORTC bit 1 BANK0:PORTC.RC0 0 PORTC bit 0 BANK0:PORTD 0x0008 PORTD REGISTER BANK0:PORTD.RD7 7 PORTD bit 7 BANK0:PORTD.RD6 6 PORTD bit 6 BANK0:PORTD.RD5 5 PORTD bit 5 BANK0:PORTD.RD4 4 PORTD bit 4 BANK0:PORTD.RD3 3 PORTD bit 3 BANK0:PORTD.RD2 2 PORTD bit 2 BANK0:PORTD.RD1 1 PORTD bit 1 BANK0:PORTD.RD0 0 PORTD bit 0 BANK0:PORTE 0x0009 PORTE REGISTER BANK0:PORTE.RE7 7 PORTE bit 7 BANK0:PORTE.RE6 6 PORTE bit 6 BANK0:PORTE.RE5 5 PORTE bit 5 BANK0:PORTE.RE4 4 PORTE bit 4 BANK0:PORTE.RE3 3 PORTE bit 3 BANK0:PORTE.RE2 2 PORTE bit 2 BANK0:PORTE.RE1 1 PORTE bit 1 BANK0:PORTE.RE0 0 PORTE bit 0 BANK0:PCLATH 0x000A Write Buffer for the upper 5 bits of the Program Counter BANK0:INTCON 0x000B INTCON REGISTER BANK0:INTCON.GIE 7 Global Interrupt Enable bit BANK0:INTCON.PEIE 6 Peripheral Interrupt Enable bit BANK0:INTCON.T0IE 5 TMR0 Overflow Interrupt Enable bit BANK0:INTCON.INTE 4 RB0/INT External Interrupt Enable bit BANK0:INTCON.RBIE 3 RB Port Change Interrupt Enable bit BANK0:INTCON.T0IF 2 TMR0 Overflow Interrupt Flag bit BANK0:INTCON.INTF 1 RB0/INT External Interrupt Flag bit BANK0:INTCON.RBIF 0 RB Port Change Interrupt Flag bit BANK0:PIR1 0x000C PIR1 REGISTER BANK0:PIR1.LCDIF 7 LCD Interrupt Flag bit BANK0:PIR1.SSPIF 3 Synchronous Serial Port Interrupt Flag bit BANK0:PIR1.CCP1IF 2 CCP1 Interrupt Flag bit BANK0:PIR1.TMR2IF 1 TMR2 to PR2 Match Interrupt Flag bit BANK0:PIR1.TMR1IF 0 TMR1 Overflow Interrupt Flag bit BANK0:RESERVED000D 0x000D RESERVED BANK0:TMR1L 0x000E Holding register for the Least Significant Byte of the 16-bit TMR1 register BANK0:TMR1H 0x000F Holding register for the Most Significant Byte of the 16-bit TMR1 register BANK0:T1CON 0x0010 TIMER1 CONTROL REGISTER BANK0:T1CON.T1CKPS1 5 Timer1 Input Clock Prescale Select bit 1 BANK0:T1CON.T1CKPS0 4 Timer1 Input Clock Prescale Select bit 0 BANK0:T1CON.T1OSCEN 3 Timer1 Oscillator Enable Control bit BANK0:T1CON.T1SYNC 2 Timer1 External Clock Input Synchronization Control bit BANK0:T1CON.TMR1CS 1 Timer1 Clock Source Select bit BANK0:T1CON.TMR1ON 0 Timer1 On bit BANK0:TMR2 0x0011 Timer2 module's register BANK0:T2CON 0x0012 TIMER2 CONTROL REGISTER BANK0:T2CON.TOUTPS3 6 Timer2 Output Postscale Select bit 3 BANK0:T2CON.TOUTPS2 5 Timer2 Output Postscale Select bit 2 BANK0:T2CON.TOUTPS1 4 Timer2 Output Postscale Select bit 1 BANK0:T2CON.TOUTPS0 3 Timer2 Output Postscale Select bit 0 BANK0:T2CON.TMR2ON 2 Timer2 On bit BANK0:T2CON.T2CKPS1 1 Timer2 Clock Prescale Select bit 1 BANK0:T2CON.T2CKPS0 0 Timer2 Clock Prescale Select bit 0 BANK0:SSPBUF 0x0013 Synchronous Serial Port Receive Buffer/Transmit Register BANK0:SSPCON 0x0014 SYNC SERIAL PORT CONTROL REGISTER BANK0:SSPCON.WCOL 7 Write Collision Detect bit BANK0:SSPCON.SSPOV 6 Receive Overflow Indicator bit BANK0:SSPCON.SSPEN 5 Synchronous Serial Port Enable bit BANK0:SSPCON.CKP 4 Clock Polarity Select bit BANK0:SSPCON.SSPM3 3 Synchronous Serial Port Mode Select bit 3 BANK0:SSPCON.SSPM2 2 Synchronous Serial Port Mode Select bit 2 BANK0:SSPCON.SSPM1 1 Synchronous Serial Port Mode Select bit 1 BANK0:SSPCON.SSPM0 0 Synchronous Serial Port Mode Select bit 0 BANK0:CCPR1L 0x0015 Capture/Compare/PWM Register1 (LSB) BANK0:CCPR1H 0x0016 Capture/Compare/PWM Register1 (MSB) BANK0:CCP1CON 0x0017 CCP1CON REGISTER BANK0:CCP1CON.CCP1X 5 PWM Least Significant bit BANK0:CCP1CON.CCP1Y 4 PWM Least Significant bit BANK0:CCP1CON.CCP1M3 3 CCP1 Mode Select bit 3 BANK0:CCP1CON.CCP1M2 2 CCP1 Mode Select bit 2 BANK0:CCP1CON.CCP1M1 1 CCP1 Mode Select bit 1 BANK0:CCP1CON.CCP1M0 0 CCP1 Mode Select bit 0 BANK0:RESERVED0018 0x0018 RESERVED BANK0:RESERVED0019 0x0019 RESERVED BANK0:RESERVED001A 0x001A RESERVED BANK0:RESERVED001B 0x001B RESERVED BANK0:RESERVED001C 0x001C RESERVED BANK0:RESERVED001D 0x001D RESERVED BANK0:RESERVED001E 0x001E RESERVED BANK0:RESERVED001F 0x001F RESERVED ; BANK1 (0x0080:0x0100) BANK1:INDF 0x0080 INDF (not a physical register) BANK1:OPTION 0x0081 OPTION REGISTER BANK1:OPTION.RBPU 7 PORTB Pull-up Enable bit BANK1:OPTION.INTEDG 6 Interrupt Edge Select bit BANK1:OPTION.T0CS 5 TMR0 Clock Source Select bit BANK1:OPTION.T0SE 4 TMR0 Source Edge Select bit BANK1:OPTION.PSA 3 Prescaler Assignment bit BANK1:OPTION.PS2 2 Prescaler Rate Select bit 2 BANK1:OPTION.PS1 1 Prescaler Rate Select bit 1 BANK1:OPTION.PS0 0 Prescaler Rate Select bit 0 BANK1:PCL 0x0082 Program Counter's (PC) Least Significant Byte BANK1:STATUS 0x0083 STATUS REGISTER BANK1:STATUS.IRP 7 Register Bank Select bit BANK1:STATUS.RP1 6 Register Bank Select bit 1 BANK1:STATUS.RP0 5 Register Bank Select bit 0 BANK1:STATUS.TO 4 Time-out bit BANK1:STATUS.PD 3 Power-down bit BANK1:STATUS.Z 2 Zero bit BANK1:STATUS.DC 1 Digit carry/borrow bit BANK1:STATUS.C 0 Carry/borrow bit BANK1:FSR 0x0084 Indirect data memory address pointer BANK1:TRISA 0x0085 PORTA Data Direction Register BANK1:TRISA.TRISA5 5 PORTA Data Direction Register bit 5 BANK1:TRISA.TRISA4 4 PORTA Data Direction Register bit 4 BANK1:TRISA.TRISA3 3 PORTA Data Direction Register bit 3 BANK1:TRISA.TRISA2 2 PORTA Data Direction Register bit 2 BANK1:TRISA.TRISA1 1 PORTA Data Direction Register bit 1 BANK1:TRISA.TRISA0 0 PORTA Data Direction Register bit 0 BANK1:TRISB 0x0086 PORTB Data Direction Register BANK1:TRISB.TRISB7 7 PORTB Data Direction Register bit 7 BANK1:TRISB.TRISB6 6 PORTB Data Direction Register bit 6 BANK1:TRISB.TRISB5 5 PORTB Data Direction Register bit 5 BANK1:TRISB.TRISB4 4 PORTB Data Direction Register bit 4 BANK1:TRISB.TRISB3 3 PORTB Data Direction Register bit 3 BANK1:TRISB.TRISB2 2 PORTB Data Direction Register bit 2 BANK1:TRISB.TRISB1 1 PORTB Data Direction Register bit 1 BANK1:TRISB.TRISB0 0 PORTB Data Direction Register bit 0 BANK1:TRISC 0x0087 PORTC Data Direction Register BANK1:TRISC.TRISC5 5 PORTC Data Direction Register bit 5 BANK1:TRISC.TRISC4 4 PORTC Data Direction Register bit 4 BANK1:TRISC.TRISC3 3 PORTC Data Direction Register bit 3 BANK1:TRISC.TRISC2 2 PORTC Data Direction Register bit 2 BANK1:TRISC.TRISC1 1 PORTC Data Direction Register bit 1 BANK1:TRISC.TRISC0 0 PORTC Data Direction Register bit 0 BANK1:TRISD 0x0088 PORTD Data Direction Register BANK1:TRISD.TRISD7 7 PORTD Data Direction Register bit 7 BANK1:TRISD.TRISD6 6 PORTD Data Direction Register bit 6 BANK1:TRISD.TRISD5 5 PORTD Data Direction Register bit 5 BANK1:TRISD.TRISD4 4 PORTD Data Direction Register bit 4 BANK1:TRISD.TRISD3 3 PORTD Data Direction Register bit 3 BANK1:TRISD.TRISD2 2 PORTD Data Direction Register bit 2 BANK1:TRISD.TRISD1 1 PORTD Data Direction Register bit 1 BANK1:TRISD.TRISD0 0 PORTD Data Direction Register bit 0 BANK1:TRISE 0x0089 PORTE Data Direction Register BANK1:TRISE.TRISE7 7 PORTE Data Direction Register bit 7 BANK1:TRISE.TRISE6 6 PORTE Data Direction Register bit 6 BANK1:TRISE.TRISE5 5 PORTE Data Direction Register bit 5 BANK1:TRISE.TRISE4 4 PORTE Data Direction Register bit 4 BANK1:TRISE.TRISE3 3 PORTE Data Direction Register bit 3 BANK1:TRISE.TRISE2 2 PORTE Data Direction Register bit 2 BANK1:TRISE.TRISE1 1 PORTE Data Direction Register bit 1 BANK1:TRISE.TRISE0 0 PORTE Data Direction Register bit 0 BANK1:PCLATH 0x008A Write Buffer for the upper 5 bits of the Program Counter BANK1:INTCON 0x008B INTCON REGISTER BANK1:INTCON.GIE 7 Global Interrupt Enable bit BANK1:INTCON.PEIE 6 Peripheral Interrupt Enable bit BANK1:INTCON.T0IE 5 TMR0 Overflow Interrupt Enable bit BANK1:INTCON.INTE 4 RB0/INT External Interrupt Enable bit BANK1:INTCON.RBIE 3 RB Port Change Interrupt Enable bit BANK1:INTCON.T0IF 2 TMR0 Overflow Interrupt Flag bit BANK1:INTCON.INTF 1 RB0/INT External Interrupt Flag bit BANK1:INTCON.RBIF 0 RB Port Change Interrupt Flag bit BANK1:PIE1 0x008C PIE1 REGISTER BANK1:PIE1.LCDIE 7 LCD Interrupt Enable bit BANK1:PIE1.SSPIE 3 Synchronous Serial Port Interrupt Enable bit BANK1:PIE1.CCP1IE 2 CCP1 Interrupt Enable bit BANK1:PIE1.TMR2IE 1 TMR2 to PR2 Match Interrupt Enable bit BANK1:PIE1.TMR1IE 0 TMR1 Overflow Interrupt Enable bit BANK1:RESERVED008D 0x008D RESERVED BANK1:PCON 0x008E PCON REGISTER BANK1:PCON.POR 1 Power-on Reset Status bit BANK1:RESERVED008F 0x008F RESERVED BANK1:RESERVED0090 0x0090 RESERVED BANK1:RESERVED0091 0x0091 RESERVED BANK1:PR2 0x0092 Timer2 Period Register BANK1:SSPADD 0x0093 Synchronous Serial Port (I2C mode) Address Register BANK1:SSPSTAT 0x0094 SYNC SERIAL PORT STATUS REGISTER BANK1:SSPSTAT.SMP 7 SPI data input sample phase BANK1:SSPSTAT.CKE 6 SPI Clock Edge Select BANK1:SSPSTAT.D_A 5 Data/Address bit (I2C mode only) BANK1:SSPSTAT.P 4 Stop bit (I2C mode only) BANK1:SSPSTAT.S 3 Start bit (I2C mode only) BANK1:SSPSTAT.R_W 2 Read/Write bit information (I2C mode only) BANK1:SSPSTAT.UA 1 Update Address (I2C mode only) BANK1:SSPSTAT.BF 0 Buffer Full Status bit BANK1:RESERVED0095 0x0095 RESERVED BANK1:RESERVED0096 0x0096 RESERVED BANK1:RESERVED0097 0x0097 RESERVED BANK1:RESERVED0098 0x0098 RESERVED BANK1:RESERVED0099 0x0099 RESERVED BANK1:RESERVED009A 0x009A RESERVED BANK1:RESERVED009B 0x009B RESERVED BANK1:RESERVED009C 0x009C RESERVED BANK1:RESERVED009D 0x009D RESERVED BANK1:RESERVED009E 0x009E RESERVED BANK1:RESERVED009F 0x009F RESERVED ; BANK2 (0x0100:0x0180) BANK2:INDF 0x0100 INDF (not a physical register) BANK2:TMR0 0x0101 Timer0 module's register BANK2:PCL 0x0102 Program Counter's (PC) Least Significant Byte BANK2:STATUS 0x0103 STATUS REGISTER BANK2:STATUS.IRP 7 Register Bank Select bit BANK2:STATUS.RP1 6 Register Bank Select bit 1 BANK2:STATUS.RP0 5 Register Bank Select bit 0 BANK2:STATUS.TO 4 Time-out bit BANK2:STATUS.PD 3 Power-down bit BANK2:STATUS.Z 2 Zero bit BANK2:STATUS.DC 1 Digit carry/borrow bit BANK2:STATUS.C 0 Carry/borrow bit BANK2:FSR 0x0104 Indirect data memory address pointer BANK2:RESERVED0105 0x0105 RESERVED BANK2:PORTB 0x0106 PORTB REGISTER BANK2:PORTB.RB7 7 PORTB bit 7 BANK2:PORTB.RB6 6 PORTB bit 6 BANK2:PORTB.RB5 5 PORTB bit 5 BANK2:PORTB.RB4 4 PORTB bit 4 BANK2:PORTB.RB3 3 PORTB bit 3 BANK2:PORTB.RB2 2 PORTB bit 2 BANK2:PORTB.RB1 1 PORTB bit 1 BANK2:PORTB.RB0 0 PORTB bit 0 BANK2:PORTF 0x0107 PORTF REGISTER BANK2:PORTF.RF7 7 PORTF bit 7 BANK2:PORTF.RF6 6 PORTF bit 6 BANK2:PORTF.RF5 5 PORTF bit 5 BANK2:PORTF.RF4 4 PORTF bit 4 BANK2:PORTF.RF3 3 PORTF bit 3 BANK2:PORTF.RF2 2 PORTF bit 2 BANK2:PORTF.RF1 1 PORTF bit 1 BANK2:PORTF.RF0 0 PORTF bit 0 BANK2:PORTG 0x0108 PORTG REGISTER BANK2:PORTG.RG7 7 PORTG bit 7 BANK2:PORTG.RG6 6 PORTG bit 6 BANK2:PORTG.RG5 5 PORTG bit 5 BANK2:PORTG.RG4 4 PORTG bit 4 BANK2:PORTG.RG3 3 PORTG bit 3 BANK2:PORTG.RG2 2 PORTG bit 2 BANK2:PORTG.RG1 1 PORTG bit 1 BANK2:PORTG.RG0 0 PORTG bit 0 BANK2:RESERVED0109 0x0109 RESERVED BANK2:PCLATH 0x010A Write Buffer for the upper 5 bits of the Program Counter BANK2:INTCON 0x010B INTCON REGISTER BANK2:INTCON.GIE 7 Global Interrupt Enable bit BANK2:INTCON.PEIE 6 Peripheral Interrupt Enable bit BANK2:INTCON.T0IE 5 TMR0 Overflow Interrupt Enable bit BANK2:INTCON.INTE 4 RB0/INT External Interrupt Enable bit BANK2:INTCON.RBIE 3 RB Port Change Interrupt Enable bit BANK2:INTCON.T0IF 2 TMR0 Overflow Interrupt Flag bit BANK2:INTCON.INTF 1 RB0/INT External Interrupt Flag bit BANK2:INTCON.RBIF 0 RB Port Change Interrupt Flag bit BANK2:RESERVED010C 0x010C RESERVED BANK2:LCDSE 0x010D LCDSE REGISTER BANK2:LCDSE.SE29 7 BANK2:LCDSE.SE27 6 BANK2:LCDSE.SE20 5 BANK2:LCDSE.SE16 4 BANK2:LCDSE.SE12 3 BANK2:LCDSE.SE9 2 BANK2:LCDSE.SE5 1 BANK2:LCDSE.SE0 0 BANK2:LCDPS 0x010E LCDPS REGISTER BANK2:LCDPS.LP3 3 Frame Clock Prescale Selection bit 3 BANK2:LCDPS.LP2 2 Frame Clock Prescale Selection bit 2 BANK2:LCDPS.LP1 1 Frame Clock Prescale Selection bit 1 BANK2:LCDPS.LP0 0 Frame Clock Prescale Selection bit 0 BANK2:LCDCON 0x010F LCDCON REGISTER BANK2:LCDCON.LCDEN 7 Module drive enable bit BANK2:LCDCON.SLPEN 6 LCD display sleep enable BANK2:LCDCON.VGEN 4 Voltage Generator Enable BANK2:LCDCON.CS1 3 Clock Source Select bit 1 BANK2:LCDCON.CS0 2 Clock Source Select bit 0 BANK2:LCDCON.LMUX1 1 Common Selection bit 1 BANK2:LCDCON.LMUX0 0 Common Selection bit 0 BANK2:LCDD00 0x0110 GENERIC LCDD REGISTER 00 BANK2:LCDD00.SEG07_COM0 7 BANK2:LCDD00.SEG06_COM0 6 BANK2:LCDD00.SEG05_COM0 5 BANK2:LCDD00.SEG04_COM0 4 BANK2:LCDD00.SEG03_COM0 3 BANK2:LCDD00.SEG02_COM0 2 BANK2:LCDD00.SEG01_COM0 1 BANK2:LCDD00.SEG00_COM0 0 BANK2:LCDD01 0x0111 GENERIC LCDD REGISTER 01 BANK2:LCDD01.SEG15_COM0 7 BANK2:LCDD01.SEG14_COM0 6 BANK2:LCDD01.SEG13_COM0 5 BANK2:LCDD01.SEG12_COM0 4 BANK2:LCDD01.SEG11_COM0 3 BANK2:LCDD01.SEG10_COM0 2 BANK2:LCDD01.SEG09_COM0 1 BANK2:LCDD01.SEG08_COM0 0 BANK2:LCDD02 0x0112 GENERIC LCDD REGISTER 02 BANK2:LCDD02.SEG23_COM0 7 BANK2:LCDD02.SEG22_COM0 6 BANK2:LCDD02.SEG21_COM0 5 BANK2:LCDD02.SEG20_COM0 4 BANK2:LCDD02.SEG19_COM0 3 BANK2:LCDD02.SEG18_COM0 2 BANK2:LCDD02.SEG17_COM0 1 BANK2:LCDD02.SEG16_COM0 0 BANK2:LCDD03 0x0113 GENERIC LCDD REGISTER 03 BANK2:LCDD03.SEG31_COM0 7 BANK2:LCDD03.SEG30_COM0 6 BANK2:LCDD03.SEG29_COM0 5 BANK2:LCDD03.SEG28_COM0 4 BANK2:LCDD03.SEG27_COM0 3 BANK2:LCDD03.SEG26_COM0 2 BANK2:LCDD03.SEG25_COM0 1 BANK2:LCDD03.SEG24_COM0 0 BANK2:LCDD04 0x0114 GENERIC LCDD REGISTER 04 BANK2:LCDD04.SEG07_COM1 7 BANK2:LCDD04.SEG06_COM1 6 BANK2:LCDD04.SEG05_COM1 5 BANK2:LCDD04.SEG04_COM1 4 BANK2:LCDD04.SEG03_COM1 3 BANK2:LCDD04.SEG02_COM1 2 BANK2:LCDD04.SEG01_COM1 1 BANK2:LCDD04.SEG00_COM1 0 BANK2:LCDD05 0x0115 GENERIC LCDD REGISTER 05 BANK2:LCDD05.SEG15_COM1 7 BANK2:LCDD05.SEG14_COM1 6 BANK2:LCDD05.SEG13_COM1 5 BANK2:LCDD05.SEG12_COM1 4 BANK2:LCDD05.SEG11_COM1 3 BANK2:LCDD05.SEG10_COM1 2 BANK2:LCDD05.SEG09_COM1 1 BANK2:LCDD05.SEG08_COM1 0 BANK2:LCDD06 0x0116 GENERIC LCDD REGISTER 06 BANK2:LCDD06.SEG23_COM1 7 BANK2:LCDD06.SEG22_COM1 6 BANK2:LCDD06.SEG21_COM1 5 BANK2:LCDD06.SEG20_COM1 4 BANK2:LCDD06.SEG19_COM1 3 BANK2:LCDD06.SEG18_COM1 2 BANK2:LCDD06.SEG17_COM1 1 BANK2:LCDD06.SEG16_COM1 0 BANK2:LCDD07 0x0117 GENERIC LCDD REGISTER 07 BANK2:LCDD07.SEG31_COM1 7 BANK2:LCDD07.SEG30_COM1 6 BANK2:LCDD07.SEG29_COM1 5 BANK2:LCDD07.SEG28_COM1 4 BANK2:LCDD07.SEG27_COM1 3 BANK2:LCDD07.SEG26_COM1 2 BANK2:LCDD07.SEG25_COM1 1 BANK2:LCDD07.SEG24_COM1 0 BANK2:LCDD08 0x0118 GENERIC LCDD REGISTER 08 BANK2:LCDD08.SEG07_COM2 7 BANK2:LCDD08.SEG06_COM2 6 BANK2:LCDD08.SEG05_COM2 5 BANK2:LCDD08.SEG04_COM2 4 BANK2:LCDD08.SEG03_COM2 3 BANK2:LCDD08.SEG02_COM2 2 BANK2:LCDD08.SEG01_COM2 1 BANK2:LCDD08.SEG00_COM2 0 BANK2:LCDD09 0x0119 GENERIC LCDD REGISTER 09 BANK2:LCDD09.SEG15_COM2 7 BANK2:LCDD09.SEG14_COM2 6 BANK2:LCDD09.SEG13_COM2 5 BANK2:LCDD09.SEG12_COM2 4 BANK2:LCDD09.SEG11_COM2 3 BANK2:LCDD09.SEG10_COM2 2 BANK2:LCDD09.SEG09_COM2 1 BANK2:LCDD09.SEG08_COM2 0 BANK2:LCDD10 0x011A GENERIC LCDD REGISTER 10 BANK2:LCDD10.SEG23_COM2 7 BANK2:LCDD10.SEG22_COM2 6 BANK2:LCDD10.SEG21_COM2 5 BANK2:LCDD10.SEG20_COM2 4 BANK2:LCDD10.SEG19_COM2 3 BANK2:LCDD10.SEG18_COM2 2 BANK2:LCDD10.SEG17_COM2 1 BANK2:LCDD10.SEG16_COM2 0 BANK2:LCDD11 0x011B GENERIC LCDD REGISTER 11 BANK2:LCDD11.SEG31_COM2 7 BANK2:LCDD11.SEG30_COM2 6 BANK2:LCDD11.SEG29_COM2 5 BANK2:LCDD11.SEG28_COM2 4 BANK2:LCDD11.SEG27_COM2 3 BANK2:LCDD11.SEG26_COM2 2 BANK2:LCDD11.SEG25_COM2 1 BANK2:LCDD11.SEG24_COM2 0 BANK2:LCDD12 0x011C GENERIC LCDD REGISTER 12 BANK2:LCDD12.SEG07_COM3 7 BANK2:LCDD12.SEG06_COM3 6 BANK2:LCDD12.SEG05_COM3 5 BANK2:LCDD12.SEG04_COM3 4 BANK2:LCDD12.SEG03_COM3 3 BANK2:LCDD12.SEG02_COM3 2 BANK2:LCDD12.SEG01_COM3 1 BANK2:LCDD12.SEG00_COM3 0 BANK2:LCDD13 0x011D GENERIC LCDD REGISTER 13 BANK2:LCDD13.SEG15_COM3 7 BANK2:LCDD13.SEG14_COM3 6 BANK2:LCDD13.SEG13_COM3 5 BANK2:LCDD13.SEG12_COM3 4 BANK2:LCDD13.SEG11_COM3 3 BANK2:LCDD13.SEG10_COM3 2 BANK2:LCDD13.SEG09_COM3 1 BANK2:LCDD13.SEG08_COM3 0 BANK2:LCDD14 0x011E GENERIC LCDD REGISTER 14 BANK2:LCDD14.SEG23_COM3 7 BANK2:LCDD14.SEG22_COM3 6 BANK2:LCDD14.SEG21_COM3 5 BANK2:LCDD14.SEG20_COM3 4 BANK2:LCDD14.SEG19_COM3 3 BANK2:LCDD14.SEG18_COM3 2 BANK2:LCDD14.SEG17_COM3 1 BANK2:LCDD14.SEG16_COM3 0 BANK2:LCDD15 0x011F GENERIC LCDD REGISTER 15 BANK2:LCDD15.SEG31_COM3 7 BANK2:LCDD15.SEG30_COM3 6 BANK2:LCDD15.SEG29_COM3 5 BANK2:LCDD15.SEG28_COM3 4 BANK2:LCDD15.SEG27_COM3 3 BANK2:LCDD15.SEG26_COM3 2 BANK2:LCDD15.SEG25_COM3 1 BANK2:LCDD15.SEG24_COM3 0 ; BANK3 (0x0180:0x0200) BANK3:INDF 0x0180 INDF (not a physical register) BANK3:OPTION 0x0181 OPTION REGISTER BANK3:OPTION.RBPU 7 PORTB Pull-up Enable bit BANK3:OPTION.INTEDG 6 Interrupt Edge Select bit BANK3:OPTION.T0CS 5 TMR0 Clock Source Select bit BANK3:OPTION.T0SE 4 TMR0 Source Edge Select bit BANK3:OPTION.PSA 3 Prescaler Assignment bit BANK3:OPTION.PS2 2 Prescaler Rate Select bit 2 BANK3:OPTION.PS1 1 Prescaler Rate Select bit 1 BANK3:OPTION.PS0 0 Prescaler Rate Select bit 0 BANK3:PCL 0x0182 Program Counter's (PC) Least Significant Byte BANK3:STATUS 0x0183 STATUS REGISTER BANK3:STATUS.IRP 7 Register Bank Select bit BANK3:STATUS.RP1 6 Register Bank Select bit 1 BANK3:STATUS.RP0 5 Register Bank Select bit 0 BANK3:STATUS.TO 4 Time-out bit BANK3:STATUS.PD 3 Power-down bit BANK3:STATUS.Z 2 Zero bit BANK3:STATUS.DC 1 Digit carry/borrow bit BANK3:STATUS.C 0 Carry/borrow bit BANK3:FSR 0x0184 Indirect data memory address pointer BANK3:RESERVED0185 0x0185 RESERVED BANK3:TRISB 0x0186 PORTB Data Direction Register BANK3:TRISB.TRISB7 7 PORTB Data Direction Register bit 7 BANK3:TRISB.TRISB6 6 PORTB Data Direction Register bit 6 BANK3:TRISB.TRISB5 5 PORTB Data Direction Register bit 5 BANK3:TRISB.TRISB4 4 PORTB Data Direction Register bit 4 BANK3:TRISB.TRISB3 3 PORTB Data Direction Register bit 3 BANK3:TRISB.TRISB2 2 PORTB Data Direction Register bit 2 BANK3:TRISB.TRISB1 1 PORTB Data Direction Register bit 1 BANK3:TRISB.TRISB0 0 PORTB Data Direction Register bit 0 BANK3:TRISF 0x0187 PORTF Data Direction Register BANK3:TRISF.TRISF7 7 PORTF Data Direction Register bit 7 BANK3:TRISF.TRISF6 6 PORTF Data Direction Register bit 6 BANK3:TRISF.TRISF5 5 PORTF Data Direction Register bit 5 BANK3:TRISF.TRISF4 4 PORTF Data Direction Register bit 4 BANK3:TRISF.TRISF3 3 PORTF Data Direction Register bit 3 BANK3:TRISF.TRISF2 2 PORTF Data Direction Register bit 2 BANK3:TRISF.TRISF1 1 PORTF Data Direction Register bit 1 BANK3:TRISF.TRISF0 0 PORTF Data Direction Register bit 0 BANK3:TRISG 0x0188 PORTG Data Direction Register BANK3:TRISG.TRISG7 7 PORTG Data Direction Register bit 7 BANK3:TRISG.TRISG6 6 PORTG Data Direction Register bit 6 BANK3:TRISG.TRISG5 5 PORTG Data Direction Register bit 5 BANK3:TRISG.TRISG4 4 PORTG Data Direction Register bit 4 BANK3:TRISG.TRISG3 3 PORTG Data Direction Register bit 3 BANK3:TRISG.TRISG2 2 PORTG Data Direction Register bit 2 BANK3:TRISG.TRISG1 1 PORTG Data Direction Register bit 1 BANK3:TRISG.TRISG0 0 PORTG Data Direction Register bit 0 BANK3:RESERVED0189 0x0189 RESERVED BANK3:PCLATH 0x018A Write Buffer for the upper 5 bits of the Program Counter BANK3:INTCON 0x018B INTCON REGISTER BANK3:INTCON.GIE 7 Global Interrupt Enable bit BANK3:INTCON.PEIE 6 Peripheral Interrupt Enable bit BANK3:INTCON.T0IE 5 TMR0 Overflow Interrupt Enable bit BANK3:INTCON.INTE 4 RB0/INT External Interrupt Enable bit BANK3:INTCON.RBIE 3 RB Port Change Interrupt Enable bit BANK3:INTCON.T0IF 2 TMR0 Overflow Interrupt Flag bit BANK3:INTCON.INTF 1 RB0/INT External Interrupt Flag bit BANK3:INTCON.RBIF 0 RB Port Change Interrupt Flag bit .16C924 ; http://www.microchip.com/download/lit/pline/picmicro/families/16c9xx/30444e.pdf ; PIC16C923_4.pdf ; MEMORY MAP ; BANK_0 area DATA FSR_ 0x0000:0x0020 area DATA Gen_Purp 0x0020:0x0080 General Purpose Register area DATA MEM_Program0 0x0080:0x0800 On-chip Program Memory (Page 0) area DATA MEM_Program1 0x0800:0x1000 On-chip Program Memory (Page 1) ; BANK_1 ; area DATA FSR_ 0x0080:0x00A0 ; area DATA Gen_Purp 0x00A0:0x00F0 General Purpose Register ; area DATA Gen_Purp_BANK0 0x00F0:0x0100 Mapped in Bank 0 70h-7Fh ; area DATA MEM_Program0 0x0100:0x0800 On-chip Program Memory (Page 0) ; area DATA MEM_Program1 0x0800:0x1000 On-chip Program Memory (Page 1) ; BANK_2 ; area DATA FSR_ 0x0100:0x0120 ; area BSS RESERVED 0x0120:0x0170 ; area DATA Gen_Purp_BANK0 0x0170:0x0180 Mapped in Bank 0 70h-7Fh ; area DATA MEM_Program0 0x0180:0x0800 On-chip Program Memory (Page 0) ; area DATA MEM_Program1 0x0800:0x1000 On-chip Program Memory (Page 1) ; BANK_3 ; area DATA FSR_ 0x0180:0x018B ; area BSS RESERVED 0x018B:0x01F0 ; area DATA Gen_Purp_BANK0 0x01F0:0x0200 Mapped in Bank 0 70h-7Fh ; area DATA MEM_Program0 0x0200:0x0800 On-chip Program Memory (Page 0) ; area DATA MEM_Program1 0x0800:0x1000 On-chip Program Memory (Page 1) ; Interrupt and reset vector assignments interrupt RESET 0x0000 RESET ; INPUT/OUTPUT PORTS ; BANK0 (0x0000:0x0080) BANK0:INDF 0x0000 INDF (not a physical register) BANK0:TMR0 0x0001 Timer0 module's register BANK0:PCL 0x0002 Program Counter's (PC) Least Significant Byte BANK0:STATUS 0x0003 STATUS REGISTER BANK0:STATUS.IRP 7 Register Bank Select bit BANK0:STATUS.RP1 6 Register Bank Select bit 1 BANK0:STATUS.RP0 5 Register Bank Select bit 0 BANK0:STATUS.TO 4 Time-out bit BANK0:STATUS.PD 3 Power-down bit BANK0:STATUS.Z 2 Zero bit BANK0:STATUS.DC 1 Digit carry/borrow bit BANK0:STATUS.C 0 Carry/borrow bit BANK0:FSR 0x0004 Indirect data memory address pointer BANK0:PORTA 0x0005 PORTA REGISTER BANK0:PORTA.RA5 5 PORTA bit 5 BANK0:PORTA.RA4 4 PORTA bit 4 BANK0:PORTA.RA3 3 PORTA bit 3 BANK0:PORTA.RA2 2 PORTA bit 2 BANK0:PORTA.RA1 1 PORTA bit 1 BANK0:PORTA.RA0 0 PORTA bit 0 BANK0:PORTB 0x0006 PORTB REGISTER BANK0:PORTB.RB7 7 PORTB bit 7 BANK0:PORTB.RB6 6 PORTB bit 6 BANK0:PORTB.RB5 5 PORTB bit 5 BANK0:PORTB.RB4 4 PORTB bit 4 BANK0:PORTB.RB3 3 PORTB bit 3 BANK0:PORTB.RB2 2 PORTB bit 2 BANK0:PORTB.RB1 1 PORTB bit 1 BANK0:PORTB.RB0 0 PORTB bit 0 BANK0:PORTC 0x0007 PORTC REGISTER BANK0:PORTC.RC5 5 PORTC bit 5 BANK0:PORTC.RC4 4 PORTC bit 4 BANK0:PORTC.RC3 3 PORTC bit 3 BANK0:PORTC.RC2 2 PORTC bit 2 BANK0:PORTC.RC1 1 PORTC bit 1 BANK0:PORTC.RC0 0 PORTC bit 0 BANK0:PORTD 0x0008 PORTD REGISTER BANK0:PORTD.RD7 7 PORTD bit 7 BANK0:PORTD.RD6 6 PORTD bit 6 BANK0:PORTD.RD5 5 PORTD bit 5 BANK0:PORTD.RD4 4 PORTD bit 4 BANK0:PORTD.RD3 3 PORTD bit 3 BANK0:PORTD.RD2 2 PORTD bit 2 BANK0:PORTD.RD1 1 PORTD bit 1 BANK0:PORTD.RD0 0 PORTD bit 0 BANK0:PORTE 0x0009 PORTE REGISTER BANK0:PORTE.RE7 7 PORTE bit 7 BANK0:PORTE.RE6 6 PORTE bit 6 BANK0:PORTE.RE5 5 PORTE bit 5 BANK0:PORTE.RE4 4 PORTE bit 4 BANK0:PORTE.RE3 3 PORTE bit 3 BANK0:PORTE.RE2 2 PORTE bit 2 BANK0:PORTE.RE1 1 PORTE bit 1 BANK0:PORTE.RE0 0 PORTE bit 0 BANK0:PCLATH 0x000A Write Buffer for the upper 5 bits of the Program Counter BANK0:INTCON 0x000B INTCON REGISTER BANK0:INTCON.GIE 7 Global Interrupt Enable bit BANK0:INTCON.PEIE 6 Peripheral Interrupt Enable bit BANK0:INTCON.T0IE 5 TMR0 Overflow Interrupt Enable bit BANK0:INTCON.INTE 4 RB0/INT External Interrupt Enable bit BANK0:INTCON.RBIE 3 RB Port Change Interrupt Enable bit BANK0:INTCON.T0IF 2 TMR0 Overflow Interrupt Flag bit BANK0:INTCON.INTF 1 RB0/INT External Interrupt Flag bit BANK0:INTCON.RBIF 0 RB Port Change Interrupt Flag bit BANK0:PIR1 0x000C PIR1 REGISTER BANK0:PIR1.LCDIF 7 LCD Interrupt Flag bit BANK0:PIR1.ADIF 6 A/D Converter Interrupt Flag bit BANK0:PIR1.SSPIF 3 Synchronous Serial Port Interrupt Flag bit BANK0:PIR1.CCP1IF 2 CCP1 Interrupt Flag bit BANK0:PIR1.TMR2IF 1 TMR2 to PR2 Match Interrupt Flag bit BANK0:PIR1.TMR1IF 0 TMR1 Overflow Interrupt Flag bit BANK0:RESERVED000D 0x000D RESERVED BANK0:TMR1L 0x000E Holding register for the Least Significant Byte of the 16-bit TMR1 register BANK0:TMR1H 0x000F Holding register for the Most Significant Byte of the 16-bit TMR1 register BANK0:T1CON 0x0010 TIMER1 CONTROL REGISTER BANK0:T1CON.T1CKPS1 5 Timer1 Input Clock Prescale Select bit 1 BANK0:T1CON.T1CKPS0 4 Timer1 Input Clock Prescale Select bit 0 BANK0:T1CON.T1OSCEN 3 Timer1 Oscillator Enable Control bit BANK0:T1CON.T1SYNC 2 Timer1 External Clock Input Synchronization Control bit BANK0:T1CON.TMR1CS 1 Timer1 Clock Source Select bit BANK0:T1CON.TMR1ON 0 Timer1 On bit BANK0:TMR2 0x0011 Timer2 module's register BANK0:T2CON 0x0012 TIMER2 CONTROL REGISTER BANK0:T2CON.TOUTPS3 6 Timer2 Output Postscale Select bit 3 BANK0:T2CON.TOUTPS2 5 Timer2 Output Postscale Select bit 2 BANK0:T2CON.TOUTPS1 4 Timer2 Output Postscale Select bit 1 BANK0:T2CON.TOUTPS0 3 Timer2 Output Postscale Select bit 0 BANK0:T2CON.TMR2ON 2 Timer2 On bit BANK0:T2CON.T2CKPS1 1 Timer2 Clock Prescale Select bit 1 BANK0:T2CON.T2CKPS0 0 Timer2 Clock Prescale Select bit 0 BANK0:SSPBUF 0x0013 Synchronous Serial Port Receive Buffer/Transmit Register BANK0:SSPCON 0x0014 SYNC SERIAL PORT CONTROL REGISTER BANK0:SSPCON.WCOL 7 Write Collision Detect bit BANK0:SSPCON.SSPOV 6 Receive Overflow Indicator bit BANK0:SSPCON.SSPEN 5 Synchronous Serial Port Enable bit BANK0:SSPCON.CKP 4 Clock Polarity Select bit BANK0:SSPCON.SSPM3 3 Synchronous Serial Port Mode Select bit 3 BANK0:SSPCON.SSPM2 2 Synchronous Serial Port Mode Select bit 2 BANK0:SSPCON.SSPM1 1 Synchronous Serial Port Mode Select bit 1 BANK0:SSPCON.SSPM0 0 Synchronous Serial Port Mode Select bit 0 BANK0:CCPR1L 0x0015 Capture/Compare/PWM Register1 (LSB) BANK0:CCPR1H 0x0016 Capture/Compare/PWM Register1 (MSB) BANK0:CCP1CON 0x0017 CCP1CON REGISTER BANK0:CCP1CON.CCP1X 5 PWM Least Significant bit BANK0:CCP1CON.CCP1Y 4 PWM Least Significant bit BANK0:CCP1CON.CCP1M3 3 CCP1 Mode Select bit 3 BANK0:CCP1CON.CCP1M2 2 CCP1 Mode Select bit 2 BANK0:CCP1CON.CCP1M1 1 CCP1 Mode Select bit 1 BANK0:CCP1CON.CCP1M0 0 CCP1 Mode Select bit 0 BANK0:RESERVED0018 0x0018 RESERVED BANK0:RESERVED0019 0x0019 RESERVED BANK0:RESERVED001A 0x001A RESERVED BANK0:RESERVED001B 0x001B RESERVED BANK0:RESERVED001C 0x001C RESERVED BANK0:RESERVED001D 0x001D RESERVED BANK0:ADRES 0x001E A/D Result Register BANK0:ADCON0 0x001F ADCON0 REGISTER BANK0:ADCON0.ADCS1 7 A/D Conversion Clock Select bit 1 BANK0:ADCON0.ADCS0 6 A/D Conversion Clock Select bit 0 BANK0:ADCON0.CHS2 5 Analog Channel Select bit 2 BANK0:ADCON0.CHS1 4 Analog Channel Select bit 1 BANK0:ADCON0.CHS0 3 Analog Channel Select bit 0 BANK0:ADCON0.GO_DONE 2 A/D Conversion Status bit BANK0:ADCON0.ADON 0 A/D On bit ; BANK1 (0x0080:0x0100) BANK1:INDF 0x0080 INDF (not a physical register) BANK1:OPTION 0x0081 OPTION REGISTER BANK1:OPTION.RBPU 7 PORTB Pull-up Enable bit BANK1:OPTION.INTEDG 6 Interrupt Edge Select bit BANK1:OPTION.T0CS 5 TMR0 Clock Source Select bit BANK1:OPTION.T0SE 4 TMR0 Source Edge Select bit BANK1:OPTION.PSA 3 Prescaler Assignment bit BANK1:OPTION.PS2 2 Prescaler Rate Select bit 2 BANK1:OPTION.PS1 1 Prescaler Rate Select bit 1 BANK1:OPTION.PS0 0 Prescaler Rate Select bit 0 BANK1:PCL 0x0082 Program Counter's (PC) Least Significant Byte BANK1:STATUS 0x0083 STATUS REGISTER BANK1:STATUS.IRP 7 Register Bank Select bit BANK1:STATUS.RP1 6 Register Bank Select bit 1 BANK1:STATUS.RP0 5 Register Bank Select bit 0 BANK1:STATUS.TO 4 Time-out bit BANK1:STATUS.PD 3 Power-down bit BANK1:STATUS.Z 2 Zero bit BANK1:STATUS.DC 1 Digit carry/borrow bit BANK1:STATUS.C 0 Carry/borrow bit BANK1:FSR 0x0084 Indirect data memory address pointer BANK1:TRISA 0x0085 PORTA Data Direction Register BANK1:TRISA.TRISA5 5 PORTA Data Direction Register bit 5 BANK1:TRISA.TRISA4 4 PORTA Data Direction Register bit 4 BANK1:TRISA.TRISA3 3 PORTA Data Direction Register bit 3 BANK1:TRISA.TRISA2 2 PORTA Data Direction Register bit 2 BANK1:TRISA.TRISA1 1 PORTA Data Direction Register bit 1 BANK1:TRISA.TRISA0 0 PORTA Data Direction Register bit 0 BANK1:TRISB 0x0086 PORTB Data Direction Register BANK1:TRISB.TRISB7 7 PORTB Data Direction Register bit 7 BANK1:TRISB.TRISB6 6 PORTB Data Direction Register bit 6 BANK1:TRISB.TRISB5 5 PORTB Data Direction Register bit 5 BANK1:TRISB.TRISB4 4 PORTB Data Direction Register bit 4 BANK1:TRISB.TRISB3 3 PORTB Data Direction Register bit 3 BANK1:TRISB.TRISB2 2 PORTB Data Direction Register bit 2 BANK1:TRISB.TRISB1 1 PORTB Data Direction Register bit 1 BANK1:TRISB.TRISB0 0 PORTB Data Direction Register bit 0 BANK1:TRISC 0x0087 PORTC Data Direction Register BANK1:TRISC.TRISC5 5 PORTC Data Direction Register bit 5 BANK1:TRISC.TRISC4 4 PORTC Data Direction Register bit 4 BANK1:TRISC.TRISC3 3 PORTC Data Direction Register bit 3 BANK1:TRISC.TRISC2 2 PORTC Data Direction Register bit 2 BANK1:TRISC.TRISC1 1 PORTC Data Direction Register bit 1 BANK1:TRISC.TRISC0 0 PORTC Data Direction Register bit 0 BANK1:TRISD 0x0088 PORTD Data Direction Register BANK1:TRISD.TRISD7 7 PORTD Data Direction Register bit 7 BANK1:TRISD.TRISD6 6 PORTD Data Direction Register bit 6 BANK1:TRISD.TRISD5 5 PORTD Data Direction Register bit 5 BANK1:TRISD.TRISD4 4 PORTD Data Direction Register bit 4 BANK1:TRISD.TRISD3 3 PORTD Data Direction Register bit 3 BANK1:TRISD.TRISD2 2 PORTD Data Direction Register bit 2 BANK1:TRISD.TRISD1 1 PORTD Data Direction Register bit 1 BANK1:TRISD.TRISD0 0 PORTD Data Direction Register bit 0 BANK1:TRISE 0x0089 PORTE Data Direction Register BANK1:TRISE.TRISE7 7 PORTE Data Direction Register bit 7 BANK1:TRISE.TRISE6 6 PORTE Data Direction Register bit 6 BANK1:TRISE.TRISE5 5 PORTE Data Direction Register bit 5 BANK1:TRISE.TRISE4 4 PORTE Data Direction Register bit 4 BANK1:TRISE.TRISE3 3 PORTE Data Direction Register bit 3 BANK1:TRISE.TRISE2 2 PORTE Data Direction Register bit 2 BANK1:TRISE.TRISE1 1 PORTE Data Direction Register bit 1 BANK1:TRISE.TRISE0 0 PORTE Data Direction Register bit 0 BANK1:PCLATH 0x008A Write Buffer for the upper 5 bits of the Program Counter BANK1:INTCON 0x008B INTCON REGISTER BANK1:INTCON.GIE 7 Global Interrupt Enable bit BANK1:INTCON.PEIE 6 Peripheral Interrupt Enable bit BANK1:INTCON.T0IE 5 TMR0 Overflow Interrupt Enable bit BANK1:INTCON.INTE 4 RB0/INT External Interrupt Enable bit BANK1:INTCON.RBIE 3 RB Port Change Interrupt Enable bit BANK1:INTCON.T0IF 2 TMR0 Overflow Interrupt Flag bit BANK1:INTCON.INTF 1 RB0/INT External Interrupt Flag bit BANK1:INTCON.RBIF 0 RB Port Change Interrupt Flag bit BANK1:PIE1 0x008C PIE1 REGISTER BANK1:PIE1.LCDIE 7 LCD Interrupt Enable bit BANK1:PIE1.ADIE 6 A/D Converter Interrupt Enable bit BANK1:PIE1.SSPIE 3 Synchronous Serial Port Interrupt Enable bit BANK1:PIE1.CCP1IE 2 CCP1 Interrupt Enable bit BANK1:PIE1.TMR2IE 1 TMR2 to PR2 Match Interrupt Enable bit BANK1:PIE1.TMR1IE 0 TMR1 Overflow Interrupt Enable bit BANK1:RESERVED008D 0x008D RESERVED BANK1:PCON 0x008E PCON REGISTER BANK1:PCON.POR 1 Power-on Reset Status bit BANK1:RESERVED008F 0x008F RESERVED BANK1:RESERVED0090 0x0090 RESERVED BANK1:RESERVED0091 0x0091 RESERVED BANK1:PR2 0x0092 Timer2 Period Register BANK1:SSPADD 0x0093 Synchronous Serial Port (I2C mode) Address Register BANK1:SSPSTAT 0x0094 SYNC SERIAL PORT STATUS REGISTER BANK1:SSPSTAT.SMP 7 SPI data input sample phase BANK1:SSPSTAT.CKE 6 SPI Clock Edge Select BANK1:SSPSTAT.D_A 5 Data/Address bit (I2C mode only) BANK1:SSPSTAT.P 4 Stop bit (I2C mode only) BANK1:SSPSTAT.S 3 Start bit (I2C mode only) BANK1:SSPSTAT.R_W 2 Read/Write bit information (I2C mode only) BANK1:SSPSTAT.UA 1 Update Address (I2C mode only) BANK1:SSPSTAT.BF 0 Buffer Full Status bit BANK1:RESERVED0095 0x0095 RESERVED BANK1:RESERVED0096 0x0096 RESERVED BANK1:RESERVED0097 0x0097 RESERVED BANK1:RESERVED0098 0x0098 RESERVED BANK1:RESERVED0099 0x0099 RESERVED BANK1:RESERVED009A 0x009A RESERVED BANK1:RESERVED009B 0x009B RESERVED BANK1:RESERVED009C 0x009C RESERVED BANK1:RESERVED009D 0x009D RESERVED BANK1:RESERVED009E 0x009E RESERVED BANK1:ADCON1 0x009F ADCON1 REGISTER BANK1:ADCON1.PCFG2 2 A/D Port Configuration Control bit 2 BANK1:ADCON1.PCFG1 1 A/D Port Configuration Control bit 1 BANK1:ADCON1.PCFG0 0 A/D Port Configuration Control bit 0 ; BANK2 (0x0100:0x0180) BANK2:INDF 0x0100 INDF (not a physical register) BANK2:TMR0 0x0101 Timer0 module's register BANK2:PCL 0x0102 Program Counter's (PC) Least Significant Byte BANK2:STATUS 0x0103 STATUS REGISTER BANK2:STATUS.IRP 7 Register Bank Select bit BANK2:STATUS.RP1 6 Register Bank Select bit 1 BANK2:STATUS.RP0 5 Register Bank Select bit 0 BANK2:STATUS.TO 4 Time-out bit BANK2:STATUS.PD 3 Power-down bit BANK2:STATUS.Z 2 Zero bit BANK2:STATUS.DC 1 Digit carry/borrow bit BANK2:STATUS.C 0 Carry/borrow bit BANK2:FSR 0x0104 Indirect data memory address pointer BANK2:RESERVED0105 0x0105 RESERVED BANK2:PORTB 0x0106 PORTB REGISTER BANK2:PORTB.RB7 7 PORTB bit 7 BANK2:PORTB.RB6 6 PORTB bit 6 BANK2:PORTB.RB5 5 PORTB bit 5 BANK2:PORTB.RB4 4 PORTB bit 4 BANK2:PORTB.RB3 3 PORTB bit 3 BANK2:PORTB.RB2 2 PORTB bit 2 BANK2:PORTB.RB1 1 PORTB bit 1 BANK2:PORTB.RB0 0 PORTB bit 0 BANK2:PORTF 0x0107 PORTF REGISTER BANK2:PORTF.RF7 7 PORTF bit 7 BANK2:PORTF.RF6 6 PORTF bit 6 BANK2:PORTF.RF5 5 PORTF bit 5 BANK2:PORTF.RF4 4 PORTF bit 4 BANK2:PORTF.RF3 3 PORTF bit 3 BANK2:PORTF.RF2 2 PORTF bit 2 BANK2:PORTF.RF1 1 PORTF bit 1 BANK2:PORTF.RF0 0 PORTF bit 0 BANK2:PORTG 0x0108 PORTG REGISTER BANK2:PORTG.RG7 7 PORTG bit 7 BANK2:PORTG.RG6 6 PORTG bit 6 BANK2:PORTG.RG5 5 PORTG bit 5 BANK2:PORTG.RG4 4 PORTG bit 4 BANK2:PORTG.RG3 3 PORTG bit 3 BANK2:PORTG.RG2 2 PORTG bit 2 BANK2:PORTG.RG1 1 PORTG bit 1 BANK2:PORTG.RG0 0 PORTG bit 0 BANK2:RESERVED0109 0x0109 RESERVED BANK2:PCLATH 0x010A Write Buffer for the upper 5 bits of the Program Counter BANK2:INTCON 0x010B INTCON REGISTER BANK2:INTCON.GIE 7 Global Interrupt Enable bit BANK2:INTCON.PEIE 6 Peripheral Interrupt Enable bit BANK2:INTCON.T0IE 5 TMR0 Overflow Interrupt Enable bit BANK2:INTCON.INTE 4 RB0/INT External Interrupt Enable bit BANK2:INTCON.RBIE 3 RB Port Change Interrupt Enable bit BANK2:INTCON.T0IF 2 TMR0 Overflow Interrupt Flag bit BANK2:INTCON.INTF 1 RB0/INT External Interrupt Flag bit BANK2:INTCON.RBIF 0 RB Port Change Interrupt Flag bit BANK2:RESERVED010C 0x010C RESERVED BANK2:LCDSE 0x010D LCDSE REGISTER BANK2:LCDSE.SE29 7 BANK2:LCDSE.SE27 6 BANK2:LCDSE.SE20 5 BANK2:LCDSE.SE16 4 BANK2:LCDSE.SE12 3 BANK2:LCDSE.SE9 2 BANK2:LCDSE.SE5 1 BANK2:LCDSE.SE0 0 BANK2:LCDPS 0x010E LCDPS REGISTER BANK2:LCDPS.LP3 3 Frame Clock Prescale Selection bit 3 BANK2:LCDPS.LP2 2 Frame Clock Prescale Selection bit 2 BANK2:LCDPS.LP1 1 Frame Clock Prescale Selection bit 1 BANK2:LCDPS.LP0 0 Frame Clock Prescale Selection bit 0 BANK2:LCDCON 0x010F LCDCON REGISTER BANK2:LCDCON.LCDEN 7 Module drive enable bit BANK2:LCDCON.SLPEN 6 LCD display sleep enable BANK2:LCDCON.VGEN 4 Voltage Generator Enable BANK2:LCDCON.CS1 3 Clock Source Select bit 1 BANK2:LCDCON.CS0 2 Clock Source Select bit 0 BANK2:LCDCON.LMUX1 1 Common Selection bit 1 BANK2:LCDCON.LMUX0 0 Common Selection bit 0 BANK2:LCDD00 0x0110 GENERIC LCDD REGISTER 00 BANK2:LCDD00.SEG07_COM0 7 BANK2:LCDD00.SEG06_COM0 6 BANK2:LCDD00.SEG05_COM0 5 BANK2:LCDD00.SEG04_COM0 4 BANK2:LCDD00.SEG03_COM0 3 BANK2:LCDD00.SEG02_COM0 2 BANK2:LCDD00.SEG01_COM0 1 BANK2:LCDD00.SEG00_COM0 0 BANK2:LCDD01 0x0111 GENERIC LCDD REGISTER 01 BANK2:LCDD01.SEG15_COM0 7 BANK2:LCDD01.SEG14_COM0 6 BANK2:LCDD01.SEG13_COM0 5 BANK2:LCDD01.SEG12_COM0 4 BANK2:LCDD01.SEG11_COM0 3 BANK2:LCDD01.SEG10_COM0 2 BANK2:LCDD01.SEG09_COM0 1 BANK2:LCDD01.SEG08_COM0 0 BANK2:LCDD02 0x0112 GENERIC LCDD REGISTER 02 BANK2:LCDD02.SEG23_COM0 7 BANK2:LCDD02.SEG22_COM0 6 BANK2:LCDD02.SEG21_COM0 5 BANK2:LCDD02.SEG20_COM0 4 BANK2:LCDD02.SEG19_COM0 3 BANK2:LCDD02.SEG18_COM0 2 BANK2:LCDD02.SEG17_COM0 1 BANK2:LCDD02.SEG16_COM0 0 BANK2:LCDD03 0x0113 GENERIC LCDD REGISTER 03 BANK2:LCDD03.SEG31_COM0 7 BANK2:LCDD03.SEG30_COM0 6 BANK2:LCDD03.SEG29_COM0 5 BANK2:LCDD03.SEG28_COM0 4 BANK2:LCDD03.SEG27_COM0 3 BANK2:LCDD03.SEG26_COM0 2 BANK2:LCDD03.SEG25_COM0 1 BANK2:LCDD03.SEG24_COM0 0 BANK2:LCDD04 0x0114 GENERIC LCDD REGISTER 04 BANK2:LCDD04.SEG07_COM1 7 BANK2:LCDD04.SEG06_COM1 6 BANK2:LCDD04.SEG05_COM1 5 BANK2:LCDD04.SEG04_COM1 4 BANK2:LCDD04.SEG03_COM1 3 BANK2:LCDD04.SEG02_COM1 2 BANK2:LCDD04.SEG01_COM1 1 BANK2:LCDD04.SEG00_COM1 0 BANK2:LCDD05 0x0115 GENERIC LCDD REGISTER 05 BANK2:LCDD05.SEG15_COM1 7 BANK2:LCDD05.SEG14_COM1 6 BANK2:LCDD05.SEG13_COM1 5 BANK2:LCDD05.SEG12_COM1 4 BANK2:LCDD05.SEG11_COM1 3 BANK2:LCDD05.SEG10_COM1 2 BANK2:LCDD05.SEG09_COM1 1 BANK2:LCDD05.SEG08_COM1 0 BANK2:LCDD06 0x0116 GENERIC LCDD REGISTER 06 BANK2:LCDD06.SEG23_COM1 7 BANK2:LCDD06.SEG22_COM1 6 BANK2:LCDD06.SEG21_COM1 5 BANK2:LCDD06.SEG20_COM1 4 BANK2:LCDD06.SEG19_COM1 3 BANK2:LCDD06.SEG18_COM1 2 BANK2:LCDD06.SEG17_COM1 1 BANK2:LCDD06.SEG16_COM1 0 BANK2:LCDD07 0x0117 GENERIC LCDD REGISTER 07 BANK2:LCDD07.SEG31_COM1 7 BANK2:LCDD07.SEG30_COM1 6 BANK2:LCDD07.SEG29_COM1 5 BANK2:LCDD07.SEG28_COM1 4 BANK2:LCDD07.SEG27_COM1 3 BANK2:LCDD07.SEG26_COM1 2 BANK2:LCDD07.SEG25_COM1 1 BANK2:LCDD07.SEG24_COM1 0 BANK2:LCDD08 0x0118 GENERIC LCDD REGISTER 08 BANK2:LCDD08.SEG07_COM2 7 BANK2:LCDD08.SEG06_COM2 6 BANK2:LCDD08.SEG05_COM2 5 BANK2:LCDD08.SEG04_COM2 4 BANK2:LCDD08.SEG03_COM2 3 BANK2:LCDD08.SEG02_COM2 2 BANK2:LCDD08.SEG01_COM2 1 BANK2:LCDD08.SEG00_COM2 0 BANK2:LCDD09 0x0119 GENERIC LCDD REGISTER 09 BANK2:LCDD09.SEG15_COM2 7 BANK2:LCDD09.SEG14_COM2 6 BANK2:LCDD09.SEG13_COM2 5 BANK2:LCDD09.SEG12_COM2 4 BANK2:LCDD09.SEG11_COM2 3 BANK2:LCDD09.SEG10_COM2 2 BANK2:LCDD09.SEG09_COM2 1 BANK2:LCDD09.SEG08_COM2 0 BANK2:LCDD10 0x011A GENERIC LCDD REGISTER 10 BANK2:LCDD10.SEG23_COM2 7 BANK2:LCDD10.SEG22_COM2 6 BANK2:LCDD10.SEG21_COM2 5 BANK2:LCDD10.SEG20_COM2 4 BANK2:LCDD10.SEG19_COM2 3 BANK2:LCDD10.SEG18_COM2 2 BANK2:LCDD10.SEG17_COM2 1 BANK2:LCDD10.SEG16_COM2 0 BANK2:LCDD11 0x011B GENERIC LCDD REGISTER 11 BANK2:LCDD11.SEG31_COM2 7 BANK2:LCDD11.SEG30_COM2 6 BANK2:LCDD11.SEG29_COM2 5 BANK2:LCDD11.SEG28_COM2 4 BANK2:LCDD11.SEG27_COM2 3 BANK2:LCDD11.SEG26_COM2 2 BANK2:LCDD11.SEG25_COM2 1 BANK2:LCDD11.SEG24_COM2 0 BANK2:LCDD12 0x011C GENERIC LCDD REGISTER 12 BANK2:LCDD12.SEG07_COM3 7 BANK2:LCDD12.SEG06_COM3 6 BANK2:LCDD12.SEG05_COM3 5 BANK2:LCDD12.SEG04_COM3 4 BANK2:LCDD12.SEG03_COM3 3 BANK2:LCDD12.SEG02_COM3 2 BANK2:LCDD12.SEG01_COM3 1 BANK2:LCDD12.SEG00_COM3 0 BANK2:LCDD13 0x011D GENERIC LCDD REGISTER 13 BANK2:LCDD13.SEG15_COM3 7 BANK2:LCDD13.SEG14_COM3 6 BANK2:LCDD13.SEG13_COM3 5 BANK2:LCDD13.SEG12_COM3 4 BANK2:LCDD13.SEG11_COM3 3 BANK2:LCDD13.SEG10_COM3 2 BANK2:LCDD13.SEG09_COM3 1 BANK2:LCDD13.SEG08_COM3 0 BANK2:LCDD14 0x011E GENERIC LCDD REGISTER 14 BANK2:LCDD14.SEG23_COM3 7 BANK2:LCDD14.SEG22_COM3 6 BANK2:LCDD14.SEG21_COM3 5 BANK2:LCDD14.SEG20_COM3 4 BANK2:LCDD14.SEG19_COM3 3 BANK2:LCDD14.SEG18_COM3 2 BANK2:LCDD14.SEG17_COM3 1 BANK2:LCDD14.SEG16_COM3 0 BANK2:LCDD15 0x011F GENERIC LCDD REGISTER 15 BANK2:LCDD15.SEG31_COM3 7 BANK2:LCDD15.SEG30_COM3 6 BANK2:LCDD15.SEG29_COM3 5 BANK2:LCDD15.SEG28_COM3 4 BANK2:LCDD15.SEG27_COM3 3 BANK2:LCDD15.SEG26_COM3 2 BANK2:LCDD15.SEG25_COM3 1 BANK2:LCDD15.SEG24_COM3 0 ; BANK3 (0x0180:0x0200) BANK3:INDF 0x0180 INDF (not a physical register) BANK3:OPTION 0x0181 OPTION REGISTER BANK3:OPTION.RBPU 7 PORTB Pull-up Enable bit BANK3:OPTION.INTEDG 6 Interrupt Edge Select bit BANK3:OPTION.T0CS 5 TMR0 Clock Source Select bit BANK3:OPTION.T0SE 4 TMR0 Source Edge Select bit BANK3:OPTION.PSA 3 Prescaler Assignment bit BANK3:OPTION.PS2 2 Prescaler Rate Select bit 2 BANK3:OPTION.PS1 1 Prescaler Rate Select bit 1 BANK3:OPTION.PS0 0 Prescaler Rate Select bit 0 BANK3:PCL 0x0182 Program Counter's (PC) Least Significant Byte BANK3:STATUS 0x0183 STATUS REGISTER BANK3:STATUS.IRP 7 Register Bank Select bit BANK3:STATUS.RP1 6 Register Bank Select bit 1 BANK3:STATUS.RP0 5 Register Bank Select bit 0 BANK3:STATUS.TO 4 Time-out bit BANK3:STATUS.PD 3 Power-down bit BANK3:STATUS.Z 2 Zero bit BANK3:STATUS.DC 1 Digit carry/borrow bit BANK3:STATUS.C 0 Carry/borrow bit BANK3:FSR 0x0184 Indirect data memory address pointer BANK3:RESERVED0185 0x0185 RESERVED BANK3:TRISB 0x0186 PORTB Data Direction Register BANK3:TRISB.TRISB7 7 PORTB Data Direction Register bit 7 BANK3:TRISB.TRISB6 6 PORTB Data Direction Register bit 6 BANK3:TRISB.TRISB5 5 PORTB Data Direction Register bit 5 BANK3:TRISB.TRISB4 4 PORTB Data Direction Register bit 4 BANK3:TRISB.TRISB3 3 PORTB Data Direction Register bit 3 BANK3:TRISB.TRISB2 2 PORTB Data Direction Register bit 2 BANK3:TRISB.TRISB1 1 PORTB Data Direction Register bit 1 BANK3:TRISB.TRISB0 0 PORTB Data Direction Register bit 0 BANK3:TRISF 0x0187 PORTF Data Direction Register BANK3:TRISF.TRISF7 7 PORTF Data Direction Register bit 7 BANK3:TRISF.TRISF6 6 PORTF Data Direction Register bit 6 BANK3:TRISF.TRISF5 5 PORTF Data Direction Register bit 5 BANK3:TRISF.TRISF4 4 PORTF Data Direction Register bit 4 BANK3:TRISF.TRISF3 3 PORTF Data Direction Register bit 3 BANK3:TRISF.TRISF2 2 PORTF Data Direction Register bit 2 BANK3:TRISF.TRISF1 1 PORTF Data Direction Register bit 1 BANK3:TRISF.TRISF0 0 PORTF Data Direction Register bit 0 BANK3:TRISG 0x0188 PORTG Data Direction Register BANK3:TRISG.TRISG7 7 PORTG Data Direction Register bit 7 BANK3:TRISG.TRISG6 6 PORTG Data Direction Register bit 6 BANK3:TRISG.TRISG5 5 PORTG Data Direction Register bit 5 BANK3:TRISG.TRISG4 4 PORTG Data Direction Register bit 4 BANK3:TRISG.TRISG3 3 PORTG Data Direction Register bit 3 BANK3:TRISG.TRISG2 2 PORTG Data Direction Register bit 2 BANK3:TRISG.TRISG1 1 PORTG Data Direction Register bit 1 BANK3:TRISG.TRISG0 0 PORTG Data Direction Register bit 0 BANK3:RESERVED0189 0x0189 RESERVED BANK3:PCLATH 0x018A Write Buffer for the upper 5 bits of the Program Counter BANK3:INTCON 0x018B INTCON REGISTER BANK3:INTCON.GIE 7 Global Interrupt Enable bit BANK3:INTCON.PEIE 6 Peripheral Interrupt Enable bit BANK3:INTCON.T0IE 5 TMR0 Overflow Interrupt Enable bit BANK3:INTCON.INTE 4 RB0/INT External Interrupt Enable bit BANK3:INTCON.RBIE 3 RB Port Change Interrupt Enable bit BANK3:INTCON.T0IF 2 TMR0 Overflow Interrupt Flag bit BANK3:INTCON.INTF 1 RB0/INT External Interrupt Flag bit BANK3:INTCON.RBIF 0 RB Port Change Interrupt Flag bit .16C925 ; http://www.microchip.com/download/lit/pline/picmicro/families/16c9xx/39544a.pdf ; PIC16C925_6.pdf ; MEMORY MAP ; BANK_0 area DATA FSR_ 0x0000:0x0020 area DATA Gen_Purp 0x0020:0x0080 General Purpose Register area DATA MEM_Program0 0x0080:0x0800 On-chip Program Memory (Page 0) area DATA MEM_Program1 0x0800:0x1000 On-chip Program Memory (Page 1) ; BANK_1 ; area DATA FSR_ 0x0080:0x00A0 ; area DATA Gen_Purp 0x00A0:0x00F0 General Purpose Register ; area DATA Gen_Purp_BANK0 0x00F0:0x0100 accesses 70h-7Fh ; area DATA MEM_Program0 0x0100:0x0800 On-chip Program Memory (Page 0) ; area DATA MEM_Program1 0x0800:0x1000 On-chip Program Memory (Page 1) ; BANK_2 ; area DATA FSR_ 0x0100:0x0120 ; area BSS RESERVED 0x0120:0x0170 ; area DATA Gen_Purp_BANK0 0x0170:0x0180 accesses 70h-7Fh ; area DATA MEM_Program0 0x0180:0x0800 On-chip Program Memory (Page 0) ; area DATA MEM_Program1 0x0800:0x1000 On-chip Program Memory (Page 1) ; BANK_3 ; area DATA FSR_ 0x0180:0x0190 ; area BSS RESERVED 0x0190:0x01F0 ; area DATA Gen_Purp_BANK0 0x01F0:0x0200 accesses 70h-7Fh ; area DATA MEM_Program0 0x0200:0x0800 On-chip Program Memory (Page 0) ; area DATA MEM_Program1 0x0800:0x1000 On-chip Program Memory (Page 1) ; Interrupt and reset vector assignments interrupt RESET 0x0000 RESET ; INPUT/OUTPUT PORTS ; BANK0 (0x0000:0x0080) BANK0:INDF 0x0000 INDF (not a physical register) BANK0:TMR0 0x0001 Timer0 module's register BANK0:PCL 0x0002 Program Counter's (PC) Least Significant Byte BANK0:STATUS 0x0003 STATUS REGISTER BANK0:STATUS.IRP 7 Register Bank Select bit BANK0:STATUS.RP1 6 Register Bank Select bit 1 BANK0:STATUS.RP0 5 Register Bank Select bit 0 BANK0:STATUS.TO 4 Time-out bit BANK0:STATUS.PD 3 Power-down bit BANK0:STATUS.Z 2 Zero bit BANK0:STATUS.DC 1 Digit carry/borrow bit BANK0:STATUS.C 0 Carry/borrow bit BANK0:FSR 0x0004 Indirect data memory address pointer BANK0:PORTA 0x0005 PORTA REGISTER BANK0:PORTA.RA5 5 PORTA bit 5 BANK0:PORTA.RA4 4 PORTA bit 4 BANK0:PORTA.RA3 3 PORTA bit 3 BANK0:PORTA.RA2 2 PORTA bit 2 BANK0:PORTA.RA1 1 PORTA bit 1 BANK0:PORTA.RA0 0 PORTA bit 0 BANK0:PORTB 0x0006 PORTB REGISTER BANK0:PORTB.RB7 7 PORTB bit 7 BANK0:PORTB.RB6 6 PORTB bit 6 BANK0:PORTB.RB5 5 PORTB bit 5 BANK0:PORTB.RB4 4 PORTB bit 4 BANK0:PORTB.RB3 3 PORTB bit 3 BANK0:PORTB.RB2 2 PORTB bit 2 BANK0:PORTB.RB1 1 PORTB bit 1 BANK0:PORTB.RB0 0 PORTB bit 0 BANK0:PORTC 0x0007 PORTC REGISTER BANK0:PORTC.RC5 5 PORTC bit 5 BANK0:PORTC.RC4 4 PORTC bit 4 BANK0:PORTC.RC3 3 PORTC bit 3 BANK0:PORTC.RC2 2 PORTC bit 2 BANK0:PORTC.RC1 1 PORTC bit 1 BANK0:PORTC.RC0 0 PORTC bit 0 BANK0:PORTD 0x0008 PORTD REGISTER BANK0:PORTD.RD7 7 PORTD bit 7 BANK0:PORTD.RD6 6 PORTD bit 6 BANK0:PORTD.RD5 5 PORTD bit 5 BANK0:PORTD.RD4 4 PORTD bit 4 BANK0:PORTD.RD3 3 PORTD bit 3 BANK0:PORTD.RD2 2 PORTD bit 2 BANK0:PORTD.RD1 1 PORTD bit 1 BANK0:PORTD.RD0 0 PORTD bit 0 BANK0:PORTE 0x0009 PORTE REGISTER BANK0:PORTE.RE7 7 PORTE bit 7 BANK0:PORTE.RE6 6 PORTE bit 6 BANK0:PORTE.RE5 5 PORTE bit 5 BANK0:PORTE.RE4 4 PORTE bit 4 BANK0:PORTE.RE3 3 PORTE bit 3 BANK0:PORTE.RE2 2 PORTE bit 2 BANK0:PORTE.RE1 1 PORTE bit 1 BANK0:PORTE.RE0 0 PORTE bit 0 BANK0:PCLATH 0x000A Write Buffer for the upper 5 bits of the Program Counter BANK0:INTCON 0x000B INTCON REGISTER BANK0:INTCON.GIE 7 Global Interrupt Enable bit BANK0:INTCON.PEIE 6 Peripheral Interrupt Enable bit BANK0:INTCON.TMR0IE 5 TMR0 Overflow Interrupt Enable bit BANK0:INTCON.INTE 4 RB0/INT External Interrupt Enable bit BANK0:INTCON.RBIE 3 RB Port Change Interrupt Enable bit BANK0:INTCON.TMR0IF 2 TMR0 Overflow Interrupt Flag bit BANK0:INTCON.INTF 1 RB0/INT External Interrupt Flag bit BANK0:INTCON.RBIF 0 RB Port Change Interrupt Flag bit BANK0:PIR1 0x000C PIR1 REGISTER BANK0:PIR1.LCDIF 7 LCD Interrupt Flag bit BANK0:PIR1.ADIF 6 A/D Converter Interrupt Flag bit BANK0:PIR1.SSPIF 3 Synchronous Serial Port Interrupt Flag bit BANK0:PIR1.CCP1IF 2 CCP1 Interrupt Flag bit BANK0:PIR1.TMR2IF 1 TMR2 to PR2 Match Interrupt Flag bit BANK0:PIR1.TMR1IF 0 TMR1 Overflow Interrupt Flag bit BANK0:RESERVED000D 0x000D RESERVED BANK0:TMR1L 0x000E Holding register for the Least Significant Byte of the 16-bit TMR1 register BANK0:TMR1H 0x000F Holding register for the Most Significant Byte of the 16-bit TMR1 register BANK0:T1CON 0x0010 TIMER1 CONTROL REGISTER BANK0:T1CON.T1CKPS1 5 Timer1 Input Clock Prescale Select bit 1 BANK0:T1CON.T1CKPS0 4 Timer1 Input Clock Prescale Select bit 0 BANK0:T1CON.T1OSCEN 3 Timer1 Oscillator Enable Control bit BANK0:T1CON.T1SYNC 2 Timer1 External Clock Input Synchronization Control bit BANK0:T1CON.TMR1CS 1 Timer1 Clock Source Select bit BANK0:T1CON.TMR1ON 0 Timer1 On bit BANK0:TMR2 0x0011 Timer2 module's register BANK0:T2CON 0x0012 TIMER2 CONTROL REGISTER BANK0:T2CON.TOUTPS3 6 Timer2 Output Postscale Select bit 3 BANK0:T2CON.TOUTPS2 5 Timer2 Output Postscale Select bit 2 BANK0:T2CON.TOUTPS1 4 Timer2 Output Postscale Select bit 1 BANK0:T2CON.TOUTPS0 3 Timer2 Output Postscale Select bit 0 BANK0:T2CON.TMR2ON 2 Timer2 On bit BANK0:T2CON.T2CKPS1 1 Timer2 Clock Prescale Select bit 1 BANK0:T2CON.T2CKPS0 0 Timer2 Clock Prescale Select bit 0 BANK0:SSPBUF 0x0013 Synchronous Serial Port Receive Buffer/Transmit Register BANK0:SSPCON 0x0014 SYNC SERIAL PORT CONTROL REGISTER BANK0:SSPCON.WCOL 7 Write Collision Detect bit BANK0:SSPCON.SSPOV 6 Receive Overflow Indicator bit BANK0:SSPCON.SSPEN 5 Synchronous Serial Port Enable bit BANK0:SSPCON.CKP 4 Clock Polarity Select bit BANK0:SSPCON.SSPM3 3 Synchronous Serial Port Mode Select bit 3 BANK0:SSPCON.SSPM2 2 Synchronous Serial Port Mode Select bit 2 BANK0:SSPCON.SSPM1 1 Synchronous Serial Port Mode Select bit 1 BANK0:SSPCON.SSPM0 0 Synchronous Serial Port Mode Select bit 0 BANK0:CCPR1L 0x0015 Capture/Compare/PWM Register1 (LSB) BANK0:CCPR1H 0x0016 Capture/Compare/PWM Register1 (MSB) BANK0:CCP1CON 0x0017 CCP1CON REGISTER BANK0:CCP1CON.CCP1X 5 PWM Least Significant bit BANK0:CCP1CON.CCP1Y 4 PWM Least Significant bit BANK0:CCP1CON.CCP1M3 3 CCP1 Mode Select bit 3 BANK0:CCP1CON.CCP1M2 2 CCP1 Mode Select bit 2 BANK0:CCP1CON.CCP1M1 1 CCP1 Mode Select bit 1 BANK0:CCP1CON.CCP1M0 0 CCP1 Mode Select bit 0 BANK0:RESERVED0018 0x0018 RESERVED BANK0:RESERVED0019 0x0019 RESERVED BANK0:RESERVED001A 0x001A RESERVED BANK0:RESERVED001B 0x001B RESERVED BANK0:RESERVED001C 0x001C RESERVED BANK0:RESERVED001D 0x001D RESERVED BANK0:ADRESH 0x001E A/D Result Register High BANK0:ADCON0 0x001F ADCON0 REGISTER BANK0:ADCON0.ADCS1 7 A/D Conversion Clock Select bit 1 BANK0:ADCON0.ADCS0 6 A/D Conversion Clock Select bit 0 BANK0:ADCON0.CHS2 5 Analog Channel Select bit 2 BANK0:ADCON0.CHS1 4 Analog Channel Select bit 1 BANK0:ADCON0.CHS0 3 Analog Channel Select bit 0 BANK0:ADCON0.GO_DONE 2 A/D Conversion Status bit BANK0:ADCON0.ADON 0 A/D On bit ; BANK1 (0x0080:0x0100) BANK1:INDF 0x0080 INDF (not a physical register) BANK1:OPTION 0x0081 OPTION REGISTER BANK1:OPTION.RBPU 7 PORTB Pull-up Enable bit BANK1:OPTION.INTEDG 6 Interrupt Edge Select bit BANK1:OPTION.T0CS 5 TMR0 Clock Source Select bit BANK1:OPTION.T0SE 4 TMR0 Source Edge Select bit BANK1:OPTION.PSA 3 Prescaler Assignment bit BANK1:OPTION.PS2 2 Prescaler Rate Select bit 2 BANK1:OPTION.PS1 1 Prescaler Rate Select bit 1 BANK1:OPTION.PS0 0 Prescaler Rate Select bit 0 BANK1:PCL 0x0082 Program Counter's (PC) Least Significant Byte BANK1:STATUS 0x0083 STATUS REGISTER BANK1:STATUS.IRP 7 Register Bank Select bit BANK1:STATUS.RP1 6 Register Bank Select bit 1 BANK1:STATUS.RP0 5 Register Bank Select bit 0 BANK1:STATUS.TO 4 Time-out bit BANK1:STATUS.PD 3 Power-down bit BANK1:STATUS.Z 2 Zero bit BANK1:STATUS.DC 1 Digit carry/borrow bit BANK1:STATUS.C 0 Carry/borrow bit BANK1:FSR 0x0084 Indirect data memory address pointer BANK1:TRISA 0x0085 PORTA Data Direction Register BANK1:TRISA.TRISA5 5 PORTA Data Direction Register bit 5 BANK1:TRISA.TRISA4 4 PORTA Data Direction Register bit 4 BANK1:TRISA.TRISA3 3 PORTA Data Direction Register bit 3 BANK1:TRISA.TRISA2 2 PORTA Data Direction Register bit 2 BANK1:TRISA.TRISA1 1 PORTA Data Direction Register bit 1 BANK1:TRISA.TRISA0 0 PORTA Data Direction Register bit 0 BANK1:TRISB 0x0086 PORTB Data Direction Register BANK1:TRISB.TRISB7 7 PORTB Data Direction Register bit 7 BANK1:TRISB.TRISB6 6 PORTB Data Direction Register bit 6 BANK1:TRISB.TRISB5 5 PORTB Data Direction Register bit 5 BANK1:TRISB.TRISB4 4 PORTB Data Direction Register bit 4 BANK1:TRISB.TRISB3 3 PORTB Data Direction Register bit 3 BANK1:TRISB.TRISB2 2 PORTB Data Direction Register bit 2 BANK1:TRISB.TRISB1 1 PORTB Data Direction Register bit 1 BANK1:TRISB.TRISB0 0 PORTB Data Direction Register bit 0 BANK1:TRISC 0x0087 PORTC Data Direction Register BANK1:TRISC.TRISC5 5 PORTC Data Direction Register bit 5 BANK1:TRISC.TRISC4 4 PORTC Data Direction Register bit 4 BANK1:TRISC.TRISC3 3 PORTC Data Direction Register bit 3 BANK1:TRISC.TRISC2 2 PORTC Data Direction Register bit 2 BANK1:TRISC.TRISC1 1 PORTC Data Direction Register bit 1 BANK1:TRISC.TRISC0 0 PORTC Data Direction Register bit 0 BANK1:TRISD 0x0088 PORTD Data Direction Register BANK1:TRISD.TRISD7 7 PORTD Data Direction Register bit 7 BANK1:TRISD.TRISD6 6 PORTD Data Direction Register bit 6 BANK1:TRISD.TRISD5 5 PORTD Data Direction Register bit 5 BANK1:TRISD.TRISD4 4 PORTD Data Direction Register bit 4 BANK1:TRISD.TRISD3 3 PORTD Data Direction Register bit 3 BANK1:TRISD.TRISD2 2 PORTD Data Direction Register bit 2 BANK1:TRISD.TRISD1 1 PORTD Data Direction Register bit 1 BANK1:TRISD.TRISD0 0 PORTD Data Direction Register bit 0 BANK1:TRISE 0x0089 PORTE Data Direction Register BANK1:TRISE.TRISE7 7 PORTE Data Direction Register bit 7 BANK1:TRISE.TRISE6 6 PORTE Data Direction Register bit 6 BANK1:TRISE.TRISE5 5 PORTE Data Direction Register bit 5 BANK1:TRISE.TRISE4 4 PORTE Data Direction Register bit 4 BANK1:TRISE.TRISE3 3 PORTE Data Direction Register bit 3 BANK1:TRISE.TRISE2 2 PORTE Data Direction Register bit 2 BANK1:TRISE.TRISE1 1 PORTE Data Direction Register bit 1 BANK1:TRISE.TRISE0 0 PORTE Data Direction Register bit 0 BANK1:PCLATH 0x008A Write Buffer for the upper 5 bits of the Program Counter BANK1:INTCON 0x008B INTCON REGISTER BANK1:INTCON.GIE 7 Global Interrupt Enable bit BANK1:INTCON.PEIE 6 Peripheral Interrupt Enable bit BANK1:INTCON.TMR0IE 5 TMR0 Overflow Interrupt Enable bit BANK1:INTCON.INTE 4 RB0/INT External Interrupt Enable bit BANK1:INTCON.RBIE 3 RB Port Change Interrupt Enable bit BANK1:INTCON.TMR0IF 2 TMR0 Overflow Interrupt Flag bit BANK1:INTCON.INTF 1 RB0/INT External Interrupt Flag bit BANK1:INTCON.RBIF 0 RB Port Change Interrupt Flag bit BANK1:PIE1 0x008C PIE1 REGISTER BANK1:PIE1.LCDIE 7 LCD Interrupt Enable bit BANK1:PIE1.ADIE 6 A/D Converter Interrupt Enable bit BANK1:PIE1.SSPIE 3 Synchronous Serial Port Interrupt Enable bit BANK1:PIE1.CCP1IE 2 CCP1 Interrupt Enable bit BANK1:PIE1.TMR2IE 1 TMR2 to PR2 Match Interrupt Enable bit BANK1:PIE1.TMR1IE 0 TMR1 Overflow Interrupt Enable bit BANK1:RESERVED008D 0x008D RESERVED BANK1:PCON 0x008E PCON REGISTER BANK1:PCON.POR 1 Power-on Reset Status bit BANK1:PCON.BOR 0 Brown-out Reset Status bit BANK1:RESERVED008F 0x008F RESERVED BANK1:RESERVED0090 0x0090 RESERVED BANK1:RESERVED0091 0x0091 RESERVED BANK1:PR2 0x0092 Timer2 Period Register BANK1:SSPADD 0x0093 Synchronous Serial Port (I2C mode) Address Register BANK1:SSPSTAT 0x0094 SYNC SERIAL PORT STATUS REGISTER BANK1:SSPSTAT.SMP 7 SPI data input sample phase BANK1:SSPSTAT.CKE 6 SPI Clock Edge Select BANK1:SSPSTAT.D_A 5 Data/Address bit (I2C mode only) BANK1:SSPSTAT.P 4 Stop bit (I2C mode only) BANK1:SSPSTAT.S 3 Start bit (I2C mode only) BANK1:SSPSTAT.R_W 2 Read/Write bit information (I2C mode only) BANK1:SSPSTAT.UA 1 Update Address (I2C mode only) BANK1:SSPSTAT.BF 0 Buffer Full Status bit BANK1:RESERVED0095 0x0095 RESERVED BANK1:RESERVED0096 0x0096 RESERVED BANK1:RESERVED0097 0x0097 RESERVED BANK1:RESERVED0098 0x0098 RESERVED BANK1:RESERVED0099 0x0099 RESERVED BANK1:RESERVED009A 0x009A RESERVED BANK1:RESERVED009B 0x009B RESERVED BANK1:RESERVED009C 0x009C RESERVED BANK1:RESERVED009D 0x009D RESERVED BANK0:ADRESL 0x009E A/D Result Register LOW BANK1:ADCON1 0x009F ADCON1 REGISTER BANK1:ADCON1.PCFG2 2 A/D Port Configuration Control bit 2 BANK1:ADCON1.PCFG1 1 A/D Port Configuration Control bit 1 BANK1:ADCON1.PCFG0 0 A/D Port Configuration Control bit 0 ; BANK2 (0x0100:0x0180) BANK2:INDF 0x0100 INDF (not a physical register) BANK2:TMR0 0x0101 Timer0 module's register BANK2:PCL 0x0102 Program Counter's (PC) Least Significant Byte BANK2:STATUS 0x0103 STATUS REGISTER BANK2:STATUS.IRP 7 Register Bank Select bit BANK2:STATUS.RP1 6 Register Bank Select bit 1 BANK2:STATUS.RP0 5 Register Bank Select bit 0 BANK2:STATUS.TO 4 Time-out bit BANK2:STATUS.PD 3 Power-down bit BANK2:STATUS.Z 2 Zero bit BANK2:STATUS.DC 1 Digit carry/borrow bit BANK2:STATUS.C 0 Carry/borrow bit BANK2:FSR 0x0104 Indirect data memory address pointer BANK2:RESERVED0105 0x0105 RESERVED BANK2:PORTB 0x0106 PORTB REGISTER BANK2:PORTB.RB7 7 PORTB bit 7 BANK2:PORTB.RB6 6 PORTB bit 6 BANK2:PORTB.RB5 5 PORTB bit 5 BANK2:PORTB.RB4 4 PORTB bit 4 BANK2:PORTB.RB3 3 PORTB bit 3 BANK2:PORTB.RB2 2 PORTB bit 2 BANK2:PORTB.RB1 1 PORTB bit 1 BANK2:PORTB.RB0 0 PORTB bit 0 BANK2:PORTF 0x0107 PORTF REGISTER BANK2:PORTF.RF7 7 PORTF bit 7 BANK2:PORTF.RF6 6 PORTF bit 6 BANK2:PORTF.RF5 5 PORTF bit 5 BANK2:PORTF.RF4 4 PORTF bit 4 BANK2:PORTF.RF3 3 PORTF bit 3 BANK2:PORTF.RF2 2 PORTF bit 2 BANK2:PORTF.RF1 1 PORTF bit 1 BANK2:PORTF.RF0 0 PORTF bit 0 BANK2:PORTG 0x0108 PORTG REGISTER BANK2:PORTG.RG7 7 PORTG bit 7 BANK2:PORTG.RG6 6 PORTG bit 6 BANK2:PORTG.RG5 5 PORTG bit 5 BANK2:PORTG.RG4 4 PORTG bit 4 BANK2:PORTG.RG3 3 PORTG bit 3 BANK2:PORTG.RG2 2 PORTG bit 2 BANK2:PORTG.RG1 1 PORTG bit 1 BANK2:PORTG.RG0 0 PORTG bit 0 BANK2:RESERVED0109 0x0109 RESERVED BANK2:PCLATH 0x010A Write Buffer for the upper 5 bits of the Program Counter BANK2:INTCON 0x010B INTCON REGISTER BANK2:INTCON.GIE 7 Global Interrupt Enable bit BANK2:INTCON.PEIE 6 Peripheral Interrupt Enable bit BANK2:INTCON.TMR0IE 5 TMR0 Overflow Interrupt Enable bit BANK2:INTCON.INTE 4 RB0/INT External Interrupt Enable bit BANK2:INTCON.RBIE 3 RB Port Change Interrupt Enable bit BANK2:INTCON.TMR0IF 2 TMR0 Overflow Interrupt Flag bit BANK2:INTCON.INTF 1 RB0/INT External Interrupt Flag bit BANK2:INTCON.RBIF 0 RB Port Change Interrupt Flag bit BANK2:PMCON1 0x010C PMCON1 REGISTER BANK2:PMCON1.RD 0 Read Control bit BANK2:LCDSE 0x010D LCDSE REGISTER BANK2:LCDSE.SE29 7 BANK2:LCDSE.SE27 6 BANK2:LCDSE.SE20 5 BANK2:LCDSE.SE16 4 BANK2:LCDSE.SE12 3 BANK2:LCDSE.SE9 2 BANK2:LCDSE.SE5 1 BANK2:LCDSE.SE0 0 BANK2:LCDPS 0x010E LCDPS REGISTER BANK2:LCDPS.LP3 3 Frame Clock Prescale Selection bit 3 BANK2:LCDPS.LP2 2 Frame Clock Prescale Selection bit 2 BANK2:LCDPS.LP1 1 Frame Clock Prescale Selection bit 1 BANK2:LCDPS.LP0 0 Frame Clock Prescale Selection bit 0 BANK2:LCDCON 0x010F LCDCON REGISTER BANK2:LCDCON.LCDEN 7 Module drive enable bit BANK2:LCDCON.SLPEN 6 LCD display sleep enable BANK2:LCDCON.VGEN 4 Voltage Generator Enable BANK2:LCDCON.CS1 3 Clock Source Select bit 1 BANK2:LCDCON.CS0 2 Clock Source Select bit 0 BANK2:LCDCON.LMUX1 1 Common Selection bit 1 BANK2:LCDCON.LMUX0 0 Common Selection bit 0 BANK2:LCDD00 0x0110 GENERIC LCDD REGISTER 00 BANK2:LCDD00.SEG07_COM0 7 BANK2:LCDD00.SEG06_COM0 6 BANK2:LCDD00.SEG05_COM0 5 BANK2:LCDD00.SEG04_COM0 4 BANK2:LCDD00.SEG03_COM0 3 BANK2:LCDD00.SEG02_COM0 2 BANK2:LCDD00.SEG01_COM0 1 BANK2:LCDD00.SEG00_COM0 0 BANK2:LCDD01 0x0111 GENERIC LCDD REGISTER 01 BANK2:LCDD01.SEG15_COM0 7 BANK2:LCDD01.SEG14_COM0 6 BANK2:LCDD01.SEG13_COM0 5 BANK2:LCDD01.SEG12_COM0 4 BANK2:LCDD01.SEG11_COM0 3 BANK2:LCDD01.SEG10_COM0 2 BANK2:LCDD01.SEG09_COM0 1 BANK2:LCDD01.SEG08_COM0 0 BANK2:LCDD02 0x0112 GENERIC LCDD REGISTER 02 BANK2:LCDD02.SEG23_COM0 7 BANK2:LCDD02.SEG22_COM0 6 BANK2:LCDD02.SEG21_COM0 5 BANK2:LCDD02.SEG20_COM0 4 BANK2:LCDD02.SEG19_COM0 3 BANK2:LCDD02.SEG18_COM0 2 BANK2:LCDD02.SEG17_COM0 1 BANK2:LCDD02.SEG16_COM0 0 BANK2:LCDD03 0x0113 GENERIC LCDD REGISTER 03 BANK2:LCDD03.SEG31_COM0 7 BANK2:LCDD03.SEG30_COM0 6 BANK2:LCDD03.SEG29_COM0 5 BANK2:LCDD03.SEG28_COM0 4 BANK2:LCDD03.SEG27_COM0 3 BANK2:LCDD03.SEG26_COM0 2 BANK2:LCDD03.SEG25_COM0 1 BANK2:LCDD03.SEG24_COM0 0 BANK2:LCDD04 0x0114 GENERIC LCDD REGISTER 04 BANK2:LCDD04.SEG07_COM1 7 BANK2:LCDD04.SEG06_COM1 6 BANK2:LCDD04.SEG05_COM1 5 BANK2:LCDD04.SEG04_COM1 4 BANK2:LCDD04.SEG03_COM1 3 BANK2:LCDD04.SEG02_COM1 2 BANK2:LCDD04.SEG01_COM1 1 BANK2:LCDD04.SEG00_COM1 0 BANK2:LCDD05 0x0115 GENERIC LCDD REGISTER 05 BANK2:LCDD05.SEG15_COM1 7 BANK2:LCDD05.SEG14_COM1 6 BANK2:LCDD05.SEG13_COM1 5 BANK2:LCDD05.SEG12_COM1 4 BANK2:LCDD05.SEG11_COM1 3 BANK2:LCDD05.SEG10_COM1 2 BANK2:LCDD05.SEG09_COM1 1 BANK2:LCDD05.SEG08_COM1 0 BANK2:LCDD06 0x0116 GENERIC LCDD REGISTER 06 BANK2:LCDD06.SEG23_COM1 7 BANK2:LCDD06.SEG22_COM1 6 BANK2:LCDD06.SEG21_COM1 5 BANK2:LCDD06.SEG20_COM1 4 BANK2:LCDD06.SEG19_COM1 3 BANK2:LCDD06.SEG18_COM1 2 BANK2:LCDD06.SEG17_COM1 1 BANK2:LCDD06.SEG16_COM1 0 BANK2:LCDD07 0x0117 GENERIC LCDD REGISTER 07 BANK2:LCDD07.SEG31_COM1 7 BANK2:LCDD07.SEG30_COM1 6 BANK2:LCDD07.SEG29_COM1 5 BANK2:LCDD07.SEG28_COM1 4 BANK2:LCDD07.SEG27_COM1 3 BANK2:LCDD07.SEG26_COM1 2 BANK2:LCDD07.SEG25_COM1 1 BANK2:LCDD07.SEG24_COM1 0 BANK2:LCDD08 0x0118 GENERIC LCDD REGISTER 08 BANK2:LCDD08.SEG07_COM2 7 BANK2:LCDD08.SEG06_COM2 6 BANK2:LCDD08.SEG05_COM2 5 BANK2:LCDD08.SEG04_COM2 4 BANK2:LCDD08.SEG03_COM2 3 BANK2:LCDD08.SEG02_COM2 2 BANK2:LCDD08.SEG01_COM2 1 BANK2:LCDD08.SEG00_COM2 0 BANK2:LCDD09 0x0119 GENERIC LCDD REGISTER 09 BANK2:LCDD09.SEG15_COM2 7 BANK2:LCDD09.SEG14_COM2 6 BANK2:LCDD09.SEG13_COM2 5 BANK2:LCDD09.SEG12_COM2 4 BANK2:LCDD09.SEG11_COM2 3 BANK2:LCDD09.SEG10_COM2 2 BANK2:LCDD09.SEG09_COM2 1 BANK2:LCDD09.SEG08_COM2 0 BANK2:LCDD10 0x011A GENERIC LCDD REGISTER 10 BANK2:LCDD10.SEG23_COM2 7 BANK2:LCDD10.SEG22_COM2 6 BANK2:LCDD10.SEG21_COM2 5 BANK2:LCDD10.SEG20_COM2 4 BANK2:LCDD10.SEG19_COM2 3 BANK2:LCDD10.SEG18_COM2 2 BANK2:LCDD10.SEG17_COM2 1 BANK2:LCDD10.SEG16_COM2 0 BANK2:LCDD11 0x011B GENERIC LCDD REGISTER 11 BANK2:LCDD11.SEG31_COM2 7 BANK2:LCDD11.SEG30_COM2 6 BANK2:LCDD11.SEG29_COM2 5 BANK2:LCDD11.SEG28_COM2 4 BANK2:LCDD11.SEG27_COM2 3 BANK2:LCDD11.SEG26_COM2 2 BANK2:LCDD11.SEG25_COM2 1 BANK2:LCDD11.SEG24_COM2 0 BANK2:LCDD12 0x011C GENERIC LCDD REGISTER 12 BANK2:LCDD12.SEG07_COM3 7 BANK2:LCDD12.SEG06_COM3 6 BANK2:LCDD12.SEG05_COM3 5 BANK2:LCDD12.SEG04_COM3 4 BANK2:LCDD12.SEG03_COM3 3 BANK2:LCDD12.SEG02_COM3 2 BANK2:LCDD12.SEG01_COM3 1 BANK2:LCDD12.SEG00_COM3 0 BANK2:LCDD13 0x011D GENERIC LCDD REGISTER 13 BANK2:LCDD13.SEG15_COM3 7 BANK2:LCDD13.SEG14_COM3 6 BANK2:LCDD13.SEG13_COM3 5 BANK2:LCDD13.SEG12_COM3 4 BANK2:LCDD13.SEG11_COM3 3 BANK2:LCDD13.SEG10_COM3 2 BANK2:LCDD13.SEG09_COM3 1 BANK2:LCDD13.SEG08_COM3 0 BANK2:LCDD14 0x011E GENERIC LCDD REGISTER 14 BANK2:LCDD14.SEG23_COM3 7 BANK2:LCDD14.SEG22_COM3 6 BANK2:LCDD14.SEG21_COM3 5 BANK2:LCDD14.SEG20_COM3 4 BANK2:LCDD14.SEG19_COM3 3 BANK2:LCDD14.SEG18_COM3 2 BANK2:LCDD14.SEG17_COM3 1 BANK2:LCDD14.SEG16_COM3 0 BANK2:LCDD15 0x011F GENERIC LCDD REGISTER 15 BANK2:LCDD15.SEG31_COM3 7 BANK2:LCDD15.SEG30_COM3 6 BANK2:LCDD15.SEG29_COM3 5 BANK2:LCDD15.SEG28_COM3 4 BANK2:LCDD15.SEG27_COM3 3 BANK2:LCDD15.SEG26_COM3 2 BANK2:LCDD15.SEG25_COM3 1 BANK2:LCDD15.SEG24_COM3 0 ; BANK3 (0x0180:0x0200) BANK3:INDF 0x0180 INDF (not a physical register) BANK3:OPTION 0x0181 OPTION REGISTER BANK3:OPTION.RBPU 7 PORTB Pull-up Enable bit BANK3:OPTION.INTEDG 6 Interrupt Edge Select bit BANK3:OPTION.T0CS 5 TMR0 Clock Source Select bit BANK3:OPTION.T0SE 4 TMR0 Source Edge Select bit BANK3:OPTION.PSA 3 Prescaler Assignment bit BANK3:OPTION.PS2 2 Prescaler Rate Select bit 2 BANK3:OPTION.PS1 1 Prescaler Rate Select bit 1 BANK3:OPTION.PS0 0 Prescaler Rate Select bit 0 BANK3:PCL 0x0182 Program Counter's (PC) Least Significant Byte BANK3:STATUS 0x0183 STATUS REGISTER BANK3:STATUS.IRP 7 Register Bank Select bit BANK3:STATUS.RP1 6 Register Bank Select bit 1 BANK3:STATUS.RP0 5 Register Bank Select bit 0 BANK3:STATUS.TO 4 Time-out bit BANK3:STATUS.PD 3 Power-down bit BANK3:STATUS.Z 2 Zero bit BANK3:STATUS.DC 1 Digit carry/borrow bit BANK3:STATUS.C 0 Carry/borrow bit BANK3:FSR 0x0184 Indirect data memory address pointer BANK3:RESERVED0185 0x0185 RESERVED BANK3:TRISB 0x0186 PORTB Data Direction Register BANK3:TRISB.TRISB7 7 PORTB Data Direction Register bit 7 BANK3:TRISB.TRISB6 6 PORTB Data Direction Register bit 6 BANK3:TRISB.TRISB5 5 PORTB Data Direction Register bit 5 BANK3:TRISB.TRISB4 4 PORTB Data Direction Register bit 4 BANK3:TRISB.TRISB3 3 PORTB Data Direction Register bit 3 BANK3:TRISB.TRISB2 2 PORTB Data Direction Register bit 2 BANK3:TRISB.TRISB1 1 PORTB Data Direction Register bit 1 BANK3:TRISB.TRISB0 0 PORTB Data Direction Register bit 0 BANK3:TRISF 0x0187 PORTF Data Direction Register BANK3:TRISF.TRISF7 7 PORTF Data Direction Register bit 7 BANK3:TRISF.TRISF6 6 PORTF Data Direction Register bit 6 BANK3:TRISF.TRISF5 5 PORTF Data Direction Register bit 5 BANK3:TRISF.TRISF4 4 PORTF Data Direction Register bit 4 BANK3:TRISF.TRISF3 3 PORTF Data Direction Register bit 3 BANK3:TRISF.TRISF2 2 PORTF Data Direction Register bit 2 BANK3:TRISF.TRISF1 1 PORTF Data Direction Register bit 1 BANK3:TRISF.TRISF0 0 PORTF Data Direction Register bit 0 BANK3:TRISG 0x0188 PORTG Data Direction Register BANK3:TRISG.TRISG7 7 PORTG Data Direction Register bit 7 BANK3:TRISG.TRISG6 6 PORTG Data Direction Register bit 6 BANK3:TRISG.TRISG5 5 PORTG Data Direction Register bit 5 BANK3:TRISG.TRISG4 4 PORTG Data Direction Register bit 4 BANK3:TRISG.TRISG3 3 PORTG Data Direction Register bit 3 BANK3:TRISG.TRISG2 2 PORTG Data Direction Register bit 2 BANK3:TRISG.TRISG1 1 PORTG Data Direction Register bit 1 BANK3:TRISG.TRISG0 0 PORTG Data Direction Register bit 0 BANK3:RESERVED0189 0x0189 RESERVED BANK3:PCLATH 0x018A Write Buffer for the upper 5 bits of the Program Counter BANK3:INTCON 0x018B INTCON REGISTER BANK3:INTCON.GIE 7 Global Interrupt Enable bit BANK3:INTCON.PEIE 6 Peripheral Interrupt Enable bit BANK3:INTCON.TMR0IE 5 TMR0 Overflow Interrupt Enable bit BANK3:INTCON.INTE 4 RB0/INT External Interrupt Enable bit BANK3:INTCON.RBIE 3 RB Port Change Interrupt Enable bit BANK3:INTCON.TMR0IF 2 TMR0 Overflow Interrupt Flag bit BANK3:INTCON.INTF 1 RB0/INT External Interrupt Flag bit BANK3:INTCON.RBIF 0 RB Port Change Interrupt Flag bit BANK3:PMDATA 0x018C Data Register Low Byte BANK3:PMADR 0x018D Address Register Low Byte BANK3:PMDATH 0x018E Data Register High Byte BANK3:PMADRH 0x018F Address Register High Byte .16C926 ; http://www.microchip.com/download/lit/pline/picmicro/families/16c9xx/39544a.pdf ; PIC16C925_6.pdf ; MEMORY MAP ; BANK_0 area DATA FSR_ 0x0000:0x0020 area DATA Gen_Purp 0x0020:0x0080 General Purpose Register area DATA MEM_Program0 0x0080:0x0800 On-chip Program Memory (Page 0) area DATA MEM_Program1 0x0800:0x1000 On-chip Program Memory (Page 1) area DATA MEM_Program2 0x1000:0x1800 On-chip Program Memory (Page 2) area DATA MEM_Program3 0x1800:0x2000 On-chip Program Memory (Page 3) ; BANK_1 ; area DATA FSR_ 0x0080:0x00A0 ; area DATA Gen_Purp 0x00A0:0x00F0 General Purpose Register ; area DATA Gen_Purp_BANK0 0x00F0:0x0100 accesses 70h-7Fh ; area DATA MEM_Program0 0x0100:0x0800 On-chip Program Memory (Page 0) ; area DATA MEM_Program1 0x0800:0x1000 On-chip Program Memory (Page 1) ; area DATA MEM_Program2 0x1000:0x1800 On-chip Program Memory (Page 2) ; area DATA MEM_Program3 0x1800:0x2000 On-chip Program Memory (Page 3) ; BANK_2 ; area DATA FSR_ 0x0100:0x0120 ; area DATA Gen_Purp 0x0120:0x0170 General Purpose Register ; area DATA Gen_Purp_BANK0 0x0170:0x0180 accesses 70h-7Fh ; area DATA MEM_Program0 0x0180:0x0800 On-chip Program Memory (Page 0) ; area DATA MEM_Program1 0x0800:0x1000 On-chip Program Memory (Page 1) ; area DATA MEM_Program2 0x1000:0x1800 On-chip Program Memory (Page 2) ; area DATA MEM_Program3 0x1800:0x2000 On-chip Program Memory (Page 3) ; BANK_3 ; area DATA FSR_ 0x0180:0x0190 ; area BSS RESERVED 0x0190:0x01A0 ; area DATA Gen_Purp 0x01A0:0x01F0 General Purpose Register ; area DATA Gen_Purp_BANK0 0x01F0:0x0200 accesses 70h-7Fh ; area DATA MEM_Program0 0x0200:0x0800 On-chip Program Memory (Page 0) ; area DATA MEM_Program1 0x0800:0x1000 On-chip Program Memory (Page 1) ; area DATA MEM_Program2 0x1000:0x1800 On-chip Program Memory (Page 2) ; area DATA MEM_Program3 0x1800:0x2000 On-chip Program Memory (Page 3) ; Interrupt and reset vector assignments interrupt RESET 0x0000 RESET ; INPUT/OUTPUT PORTS ; BANK0 (0x0000:0x0080) BANK0:INDF 0x0000 INDF (not a physical register) BANK0:TMR0 0x0001 Timer0 module's register BANK0:PCL 0x0002 Program Counter's (PC) Least Significant Byte BANK0:STATUS 0x0003 STATUS REGISTER BANK0:STATUS.IRP 7 Register Bank Select bit BANK0:STATUS.RP1 6 Register Bank Select bit 1 BANK0:STATUS.RP0 5 Register Bank Select bit 0 BANK0:STATUS.TO 4 Time-out bit BANK0:STATUS.PD 3 Power-down bit BANK0:STATUS.Z 2 Zero bit BANK0:STATUS.DC 1 Digit carry/borrow bit BANK0:STATUS.C 0 Carry/borrow bit BANK0:FSR 0x0004 Indirect data memory address pointer BANK0:PORTA 0x0005 PORTA REGISTER BANK0:PORTA.RA5 5 PORTA bit 5 BANK0:PORTA.RA4 4 PORTA bit 4 BANK0:PORTA.RA3 3 PORTA bit 3 BANK0:PORTA.RA2 2 PORTA bit 2 BANK0:PORTA.RA1 1 PORTA bit 1 BANK0:PORTA.RA0 0 PORTA bit 0 BANK0:PORTB 0x0006 PORTB REGISTER BANK0:PORTB.RB7 7 PORTB bit 7 BANK0:PORTB.RB6 6 PORTB bit 6 BANK0:PORTB.RB5 5 PORTB bit 5 BANK0:PORTB.RB4 4 PORTB bit 4 BANK0:PORTB.RB3 3 PORTB bit 3 BANK0:PORTB.RB2 2 PORTB bit 2 BANK0:PORTB.RB1 1 PORTB bit 1 BANK0:PORTB.RB0 0 PORTB bit 0 BANK0:PORTC 0x0007 PORTC REGISTER BANK0:PORTC.RC5 5 PORTC bit 5 BANK0:PORTC.RC4 4 PORTC bit 4 BANK0:PORTC.RC3 3 PORTC bit 3 BANK0:PORTC.RC2 2 PORTC bit 2 BANK0:PORTC.RC1 1 PORTC bit 1 BANK0:PORTC.RC0 0 PORTC bit 0 BANK0:PORTD 0x0008 PORTD REGISTER BANK0:PORTD.RD7 7 PORTD bit 7 BANK0:PORTD.RD6 6 PORTD bit 6 BANK0:PORTD.RD5 5 PORTD bit 5 BANK0:PORTD.RD4 4 PORTD bit 4 BANK0:PORTD.RD3 3 PORTD bit 3 BANK0:PORTD.RD2 2 PORTD bit 2 BANK0:PORTD.RD1 1 PORTD bit 1 BANK0:PORTD.RD0 0 PORTD bit 0 BANK0:PORTE 0x0009 PORTE REGISTER BANK0:PORTE.RE7 7 PORTE bit 7 BANK0:PORTE.RE6 6 PORTE bit 6 BANK0:PORTE.RE5 5 PORTE bit 5 BANK0:PORTE.RE4 4 PORTE bit 4 BANK0:PORTE.RE3 3 PORTE bit 3 BANK0:PORTE.RE2 2 PORTE bit 2 BANK0:PORTE.RE1 1 PORTE bit 1 BANK0:PORTE.RE0 0 PORTE bit 0 BANK0:PCLATH 0x000A Write Buffer for the upper 5 bits of the Program Counter BANK0:INTCON 0x000B INTCON REGISTER BANK0:INTCON.GIE 7 Global Interrupt Enable bit BANK0:INTCON.PEIE 6 Peripheral Interrupt Enable bit BANK0:INTCON.TMR0IE 5 TMR0 Overflow Interrupt Enable bit BANK0:INTCON.INTE 4 RB0/INT External Interrupt Enable bit BANK0:INTCON.RBIE 3 RB Port Change Interrupt Enable bit BANK0:INTCON.TMR0IF 2 TMR0 Overflow Interrupt Flag bit BANK0:INTCON.INTF 1 RB0/INT External Interrupt Flag bit BANK0:INTCON.RBIF 0 RB Port Change Interrupt Flag bit BANK0:PIR1 0x000C PIR1 REGISTER BANK0:PIR1.LCDIF 7 LCD Interrupt Flag bit BANK0:PIR1.ADIF 6 A/D Converter Interrupt Flag bit BANK0:PIR1.SSPIF 3 Synchronous Serial Port Interrupt Flag bit BANK0:PIR1.CCP1IF 2 CCP1 Interrupt Flag bit BANK0:PIR1.TMR2IF 1 TMR2 to PR2 Match Interrupt Flag bit BANK0:PIR1.TMR1IF 0 TMR1 Overflow Interrupt Flag bit BANK0:RESERVED000D 0x000D RESERVED BANK0:TMR1L 0x000E Holding register for the Least Significant Byte of the 16-bit TMR1 register BANK0:TMR1H 0x000F Holding register for the Most Significant Byte of the 16-bit TMR1 register BANK0:T1CON 0x0010 TIMER1 CONTROL REGISTER BANK0:T1CON.T1CKPS1 5 Timer1 Input Clock Prescale Select bit 1 BANK0:T1CON.T1CKPS0 4 Timer1 Input Clock Prescale Select bit 0 BANK0:T1CON.T1OSCEN 3 Timer1 Oscillator Enable Control bit BANK0:T1CON.T1SYNC 2 Timer1 External Clock Input Synchronization Control bit BANK0:T1CON.TMR1CS 1 Timer1 Clock Source Select bit BANK0:T1CON.TMR1ON 0 Timer1 On bit BANK0:TMR2 0x0011 Timer2 module's register BANK0:T2CON 0x0012 TIMER2 CONTROL REGISTER BANK0:T2CON.TOUTPS3 6 Timer2 Output Postscale Select bit 3 BANK0:T2CON.TOUTPS2 5 Timer2 Output Postscale Select bit 2 BANK0:T2CON.TOUTPS1 4 Timer2 Output Postscale Select bit 1 BANK0:T2CON.TOUTPS0 3 Timer2 Output Postscale Select bit 0 BANK0:T2CON.TMR2ON 2 Timer2 On bit BANK0:T2CON.T2CKPS1 1 Timer2 Clock Prescale Select bit 1 BANK0:T2CON.T2CKPS0 0 Timer2 Clock Prescale Select bit 0 BANK0:SSPBUF 0x0013 Synchronous Serial Port Receive Buffer/Transmit Register BANK0:SSPCON 0x0014 SYNC SERIAL PORT CONTROL REGISTER BANK0:SSPCON.WCOL 7 Write Collision Detect bit BANK0:SSPCON.SSPOV 6 Receive Overflow Indicator bit BANK0:SSPCON.SSPEN 5 Synchronous Serial Port Enable bit BANK0:SSPCON.CKP 4 Clock Polarity Select bit BANK0:SSPCON.SSPM3 3 Synchronous Serial Port Mode Select bit 3 BANK0:SSPCON.SSPM2 2 Synchronous Serial Port Mode Select bit 2 BANK0:SSPCON.SSPM1 1 Synchronous Serial Port Mode Select bit 1 BANK0:SSPCON.SSPM0 0 Synchronous Serial Port Mode Select bit 0 BANK0:CCPR1L 0x0015 Capture/Compare/PWM Register1 (LSB) BANK0:CCPR1H 0x0016 Capture/Compare/PWM Register1 (MSB) BANK0:CCP1CON 0x0017 CCP1CON REGISTER BANK0:CCP1CON.CCP1X 5 PWM Least Significant bit BANK0:CCP1CON.CCP1Y 4 PWM Least Significant bit BANK0:CCP1CON.CCP1M3 3 CCP1 Mode Select bit 3 BANK0:CCP1CON.CCP1M2 2 CCP1 Mode Select bit 2 BANK0:CCP1CON.CCP1M1 1 CCP1 Mode Select bit 1 BANK0:CCP1CON.CCP1M0 0 CCP1 Mode Select bit 0 BANK0:RESERVED0018 0x0018 RESERVED BANK0:RESERVED0019 0x0019 RESERVED BANK0:RESERVED001A 0x001A RESERVED BANK0:RESERVED001B 0x001B RESERVED BANK0:RESERVED001C 0x001C RESERVED BANK0:RESERVED001D 0x001D RESERVED BANK0:ADRESH 0x001E A/D Result Register High BANK0:ADCON0 0x001F ADCON0 REGISTER BANK0:ADCON0.ADCS1 7 A/D Conversion Clock Select bit 1 BANK0:ADCON0.ADCS0 6 A/D Conversion Clock Select bit 0 BANK0:ADCON0.CHS2 5 Analog Channel Select bit 2 BANK0:ADCON0.CHS1 4 Analog Channel Select bit 1 BANK0:ADCON0.CHS0 3 Analog Channel Select bit 0 BANK0:ADCON0.GO_DONE 2 A/D Conversion Status bit BANK0:ADCON0.ADON 0 A/D On bit ; BANK1 (0x0080:0x0200) BANK1:INDF 0x0080 INDF (not a physical register) BANK1:OPTION 0x0081 OPTION REGISTER BANK1:OPTION.RBPU 7 PORTB Pull-up Enable bit BANK1:OPTION.INTEDG 6 Interrupt Edge Select bit BANK1:OPTION.T0CS 5 TMR0 Clock Source Select bit BANK1:OPTION.T0SE 4 TMR0 Source Edge Select bit BANK1:OPTION.PSA 3 Prescaler Assignment bit BANK1:OPTION.PS2 2 Prescaler Rate Select bit 2 BANK1:OPTION.PS1 1 Prescaler Rate Select bit 1 BANK1:OPTION.PS0 0 Prescaler Rate Select bit 0 BANK1:PCL 0x0082 Program Counter's (PC) Least Significant Byte BANK1:STATUS 0x0083 STATUS REGISTER BANK1:STATUS.IRP 7 Register Bank Select bit BANK1:STATUS.RP1 6 Register Bank Select bit 1 BANK1:STATUS.RP0 5 Register Bank Select bit 0 BANK1:STATUS.TO 4 Time-out bit BANK1:STATUS.PD 3 Power-down bit BANK1:STATUS.Z 2 Zero bit BANK1:STATUS.DC 1 Digit carry/borrow bit BANK1:STATUS.C 0 Carry/borrow bit BANK1:FSR 0x0084 Indirect data memory address pointer BANK1:TRISA 0x0085 PORTA Data Direction Register BANK1:TRISA.TRISA5 5 PORTA Data Direction Register bit 5 BANK1:TRISA.TRISA4 4 PORTA Data Direction Register bit 4 BANK1:TRISA.TRISA3 3 PORTA Data Direction Register bit 3 BANK1:TRISA.TRISA2 2 PORTA Data Direction Register bit 2 BANK1:TRISA.TRISA1 1 PORTA Data Direction Register bit 1 BANK1:TRISA.TRISA0 0 PORTA Data Direction Register bit 0 BANK1:TRISB 0x0086 PORTB Data Direction Register BANK1:TRISB.TRISB7 7 PORTB Data Direction Register bit 7 BANK1:TRISB.TRISB6 6 PORTB Data Direction Register bit 6 BANK1:TRISB.TRISB5 5 PORTB Data Direction Register bit 5 BANK1:TRISB.TRISB4 4 PORTB Data Direction Register bit 4 BANK1:TRISB.TRISB3 3 PORTB Data Direction Register bit 3 BANK1:TRISB.TRISB2 2 PORTB Data Direction Register bit 2 BANK1:TRISB.TRISB1 1 PORTB Data Direction Register bit 1 BANK1:TRISB.TRISB0 0 PORTB Data Direction Register bit 0 BANK1:TRISC 0x0087 PORTC Data Direction Register BANK1:TRISC.TRISC5 5 PORTC Data Direction Register bit 5 BANK1:TRISC.TRISC4 4 PORTC Data Direction Register bit 4 BANK1:TRISC.TRISC3 3 PORTC Data Direction Register bit 3 BANK1:TRISC.TRISC2 2 PORTC Data Direction Register bit 2 BANK1:TRISC.TRISC1 1 PORTC Data Direction Register bit 1 BANK1:TRISC.TRISC0 0 PORTC Data Direction Register bit 0 BANK1:TRISD 0x0088 PORTD Data Direction Register BANK1:TRISD.TRISD7 7 PORTD Data Direction Register bit 7 BANK1:TRISD.TRISD6 6 PORTD Data Direction Register bit 6 BANK1:TRISD.TRISD5 5 PORTD Data Direction Register bit 5 BANK1:TRISD.TRISD4 4 PORTD Data Direction Register bit 4 BANK1:TRISD.TRISD3 3 PORTD Data Direction Register bit 3 BANK1:TRISD.TRISD2 2 PORTD Data Direction Register bit 2 BANK1:TRISD.TRISD1 1 PORTD Data Direction Register bit 1 BANK1:TRISD.TRISD0 0 PORTD Data Direction Register bit 0 BANK1:TRISE 0x0089 PORTE Data Direction Register BANK1:TRISE.TRISE7 7 PORTE Data Direction Register bit 7 BANK1:TRISE.TRISE6 6 PORTE Data Direction Register bit 6 BANK1:TRISE.TRISE5 5 PORTE Data Direction Register bit 5 BANK1:TRISE.TRISE4 4 PORTE Data Direction Register bit 4 BANK1:TRISE.TRISE3 3 PORTE Data Direction Register bit 3 BANK1:TRISE.TRISE2 2 PORTE Data Direction Register bit 2 BANK1:TRISE.TRISE1 1 PORTE Data Direction Register bit 1 BANK1:TRISE.TRISE0 0 PORTE Data Direction Register bit 0 BANK1:PCLATH 0x008A Write Buffer for the upper 5 bits of the Program Counter BANK1:INTCON 0x008B INTCON REGISTER BANK1:INTCON.GIE 7 Global Interrupt Enable bit BANK1:INTCON.PEIE 6 Peripheral Interrupt Enable bit BANK1:INTCON.TMR0IE 5 TMR0 Overflow Interrupt Enable bit BANK1:INTCON.INTE 4 RB0/INT External Interrupt Enable bit BANK1:INTCON.RBIE 3 RB Port Change Interrupt Enable bit BANK1:INTCON.TMR0IF 2 TMR0 Overflow Interrupt Flag bit BANK1:INTCON.INTF 1 RB0/INT External Interrupt Flag bit BANK1:INTCON.RBIF 0 RB Port Change Interrupt Flag bit BANK1:PIE1 0x008C PIE1 REGISTER BANK1:PIE1.LCDIE 7 LCD Interrupt Enable bit BANK1:PIE1.ADIE 6 A/D Converter Interrupt Enable bit BANK1:PIE1.SSPIE 3 Synchronous Serial Port Interrupt Enable bit BANK1:PIE1.CCP1IE 2 CCP1 Interrupt Enable bit BANK1:PIE1.TMR2IE 1 TMR2 to PR2 Match Interrupt Enable bit BANK1:PIE1.TMR1IE 0 TMR1 Overflow Interrupt Enable bit BANK1:RESERVED008D 0x008D RESERVED BANK1:PCON 0x008E PCON REGISTER BANK1:PCON.POR 1 Power-on Reset Status bit BANK1:PCON.BOR 0 Brown-out Reset Status bit BANK1:RESERVED008F 0x008F RESERVED BANK1:RESERVED0090 0x0090 RESERVED BANK1:RESERVED0091 0x0091 RESERVED BANK1:PR2 0x0092 Timer2 Period Register BANK1:SSPADD 0x0093 Synchronous Serial Port (I2C mode) Address Register BANK1:SSPSTAT 0x0094 SYNC SERIAL PORT STATUS REGISTER BANK1:SSPSTAT.SMP 7 SPI data input sample phase BANK1:SSPSTAT.CKE 6 SPI Clock Edge Select BANK1:SSPSTAT.D_A 5 Data/Address bit (I2C mode only) BANK1:SSPSTAT.P 4 Stop bit (I2C mode only) BANK1:SSPSTAT.S 3 Start bit (I2C mode only) BANK1:SSPSTAT.R_W 2 Read/Write bit information (I2C mode only) BANK1:SSPSTAT.UA 1 Update Address (I2C mode only) BANK1:SSPSTAT.BF 0 Buffer Full Status bit BANK1:RESERVED0095 0x0095 RESERVED BANK1:RESERVED0096 0x0096 RESERVED BANK1:RESERVED0097 0x0097 RESERVED BANK1:RESERVED0098 0x0098 RESERVED BANK1:RESERVED0099 0x0099 RESERVED BANK1:RESERVED009A 0x009A RESERVED BANK1:RESERVED009B 0x009B RESERVED BANK1:RESERVED009C 0x009C RESERVED BANK1:RESERVED009D 0x009D RESERVED BANK0:ADRESL 0x009E A/D Result Register LOW BANK1:ADCON1 0x009F ADCON1 REGISTER BANK1:ADCON1.PCFG2 2 A/D Port Configuration Control bit 2 BANK1:ADCON1.PCFG1 1 A/D Port Configuration Control bit 1 BANK1:ADCON1.PCFG0 0 A/D Port Configuration Control bit 0 ; BANK2 (0x0100:0x0180) BANK2:INDF 0x0100 INDF (not a physical register) BANK2:TMR0 0x0101 Timer0 module's register BANK2:PCL 0x0102 Program Counter's (PC) Least Significant Byte BANK2:STATUS 0x0103 STATUS REGISTER BANK2:STATUS.IRP 7 Register Bank Select bit BANK2:STATUS.RP1 6 Register Bank Select bit 1 BANK2:STATUS.RP0 5 Register Bank Select bit 0 BANK2:STATUS.TO 4 Time-out bit BANK2:STATUS.PD 3 Power-down bit BANK2:STATUS.Z 2 Zero bit BANK2:STATUS.DC 1 Digit carry/borrow bit BANK2:STATUS.C 0 Carry/borrow bit BANK2:FSR 0x0104 Indirect data memory address pointer BANK2:RESERVED0105 0x0105 RESERVED BANK2:PORTB 0x0106 PORTB REGISTER BANK2:PORTB.RB7 7 PORTB bit 7 BANK2:PORTB.RB6 6 PORTB bit 6 BANK2:PORTB.RB5 5 PORTB bit 5 BANK2:PORTB.RB4 4 PORTB bit 4 BANK2:PORTB.RB3 3 PORTB bit 3 BANK2:PORTB.RB2 2 PORTB bit 2 BANK2:PORTB.RB1 1 PORTB bit 1 BANK2:PORTB.RB0 0 PORTB bit 0 BANK2:PORTF 0x0107 PORTF REGISTER BANK2:PORTF.RF7 7 PORTF bit 7 BANK2:PORTF.RF6 6 PORTF bit 6 BANK2:PORTF.RF5 5 PORTF bit 5 BANK2:PORTF.RF4 4 PORTF bit 4 BANK2:PORTF.RF3 3 PORTF bit 3 BANK2:PORTF.RF2 2 PORTF bit 2 BANK2:PORTF.RF1 1 PORTF bit 1 BANK2:PORTF.RF0 0 PORTF bit 0 BANK2:PORTG 0x0108 PORTG REGISTER BANK2:PORTG.RG7 7 PORTG bit 7 BANK2:PORTG.RG6 6 PORTG bit 6 BANK2:PORTG.RG5 5 PORTG bit 5 BANK2:PORTG.RG4 4 PORTG bit 4 BANK2:PORTG.RG3 3 PORTG bit 3 BANK2:PORTG.RG2 2 PORTG bit 2 BANK2:PORTG.RG1 1 PORTG bit 1 BANK2:PORTG.RG0 0 PORTG bit 0 BANK2:RESERVED0109 0x0109 RESERVED BANK2:PCLATH 0x010A Write Buffer for the upper 5 bits of the Program Counter BANK2:INTCON 0x010B INTCON REGISTER BANK2:INTCON.GIE 7 Global Interrupt Enable bit BANK2:INTCON.PEIE 6 Peripheral Interrupt Enable bit BANK2:INTCON.TMR0IE 5 TMR0 Overflow Interrupt Enable bit BANK2:INTCON.INTE 4 RB0/INT External Interrupt Enable bit BANK2:INTCON.RBIE 3 RB Port Change Interrupt Enable bit BANK2:INTCON.TMR0IF 2 TMR0 Overflow Interrupt Flag bit BANK2:INTCON.INTF 1 RB0/INT External Interrupt Flag bit BANK2:INTCON.RBIF 0 RB Port Change Interrupt Flag bit BANK2:PMCON1 0x010C PMCON1 REGISTER BANK2:PMCON1.RD 0 Read Control bit BANK2:LCDSE 0x010D LCDSE REGISTER BANK2:LCDSE.SE29 7 BANK2:LCDSE.SE27 6 BANK2:LCDSE.SE20 5 BANK2:LCDSE.SE16 4 BANK2:LCDSE.SE12 3 BANK2:LCDSE.SE9 2 BANK2:LCDSE.SE5 1 BANK2:LCDSE.SE0 0 BANK2:LCDPS 0x010E LCDPS REGISTER BANK2:LCDPS.LP3 3 Frame Clock Prescale Selection bit 3 BANK2:LCDPS.LP2 2 Frame Clock Prescale Selection bit 2 BANK2:LCDPS.LP1 1 Frame Clock Prescale Selection bit 1 BANK2:LCDPS.LP0 0 Frame Clock Prescale Selection bit 0 BANK2:LCDCON 0x010F LCDCON REGISTER BANK2:LCDCON.LCDEN 7 Module drive enable bit BANK2:LCDCON.SLPEN 6 LCD display sleep enable BANK2:LCDCON.VGEN 4 Voltage Generator Enable BANK2:LCDCON.CS1 3 Clock Source Select bit 1 BANK2:LCDCON.CS0 2 Clock Source Select bit 0 BANK2:LCDCON.LMUX1 1 Common Selection bit 1 BANK2:LCDCON.LMUX0 0 Common Selection bit 0 BANK2:LCDD00 0x0110 GENERIC LCDD REGISTER 00 BANK2:LCDD00.SEG07_COM0 7 BANK2:LCDD00.SEG06_COM0 6 BANK2:LCDD00.SEG05_COM0 5 BANK2:LCDD00.SEG04_COM0 4 BANK2:LCDD00.SEG03_COM0 3 BANK2:LCDD00.SEG02_COM0 2 BANK2:LCDD00.SEG01_COM0 1 BANK2:LCDD00.SEG00_COM0 0 BANK2:LCDD01 0x0111 GENERIC LCDD REGISTER 01 BANK2:LCDD01.SEG15_COM0 7 BANK2:LCDD01.SEG14_COM0 6 BANK2:LCDD01.SEG13_COM0 5 BANK2:LCDD01.SEG12_COM0 4 BANK2:LCDD01.SEG11_COM0 3 BANK2:LCDD01.SEG10_COM0 2 BANK2:LCDD01.SEG09_COM0 1 BANK2:LCDD01.SEG08_COM0 0 BANK2:LCDD02 0x0112 GENERIC LCDD REGISTER 02 BANK2:LCDD02.SEG23_COM0 7 BANK2:LCDD02.SEG22_COM0 6 BANK2:LCDD02.SEG21_COM0 5 BANK2:LCDD02.SEG20_COM0 4 BANK2:LCDD02.SEG19_COM0 3 BANK2:LCDD02.SEG18_COM0 2 BANK2:LCDD02.SEG17_COM0 1 BANK2:LCDD02.SEG16_COM0 0 BANK2:LCDD03 0x0113 GENERIC LCDD REGISTER 03 BANK2:LCDD03.SEG31_COM0 7 BANK2:LCDD03.SEG30_COM0 6 BANK2:LCDD03.SEG29_COM0 5 BANK2:LCDD03.SEG28_COM0 4 BANK2:LCDD03.SEG27_COM0 3 BANK2:LCDD03.SEG26_COM0 2 BANK2:LCDD03.SEG25_COM0 1 BANK2:LCDD03.SEG24_COM0 0 BANK2:LCDD04 0x0114 GENERIC LCDD REGISTER 04 BANK2:LCDD04.SEG07_COM1 7 BANK2:LCDD04.SEG06_COM1 6 BANK2:LCDD04.SEG05_COM1 5 BANK2:LCDD04.SEG04_COM1 4 BANK2:LCDD04.SEG03_COM1 3 BANK2:LCDD04.SEG02_COM1 2 BANK2:LCDD04.SEG01_COM1 1 BANK2:LCDD04.SEG00_COM1 0 BANK2:LCDD05 0x0115 GENERIC LCDD REGISTER 05 BANK2:LCDD05.SEG15_COM1 7 BANK2:LCDD05.SEG14_COM1 6 BANK2:LCDD05.SEG13_COM1 5 BANK2:LCDD05.SEG12_COM1 4 BANK2:LCDD05.SEG11_COM1 3 BANK2:LCDD05.SEG10_COM1 2 BANK2:LCDD05.SEG09_COM1 1 BANK2:LCDD05.SEG08_COM1 0 BANK2:LCDD06 0x0116 GENERIC LCDD REGISTER 06 BANK2:LCDD06.SEG23_COM1 7 BANK2:LCDD06.SEG22_COM1 6 BANK2:LCDD06.SEG21_COM1 5 BANK2:LCDD06.SEG20_COM1 4 BANK2:LCDD06.SEG19_COM1 3 BANK2:LCDD06.SEG18_COM1 2 BANK2:LCDD06.SEG17_COM1 1 BANK2:LCDD06.SEG16_COM1 0 BANK2:LCDD07 0x0117 GENERIC LCDD REGISTER 07 BANK2:LCDD07.SEG31_COM1 7 BANK2:LCDD07.SEG30_COM1 6 BANK2:LCDD07.SEG29_COM1 5 BANK2:LCDD07.SEG28_COM1 4 BANK2:LCDD07.SEG27_COM1 3 BANK2:LCDD07.SEG26_COM1 2 BANK2:LCDD07.SEG25_COM1 1 BANK2:LCDD07.SEG24_COM1 0 BANK2:LCDD08 0x0118 GENERIC LCDD REGISTER 08 BANK2:LCDD08.SEG07_COM2 7 BANK2:LCDD08.SEG06_COM2 6 BANK2:LCDD08.SEG05_COM2 5 BANK2:LCDD08.SEG04_COM2 4 BANK2:LCDD08.SEG03_COM2 3 BANK2:LCDD08.SEG02_COM2 2 BANK2:LCDD08.SEG01_COM2 1 BANK2:LCDD08.SEG00_COM2 0 BANK2:LCDD09 0x0119 GENERIC LCDD REGISTER 09 BANK2:LCDD09.SEG15_COM2 7 BANK2:LCDD09.SEG14_COM2 6 BANK2:LCDD09.SEG13_COM2 5 BANK2:LCDD09.SEG12_COM2 4 BANK2:LCDD09.SEG11_COM2 3 BANK2:LCDD09.SEG10_COM2 2 BANK2:LCDD09.SEG09_COM2 1 BANK2:LCDD09.SEG08_COM2 0 BANK2:LCDD10 0x011A GENERIC LCDD REGISTER 10 BANK2:LCDD10.SEG23_COM2 7 BANK2:LCDD10.SEG22_COM2 6 BANK2:LCDD10.SEG21_COM2 5 BANK2:LCDD10.SEG20_COM2 4 BANK2:LCDD10.SEG19_COM2 3 BANK2:LCDD10.SEG18_COM2 2 BANK2:LCDD10.SEG17_COM2 1 BANK2:LCDD10.SEG16_COM2 0 BANK2:LCDD11 0x011B GENERIC LCDD REGISTER 11 BANK2:LCDD11.SEG31_COM2 7 BANK2:LCDD11.SEG30_COM2 6 BANK2:LCDD11.SEG29_COM2 5 BANK2:LCDD11.SEG28_COM2 4 BANK2:LCDD11.SEG27_COM2 3 BANK2:LCDD11.SEG26_COM2 2 BANK2:LCDD11.SEG25_COM2 1 BANK2:LCDD11.SEG24_COM2 0 BANK2:LCDD12 0x011C GENERIC LCDD REGISTER 12 BANK2:LCDD12.SEG07_COM3 7 BANK2:LCDD12.SEG06_COM3 6 BANK2:LCDD12.SEG05_COM3 5 BANK2:LCDD12.SEG04_COM3 4 BANK2:LCDD12.SEG03_COM3 3 BANK2:LCDD12.SEG02_COM3 2 BANK2:LCDD12.SEG01_COM3 1 BANK2:LCDD12.SEG00_COM3 0 BANK2:LCDD13 0x011D GENERIC LCDD REGISTER 13 BANK2:LCDD13.SEG15_COM3 7 BANK2:LCDD13.SEG14_COM3 6 BANK2:LCDD13.SEG13_COM3 5 BANK2:LCDD13.SEG12_COM3 4 BANK2:LCDD13.SEG11_COM3 3 BANK2:LCDD13.SEG10_COM3 2 BANK2:LCDD13.SEG09_COM3 1 BANK2:LCDD13.SEG08_COM3 0 BANK2:LCDD14 0x011E GENERIC LCDD REGISTER 14 BANK2:LCDD14.SEG23_COM3 7 BANK2:LCDD14.SEG22_COM3 6 BANK2:LCDD14.SEG21_COM3 5 BANK2:LCDD14.SEG20_COM3 4 BANK2:LCDD14.SEG19_COM3 3 BANK2:LCDD14.SEG18_COM3 2 BANK2:LCDD14.SEG17_COM3 1 BANK2:LCDD14.SEG16_COM3 0 BANK2:LCDD15 0x011F GENERIC LCDD REGISTER 15 BANK2:LCDD15.SEG31_COM3 7 BANK2:LCDD15.SEG30_COM3 6 BANK2:LCDD15.SEG29_COM3 5 BANK2:LCDD15.SEG28_COM3 4 BANK2:LCDD15.SEG27_COM3 3 BANK2:LCDD15.SEG26_COM3 2 BANK2:LCDD15.SEG25_COM3 1 BANK2:LCDD15.SEG24_COM3 0 ; BANK3 (0x0180:0x0200) BANK3:INDF 0x0180 INDF (not a physical register) BANK3:OPTION 0x0181 OPTION REGISTER BANK3:OPTION.RBPU 7 PORTB Pull-up Enable bit BANK3:OPTION.INTEDG 6 Interrupt Edge Select bit BANK3:OPTION.T0CS 5 TMR0 Clock Source Select bit BANK3:OPTION.T0SE 4 TMR0 Source Edge Select bit BANK3:OPTION.PSA 3 Prescaler Assignment bit BANK3:OPTION.PS2 2 Prescaler Rate Select bit 2 BANK3:OPTION.PS1 1 Prescaler Rate Select bit 1 BANK3:OPTION.PS0 0 Prescaler Rate Select bit 0 BANK3:PCL 0x0182 Program Counter's (PC) Least Significant Byte BANK3:STATUS 0x0183 STATUS REGISTER BANK3:STATUS.IRP 7 Register Bank Select bit BANK3:STATUS.RP1 6 Register Bank Select bit 1 BANK3:STATUS.RP0 5 Register Bank Select bit 0 BANK3:STATUS.TO 4 Time-out bit BANK3:STATUS.PD 3 Power-down bit BANK3:STATUS.Z 2 Zero bit BANK3:STATUS.DC 1 Digit carry/borrow bit BANK3:STATUS.C 0 Carry/borrow bit BANK3:FSR 0x0184 Indirect data memory address pointer BANK3:RESERVED0185 0x0185 RESERVED BANK3:TRISB 0x0186 PORTB Data Direction Register BANK3:TRISB.TRISB7 7 PORTB Data Direction Register bit 7 BANK3:TRISB.TRISB6 6 PORTB Data Direction Register bit 6 BANK3:TRISB.TRISB5 5 PORTB Data Direction Register bit 5 BANK3:TRISB.TRISB4 4 PORTB Data Direction Register bit 4 BANK3:TRISB.TRISB3 3 PORTB Data Direction Register bit 3 BANK3:TRISB.TRISB2 2 PORTB Data Direction Register bit 2 BANK3:TRISB.TRISB1 1 PORTB Data Direction Register bit 1 BANK3:TRISB.TRISB0 0 PORTB Data Direction Register bit 0 BANK3:TRISF 0x0187 PORTF Data Direction Register BANK3:TRISF.TRISF7 7 PORTF Data Direction Register bit 7 BANK3:TRISF.TRISF6 6 PORTF Data Direction Register bit 6 BANK3:TRISF.TRISF5 5 PORTF Data Direction Register bit 5 BANK3:TRISF.TRISF4 4 PORTF Data Direction Register bit 4 BANK3:TRISF.TRISF3 3 PORTF Data Direction Register bit 3 BANK3:TRISF.TRISF2 2 PORTF Data Direction Register bit 2 BANK3:TRISF.TRISF1 1 PORTF Data Direction Register bit 1 BANK3:TRISF.TRISF0 0 PORTF Data Direction Register bit 0 BANK3:TRISG 0x0188 PORTG Data Direction Register BANK3:TRISG.TRISG7 7 PORTG Data Direction Register bit 7 BANK3:TRISG.TRISG6 6 PORTG Data Direction Register bit 6 BANK3:TRISG.TRISG5 5 PORTG Data Direction Register bit 5 BANK3:TRISG.TRISG4 4 PORTG Data Direction Register bit 4 BANK3:TRISG.TRISG3 3 PORTG Data Direction Register bit 3 BANK3:TRISG.TRISG2 2 PORTG Data Direction Register bit 2 BANK3:TRISG.TRISG1 1 PORTG Data Direction Register bit 1 BANK3:TRISG.TRISG0 0 PORTG Data Direction Register bit 0 BANK3:RESERVED0189 0x0189 RESERVED BANK3:PCLATH 0x018A Write Buffer for the upper 5 bits of the Program Counter BANK3:INTCON 0x018B INTCON REGISTER BANK3:INTCON.GIE 7 Global Interrupt Enable bit BANK3:INTCON.PEIE 6 Peripheral Interrupt Enable bit BANK3:INTCON.TMR0IE 5 TMR0 Overflow Interrupt Enable bit BANK3:INTCON.INTE 4 RB0/INT External Interrupt Enable bit BANK3:INTCON.RBIE 3 RB Port Change Interrupt Enable bit BANK3:INTCON.TMR0IF 2 TMR0 Overflow Interrupt Flag bit BANK3:INTCON.INTF 1 RB0/INT External Interrupt Flag bit BANK3:INTCON.RBIF 0 RB Port Change Interrupt Flag bit BANK3:PMDATA 0x018C Data Register Low Byte BANK3:PMADR 0x018D Address Register Low Byte BANK3:PMDATH 0x018E Data Register High Byte BANK3:PMADRH 0x018F Address Register High Byte .16CE623 ; http://www.microchip.com/download/lit/pline/picmicro/families/16ce62x/40182c.pdf ; PIC16CE62X.pdf ; MEMORY MAP ; BANK_0 area DATA FSR_ 0x0000:0x0020 area DATA Gen_Purp 0x0020:0x0080 General Purpose Register area DATA MEM_Program 0x0080:0x0200 On-chip Program Memory ; BANK_1 ; area DATA FSR_ 0x0080:0x00A0 ; area BSS RESERVED 0x00A0:0x00F0 ; area DATA Gen_Purp_BANK0 0x00F0:0x0100 Accesses 70h-7Fh ; area DATA MEM_Program 0x0100:0x0200 On-chip Program Memory ; Interrupt and reset vector assignments interrupt RESET 0x0000 RESET ; INPUT/OUTPUT PORTS ; BANK0 (0x0000:0x0080) BANK0:INDF 0x0000 INDF (not a physical register) BANK0:TMR0 0x0001 Timer0 module's register BANK0:PCL 0x0002 Program Counter's (PC) Least Significant Byte BANK0:STATUS 0x0003 STATUS REGISTER BANK0:STATUS.RP0 5 Register Bank Select bit 0 BANK0:STATUS.TO 4 Time-out bit BANK0:STATUS.PD 3 Power-down bit BANK0:STATUS.Z 2 Zero bit BANK0:STATUS.DC 1 Digit carry/borrow bit BANK0:STATUS.C 0 Carry/borrow bit BANK0:FSR 0x0004 Indirect data memory address pointer BANK0:PORTA 0x0005 PORTA REGISTER BANK0:PORTA.RA4 4 PORTA bit 4 BANK0:PORTA.RA3 3 PORTA bit 3 BANK0:PORTA.RA2 2 PORTA bit 2 BANK0:PORTA.RA1 1 PORTA bit 1 BANK0:PORTA.RA0 0 PORTA bit 0 BANK0:PORTB 0x0006 PORTB REGISTER BANK0:PORTB.RB7 7 PORTB bit 7 BANK0:PORTB.RB6 6 PORTB bit 6 BANK0:PORTB.RB5 5 PORTB bit 5 BANK0:PORTB.RB4 4 PORTB bit 4 BANK0:PORTB.RB3 3 PORTB bit 3 BANK0:PORTB.RB2 2 PORTB bit 2 BANK0:PORTB.RB1 1 PORTB bit 1 BANK0:PORTB.RB0 0 PORTB bit 0 BANK0:RESERVED0007 0x0007 RESERVED BANK0:RESERVED0008 0x0008 RESERVED BANK0:RESERVED0009 0x0009 RESERVED BANK0:PCLATH 0x000A Write Buffer for the upper 5 bits of Program Counter BANK0:INTCON 0x000B INTCON REGISTER BANK0:INTCON.GIE 7 Global Interrupt Enable bit BANK0:INTCON.PEIE 6 Peripheral Interrupt Enable bit BANK0:INTCON.T0IE 5 TMR0 Overflow Interrupt Enable bit BANK0:INTCON.INTE 4 RB0/INT External Interrupt Enable bit BANK0:INTCON.RBIE 3 RB Port Change Interrupt Enable bit BANK0:INTCON.T0IF 2 TMR0 Overflow Interrupt Flag bit BANK0:INTCON.INTF 1 RB0/INT External Interrupt Flag bit BANK0:INTCON.RBIF 0 RB Port Change Interrupt Flag bit BANK0:PIR1 0x000C PIR1 REGISTER BANK0:PIR1.CMIF 6 Comparator Interrupt Flag bit BANK0:RESERVED000D 0x000D RESERVED BANK0:RESERVED000E 0x000E RESERVED BANK0:RESERVED000F 0x000F RESERVED BANK0:RESERVED0010 0x0010 RESERVED BANK0:RESERVED0011 0x0011 RESERVED BANK0:RESERVED0012 0x0012 RESERVED BANK0:RESERVED0013 0x0013 RESERVED BANK0:RESERVED0014 0x0014 RESERVED BANK0:RESERVED0015 0x0015 RESERVED BANK0:RESERVED0016 0x0016 RESERVED BANK0:RESERVED0017 0x0017 RESERVED BANK0:RESERVED0018 0x0018 RESERVED BANK0:RESERVED0019 0x0019 RESERVED BANK0:RESERVED001A 0x001A RESERVED BANK0:RESERVED001B 0x001B RESERVED BANK0:RESERVED001C 0x001C RESERVED BANK0:RESERVED001D 0x001D RESERVED BANK0:RESERVED001E 0x001E RESERVED BANK0:CMCON 0x001F CMCON REGISTER BANK0:CMCON.C2OUT 7 Comparator 2 output BANK0:CMCON.C1OUT 6 Comparator 1 output BANK0:CMCON.CIS 3 Comparator Input Switch BANK0:CMCON.CM2 2 Comparator mode 2 BANK0:CMCON.CM1 1 Comparator mode 1 BANK0:CMCON.CM0 0 Comparator mode 0 ; BANK1 (0x0080:0x0100) BANK1:INDF 0x0080 INDF (not a physical register) BANK1:OPTION 0x0081 OPTION REGISTER BANK1:OPTION.RBPU 7 PORTB Pull-up Enable bit BANK1:OPTION.INTEDG 6 Interrupt Edge Select bit BANK1:OPTION.T0CS 5 TMR0 Clock Source Select bit BANK1:OPTION.T0SE 4 TMR0 Source Edge Select bit BANK1:OPTION.PSA 3 Prescaler Assignment bit BANK1:OPTION.PS2 2 Prescaler Rate Select bit 2 BANK1:OPTION.PS1 1 Prescaler Rate Select bit 1 BANK1:OPTION.PS0 0 Prescaler Rate Select bit 0 BANK1:PCL 0x0082 Program Counter's (PC) Least Significant Byte BANK1:STATUS 0x0083 STATUS REGISTER BANK1:STATUS.RP1 6 Register Bank Select bit 1 BANK1:STATUS.RP0 5 Register Bank Select bit 0 BANK1:STATUS.TO 4 Time-out bit BANK1:STATUS.PD 3 Power-down bit BANK1:STATUS.Z 2 Zero bit BANK1:STATUS.DC 1 Digit carry/borrow bit BANK1:STATUS.C 0 Carry/borrow bit BANK1:FSR 0x0084 Indirect data memory address pointer BANK1:TRISA 0x0085 PORTA Data Direction Register BANK1:TRISA.TRISA4 4 PORTA Data Direction Register bit 4 BANK1:TRISA.TRISA3 3 PORTA Data Direction Register bit 3 BANK1:TRISA.TRISA2 2 PORTA Data Direction Register bit 2 BANK1:TRISA.TRISA1 1 PORTA Data Direction Register bit 1 BANK1:TRISA.TRISA0 0 PORTA Data Direction Register bit 0 BANK1:TRISB 0x0086 PORTB Data Direction Register BANK1:TRISB.TRISB7 7 PORTB Data Direction Register bit 7 BANK1:TRISB.TRISB6 6 PORTB Data Direction Register bit 6 BANK1:TRISB.TRISB5 5 PORTB Data Direction Register bit 5 BANK1:TRISB.TRISB4 4 PORTB Data Direction Register bit 4 BANK1:TRISB.TRISB3 3 PORTB Data Direction Register bit 3 BANK1:TRISB.TRISB2 2 PORTB Data Direction Register bit 2 BANK1:TRISB.TRISB1 1 PORTB Data Direction Register bit 1 BANK1:TRISB.TRISB0 0 PORTB Data Direction Register bit 0 BANK1:RESERVED0087 0x0087 RESERVED BANK1:RESERVED0088 0x0088 RESERVED BANK1:RESERVED0089 0x0089 RESERVED BANK1:PCLATH 0x008A Write Buffer for the upper 5 bits of Program Counter BANK1:INTCON 0x008B INTCON REGISTER BANK1:INTCON.GIE 7 Global Interrupt Enable bit BANK1:INTCON.PEIE 6 Peripheral Interrupt Enable bit BANK1:INTCON.T0IE 5 TMR0 Overflow Interrupt Enable bit BANK1:INTCON.INTE 4 RB0/INT External Interrupt Enable bit BANK1:INTCON.RBIE 3 RB Port Change Interrupt Enable bit BANK1:INTCON.T0IF 2 TMR0 Overflow Interrupt Flag bit BANK1:INTCON.INTF 1 RB0/INT External Interrupt Flag bit BANK1:INTCON.RBIF 0 RB Port Change Interrupt Flag bit BANK1:PIE1 0x008C PIE1 REGISTER BANK1:PIE1.CMIE 6 Comparator Interrupt Enable bit BANK1:RESERVED008D 0x008D RESERVED BANK1:PCON 0x008E PCON REGISTER BANK1:PCON.POR 1 Power-on Reset Status bit BANK1:PCON.BOR 0 Brown-out Reset Status bit BANK1:RESERVED008F 0x008F RESERVED BANK1:EEINTF 0x0090 EEINTF REGISTER BANK1:EEINTF.EESCL 2 Clock line to the EEPROM BANK1:EEINTF.EESDA 1 Data line to EEPROM BANK1:EEINTF.EEVDD 0 VDD control bit for EEPROM BANK1:RESERVED0091 0x0091 RESERVED BANK1:RESERVED0092 0x0092 RESERVED BANK1:RESERVED0093 0x0093 RESERVED BANK1:RESERVED0094 0x0094 RESERVED BANK1:RESERVED0095 0x0095 RESERVED BANK1:RESERVED0096 0x0096 RESERVED BANK1:RESERVED0097 0x0097 RESERVED BANK1:RESERVED0098 0x0098 RESERVED BANK1:RESERVED0099 0x0099 RESERVED BANK1:RESERVED009A 0x009A RESERVED BANK1:RESERVED009B 0x009B RESERVED BANK1:RESERVED009C 0x009C RESERVED BANK1:RESERVED009D 0x009D RESERVED BANK1:RESERVED009E 0x009E RESERVED BANK1:VRCON 0x009F VRCON REGISTER BANK1:VRCON.VREN 7 VREF Enable BANK1:VRCON.VROE 6 VREF Output Enable BANK1:VRCON.VRR 5 VREF Range selection BANK1:VRCON.VR3 3 VREF value selection 3 BANK1:VRCON.VR2 2 VREF value selection 2 BANK1:VRCON.VR1 1 VREF value selection 1 BANK1:VRCON.VR0 0 VREF value selection 0 .16CE624 ; http://www.microchip.com/download/lit/pline/picmicro/families/16ce62x/40182c.pdf ; PIC16CE62X.pdf ; MEMORY MAP ; BANK_0 area DATA FSR_ 0x0000:0x0020 area DATA Gen_Purp 0x0020:0x0080 General Purpose Register area DATA MEM_Program 0x0080:0x0400 On-chip Program Memory ; BANK_1 ; area DATA FSR_ 0x0080:0x00A0 ; area BSS RESERVED 0x00A0:0x00F0 ; area DATA Gen_Purp_BANK0 0x00F0:0x0100 Accesses 70h-7Fh ; area DATA MEM_Program 0x0100:0x0400 On-chip Program Memory ; Interrupt and reset vector assignments interrupt RESET 0x0000 RESET ; INPUT/OUTPUT PORTS ; BANK0 (0x0000:0x0080) BANK0:INDF 0x0000 INDF (not a physical register) BANK0:TMR0 0x0001 Timer0 module's register BANK0:PCL 0x0002 Program Counter's (PC) Least Significant Byte BANK0:STATUS 0x0003 STATUS REGISTER BANK0:STATUS.RP0 5 Register Bank Select bit 0 BANK0:STATUS.TO 4 Time-out bit BANK0:STATUS.PD 3 Power-down bit BANK0:STATUS.Z 2 Zero bit BANK0:STATUS.DC 1 Digit carry/borrow bit BANK0:STATUS.C 0 Carry/borrow bit BANK0:FSR 0x0004 Indirect data memory address pointer BANK0:PORTA 0x0005 PORTA REGISTER BANK0:PORTA.RA4 4 PORTA bit 4 BANK0:PORTA.RA3 3 PORTA bit 3 BANK0:PORTA.RA2 2 PORTA bit 2 BANK0:PORTA.RA1 1 PORTA bit 1 BANK0:PORTA.RA0 0 PORTA bit 0 BANK0:PORTB 0x0006 PORTB REGISTER BANK0:PORTB.RB7 7 PORTB bit 7 BANK0:PORTB.RB6 6 PORTB bit 6 BANK0:PORTB.RB5 5 PORTB bit 5 BANK0:PORTB.RB4 4 PORTB bit 4 BANK0:PORTB.RB3 3 PORTB bit 3 BANK0:PORTB.RB2 2 PORTB bit 2 BANK0:PORTB.RB1 1 PORTB bit 1 BANK0:PORTB.RB0 0 PORTB bit 0 BANK0:RESERVED0007 0x0007 RESERVED BANK0:RESERVED0008 0x0008 RESERVED BANK0:RESERVED0009 0x0009 RESERVED BANK0:PCLATH 0x000A Write Buffer for the upper 5 bits of Program Counter BANK0:INTCON 0x000B INTCON REGISTER BANK0:INTCON.GIE 7 Global Interrupt Enable bit BANK0:INTCON.PEIE 6 Peripheral Interrupt Enable bit BANK0:INTCON.T0IE 5 TMR0 Overflow Interrupt Enable bit BANK0:INTCON.INTE 4 RB0/INT External Interrupt Enable bit BANK0:INTCON.RBIE 3 RB Port Change Interrupt Enable bit BANK0:INTCON.T0IF 2 TMR0 Overflow Interrupt Flag bit BANK0:INTCON.INTF 1 RB0/INT External Interrupt Flag bit BANK0:INTCON.RBIF 0 RB Port Change Interrupt Flag bit BANK0:PIR1 0x000C PIR1 REGISTER BANK0:PIR1.CMIF 6 Comparator Interrupt Flag bit BANK0:RESERVED000D 0x000D RESERVED BANK0:RESERVED000E 0x000E RESERVED BANK0:RESERVED000F 0x000F RESERVED BANK0:RESERVED0010 0x0010 RESERVED BANK0:RESERVED0011 0x0011 RESERVED BANK0:RESERVED0012 0x0012 RESERVED BANK0:RESERVED0013 0x0013 RESERVED BANK0:RESERVED0014 0x0014 RESERVED BANK0:RESERVED0015 0x0015 RESERVED BANK0:RESERVED0016 0x0016 RESERVED BANK0:RESERVED0017 0x0017 RESERVED BANK0:RESERVED0018 0x0018 RESERVED BANK0:RESERVED0019 0x0019 RESERVED BANK0:RESERVED001A 0x001A RESERVED BANK0:RESERVED001B 0x001B RESERVED BANK0:RESERVED001C 0x001C RESERVED BANK0:RESERVED001D 0x001D RESERVED BANK0:RESERVED001E 0x001E RESERVED BANK0:CMCON 0x001F CMCON REGISTER BANK0:CMCON.C2OUT 7 Comparator 2 output BANK0:CMCON.C1OUT 6 Comparator 1 output BANK0:CMCON.CIS 3 Comparator Input Switch BANK0:CMCON.CM2 2 Comparator mode 2 BANK0:CMCON.CM1 1 Comparator mode 1 BANK0:CMCON.CM0 0 Comparator mode 0 ; BANK1 (0x0080:0x0100) BANK1:INDF 0x0080 INDF (not a physical register) BANK1:OPTION 0x0081 OPTION REGISTER BANK1:OPTION.RBPU 7 PORTB Pull-up Enable bit BANK1:OPTION.INTEDG 6 Interrupt Edge Select bit BANK1:OPTION.T0CS 5 TMR0 Clock Source Select bit BANK1:OPTION.T0SE 4 TMR0 Source Edge Select bit BANK1:OPTION.PSA 3 Prescaler Assignment bit BANK1:OPTION.PS2 2 Prescaler Rate Select bit 2 BANK1:OPTION.PS1 1 Prescaler Rate Select bit 1 BANK1:OPTION.PS0 0 Prescaler Rate Select bit 0 BANK1:PCL 0x0082 Program Counter's (PC) Least Significant Byte BANK1:STATUS 0x0083 STATUS REGISTER BANK1:STATUS.RP1 6 Register Bank Select bit 1 BANK1:STATUS.RP0 5 Register Bank Select bit 0 BANK1:STATUS.TO 4 Time-out bit BANK1:STATUS.PD 3 Power-down bit BANK1:STATUS.Z 2 Zero bit BANK1:STATUS.DC 1 Digit carry/borrow bit BANK1:STATUS.C 0 Carry/borrow bit BANK1:FSR 0x0084 Indirect data memory address pointer BANK1:TRISA 0x0085 PORTA Data Direction Register BANK1:TRISA.TRISA4 4 PORTA Data Direction Register bit 4 BANK1:TRISA.TRISA3 3 PORTA Data Direction Register bit 3 BANK1:TRISA.TRISA2 2 PORTA Data Direction Register bit 2 BANK1:TRISA.TRISA1 1 PORTA Data Direction Register bit 1 BANK1:TRISA.TRISA0 0 PORTA Data Direction Register bit 0 BANK1:TRISB 0x0086 PORTB Data Direction Register BANK1:TRISB.TRISB7 7 PORTB Data Direction Register bit 7 BANK1:TRISB.TRISB6 6 PORTB Data Direction Register bit 6 BANK1:TRISB.TRISB5 5 PORTB Data Direction Register bit 5 BANK1:TRISB.TRISB4 4 PORTB Data Direction Register bit 4 BANK1:TRISB.TRISB3 3 PORTB Data Direction Register bit 3 BANK1:TRISB.TRISB2 2 PORTB Data Direction Register bit 2 BANK1:TRISB.TRISB1 1 PORTB Data Direction Register bit 1 BANK1:TRISB.TRISB0 0 PORTB Data Direction Register bit 0 BANK1:RESERVED0087 0x0087 RESERVED BANK1:RESERVED0088 0x0088 RESERVED BANK1:RESERVED0089 0x0089 RESERVED BANK1:PCLATH 0x008A Write Buffer for the upper 5 bits of Program Counter BANK1:INTCON 0x008B INTCON REGISTER BANK1:INTCON.GIE 7 Global Interrupt Enable bit BANK1:INTCON.PEIE 6 Peripheral Interrupt Enable bit BANK1:INTCON.T0IE 5 TMR0 Overflow Interrupt Enable bit BANK1:INTCON.INTE 4 RB0/INT External Interrupt Enable bit BANK1:INTCON.RBIE 3 RB Port Change Interrupt Enable bit BANK1:INTCON.T0IF 2 TMR0 Overflow Interrupt Flag bit BANK1:INTCON.INTF 1 RB0/INT External Interrupt Flag bit BANK1:INTCON.RBIF 0 RB Port Change Interrupt Flag bit BANK1:PIE1 0x008C PIE1 REGISTER BANK1:PIE1.CMIE 6 Comparator Interrupt Enable bit BANK1:RESERVED008D 0x008D RESERVED BANK1:PCON 0x008E PCON REGISTER BANK1:PCON.POR 1 Power-on Reset Status bit BANK1:PCON.BOR 0 Brown-out Reset Status bit BANK1:RESERVED008F 0x008F RESERVED BANK1:EEINTF 0x0090 EEINTF REGISTER BANK1:EEINTF.EESCL 2 Clock line to the EEPROM BANK1:EEINTF.EESDA 1 Data line to EEPROM BANK1:EEINTF.EEVDD 0 VDD control bit for EEPROM BANK1:RESERVED0091 0x0091 RESERVED BANK1:RESERVED0092 0x0092 RESERVED BANK1:RESERVED0093 0x0093 RESERVED BANK1:RESERVED0094 0x0094 RESERVED BANK1:RESERVED0095 0x0095 RESERVED BANK1:RESERVED0096 0x0096 RESERVED BANK1:RESERVED0097 0x0097 RESERVED BANK1:RESERVED0098 0x0098 RESERVED BANK1:RESERVED0099 0x0099 RESERVED BANK1:RESERVED009A 0x009A RESERVED BANK1:RESERVED009B 0x009B RESERVED BANK1:RESERVED009C 0x009C RESERVED BANK1:RESERVED009D 0x009D RESERVED BANK1:RESERVED009E 0x009E RESERVED BANK1:VRCON 0x009F VRCON REGISTER BANK1:VRCON.VREN 7 VREF Enable BANK1:VRCON.VROE 6 VREF Output Enable BANK1:VRCON.VRR 5 VREF Range selection BANK1:VRCON.VR3 3 VREF value selection 3 BANK1:VRCON.VR2 2 VREF value selection 2 BANK1:VRCON.VR1 1 VREF value selection 1 BANK1:VRCON.VR0 0 VREF value selection 0 .16CE625 ; http://www.microchip.com/download/lit/pline/picmicro/families/16ce62x/40182c.pdf ; PIC16CE62X.pdf ; MEMORY MAP ; BANK_0 area DATA FSR_ 0x0000:0x0020 area DATA Gen_Purp 0x0020:0x0080 General Purpose Register area DATA MEM_Program 0x0080:0x0800 On-chip Program Memory ; BANK_1 ; area DATA FSR_ 0x0080:0x00A0 ; area DATA Gen_Purp 0x00A0:0x00C0 General Purpose Register ; area BSS RESERVED 0x00C0:0x00F0 ; area DATA Gen_Purp_BANK0 0x00F0:0x0100 Accesses 70h-7Fh ; area DATA MEM_Program 0x0100:0x0800 On-chip Program Memory ; Interrupt and reset vector assignments interrupt RESET 0x0000 RESET ; INPUT/OUTPUT PORTS ; BANK0 (0x0000:0x0080) BANK0:INDF 0x0000 INDF (not a physical register) BANK0:TMR0 0x0001 Timer0 module's register BANK0:PCL 0x0002 Program Counter's (PC) Least Significant Byte BANK0:STATUS 0x0003 STATUS REGISTER BANK0:STATUS.RP0 5 Register Bank Select bit 0 BANK0:STATUS.TO 4 Time-out bit BANK0:STATUS.PD 3 Power-down bit BANK0:STATUS.Z 2 Zero bit BANK0:STATUS.DC 1 Digit carry/borrow bit BANK0:STATUS.C 0 Carry/borrow bit BANK0:FSR 0x0004 Indirect data memory address pointer BANK0:PORTA 0x0005 PORTA REGISTER BANK0:PORTA.RA4 4 PORTA bit 4 BANK0:PORTA.RA3 3 PORTA bit 3 BANK0:PORTA.RA2 2 PORTA bit 2 BANK0:PORTA.RA1 1 PORTA bit 1 BANK0:PORTA.RA0 0 PORTA bit 0 BANK0:PORTB 0x0006 PORTB REGISTER BANK0:PORTB.RB7 7 PORTB bit 7 BANK0:PORTB.RB6 6 PORTB bit 6 BANK0:PORTB.RB5 5 PORTB bit 5 BANK0:PORTB.RB4 4 PORTB bit 4 BANK0:PORTB.RB3 3 PORTB bit 3 BANK0:PORTB.RB2 2 PORTB bit 2 BANK0:PORTB.RB1 1 PORTB bit 1 BANK0:PORTB.RB0 0 PORTB bit 0 BANK0:RESERVED0007 0x0007 RESERVED BANK0:RESERVED0008 0x0008 RESERVED BANK0:RESERVED0009 0x0009 RESERVED BANK0:PCLATH 0x000A Write Buffer for the upper 5 bits of Program Counter BANK0:INTCON 0x000B INTCON REGISTER BANK0:INTCON.GIE 7 Global Interrupt Enable bit BANK0:INTCON.PEIE 6 Peripheral Interrupt Enable bit BANK0:INTCON.T0IE 5 TMR0 Overflow Interrupt Enable bit BANK0:INTCON.INTE 4 RB0/INT External Interrupt Enable bit BANK0:INTCON.RBIE 3 RB Port Change Interrupt Enable bit BANK0:INTCON.T0IF 2 TMR0 Overflow Interrupt Flag bit BANK0:INTCON.INTF 1 RB0/INT External Interrupt Flag bit BANK0:INTCON.RBIF 0 RB Port Change Interrupt Flag bit BANK0:PIR1 0x000C PIR1 REGISTER BANK0:PIR1.CMIF 6 Comparator Interrupt Flag bit BANK0:RESERVED000D 0x000D RESERVED BANK0:RESERVED000E 0x000E RESERVED BANK0:RESERVED000F 0x000F RESERVED BANK0:RESERVED0010 0x0010 RESERVED BANK0:RESERVED0011 0x0011 RESERVED BANK0:RESERVED0012 0x0012 RESERVED BANK0:RESERVED0013 0x0013 RESERVED BANK0:RESERVED0014 0x0014 RESERVED BANK0:RESERVED0015 0x0015 RESERVED BANK0:RESERVED0016 0x0016 RESERVED BANK0:RESERVED0017 0x0017 RESERVED BANK0:RESERVED0018 0x0018 RESERVED BANK0:RESERVED0019 0x0019 RESERVED BANK0:RESERVED001A 0x001A RESERVED BANK0:RESERVED001B 0x001B RESERVED BANK0:RESERVED001C 0x001C RESERVED BANK0:RESERVED001D 0x001D RESERVED BANK0:RESERVED001E 0x001E RESERVED BANK0:CMCON 0x001F CMCON REGISTER BANK0:CMCON.C2OUT 7 Comparator 2 output BANK0:CMCON.C1OUT 6 Comparator 1 output BANK0:CMCON.CIS 3 Comparator Input Switch BANK0:CMCON.CM2 2 Comparator mode 2 BANK0:CMCON.CM1 1 Comparator mode 1 BANK0:CMCON.CM0 0 Comparator mode 0 ; BANK1 (0x0080:0x0100) BANK1:INDF 0x0080 INDF (not a physical register) BANK1:OPTION 0x0081 OPTION REGISTER BANK1:OPTION.RBPU 7 PORTB Pull-up Enable bit BANK1:OPTION.INTEDG 6 Interrupt Edge Select bit BANK1:OPTION.T0CS 5 TMR0 Clock Source Select bit BANK1:OPTION.T0SE 4 TMR0 Source Edge Select bit BANK1:OPTION.PSA 3 Prescaler Assignment bit BANK1:OPTION.PS2 2 Prescaler Rate Select bit 2 BANK1:OPTION.PS1 1 Prescaler Rate Select bit 1 BANK1:OPTION.PS0 0 Prescaler Rate Select bit 0 BANK1:PCL 0x0082 Program Counter's (PC) Least Significant Byte BANK1:STATUS 0x0083 STATUS REGISTER BANK1:STATUS.RP1 6 Register Bank Select bit 1 BANK1:STATUS.RP0 5 Register Bank Select bit 0 BANK1:STATUS.TO 4 Time-out bit BANK1:STATUS.PD 3 Power-down bit BANK1:STATUS.Z 2 Zero bit BANK1:STATUS.DC 1 Digit carry/borrow bit BANK1:STATUS.C 0 Carry/borrow bit BANK1:FSR 0x0084 Indirect data memory address pointer BANK1:TRISA 0x0085 PORTA Data Direction Register BANK1:TRISA.TRISA4 4 PORTA Data Direction Register bit 4 BANK1:TRISA.TRISA3 3 PORTA Data Direction Register bit 3 BANK1:TRISA.TRISA2 2 PORTA Data Direction Register bit 2 BANK1:TRISA.TRISA1 1 PORTA Data Direction Register bit 1 BANK1:TRISA.TRISA0 0 PORTA Data Direction Register bit 0 BANK1:TRISB 0x0086 PORTB Data Direction Register BANK1:TRISB.TRISB7 7 PORTB Data Direction Register bit 7 BANK1:TRISB.TRISB6 6 PORTB Data Direction Register bit 6 BANK1:TRISB.TRISB5 5 PORTB Data Direction Register bit 5 BANK1:TRISB.TRISB4 4 PORTB Data Direction Register bit 4 BANK1:TRISB.TRISB3 3 PORTB Data Direction Register bit 3 BANK1:TRISB.TRISB2 2 PORTB Data Direction Register bit 2 BANK1:TRISB.TRISB1 1 PORTB Data Direction Register bit 1 BANK1:TRISB.TRISB0 0 PORTB Data Direction Register bit 0 BANK1:RESERVED0087 0x0087 RESERVED BANK1:RESERVED0088 0x0088 RESERVED BANK1:RESERVED0089 0x0089 RESERVED BANK1:PCLATH 0x008A Write Buffer for the upper 5 bits of Program Counter BANK1:INTCON 0x008B INTCON REGISTER BANK1:INTCON.GIE 7 Global Interrupt Enable bit BANK1:INTCON.PEIE 6 Peripheral Interrupt Enable bit BANK1:INTCON.T0IE 5 TMR0 Overflow Interrupt Enable bit BANK1:INTCON.INTE 4 RB0/INT External Interrupt Enable bit BANK1:INTCON.RBIE 3 RB Port Change Interrupt Enable bit BANK1:INTCON.T0IF 2 TMR0 Overflow Interrupt Flag bit BANK1:INTCON.INTF 1 RB0/INT External Interrupt Flag bit BANK1:INTCON.RBIF 0 RB Port Change Interrupt Flag bit BANK1:PIE1 0x008C PIE1 REGISTER BANK1:PIE1.CMIE 6 Comparator Interrupt Enable bit BANK1:RESERVED008D 0x008D RESERVED BANK1:PCON 0x008E PCON REGISTER BANK1:PCON.POR 1 Power-on Reset Status bit BANK1:PCON.BOR 0 Brown-out Reset Status bit BANK1:RESERVED008F 0x008F RESERVED BANK1:EEINTF 0x0090 EEINTF REGISTER BANK1:EEINTF.EESCL 2 Clock line to the EEPROM BANK1:EEINTF.EESDA 1 Data line to EEPROM BANK1:EEINTF.EEVDD 0 VDD control bit for EEPROM BANK1:RESERVED0091 0x0091 RESERVED BANK1:RESERVED0092 0x0092 RESERVED BANK1:RESERVED0093 0x0093 RESERVED BANK1:RESERVED0094 0x0094 RESERVED BANK1:RESERVED0095 0x0095 RESERVED BANK1:RESERVED0096 0x0096 RESERVED BANK1:RESERVED0097 0x0097 RESERVED BANK1:RESERVED0098 0x0098 RESERVED BANK1:RESERVED0099 0x0099 RESERVED BANK1:RESERVED009A 0x009A RESERVED BANK1:RESERVED009B 0x009B RESERVED BANK1:RESERVED009C 0x009C RESERVED BANK1:RESERVED009D 0x009D RESERVED BANK1:RESERVED009E 0x009E RESERVED BANK1:VRCON 0x009F VRCON REGISTER BANK1:VRCON.VREN 7 VREF Enable BANK1:VRCON.VROE 6 VREF Output Enable BANK1:VRCON.VRR 5 VREF Range selection BANK1:VRCON.VR3 3 VREF value selection 3 BANK1:VRCON.VR2 2 VREF value selection 2 BANK1:VRCON.VR1 1 VREF value selection 1 BANK1:VRCON.VR0 0 VREF value selection 0 .16CR83 ; http://www.microchip.com/download/lit/pline/picmicro/families/16f8x/30430c.pdf ; PIC16CR84_F84_CR83_F83.pdf ; MEMORY MAP ; BANK_0 area DATA FSR_ 0x0000:0x000C area DATA Gen_Purp 0x000C:0x0030 36 General Purpose Register (SRAM) area BSS RESERVED 0x0030:0x0080 area DATA MEM_Program 0x0080:0x0200 On-chip Program Memory ; BANK_1 ; area DATA FSR_ 0x0080:0x008C ; area DATA Gen_Purp_BANK0 0x008C:0x00B0 Mapped (accesses) in Bank 0 ; area BSS RESERVED 0x00B0:0x0100 ; area DATA MEM_Program 0x0100:0x0200 On-chip Program Memory ; Interrupt and reset vector assignments interrupt RESET 0x0000 RESET ; INPUT/OUTPUT PORTS ; BANK0 (0x0000:0x0080) BANK0:INDF 0x0000 INDF (not a physical register) BANK0:TMR0 0x0001 8-bit real-time clock/counter BANK0:PCL 0x0002 Low order 8 bits of the Program Counter (PC) BANK0:STATUS 0x0003 STATUS REGISTER BANK0:STATUS.IRP 7 Register Bank Select bit BANK0:STATUS.RP1 6 Register Bank Select bit 1 BANK0:STATUS.RP0 5 Register Bank Select bit 0 BANK0:STATUS.TO 4 Time-out bit BANK0:STATUS.PD 3 Power-down bit BANK0:STATUS.Z 2 Zero bit BANK0:STATUS.DC 1 Digit carry/borrow bit BANK0:STATUS.C 0 Carry/borrow bit BANK0:FSR 0x0004 Indirect data memory address pointer 0 BANK0:PORTA 0x0005 PORTA REGISTER BANK0:PORTA.RA4_T0CKI 4 PORTA bit 4 BANK0:PORTA.RA3 3 PORTA bit 3 BANK0:PORTA.RA2 2 PORTA bit 2 BANK0:PORTA.RA1 1 PORTA bit 1 BANK0:PORTA.RA0 0 PORTA bit 0 BANK0:PORTB 0x0006 PORTB REGISTER BANK0:PORTB.RB7 7 PORTB bit 7 BANK0:PORTB.RB6 6 PORTB bit 6 BANK0:PORTB.RB5 5 PORTB bit 5 BANK0:PORTB.RB4 4 PORTB bit 4 BANK0:PORTB.RB3 3 PORTB bit 3 BANK0:PORTB.RB2 2 PORTB bit 2 BANK0:PORTB.RB1 1 PORTB bit 1 BANK0:PORTB.RB0_INT 0 PORTB bit 0 BANK0:RESERVED0007 0x0007 RESERVED BANK0:EEDATA 0x0008 EEPROM data register BANK0:EEADR 0x0009 EEPROM address register BANK0:PCLATH 0x000A Write Buffer for upper 5 bits of the Program Counter BANK0:INTCON 0x000B INTCON REGISTER BANK0:INTCON.GIE 7 Global Interrupt Enable bit BANK0:INTCON.EEIE 6 EE Write Complete Interrupt Enable bit BANK0:INTCON.T0IE 5 TMR0 Overflow Interrupt Enable bit BANK0:INTCON.INTE 4 RB0/INT External Interrupt Enable bit BANK0:INTCON.RBIE 3 RB Port Change Interrupt Enable bit BANK0:INTCON.T0IF 2 TMR0 Overflow Interrupt Flag bit BANK0:INTCON.INTF 1 RB0/INT External Interrupt Flag bit BANK0:INTCON.RBIF 0 RB Port Change Interrupt Flag bit ; BANK1 (0x0080:0x0100) BANK1:INDF 0x0080 INDF (not a physical register) BANK1:OPTION 0x0081 OPTION REGISTER BANK1:OPTION.RBPU 7 PORTB Pull-up Enable bit BANK1:OPTION.INTEDG 6 Interrupt Edge Select bit BANK1:OPTION.T0CS 5 TMR0 Clock Source Select bit BANK1:OPTION.T0SE 4 TMR0 Source Edge Select bit BANK1:OPTION.PSA 3 Prescaler Assignment bit BANK1:OPTION.PS2 2 Prescaler Rate Select bit 2 BANK1:OPTION.PS1 1 Prescaler Rate Select bit 1 BANK1:OPTION.PS0 0 Prescaler Rate Select bit 0 BANK1:PCL 0x0082 Low order 8 bits of Program Counter (PC) BANK1:STATUS 0x0083 STATUS REGISTER BANK1:STATUS.IRP 7 Register Bank Select bit BANK1:STATUS.RP1 6 Register Bank Select bit 1 BANK1:STATUS.RP0 5 Register Bank Select bit 0 BANK1:STATUS.TO 4 Time-out bit BANK1:STATUS.PD 3 Power-down bit BANK1:STATUS.Z 2 Zero bit BANK1:STATUS.DC 1 Digit carry/borrow bit BANK1:STATUS.C 0 Carry/borrow bit BANK1:FSR 0x0084 Indirect data memory address pointer 0 BANK1:TRISA 0x0085 PORTA Data Direction Register BANK1:TRISA.TRISA4 4 PORTA Data Direction Register bit 4 BANK1:TRISA.TRISA3 3 PORTA Data Direction Register bit 3 BANK1:TRISA.TRISA2 2 PORTA Data Direction Register bit 2 BANK1:TRISA.TRISA1 1 PORTA Data Direction Register bit 1 BANK1:TRISA.TRISA0 0 PORTA Data Direction Register bit 0 BANK1:TRISB 0x0086 PORTB Data Direction Register BANK1:TRISB.TRISB7 7 PORTB Data Direction Register bit 7 BANK1:TRISB.TRISB6 6 PORTB Data Direction Register bit 6 BANK1:TRISB.TRISB5 5 PORTB Data Direction Register bit 5 BANK1:TRISB.TRISB4 4 PORTB Data Direction Register bit 4 BANK1:TRISB.TRISB3 3 PORTB Data Direction Register bit 3 BANK1:TRISB.TRISB2 2 PORTB Data Direction Register bit 2 BANK1:TRISB.TRISB1 1 PORTB Data Direction Register bit 1 BANK1:TRISB.TRISB0 0 PORTB Data Direction Register bit 0 BANK1:RESERVED0087 0x0087 RESERVED BANK1:EECON1 0x0088 EECON1 REGISTER BANK1:EECON1.EEIF 4 EEPROM Write Operation Interrupt Flag bit BANK1:EECON1.WRERR 3 EEPROM Error Flag bit BANK1:EECON1.WREN 2 EEPROM Write Enable bit BANK1:EECON1.WR 1 Write Control bit BANK1:EECON1.RD 0 Read Control bit BANK1:EECON2 0x0089 EEPROM control register 2 (not a physical register) BANK1:PCLATH 0x008A Write Buffer for upper 5 bits of the Program Counter BANK1:INTCON 0x008B INTCON REGISTER BANK1:INTCON.GIE 7 Global Interrupt Enable bit BANK1:INTCON.EEIE 6 EE Write Complete Interrupt Enable bit BANK1:INTCON.T0IE 5 TMR0 Overflow Interrupt Enable bit BANK1:INTCON.INTE 4 RB0/INT External Interrupt Enable bit BANK1:INTCON.RBIE 3 RB Port Change Interrupt Enable bit BANK1:INTCON.T0IF 2 TMR0 Overflow Interrupt Flag bit BANK1:INTCON.INTF 1 RB0/INT External Interrupt Flag bit BANK1:INTCON.RBIF 0 RB Port Change Interrupt Flag bit .16CR84 ; http://www.microchip.com/download/lit/pline/picmicro/families/16f8x/30430c.pdf ; PIC16CR84_F84_CR83_F83.pdf ; MEMORY MAP ; BANK_0 area DATA FSR_ 0x0000:0x000C area DATA Gen_Purp 0x000C:0x0050 68 General Purpose Register (SRAM) area BSS RESERVED 0x0050:0x0080 area DATA MEM_Program 0x0080:0x0200 On-chip Program Memory ; BANK_1 ; area DATA FSR_ 0x0080:0x008C ; area DATA Gen_Purp_BANK0 0x008C:0x00D0 Mapped (accesses) in Bank 0 ; area BSS RESERVED 0x00D0:0x0100 ; area DATA MEM_Program 0x0100:0x0200 On-chip Program Memory ; Interrupt and reset vector assignments interrupt RESET 0x0000 RESET ; INPUT/OUTPUT PORTS ; BANK0 (0x0000:0x0080) BANK0:INDF 0x0000 INDF (not a physical register) BANK0:TMR0 0x0001 8-bit real-time clock/counter BANK0:PCL 0x0002 Low order 8 bits of the Program Counter (PC) BANK0:STATUS 0x0003 STATUS REGISTER BANK0:STATUS.IRP 7 Register Bank Select bit BANK0:STATUS.RP1 6 Register Bank Select bit 1 BANK0:STATUS.RP0 5 Register Bank Select bit 0 BANK0:STATUS.TO 4 Time-out bit BANK0:STATUS.PD 3 Power-down bit BANK0:STATUS.Z 2 Zero bit BANK0:STATUS.DC 1 Digit carry/borrow bit BANK0:STATUS.C 0 Carry/borrow bit BANK0:FSR 0x0004 Indirect data memory address pointer 0 BANK0:PORTA 0x0005 PORTA REGISTER BANK0:PORTA.RA4_T0CKI 4 PORTA bit 4 BANK0:PORTA.RA3 3 PORTA bit 3 BANK0:PORTA.RA2 2 PORTA bit 2 BANK0:PORTA.RA1 1 PORTA bit 1 BANK0:PORTA.RA0 0 PORTA bit 0 BANK0:PORTB 0x0006 PORTB REGISTER BANK0:PORTB.RB7 7 PORTB bit 7 BANK0:PORTB.RB6 6 PORTB bit 6 BANK0:PORTB.RB5 5 PORTB bit 5 BANK0:PORTB.RB4 4 PORTB bit 4 BANK0:PORTB.RB3 3 PORTB bit 3 BANK0:PORTB.RB2 2 PORTB bit 2 BANK0:PORTB.RB1 1 PORTB bit 1 BANK0:PORTB.RB0_INT 0 PORTB bit 0 BANK0:RESERVED0007 0x0007 RESERVED BANK0:EEDATA 0x0008 EEPROM data register BANK0:EEADR 0x0009 EEPROM address register BANK0:PCLATH 0x000A Write Buffer for upper 5 bits of the Program Counter BANK0:INTCON 0x000B INTCON REGISTER BANK0:INTCON.GIE 7 Global Interrupt Enable bit BANK0:INTCON.EEIE 6 EE Write Complete Interrupt Enable bit BANK0:INTCON.T0IE 5 TMR0 Overflow Interrupt Enable bit BANK0:INTCON.INTE 4 RB0/INT External Interrupt Enable bit BANK0:INTCON.RBIE 3 RB Port Change Interrupt Enable bit BANK0:INTCON.T0IF 2 TMR0 Overflow Interrupt Flag bit BANK0:INTCON.INTF 1 RB0/INT External Interrupt Flag bit BANK0:INTCON.RBIF 0 RB Port Change Interrupt Flag bit ; BANK1 (0x0080:0x0100) BANK1:INDF 0x0080 INDF (not a physical register) BANK1:OPTION 0x0081 OPTION REGISTER BANK1:OPTION.RBPU 7 PORTB Pull-up Enable bit BANK1:OPTION.INTEDG 6 Interrupt Edge Select bit BANK1:OPTION.T0CS 5 TMR0 Clock Source Select bit BANK1:OPTION.T0SE 4 TMR0 Source Edge Select bit BANK1:OPTION.PSA 3 Prescaler Assignment bit BANK1:OPTION.PS2 2 Prescaler Rate Select bit 2 BANK1:OPTION.PS1 1 Prescaler Rate Select bit 1 BANK1:OPTION.PS0 0 Prescaler Rate Select bit 0 BANK1:PCL 0x0082 Low order 8 bits of Program Counter (PC) BANK1:STATUS 0x0083 STATUS REGISTER BANK1:STATUS.IRP 7 Register Bank Select bit BANK1:STATUS.RP1 6 Register Bank Select bit 1 BANK1:STATUS.RP0 5 Register Bank Select bit 0 BANK1:STATUS.TO 4 Time-out bit BANK1:STATUS.PD 3 Power-down bit BANK1:STATUS.Z 2 Zero bit BANK1:STATUS.DC 1 Digit carry/borrow bit BANK1:STATUS.C 0 Carry/borrow bit BANK1:FSR 0x0084 Indirect data memory address pointer 0 BANK1:TRISA 0x0085 PORTA Data Direction Register BANK1:TRISA.TRISA4 4 PORTA Data Direction Register bit 4 BANK1:TRISA.TRISA3 3 PORTA Data Direction Register bit 3 BANK1:TRISA.TRISA2 2 PORTA Data Direction Register bit 2 BANK1:TRISA.TRISA1 1 PORTA Data Direction Register bit 1 BANK1:TRISA.TRISA0 0 PORTA Data Direction Register bit 0 BANK1:TRISB 0x0086 PORTB Data Direction Register BANK1:TRISB.TRISB7 7 PORTB Data Direction Register bit 7 BANK1:TRISB.TRISB6 6 PORTB Data Direction Register bit 6 BANK1:TRISB.TRISB5 5 PORTB Data Direction Register bit 5 BANK1:TRISB.TRISB4 4 PORTB Data Direction Register bit 4 BANK1:TRISB.TRISB3 3 PORTB Data Direction Register bit 3 BANK1:TRISB.TRISB2 2 PORTB Data Direction Register bit 2 BANK1:TRISB.TRISB1 1 PORTB Data Direction Register bit 1 BANK1:TRISB.TRISB0 0 PORTB Data Direction Register bit 0 BANK1:RESERVED0087 0x0087 RESERVED BANK1:EECON1 0x0088 EECON1 REGISTER BANK1:EECON1.EEIF 4 EEPROM Write Operation Interrupt Flag bit BANK1:EECON1.WRERR 3 EEPROM Error Flag bit BANK1:EECON1.WREN 2 EEPROM Write Enable bit BANK1:EECON1.WR 1 Write Control bit BANK1:EECON1.RD 0 Read Control bit BANK1:EECON2 0x0089 EEPROM control register 2 (not a physical register) BANK1:PCLATH 0x008A Write Buffer for upper 5 bits of the Program Counter BANK1:INTCON 0x008B INTCON REGISTER BANK1:INTCON.GIE 7 Global Interrupt Enable bit BANK1:INTCON.EEIE 6 EE Write Complete Interrupt Enable bit BANK1:INTCON.T0IE 5 TMR0 Overflow Interrupt Enable bit BANK1:INTCON.INTE 4 RB0/INT External Interrupt Enable bit BANK1:INTCON.RBIE 3 RB Port Change Interrupt Enable bit BANK1:INTCON.T0IF 2 TMR0 Overflow Interrupt Flag bit BANK1:INTCON.INTF 1 RB0/INT External Interrupt Flag bit BANK1:INTCON.RBIF 0 RB Port Change Interrupt Flag bit .16F83 ; http://www.microchip.com/download/lit/pline/picmicro/families/16f8x/30430c.pdf ; PIC16CR84_F84_CR83_F83.pdf ; MEMORY MAP ; BANK_0 area DATA FSR_ 0x0000:0x000C area DATA Gen_Purp 0x000C:0x0030 36 General Purpose Register (SRAM) area BSS RESERVED 0x0030:0x0080 area DATA MEM_Program 0x0080:0x0200 On-chip Program Memory ; BANK_1 ; area DATA FSR_ 0x0080:0x008C ; area DATA Gen_Purp_BANK0 0x008C:0x00B0 Mapped (accesses) in Bank 0 ; area BSS RESERVED 0x00B0:0x0100 ; area DATA MEM_Program 0x0100:0x0200 On-chip Program Memory ; Interrupt and reset vector assignments interrupt RESET 0x0000 RESET ; INPUT/OUTPUT PORTS ; BANK0 (0x0000:0x0080) BANK0:INDF 0x0000 INDF (not a physical register) BANK0:TMR0 0x0001 8-bit real-time clock/counter BANK0:PCL 0x0002 Low order 8 bits of the Program Counter (PC) BANK0:STATUS 0x0003 STATUS REGISTER BANK0:STATUS.IRP 7 Register Bank Select bit BANK0:STATUS.RP1 6 Register Bank Select bit 1 BANK0:STATUS.RP0 5 Register Bank Select bit 0 BANK0:STATUS.TO 4 Time-out bit BANK0:STATUS.PD 3 Power-down bit BANK0:STATUS.Z 2 Zero bit BANK0:STATUS.DC 1 Digit carry/borrow bit BANK0:STATUS.C 0 Carry/borrow bit BANK0:FSR 0x0004 Indirect data memory address pointer 0 BANK0:PORTA 0x0005 PORTA REGISTER BANK0:PORTA.RA4_T0CKI 4 PORTA bit 4 BANK0:PORTA.RA3 3 PORTA bit 3 BANK0:PORTA.RA2 2 PORTA bit 2 BANK0:PORTA.RA1 1 PORTA bit 1 BANK0:PORTA.RA0 0 PORTA bit 0 BANK0:PORTB 0x0006 PORTB REGISTER BANK0:PORTB.RB7 7 PORTB bit 7 BANK0:PORTB.RB6 6 PORTB bit 6 BANK0:PORTB.RB5 5 PORTB bit 5 BANK0:PORTB.RB4 4 PORTB bit 4 BANK0:PORTB.RB3 3 PORTB bit 3 BANK0:PORTB.RB2 2 PORTB bit 2 BANK0:PORTB.RB1 1 PORTB bit 1 BANK0:PORTB.RB0_INT 0 PORTB bit 0 BANK0:RESERVED0007 0x0007 RESERVED BANK0:EEDATA 0x0008 EEPROM data register BANK0:EEADR 0x0009 EEPROM address register BANK0:PCLATH 0x000A Write Buffer for upper 5 bits of the Program Counter BANK0:INTCON 0x000B INTCON REGISTER BANK0:INTCON.GIE 7 Global Interrupt Enable bit BANK0:INTCON.EEIE 6 EE Write Complete Interrupt Enable bit BANK0:INTCON.T0IE 5 TMR0 Overflow Interrupt Enable bit BANK0:INTCON.INTE 4 RB0/INT External Interrupt Enable bit BANK0:INTCON.RBIE 3 RB Port Change Interrupt Enable bit BANK0:INTCON.T0IF 2 TMR0 Overflow Interrupt Flag bit BANK0:INTCON.INTF 1 RB0/INT External Interrupt Flag bit BANK0:INTCON.RBIF 0 RB Port Change Interrupt Flag bit ; BANK1 (0x0080:0x0100) BANK1:INDF 0x0080 INDF (not a physical register) BANK1:OPTION 0x0081 OPTION REGISTER BANK1:OPTION.RBPU 7 PORTB Pull-up Enable bit BANK1:OPTION.INTEDG 6 Interrupt Edge Select bit BANK1:OPTION.T0CS 5 TMR0 Clock Source Select bit BANK1:OPTION.T0SE 4 TMR0 Source Edge Select bit BANK1:OPTION.PSA 3 Prescaler Assignment bit BANK1:OPTION.PS2 2 Prescaler Rate Select bit 2 BANK1:OPTION.PS1 1 Prescaler Rate Select bit 1 BANK1:OPTION.PS0 0 Prescaler Rate Select bit 0 BANK1:PCL 0x0082 Low order 8 bits of Program Counter (PC) BANK1:STATUS 0x0083 STATUS REGISTER BANK1:STATUS.IRP 7 Register Bank Select bit BANK1:STATUS.RP1 6 Register Bank Select bit 1 BANK1:STATUS.RP0 5 Register Bank Select bit 0 BANK1:STATUS.TO 4 Time-out bit BANK1:STATUS.PD 3 Power-down bit BANK1:STATUS.Z 2 Zero bit BANK1:STATUS.DC 1 Digit carry/borrow bit BANK1:STATUS.C 0 Carry/borrow bit BANK1:FSR 0x0084 Indirect data memory address pointer 0 BANK1:TRISA 0x0085 PORTA Data Direction Register BANK1:TRISA.TRISA4 4 PORTA Data Direction Register bit 4 BANK1:TRISA.TRISA3 3 PORTA Data Direction Register bit 3 BANK1:TRISA.TRISA2 2 PORTA Data Direction Register bit 2 BANK1:TRISA.TRISA1 1 PORTA Data Direction Register bit 1 BANK1:TRISA.TRISA0 0 PORTA Data Direction Register bit 0 BANK1:TRISB 0x0086 PORTB Data Direction Register BANK1:TRISB.TRISB7 7 PORTB Data Direction Register bit 7 BANK1:TRISB.TRISB6 6 PORTB Data Direction Register bit 6 BANK1:TRISB.TRISB5 5 PORTB Data Direction Register bit 5 BANK1:TRISB.TRISB4 4 PORTB Data Direction Register bit 4 BANK1:TRISB.TRISB3 3 PORTB Data Direction Register bit 3 BANK1:TRISB.TRISB2 2 PORTB Data Direction Register bit 2 BANK1:TRISB.TRISB1 1 PORTB Data Direction Register bit 1 BANK1:TRISB.TRISB0 0 PORTB Data Direction Register bit 0 BANK1:RESERVED0087 0x0087 RESERVED BANK1:EECON1 0x0088 EECON1 REGISTER BANK1:EECON1.EEIF 4 EEPROM Write Operation Interrupt Flag bit BANK1:EECON1.WRERR 3 EEPROM Error Flag bit BANK1:EECON1.WREN 2 EEPROM Write Enable bit BANK1:EECON1.WR 1 Write Control bit BANK1:EECON1.RD 0 Read Control bit BANK1:EECON2 0x0089 EEPROM control register 2 (not a physical register) BANK1:PCLATH 0x008A Write Buffer for upper 5 bits of the Program Counter BANK1:INTCON 0x008B INTCON REGISTER BANK1:INTCON.GIE 7 Global Interrupt Enable bit BANK1:INTCON.EEIE 6 EE Write Complete Interrupt Enable bit BANK1:INTCON.T0IE 5 TMR0 Overflow Interrupt Enable bit BANK1:INTCON.INTE 4 RB0/INT External Interrupt Enable bit BANK1:INTCON.RBIE 3 RB Port Change Interrupt Enable bit BANK1:INTCON.T0IF 2 TMR0 Overflow Interrupt Flag bit BANK1:INTCON.INTF 1 RB0/INT External Interrupt Flag bit BANK1:INTCON.RBIF 0 RB Port Change Interrupt Flag bit .16F84 ; http://www.microchip.com/download/lit/pline/picmicro/families/16f8x/30430c.pdf ; PIC16CR84_F84_CR83_F83.pdf ; MEMORY MAP ; BANK_0 area DATA FSR_ 0x0000:0x000C area DATA Gen_Purp 0x000C:0x0050 68 General Purpose Register (SRAM) area BSS RESERVED 0x0050:0x0080 area DATA MEM_Program 0x0080:0x0200 On-chip Program Memory ; BANK_1 ; area DATA FSR_ 0x0080:0x008C ; area DATA Gen_Purp_BANK0 0x008C:0x00D0 Mapped (accesses) in Bank 0 ; area BSS RESERVED 0x00D0:0x0100 ; area DATA MEM_Program 0x0100:0x0200 On-chip Program Memory ; Interrupt and reset vector assignments interrupt RESET 0x0000 RESET ; INPUT/OUTPUT PORTS ; BANK0 (0x0000:0x0080) BANK0:INDF 0x0000 INDF (not a physical register) BANK0:TMR0 0x0001 8-bit real-time clock/counter BANK0:PCL 0x0002 Low order 8 bits of the Program Counter (PC) BANK0:STATUS 0x0003 STATUS REGISTER BANK0:STATUS.IRP 7 Register Bank Select bit BANK0:STATUS.RP1 6 Register Bank Select bit 1 BANK0:STATUS.RP0 5 Register Bank Select bit 0 BANK0:STATUS.TO 4 Time-out bit BANK0:STATUS.PD 3 Power-down bit BANK0:STATUS.Z 2 Zero bit BANK0:STATUS.DC 1 Digit carry/borrow bit BANK0:STATUS.C 0 Carry/borrow bit BANK0:FSR 0x0004 Indirect data memory address pointer 0 BANK0:PORTA 0x0005 PORTA REGISTER BANK0:PORTA.RA4_T0CKI 4 PORTA bit 4 BANK0:PORTA.RA3 3 PORTA bit 3 BANK0:PORTA.RA2 2 PORTA bit 2 BANK0:PORTA.RA1 1 PORTA bit 1 BANK0:PORTA.RA0 0 PORTA bit 0 BANK0:PORTB 0x0006 PORTB REGISTER BANK0:PORTB.RB7 7 PORTB bit 7 BANK0:PORTB.RB6 6 PORTB bit 6 BANK0:PORTB.RB5 5 PORTB bit 5 BANK0:PORTB.RB4 4 PORTB bit 4 BANK0:PORTB.RB3 3 PORTB bit 3 BANK0:PORTB.RB2 2 PORTB bit 2 BANK0:PORTB.RB1 1 PORTB bit 1 BANK0:PORTB.RB0_INT 0 PORTB bit 0 BANK0:RESERVED0007 0x0007 RESERVED BANK0:EEDATA 0x0008 EEPROM data register BANK0:EEADR 0x0009 EEPROM address register BANK0:PCLATH 0x000A Write Buffer for upper 5 bits of the Program Counter BANK0:INTCON 0x000B INTCON REGISTER BANK0:INTCON.GIE 7 Global Interrupt Enable bit BANK0:INTCON.EEIE 6 EE Write Complete Interrupt Enable bit BANK0:INTCON.T0IE 5 TMR0 Overflow Interrupt Enable bit BANK0:INTCON.INTE 4 RB0/INT External Interrupt Enable bit BANK0:INTCON.RBIE 3 RB Port Change Interrupt Enable bit BANK0:INTCON.T0IF 2 TMR0 Overflow Interrupt Flag bit BANK0:INTCON.INTF 1 RB0/INT External Interrupt Flag bit BANK0:INTCON.RBIF 0 RB Port Change Interrupt Flag bit ; BANK1 (0x0080:0x0100) BANK1:INDF 0x0080 INDF (not a physical register) BANK1:OPTION 0x0081 OPTION REGISTER BANK1:OPTION.RBPU 7 PORTB Pull-up Enable bit BANK1:OPTION.INTEDG 6 Interrupt Edge Select bit BANK1:OPTION.T0CS 5 TMR0 Clock Source Select bit BANK1:OPTION.T0SE 4 TMR0 Source Edge Select bit BANK1:OPTION.PSA 3 Prescaler Assignment bit BANK1:OPTION.PS2 2 Prescaler Rate Select bit 2 BANK1:OPTION.PS1 1 Prescaler Rate Select bit 1 BANK1:OPTION.PS0 0 Prescaler Rate Select bit 0 BANK1:PCL 0x0082 Low order 8 bits of Program Counter (PC) BANK1:STATUS 0x0083 STATUS REGISTER BANK1:STATUS.IRP 7 Register Bank Select bit BANK1:STATUS.RP1 6 Register Bank Select bit 1 BANK1:STATUS.RP0 5 Register Bank Select bit 0 BANK1:STATUS.TO 4 Time-out bit BANK1:STATUS.PD 3 Power-down bit BANK1:STATUS.Z 2 Zero bit BANK1:STATUS.DC 1 Digit carry/borrow bit BANK1:STATUS.C 0 Carry/borrow bit BANK1:FSR 0x0084 Indirect data memory address pointer 0 BANK1:TRISA 0x0085 PORTA Data Direction Register BANK1:TRISA.TRISA4 4 PORTA Data Direction Register bit 4 BANK1:TRISA.TRISA3 3 PORTA Data Direction Register bit 3 BANK1:TRISA.TRISA2 2 PORTA Data Direction Register bit 2 BANK1:TRISA.TRISA1 1 PORTA Data Direction Register bit 1 BANK1:TRISA.TRISA0 0 PORTA Data Direction Register bit 0 BANK1:TRISB 0x0086 PORTB Data Direction Register BANK1:TRISB.TRISB7 7 PORTB Data Direction Register bit 7 BANK1:TRISB.TRISB6 6 PORTB Data Direction Register bit 6 BANK1:TRISB.TRISB5 5 PORTB Data Direction Register bit 5 BANK1:TRISB.TRISB4 4 PORTB Data Direction Register bit 4 BANK1:TRISB.TRISB3 3 PORTB Data Direction Register bit 3 BANK1:TRISB.TRISB2 2 PORTB Data Direction Register bit 2 BANK1:TRISB.TRISB1 1 PORTB Data Direction Register bit 1 BANK1:TRISB.TRISB0 0 PORTB Data Direction Register bit 0 BANK1:RESERVED0087 0x0087 RESERVED BANK1:EECON1 0x0088 EECON1 REGISTER BANK1:EECON1.EEIF 4 EEPROM Write Operation Interrupt Flag bit BANK1:EECON1.WRERR 3 EEPROM Error Flag bit BANK1:EECON1.WREN 2 EEPROM Write Enable bit BANK1:EECON1.WR 1 Write Control bit BANK1:EECON1.RD 0 Read Control bit BANK1:EECON2 0x0089 EEPROM control register 2 (not a physical register) BANK1:PCLATH 0x008A Write Buffer for upper 5 bits of the Program Counter BANK1:INTCON 0x008B INTCON REGISTER BANK1:INTCON.GIE 7 Global Interrupt Enable bit BANK1:INTCON.EEIE 6 EE Write Complete Interrupt Enable bit BANK1:INTCON.T0IE 5 TMR0 Overflow Interrupt Enable bit BANK1:INTCON.INTE 4 RB0/INT External Interrupt Enable bit BANK1:INTCON.RBIE 3 RB Port Change Interrupt Enable bit BANK1:INTCON.T0IF 2 TMR0 Overflow Interrupt Flag bit BANK1:INTCON.INTF 1 RB0/INT External Interrupt Flag bit BANK1:INTCON.RBIF 0 RB Port Change Interrupt Flag bit .16F627 ; http://www.microchip.com/download/lit/pline/picmicro/families/16c62x/40300b.pdf ; PIC16F627_8.pdf ; MEMORY MAP ; BANK_0 area DATA FSR_ 0x0000:0x0020 area DATA Gen_Purp 0x0020:0x0080 General Purpose Register area DATA MEM_Program 0x0080:0x0400 On-chip Program Memory ; BANK_1 ; area DATA FSR_ 0x0080:0x00A0 ; area DATA Gen_Purp 0x00A0:0x00F0 General Purpose Register ; area DATA Gen_Purp_BANK0 0x00F0:0x0100 accesses 70h-7Fh ; area DATA MEM_Program 0x0100:0x0400 On-chip Program Memory ; BANK_2 ; area DATA FSR_ 0x0100:0x010C ; area BSS RESERVED 0x010C:0x0120 ; area DATA Gen_Purp 0x0120:0x0150 ; area BSS RESERVED 0x0150:0x0170 ; area DATA Gen_Purp_BANK0 0x0170:0x0180 accesses 70h-7Fh ; area DATA MEM_Program 0x0180:0x0400 On-chip Program Memory ; BANK_3 ; area DATA FSR_ 0x0180:0x018C ; area BSS RESERVED 0x018C:0x01F0 ; area DATA Gen_Purp_BANK0 0x01F0:0x0200 accesses 70h-7Fh ; area DATA MEM_Program 0x0200:0x0400 On-chip Program Memory ; Interrupt and reset vector assignments interrupt RESET 0x0000 RESET ; INPUT/OUTPUT PORTS ; BANK0 (0x0000:0x0080) BANK0:INDF 0x0000 INDF (not a physical register) BANK0:TMR0 0x0001 Timer0 module's register BANK0:PCL 0x0002 Program Counter's (PC) Least Significant Byte BANK0:STATUS 0x0003 STATUS REGISTER BANK0:STATUS.IRP 7 Register Bank Select bit BANK0:STATUS.RP1 6 Register Bank Select bit 1 BANK0:STATUS.RP0 5 Register Bank Select bit 0 BANK0:STATUS.TO 4 Time-out bit BANK0:STATUS.PD 3 Power-down bit BANK0:STATUS.Z 2 Zero bit BANK0:STATUS.DC 1 Digit carry/borrow bit BANK0:STATUS.C 0 Carry/borrow bit BANK0:FSR 0x0004 Indirect data memory address pointer BANK0:PORTA 0x0005 PORTA REGISTER BANK0:PORTA.RA7 7 PORTA bit 7 BANK0:PORTA.RA6 6 PORTA bit 6 BANK0:PORTA.RA5 5 PORTA bit 5 BANK0:PORTA.RA4 4 PORTA bit 4 BANK0:PORTA.RA3 3 PORTA bit 3 BANK0:PORTA.RA2 2 PORTA bit 2 BANK0:PORTA.RA1 1 PORTA bit 1 BANK0:PORTA.RA0 0 PORTA bit 0 BANK0:PORTB 0x0006 PORTB REGISTER BANK0:PORTB.RB7 7 PORTB bit 7 BANK0:PORTB.RB6 6 PORTB bit 6 BANK0:PORTB.RB5 5 PORTB bit 5 BANK0:PORTB.RB4 4 PORTB bit 4 BANK0:PORTB.RB3 3 PORTB bit 3 BANK0:PORTB.RB2 2 PORTB bit 2 BANK0:PORTB.RB1 1 PORTB bit 1 BANK0:PORTB.RB0 0 PORTB bit 0 BANK0:RESERVED0007 0x0007 RESERVED BANK0:RESERVED0008 0x0008 RESERVED BANK0:RESERVED0009 0x0009 RESERVED BANK0:PCLATH 0x000A Write Buffer for the upper 5 bits of the Program Counter BANK0:INTCON 0x000B INTCON REGISTER BANK0:INTCON.GIE 7 Global Interrupt Enable bit BANK0:INTCON.PEIE 6 Peripheral Interrupt Enable bit BANK0:INTCON.T0IE 5 TMR0 Overflow Interrupt Enable bit BANK0:INTCON.INTE 4 RB0/INT External Interrupt Enable bit BANK0:INTCON.RBIE 3 RB Port Change Interrupt Enable bit BANK0:INTCON.T0IF 2 TMR0 Overflow Interrupt Flag bit BANK0:INTCON.INTF 1 RB0/INT External Interrupt Flag bit BANK0:INTCON.RBIF 0 RB Port Change Interrupt Flag bit BANK0:PIR1 0x000C PIR1 REGISTER BANK0:PIR1.EEIF 7 EEPROM Write Operation Interrupt Flag bit BANK0:PIR1.CMIF 6 Comparator Interrupt Flag bit BANK0:PIR1.RCIF 5 USART Receive Interrupt Flag bit BANK0:PIR1.TXIF 4 USART Transmit Interrupt Flag bit BANK0:PIR1.CCP1IF 2 CCP1 Interrupt Flag bit BANK0:PIR1.TMR2IF 1 TMR2 to PR2 Match Interrupt Flag bit BANK0:PIR1.TMR1IF 0 TMR1 Overflow Interrupt Flag bit BANK0:RESERVED000D 0x000D RESERVED BANK0:TMR1L 0x000E Holding register for the Least Significant Byte of the 16-bit TMR1 register BANK0:TMR1H 0x000F Holding register for the Most Significant Byte of the 16-bit TMR1 register BANK0:T1CON 0x0010 TIMER1 CONTROL REGISTER BANK0:T1CON.T1CKPS1 5 Timer1 Input Clock Prescale Select bit 1 BANK0:T1CON.T1CKPS0 4 Timer1 Input Clock Prescale Select bit 0 BANK0:T1CON.T1OSCEN 3 Timer1 Oscillator Enable Control bit BANK0:T1CON.T1SYNC 2 Timer1 External Clock Input Synchronization Control bit BANK0:T1CON.TMR1CS 1 Timer1 Clock Source Select bit BANK0:T1CON.TMR1ON 0 Timer1 On bit BANK0:TMR2 0x0011 Timer2 module's register BANK0:T2CON 0x0012 TIMER2 CONTROL REGISTER BANK0:T2CON.TOUTPS3 6 Timer2 Output Postscale Select bit 3 BANK0:T2CON.TOUTPS2 5 Timer2 Output Postscale Select bit 2 BANK0:T2CON.TOUTPS1 4 Timer2 Output Postscale Select bit 1 BANK0:T2CON.TOUTPS0 3 Timer2 Output Postscale Select bit 0 BANK0:T2CON.TMR2ON 2 Timer2 On bit BANK0:T2CON.T2CKPS1 1 Timer2 Clock Prescale Select bit 1 BANK0:T2CON.T2CKPS0 0 Timer2 Clock Prescale Select bit 0 BANK0:RESERVED0013 0x0013 RESERVED BANK0:RESERVED0014 0x0014 RESERVED BANK0:CCPR1L 0x0015 Capture/Compare/PWM Register1 (LSB) BANK0:CCPR1H 0x0016 Capture/Compare/PWM Register1 (MSB) BANK0:CCP1CON 0x0017 CCP1CON REGISTER BANK0:CCP1CON.CCP1X 5 PWM Least Significant bit BANK0:CCP1CON.CCP1Y 4 PWM Least Significant bit BANK0:CCP1CON.CCP1M3 3 CCP1 Mode Select bit 3 BANK0:CCP1CON.CCP1M2 2 CCP1 Mode Select bit 2 BANK0:CCP1CON.CCP1M1 1 CCP1 Mode Select bit 1 BANK0:CCP1CON.CCP1M0 0 CCP1 Mode Select bit 0 BANK0:RCSTA 0x0018 RECEIVE STATUS AND CONTROL REGISTER BANK0:RCSTA.SPEN 7 Serial Port Enable bit BANK0:RCSTA.RX9 6 9-bit Receive Enable bit BANK0:RCSTA.SREN 5 Single Receive Enable bit BANK0:RCSTA.CREN 4 Continuous Receive Enable bit BANK0:RCSTA.ADEN 3 Address Detect Enable bit BANK0:RCSTA.FERR 2 Framing Error bit BANK0:RCSTA.OERR 1 Overrun Error bit BANK0:RCSTA.RX9D 0 9th bit of received data (Can be parity bit) BANK0:TXREG 0x0019 USART Transmit data register BANK0:RCREG 0x001A USART Receive data register BANK0:RESERVED001B 0x001B RESERVED BANK0:RESERVED001C 0x001C RESERVED BANK0:RESERVED001D 0x001D RESERVED BANK0:RESERVED001E 0x001E RESERVED BANK0:CMCON 0x001F CMCON REGISTER BANK0:CMCON.C2OUT 7 Comparator 2 output BANK0:CMCON.C1OUT 6 Comparator 1 output BANK0:CMCON.C2INV 5 Comparator 2 output inversion BANK0:CMCON.C1INV 4 Comparator 1 output inversion BANK0:CMCON.CIS 3 Comparator Input Switch BANK0:CMCON.CM2 2 Comparator mode 2 BANK0:CMCON.CM1 1 Comparator mode 1 BANK0:CMCON.CM0 0 Comparator mode 0 ; BANK1 (0x0080:0x0100) BANK1:INDF 0x0080 INDF (not a physical register) BANK1:OPTION 0x0081 OPTION REGISTER BANK1:OPTION.RBPU 7 PORTB Pull-up Enable bit BANK1:OPTION.INTEDG 6 Interrupt Edge Select bit BANK1:OPTION.T0CS 5 TMR0 Clock Source Select bit BANK1:OPTION.T0SE 4 TMR0 Source Edge Select bit BANK1:OPTION.PSA 3 Prescaler Assignment bit BANK1:OPTION.PS2 2 Prescaler Rate Select bit 2 BANK1:OPTION.PS1 1 Prescaler Rate Select bit 1 BANK1:OPTION.PS0 0 Prescaler Rate Select bit 0 BANK1:PCL 0x0082 Program Counter's (PC) Least Significant Byte BANK1:STATUS 0x0083 STATUS REGISTER BANK1:STATUS.IRP 7 Register Bank Select bit BANK1:STATUS.RP1 6 Register Bank Select bit 1 BANK1:STATUS.RP0 5 Register Bank Select bit 0 BANK1:STATUS.TO 4 Time-out bit BANK1:STATUS.PD 3 Power-down bit BANK1:STATUS.Z 2 Zero bit BANK1:STATUS.DC 1 Digit carry/borrow bit BANK1:STATUS.C 0 Carry/borrow bit BANK1:FSR 0x0084 Indirect data memory address pointer BANK1:TRISA 0x0085 PORTA Data Direction Register BANK1:TRISA.TRISA7 7 PORTA Data Direction Register bit 7 BANK1:TRISA.TRISA6 6 PORTA Data Direction Register bit 6 BANK1:TRISA.TRISA4 4 PORTA Data Direction Register bit 4 BANK1:TRISA.TRISA3 3 PORTA Data Direction Register bit 3 BANK1:TRISA.TRISA2 2 PORTA Data Direction Register bit 2 BANK1:TRISA.TRISA1 1 PORTA Data Direction Register bit 1 BANK1:TRISA.TRISA0 0 PORTA Data Direction Register bit 0 BANK1:TRISB 0x0086 PORTB Data Direction Register BANK1:TRISB.TRISB7 7 PORTB Data Direction Register bit 7 BANK1:TRISB.TRISB6 6 PORTB Data Direction Register bit 6 BANK1:TRISB.TRISB5 5 PORTB Data Direction Register bit 5 BANK1:TRISB.TRISB4 4 PORTB Data Direction Register bit 4 BANK1:TRISB.TRISB3 3 PORTB Data Direction Register bit 3 BANK1:TRISB.TRISB2 2 PORTB Data Direction Register bit 2 BANK1:TRISB.TRISB1 1 PORTB Data Direction Register bit 1 BANK1:TRISB.TRISB0 0 PORTB Data Direction Register bit 0 BANK1:RESERVED0087 0x0087 RESERVED BANK1:RESERVED0088 0x0088 RESERVED BANK1:RESERVED0089 0x0089 RESERVED BANK1:PCLATH 0x008A Write Buffer for the upper 5 bits of the Program Counter BANK1:INTCON 0x008B INTCON REGISTER BANK1:INTCON.GIE 7 Global Interrupt Enable bit BANK1:INTCON.PEIE 6 Peripheral Interrupt Enable bit BANK1:INTCON.T0IE 5 TMR0 Overflow Interrupt Enable bit BANK1:INTCON.INTE 4 RB0/INT External Interrupt Enable bit BANK1:INTCON.RBIE 3 RB Port Change Interrupt Enable bit BANK1:INTCON.T0IF 2 TMR0 Overflow Interrupt Flag bit BANK1:INTCON.INTF 1 RB0/INT External Interrupt Flag bit BANK1:INTCON.RBIF 0 RB Port Change Interrupt Flag bit BANK1:PIE1 0x008C PIE1 REGISTER BANK1:PIE1.EEIE 7 EE Write Complete Interrupt Enable Bit BANK1:PIE1.CMIE 6 Comparator Interrupt Enable bit BANK1:PIE1.RCIE 5 USART Receive Interrupt Enable bit BANK1:PIE1.TXIE 4 USART Transmit Interrupt Enable bit BANK1:PIE1.CCP1IE 2 CCP1 Interrupt Enable bit BANK1:PIE1.TMR2IE 1 TMR2 to PR2 Match Interrupt Enable bit BANK1:PIE1.TMR1IE 0 TMR1 Overflow Interrupt Enable bit BANK1:RESERVED008D 0x008D RESERVED BANK1:PCON 0x008E PCON REGISTER BANK1:PCON.OSCF 3 INTRC/ER oscillator speed BANK1:PCON.POR 1 Power-on Reset Status bit BANK1:PCON.BOR 0 Brown-out Reset Status bit BANK1:RESERVED008F 0x008F RESERVED BANK1:RESERVED0090 0x0090 RESERVED BANK1:RESERVED0091 0x0091 RESERVED BANK1:PR2 0x0092 Timer2 Period Register BANK1:RESERVED0093 0x0093 RESERVED BANK1:RESERVED0094 0x0094 RESERVED BANK1:RESERVED0095 0x0095 RESERVED BANK1:RESERVED0096 0x0096 RESERVED BANK1:RESERVED0097 0x0097 RESERVED BANK1:TXSTA 0x0098 TRANSMIT STATUS AND CONTROL REGISTER BANK1:TXSTA.CSRC 7 Clock Source Select bit BANK1:TXSTA.TX9 6 9-bit Transmit Enable bit BANK1:TXSTA.TXEN 5 Transmit Enable bit BANK1:TXSTA.SYNC 4 USART Mode Select bit BANK1:TXSTA.BRGH 2 High Baud Rate Select bit BANK1:TXSTA.TRMT 1 Transmit Shift Register Status bit BANK1:TXSTA.TX9D 0 9th bit of transmit data. Can be parity bit BANK1:SPBRG 0x0099 Baud Rate Generator Register BANK1:EEDATA 0x009A EEPROM data register BANK1:EEADR 0x009B EEPROM address register BANK1:EECON1 0x009C EECON1 REGISTER BANK1:EECON1.WRERR 3 EEPROM Error Flag bit BANK1:EECON1.WREN 2 EEPROM Write Enable bit BANK1:EECON1.WR 1 Write Control bit BANK1:EECON1.RD 0 Read Control bit BANK1:EECON2 0x009D EEPROM control register 2 (not a physical register) BANK1:RESERVED009E 0x009E RESERVED BANK1:VRCON 0x009F VRCON REGISTER( BANK1:VRCON.VREN 7 VREF Enable BANK1:VRCON.VROE 6 VREF Output Enable BANK1:VRCON.VRR 5 VREF Range selection BANK1:VRCON.VR3 3 VREF value selection 3 BANK1:VRCON.VR2 2 VREF value selection 2 BANK1:VRCON.VR1 1 VREF value selection 1 BANK1:VRCON.VR0 0 VREF value selection 0 ; BANK2 (0x0100:0x0180) BANK2:INDF 0x0100 INDF (not a physical register) BANK2:TMR0 0x0101 Timer0 module's register BANK2:PCL 0x0102 Program Counter's (PC) Least Significant Byte BANK2:STATUS 0x0103 STATUS REGISTER BANK2:STATUS.IRP 7 Register Bank Select bit BANK2:STATUS.RP1 6 Register Bank Select bit 1 BANK2:STATUS.RP0 5 Register Bank Select bit 0 BANK2:STATUS.TO 4 Time-out bit BANK2:STATUS.PD 3 Power-down bit BANK2:STATUS.Z 2 Zero bit BANK2:STATUS.DC 1 Digit carry/borrow bit BANK2:STATUS.C 0 Carry/borrow bit BANK2:FSR 0x0104 Indirect data memory address pointer BANK2:RESERVED0105 0x0105 RESERVED BANK2:PORTB 0x0106 PORTB REGISTER BANK2:PORTB.RB7 7 PORTB bit 7 BANK2:PORTB.RB6 6 PORTB bit 6 BANK2:PORTB.RB5 5 PORTB bit 5 BANK2:PORTB.RB4 4 PORTB bit 4 BANK2:PORTB.RB3 3 PORTB bit 3 BANK2:PORTB.RB2 2 PORTB bit 2 BANK2:PORTB.RB1 1 PORTB bit 1 BANK2:PORTB.RB0 0 PORTB bit 0 BANK2:RESERVED0107 0x0107 RESERVED BANK2:RESERVED0108 0x0108 RESERVED BANK2:RESERVED0109 0x0109 RESERVED BANK2:PCLATH 0x010A Write Buffer for the upper 5 bits of the Program Counter BANK2:INTCON 0x010B INTCON REGISTER BANK2:INTCON.GIE 7 Global Interrupt Enable bit BANK2:INTCON.PEIE 6 Peripheral Interrupt Enable bit BANK2:INTCON.T0IE 5 TMR0 Overflow Interrupt Enable bit BANK2:INTCON.INTE 4 RB0/INT External Interrupt Enable bit BANK2:INTCON.RBIE 3 RB Port Change Interrupt Enable bit BANK2:INTCON.T0IF 2 TMR0 Overflow Interrupt Flag bit BANK2:INTCON.INTF 1 RB0/INT External Interrupt Flag bit BANK2:INTCON.RBIF 0 RB Port Change Interrupt Flag bit ; BANK3 (0x0180:0x0200) BANK3:INDF 0x0180 INDF (not a physical register) BANK3:OPTION 0x0181 OPTION REGISTER BANK3:OPTION.RBPU 7 PORTB Pull-up Enable bit BANK3:OPTION.INTEDG 6 Interrupt Edge Select bit BANK3:OPTION.T0CS 5 TMR0 Clock Source Select bit BANK3:OPTION.T0SE 4 TMR0 Source Edge Select bit BANK3:OPTION.PSA 3 Prescaler Assignment bit BANK3:OPTION.PS2 2 Prescaler Rate Select bit 2 BANK3:OPTION.PS1 1 Prescaler Rate Select bit 1 BANK3:OPTION.PS0 0 Prescaler Rate Select bit 0 BANK3:PCL 0x0182 Program Counter's (PC) Least Significant Byte BANK3:STATUS 0x0183 STATUS REGISTER BANK3:STATUS.IRP 7 Register Bank Select bit BANK3:STATUS.RP1 6 Register Bank Select bit 1 BANK3:STATUS.RP0 5 Register Bank Select bit 0 BANK3:STATUS.TO 4 Time-out bit BANK3:STATUS.PD 3 Power-down bit BANK3:STATUS.Z 2 Zero bit BANK3:STATUS.DC 1 Digit carry/borrow bit BANK3:STATUS.C 0 Carry/borrow bit BANK3:FSR 0x0184 Indirect data memory address pointer BANK3:RESERVED0185 0x0185 RESERVED BANK3:TRISB 0x0186 PORTB Data Direction Register BANK3:TRISB.TRISB7 7 PORTB Data Direction Register bit 7 BANK3:TRISB.TRISB6 6 PORTB Data Direction Register bit 6 BANK3:TRISB.TRISB5 5 PORTB Data Direction Register bit 5 BANK3:TRISB.TRISB4 4 PORTB Data Direction Register bit 4 BANK3:TRISB.TRISB3 3 PORTB Data Direction Register bit 3 BANK3:TRISB.TRISB2 2 PORTB Data Direction Register bit 2 BANK3:TRISB.TRISB1 1 PORTB Data Direction Register bit 1 BANK3:TRISB.TRISB0 0 PORTB Data Direction Register bit 0 BANK3:RESERVED0187 0x0187 RESERVED BANK3:RESERVED0188 0x0188 RESERVED BANK3:RESERVED0189 0x0189 RESERVED BANK3:PCLATH 0x018A Write Buffer for the upper 5 bits of the Program Counter BANK3:INTCON 0x018B INTCON REGISTER BANK3:INTCON.GIE 7 Global Interrupt Enable bit BANK3:INTCON.PEIE 6 Peripheral Interrupt Enable bit BANK3:INTCON.T0IE 5 TMR0 Overflow Interrupt Enable bit BANK3:INTCON.INTE 4 RB0/INT External Interrupt Enable bit BANK3:INTCON.RBIE 3 RB Port Change Interrupt Enable bit BANK3:INTCON.T0IF 2 TMR0 Overflow Interrupt Flag bit BANK3:INTCON.INTF 1 RB0/INT External Interrupt Flag bit BANK3:INTCON.RBIF 0 RB Port Change Interrupt Flag bit .16F628 ; http://www.microchip.com/download/lit/pline/picmicro/families/16c62x/40300b.pdf ; PIC16F627_8.pdf ; MEMORY MAP ; BANK_0 area DATA FSR_ 0x0000:0x0020 area DATA Gen_Purp 0x0020:0x0080 General Purpose Register area DATA MEM_Program 0x0080:0x0800 On-chip Program Memory ; BANK_1 ; area DATA FSR_ 0x0080:0x00A0 ; area DATA Gen_Purp 0x00A0:0x00F0 General Purpose Register ; area DATA Gen_Purp_BANK0 0x00F0:0x0100 accesses 70h-7Fh ; area DATA MEM_Program 0x0100:0x0800 On-chip Program Memory ; BANK_2 ; area DATA FSR_ 0x0100:0x010C ; area BSS RESERVED 0x010C:0x0120 ; area DATA Gen_Purp 0x0120:0x0150 ; area BSS RESERVED 0x0150:0x0170 ; area DATA Gen_Purp_BANK0 0x0170:0x0180 accesses 70h-7Fh ; area DATA MEM_Program 0x0180:0x0800 On-chip Program Memory ; BANK_3 ; area DATA FSR_ 0x0180:0x018C ; area BSS RESERVED 0x018C:0x01F0 ; area DATA Gen_Purp_BANK0 0x01F0:0x0200 accesses 70h-7Fh ; area DATA MEM_Program 0x0200:0x0800 On-chip Program Memory ; Interrupt and reset vector assignments interrupt RESET 0x0000 RESET ; INPUT/OUTPUT PORTS ; BANK0 (0x0000:0x0080) BANK0:INDF 0x0000 INDF (not a physical register) BANK0:TMR0 0x0001 Timer0 module's register BANK0:PCL 0x0002 Program Counter's (PC) Least Significant Byte BANK0:STATUS 0x0003 STATUS REGISTER BANK0:STATUS.IRP 7 Register Bank Select bit BANK0:STATUS.RP1 6 Register Bank Select bit 1 BANK0:STATUS.RP0 5 Register Bank Select bit 0 BANK0:STATUS.TO 4 Time-out bit BANK0:STATUS.PD 3 Power-down bit BANK0:STATUS.Z 2 Zero bit BANK0:STATUS.DC 1 Digit carry/borrow bit BANK0:STATUS.C 0 Carry/borrow bit BANK0:FSR 0x0004 Indirect data memory address pointer BANK0:PORTA 0x0005 PORTA REGISTER BANK0:PORTA.RA7 7 PORTA bit 7 BANK0:PORTA.RA6 6 PORTA bit 6 BANK0:PORTA.RA5 5 PORTA bit 5 BANK0:PORTA.RA4 4 PORTA bit 4 BANK0:PORTA.RA3 3 PORTA bit 3 BANK0:PORTA.RA2 2 PORTA bit 2 BANK0:PORTA.RA1 1 PORTA bit 1 BANK0:PORTA.RA0 0 PORTA bit 0 BANK0:PORTB 0x0006 PORTB REGISTER BANK0:PORTB.RB7 7 PORTB bit 7 BANK0:PORTB.RB6 6 PORTB bit 6 BANK0:PORTB.RB5 5 PORTB bit 5 BANK0:PORTB.RB4 4 PORTB bit 4 BANK0:PORTB.RB3 3 PORTB bit 3 BANK0:PORTB.RB2 2 PORTB bit 2 BANK0:PORTB.RB1 1 PORTB bit 1 BANK0:PORTB.RB0 0 PORTB bit 0 BANK0:RESERVED0007 0x0007 RESERVED BANK0:RESERVED0008 0x0008 RESERVED BANK0:RESERVED0009 0x0009 RESERVED BANK0:PCLATH 0x000A Write Buffer for the upper 5 bits of the Program Counter BANK0:INTCON 0x000B INTCON REGISTER BANK0:INTCON.GIE 7 Global Interrupt Enable bit BANK0:INTCON.PEIE 6 Peripheral Interrupt Enable bit BANK0:INTCON.T0IE 5 TMR0 Overflow Interrupt Enable bit BANK0:INTCON.INTE 4 RB0/INT External Interrupt Enable bit BANK0:INTCON.RBIE 3 RB Port Change Interrupt Enable bit BANK0:INTCON.T0IF 2 TMR0 Overflow Interrupt Flag bit BANK0:INTCON.INTF 1 RB0/INT External Interrupt Flag bit BANK0:INTCON.RBIF 0 RB Port Change Interrupt Flag bit BANK0:PIR1 0x000C PIR1 REGISTER BANK0:PIR1.EEIF 7 EEPROM Write Operation Interrupt Flag bit BANK0:PIR1.CMIF 6 Comparator Interrupt Flag bit BANK0:PIR1.RCIF 5 USART Receive Interrupt Flag bit BANK0:PIR1.TXIF 4 USART Transmit Interrupt Flag bit BANK0:PIR1.CCP1IF 2 CCP1 Interrupt Flag bit BANK0:PIR1.TMR2IF 1 TMR2 to PR2 Match Interrupt Flag bit BANK0:PIR1.TMR1IF 0 TMR1 Overflow Interrupt Flag bit BANK0:RESERVED000D 0x000D RESERVED BANK0:TMR1L 0x000E Holding register for the Least Significant Byte of the 16-bit TMR1 register BANK0:TMR1H 0x000F Holding register for the Most Significant Byte of the 16-bit TMR1 register BANK0:T1CON 0x0010 TIMER1 CONTROL REGISTER BANK0:T1CON.T1CKPS1 5 Timer1 Input Clock Prescale Select bit 1 BANK0:T1CON.T1CKPS0 4 Timer1 Input Clock Prescale Select bit 0 BANK0:T1CON.T1OSCEN 3 Timer1 Oscillator Enable Control bit BANK0:T1CON.T1SYNC 2 Timer1 External Clock Input Synchronization Control bit BANK0:T1CON.TMR1CS 1 Timer1 Clock Source Select bit BANK0:T1CON.TMR1ON 0 Timer1 On bit BANK0:TMR2 0x0011 Timer2 module's register BANK0:T2CON 0x0012 TIMER2 CONTROL REGISTER BANK0:T2CON.TOUTPS3 6 Timer2 Output Postscale Select bit 3 BANK0:T2CON.TOUTPS2 5 Timer2 Output Postscale Select bit 2 BANK0:T2CON.TOUTPS1 4 Timer2 Output Postscale Select bit 1 BANK0:T2CON.TOUTPS0 3 Timer2 Output Postscale Select bit 0 BANK0:T2CON.TMR2ON 2 Timer2 On bit BANK0:T2CON.T2CKPS1 1 Timer2 Clock Prescale Select bit 1 BANK0:T2CON.T2CKPS0 0 Timer2 Clock Prescale Select bit 0 BANK0:RESERVED0013 0x0013 RESERVED BANK0:RESERVED0014 0x0014 RESERVED BANK0:CCPR1L 0x0015 Capture/Compare/PWM Register1 (LSB) BANK0:CCPR1H 0x0016 Capture/Compare/PWM Register1 (MSB) BANK0:CCP1CON 0x0017 CCP1CON REGISTER BANK0:CCP1CON.CCP1X 5 PWM Least Significant bit BANK0:CCP1CON.CCP1Y 4 PWM Least Significant bit BANK0:CCP1CON.CCP1M3 3 CCP1 Mode Select bit 3 BANK0:CCP1CON.CCP1M2 2 CCP1 Mode Select bit 2 BANK0:CCP1CON.CCP1M1 1 CCP1 Mode Select bit 1 BANK0:CCP1CON.CCP1M0 0 CCP1 Mode Select bit 0 BANK0:RCSTA 0x0018 RECEIVE STATUS AND CONTROL REGISTER BANK0:RCSTA.SPEN 7 Serial Port Enable bit BANK0:RCSTA.RX9 6 9-bit Receive Enable bit BANK0:RCSTA.SREN 5 Single Receive Enable bit BANK0:RCSTA.CREN 4 Continuous Receive Enable bit BANK0:RCSTA.ADEN 3 Address Detect Enable bit BANK0:RCSTA.FERR 2 Framing Error bit BANK0:RCSTA.OERR 1 Overrun Error bit BANK0:RCSTA.RX9D 0 9th bit of received data (Can be parity bit) BANK0:TXREG 0x0019 USART Transmit data register BANK0:RCREG 0x001A USART Receive data register BANK0:RESERVED001B 0x001B RESERVED BANK0:RESERVED001C 0x001C RESERVED BANK0:RESERVED001D 0x001D RESERVED BANK0:RESERVED001E 0x001E RESERVED BANK0:CMCON 0x001F CMCON REGISTER BANK0:CMCON.C2OUT 7 Comparator 2 output BANK0:CMCON.C1OUT 6 Comparator 1 output BANK0:CMCON.C2INV 5 Comparator 2 output inversion BANK0:CMCON.C1INV 4 Comparator 1 output inversion BANK0:CMCON.CIS 3 Comparator Input Switch BANK0:CMCON.CM2 2 Comparator mode 2 BANK0:CMCON.CM1 1 Comparator mode 1 BANK0:CMCON.CM0 0 Comparator mode 0 ; BANK1 (0x0080:0x0100) BANK1:INDF 0x0080 INDF (not a physical register) BANK1:OPTION 0x0081 OPTION REGISTER BANK1:OPTION.RBPU 7 PORTB Pull-up Enable bit BANK1:OPTION.INTEDG 6 Interrupt Edge Select bit BANK1:OPTION.T0CS 5 TMR0 Clock Source Select bit BANK1:OPTION.T0SE 4 TMR0 Source Edge Select bit BANK1:OPTION.PSA 3 Prescaler Assignment bit BANK1:OPTION.PS2 2 Prescaler Rate Select bit 2 BANK1:OPTION.PS1 1 Prescaler Rate Select bit 1 BANK1:OPTION.PS0 0 Prescaler Rate Select bit 0 BANK1:PCL 0x0082 Program Counter's (PC) Least Significant Byte BANK1:STATUS 0x0083 STATUS REGISTER BANK1:STATUS.IRP 7 Register Bank Select bit BANK1:STATUS.RP1 6 Register Bank Select bit 1 BANK1:STATUS.RP0 5 Register Bank Select bit 0 BANK1:STATUS.TO 4 Time-out bit BANK1:STATUS.PD 3 Power-down bit BANK1:STATUS.Z 2 Zero bit BANK1:STATUS.DC 1 Digit carry/borrow bit BANK1:STATUS.C 0 Carry/borrow bit BANK1:FSR 0x0084 Indirect data memory address pointer BANK1:TRISA 0x0085 PORTA Data Direction Register BANK1:TRISA.TRISA7 7 PORTA Data Direction Register bit 7 BANK1:TRISA.TRISA6 6 PORTA Data Direction Register bit 6 BANK1:TRISA.TRISA4 4 PORTA Data Direction Register bit 4 BANK1:TRISA.TRISA3 3 PORTA Data Direction Register bit 3 BANK1:TRISA.TRISA2 2 PORTA Data Direction Register bit 2 BANK1:TRISA.TRISA1 1 PORTA Data Direction Register bit 1 BANK1:TRISA.TRISA0 0 PORTA Data Direction Register bit 0 BANK1:TRISB 0x0086 PORTB Data Direction Register BANK1:TRISB.TRISB7 7 PORTB Data Direction Register bit 7 BANK1:TRISB.TRISB6 6 PORTB Data Direction Register bit 6 BANK1:TRISB.TRISB5 5 PORTB Data Direction Register bit 5 BANK1:TRISB.TRISB4 4 PORTB Data Direction Register bit 4 BANK1:TRISB.TRISB3 3 PORTB Data Direction Register bit 3 BANK1:TRISB.TRISB2 2 PORTB Data Direction Register bit 2 BANK1:TRISB.TRISB1 1 PORTB Data Direction Register bit 1 BANK1:TRISB.TRISB0 0 PORTB Data Direction Register bit 0 BANK1:RESERVED0087 0x0087 RESERVED BANK1:RESERVED0088 0x0088 RESERVED BANK1:RESERVED0089 0x0089 RESERVED BANK1:PCLATH 0x008A Write Buffer for the upper 5 bits of the Program Counter BANK1:INTCON 0x008B INTCON REGISTER BANK1:INTCON.GIE 7 Global Interrupt Enable bit BANK1:INTCON.PEIE 6 Peripheral Interrupt Enable bit BANK1:INTCON.T0IE 5 TMR0 Overflow Interrupt Enable bit BANK1:INTCON.INTE 4 RB0/INT External Interrupt Enable bit BANK1:INTCON.RBIE 3 RB Port Change Interrupt Enable bit BANK1:INTCON.T0IF 2 TMR0 Overflow Interrupt Flag bit BANK1:INTCON.INTF 1 RB0/INT External Interrupt Flag bit BANK1:INTCON.RBIF 0 RB Port Change Interrupt Flag bit BANK1:PIE1 0x008C PIE1 REGISTER BANK1:PIE1.EEIE 7 EE Write Complete Interrupt Enable Bit BANK1:PIE1.CMIE 6 Comparator Interrupt Enable bit BANK1:PIE1.RCIE 5 USART Receive Interrupt Enable bit BANK1:PIE1.TXIE 4 USART Transmit Interrupt Enable bit BANK1:PIE1.CCP1IE 2 CCP1 Interrupt Enable bit BANK1:PIE1.TMR2IE 1 TMR2 to PR2 Match Interrupt Enable bit BANK1:PIE1.TMR1IE 0 TMR1 Overflow Interrupt Enable bit BANK1:RESERVED008D 0x008D RESERVED BANK1:PCON 0x008E PCON REGISTER BANK1:PCON.OSCF 3 INTRC/ER oscillator speed BANK1:PCON.POR 1 Power-on Reset Status bit BANK1:PCON.BOR 0 Brown-out Reset Status bit BANK1:RESERVED008F 0x008F RESERVED BANK1:RESERVED0090 0x0090 RESERVED BANK1:RESERVED0091 0x0091 RESERVED BANK1:PR2 0x0092 Timer2 Period Register BANK1:RESERVED0093 0x0093 RESERVED BANK1:RESERVED0094 0x0094 RESERVED BANK1:RESERVED0095 0x0095 RESERVED BANK1:RESERVED0096 0x0096 RESERVED BANK1:RESERVED0097 0x0097 RESERVED BANK1:TXSTA 0x0098 TRANSMIT STATUS AND CONTROL REGISTER BANK1:TXSTA.CSRC 7 Clock Source Select bit BANK1:TXSTA.TX9 6 9-bit Transmit Enable bit BANK1:TXSTA.TXEN 5 Transmit Enable bit BANK1:TXSTA.SYNC 4 USART Mode Select bit BANK1:TXSTA.BRGH 2 High Baud Rate Select bit BANK1:TXSTA.TRMT 1 Transmit Shift Register Status bit BANK1:TXSTA.TX9D 0 9th bit of transmit data. Can be parity bit BANK1:SPBRG 0x0099 Baud Rate Generator Register BANK1:EEDATA 0x009A EEPROM data register BANK1:EEADR 0x009B EEPROM address register BANK1:EECON1 0x009C EECON1 REGISTER BANK1:EECON1.WRERR 3 EEPROM Error Flag bit BANK1:EECON1.WREN 2 EEPROM Write Enable bit BANK1:EECON1.WR 1 Write Control bit BANK1:EECON1.RD 0 Read Control bit BANK1:EECON2 0x009D EEPROM control register 2 (not a physical register) BANK1:RESERVED009E 0x009E RESERVED BANK1:VRCON 0x009F VRCON REGISTER( BANK1:VRCON.VREN 7 VREF Enable BANK1:VRCON.VROE 6 VREF Output Enable BANK1:VRCON.VRR 5 VREF Range selection BANK1:VRCON.VR3 3 VREF value selection 3 BANK1:VRCON.VR2 2 VREF value selection 2 BANK1:VRCON.VR1 1 VREF value selection 1 BANK1:VRCON.VR0 0 VREF value selection 0 ; BANK2 (0x0100:0x0180) BANK2:INDF 0x0100 INDF (not a physical register) BANK2:TMR0 0x0101 Timer0 module's register BANK2:PCL 0x0102 Program Counter's (PC) Least Significant Byte BANK2:STATUS 0x0103 STATUS REGISTER BANK2:STATUS.IRP 7 Register Bank Select bit BANK2:STATUS.RP1 6 Register Bank Select bit 1 BANK2:STATUS.RP0 5 Register Bank Select bit 0 BANK2:STATUS.TO 4 Time-out bit BANK2:STATUS.PD 3 Power-down bit BANK2:STATUS.Z 2 Zero bit BANK2:STATUS.DC 1 Digit carry/borrow bit BANK2:STATUS.C 0 Carry/borrow bit BANK2:FSR 0x0104 Indirect data memory address pointer BANK2:RESERVED0105 0x0105 RESERVED BANK2:PORTB 0x0106 PORTB REGISTER BANK2:PORTB.RB7 7 PORTB bit 7 BANK2:PORTB.RB6 6 PORTB bit 6 BANK2:PORTB.RB5 5 PORTB bit 5 BANK2:PORTB.RB4 4 PORTB bit 4 BANK2:PORTB.RB3 3 PORTB bit 3 BANK2:PORTB.RB2 2 PORTB bit 2 BANK2:PORTB.RB1 1 PORTB bit 1 BANK2:PORTB.RB0 0 PORTB bit 0 BANK2:RESERVED0107 0x0107 RESERVED BANK2:RESERVED0108 0x0108 RESERVED BANK2:RESERVED0109 0x0109 RESERVED BANK2:PCLATH 0x010A Write Buffer for the upper 5 bits of the Program Counter BANK2:INTCON 0x010B INTCON REGISTER BANK2:INTCON.GIE 7 Global Interrupt Enable bit BANK2:INTCON.PEIE 6 Peripheral Interrupt Enable bit BANK2:INTCON.T0IE 5 TMR0 Overflow Interrupt Enable bit BANK2:INTCON.INTE 4 RB0/INT External Interrupt Enable bit BANK2:INTCON.RBIE 3 RB Port Change Interrupt Enable bit BANK2:INTCON.T0IF 2 TMR0 Overflow Interrupt Flag bit BANK2:INTCON.INTF 1 RB0/INT External Interrupt Flag bit BANK2:INTCON.RBIF 0 RB Port Change Interrupt Flag bit ; BANK3 (0x0180:0x0200) BANK3:INDF 0x0180 INDF (not a physical register) BANK3:OPTION 0x0181 OPTION REGISTER BANK3:OPTION.RBPU 7 PORTB Pull-up Enable bit BANK3:OPTION.INTEDG 6 Interrupt Edge Select bit BANK3:OPTION.T0CS 5 TMR0 Clock Source Select bit BANK3:OPTION.T0SE 4 TMR0 Source Edge Select bit BANK3:OPTION.PSA 3 Prescaler Assignment bit BANK3:OPTION.PS2 2 Prescaler Rate Select bit 2 BANK3:OPTION.PS1 1 Prescaler Rate Select bit 1 BANK3:OPTION.PS0 0 Prescaler Rate Select bit 0 BANK3:PCL 0x0182 Program Counter's (PC) Least Significant Byte BANK3:STATUS 0x0183 STATUS REGISTER BANK3:STATUS.IRP 7 Register Bank Select bit BANK3:STATUS.RP1 6 Register Bank Select bit 1 BANK3:STATUS.RP0 5 Register Bank Select bit 0 BANK3:STATUS.TO 4 Time-out bit BANK3:STATUS.PD 3 Power-down bit BANK3:STATUS.Z 2 Zero bit BANK3:STATUS.DC 1 Digit carry/borrow bit BANK3:STATUS.C 0 Carry/borrow bit BANK3:FSR 0x0184 Indirect data memory address pointer BANK3:RESERVED0185 0x0185 RESERVED BANK3:TRISB 0x0186 PORTB Data Direction Register BANK3:TRISB.TRISB7 7 PORTB Data Direction Register bit 7 BANK3:TRISB.TRISB6 6 PORTB Data Direction Register bit 6 BANK3:TRISB.TRISB5 5 PORTB Data Direction Register bit 5 BANK3:TRISB.TRISB4 4 PORTB Data Direction Register bit 4 BANK3:TRISB.TRISB3 3 PORTB Data Direction Register bit 3 BANK3:TRISB.TRISB2 2 PORTB Data Direction Register bit 2 BANK3:TRISB.TRISB1 1 PORTB Data Direction Register bit 1 BANK3:TRISB.TRISB0 0 PORTB Data Direction Register bit 0 BANK3:RESERVED0187 0x0187 RESERVED BANK3:RESERVED0188 0x0188 RESERVED BANK3:RESERVED0189 0x0189 RESERVED BANK3:PCLATH 0x018A Write Buffer for the upper 5 bits of the Program Counter BANK3:INTCON 0x018B INTCON REGISTER BANK3:INTCON.GIE 7 Global Interrupt Enable bit BANK3:INTCON.PEIE 6 Peripheral Interrupt Enable bit BANK3:INTCON.T0IE 5 TMR0 Overflow Interrupt Enable bit BANK3:INTCON.INTE 4 RB0/INT External Interrupt Enable bit BANK3:INTCON.RBIE 3 RB Port Change Interrupt Enable bit BANK3:INTCON.T0IF 2 TMR0 Overflow Interrupt Flag bit BANK3:INTCON.INTF 1 RB0/INT External Interrupt Flag bit BANK3:INTCON.RBIF 0 RB Port Change Interrupt Flag bit .16F73 ; http://www.microchip.com/download/lit/pline/picmicro/families/16f7x/30325b.pdf ; PIC16F73_4_6_7.pdf ; MEMORY MAP ; BANK_0 area DATA FSR_ 0x0000:0x0020 area DATA Gen_Purp 0x0020:0x0080 General Purpose Register area DATA MEM_Program0 0x0080:0x0800 On-chip Program Memory (Page 0) area DATA MEM_Program1 0x0800:0x1000 On-chip Program Memory (Page 1) ; BANK_1 ; area DATA FSR_ 0x0080:0x00A0 ; area DATA Gen_Purp 0x00A0:0x0100 General Purpose Register ; area DATA MEM_Program0 0x0100:0x0800 On-chip Program Memory (Page 0) ; area DATA MEM_Program1 0x0800:0x1000 On-chip Program Memory (Page 1) ; BANK_2 ; area DATA FSR_ 0x0100:0x0110 ; area BSS RESERVED 0x0110:0x0120 ; area DATA Gen_Purp_BANK0 0x0120:0x0180 accesses 20h-7Fh ; area DATA MEM_Program0 0x0180:0x0800 On-chip Program Memory (Page 0) ; area DATA MEM_Program1 0x0800:0x1000 On-chip Program Memory (Page 1) ; BANK_3 ; area DATA FSR_ 0x0180:0x0190 ; area BSS RESERVED 0x0190:0x01A0 ; area DATA Gen_Purp_BANK1 0x01A0:0x0200 accesses A0h-FFh ; area DATA MEM_Program0 0x0200:0x0800 On-chip Program Memory (Page 0) ; area DATA MEM_Program1 0x0800:0x1000 On-chip Program Memory (Page 1) ; Interrupt and reset vector assignments interrupt RESET 0x0000 RESET ; INPUT/OUTPUT PORTS ; BANK0 (0x0000:0x0080) BANK0:INDF 0x0000 INDF (not a physical register) BANK0:TMR0 0x0001 Timer0 module's register BANK0:PCL 0x0002 Program Counter's (PC) Least Significant Byte BANK0:STATUS 0x0003 STATUS REGISTER BANK0:STATUS.IRP 7 RegIster Bank Select bit BANK0:STATUS.RP1 6 Register Bank Select bit 1 BANK0:STATUS.RP0 5 Register Bank Select bit 0 BANK0:STATUS.TO 4 Time-out bit BANK0:STATUS.PD 3 Power-down bit BANK0:STATUS.Z 2 Zero bit BANK0:STATUS.DC 1 Digit carry/borrow bit BANK0:STATUS.C 0 Carry/borrow bit BANK0:FSR 0x0004 Indirect data memory address pointer BANK0:PORTA 0x0005 PORTA register BANK0:PORTA.RA5 5 PORTA bit 5 BANK0:PORTA.RA4 4 PORTA bit 4 BANK0:PORTA.RA3 3 PORTA bit 3 BANK0:PORTA.RA2 2 PORTA bit 2 BANK0:PORTA.RA1 1 PORTA bit 1 BANK0:PORTA.RA0 0 PORTA bit 0 BANK0:PORTB 0x0006 PORTB register BANK0:PORTB.RB7 7 PORTB bit 7 BANK0:PORTB.RB6 6 PORTB bit 6 BANK0:PORTB.RB5 5 PORTB bit 5 BANK0:PORTB.RB4 4 PORTB bit 4 BANK0:PORTB.RB3 3 PORTB bit 3 BANK0:PORTB.RB2 2 PORTB bit 2 BANK0:PORTB.RB1 1 PORTB bit 1 BANK0:PORTB.RB0 0 PORTB bit 0 BANK0:PORTC 0x0007 PORTC register BANK0:PORTC.RC7 7 PORTC bit 7 BANK0:PORTC.RC6 6 PORTC bit 6 BANK0:PORTC.RC5 5 PORTC bit 5 BANK0:PORTC.RC4 4 PORTC bit 4 BANK0:PORTC.RC3 3 PORTC bit 3 BANK0:PORTC.RC2 2 PORTC bit 2 BANK0:PORTC.RC1 1 PORTC bit 1 BANK0:PORTC.RC0 0 PORTC bit 0 BANK0:PORTD 0x0008 PORTD register (not implemented on the 28-pin devices) BANK0:PORTD.RD7 7 PORTD bit 7 BANK0:PORTD.RD6 6 PORTD bit 6 BANK0:PORTD.RD5 5 PORTD bit 5 BANK0:PORTD.RD4 4 PORTD bit 4 BANK0:PORTD.RD3 3 PORTD bit 3 BANK0:PORTD.RD2 2 PORTD bit 2 BANK0:PORTD.RD1 1 PORTD bit 1 BANK0:PORTD.RD0 0 PORTD bit 0 BANK0:PORTE 0x0009 PORTE register (not implemented on the 28-pin devices) BANK0:PORTE.RE2 2 PORTE bit 2 BANK0:PORTE.RE1 1 PORTE bit 1 BANK0:PORTE.RE0 0 PORTE bit 0 BANK0:PCLATH 0x000A Write Buffer for the upper 5 bits of the Program Counter BANK0:INTCON 0x000B INTCON REGISTER BANK0:INTCON.GIE 7 Global Interrupt Enable bit BANK0:INTCON.PEIE 6 Peripheral Interrupt Enable bit BANK0:INTCON.TMR0IE 5 TMR0 Overflow Interrupt Enable bit BANK0:INTCON.INTE 4 RB0/INT External Interrupt Enable bit BANK0:INTCON.RBIE 3 RB Port Change Interrupt Enable bit BANK0:INTCON.TMR0IF 2 TMR0 Overflow Interrupt Flag bit BANK0:INTCON.INTF 1 RB0/INT External Interrupt Flag bit BANK0:INTCON.RBIF 0 RB Port Change Interrupt Flag bit BANK0:PIR1 0x000C PIR1 REGISTER BANK0:PIR1.PSPIF 7 Parallel Slave Port Interrupt Flag bit (reserved on the 28-pin devices) BANK0:PIR1.ADIF 6 A/D Converter Interrupt Flag bit BANK0:PIR1.RCIF 5 USART Receive Interrupt Flag bit BANK0:PIR1.TXIF 4 USART Transmit Interrupt Flag bit BANK0:PIR1.SSPIF 3 Synchronous Serial Port Interrupt Flag bit BANK0:PIR1.CCP1IF 2 CCP1 Interrupt Flag bit BANK0:PIR1.TMR2IF 1 TMR2 to PR2 Match Interrupt Flag bit BANK0:PIR1.TMR1IF 0 TMR1 Overflow Interrupt Flag bit BANK0:PIR2 0x000D PIR2 REGISTER BANK0:PIR2.CCP2IF 0 CCP2 Interrupt Flag bit BANK0:TMR1L 0x000E Holding register for the Least Significant Byte of the 16-bit TMR1 register BANK0:TMR1H 0x000F Holding register for the Most Significant Byte of the 16-bit TMR1 register BANK0:T1CON 0x0010 TIMER1 CONTROL REGISTER BANK0:T1CON.T1CKPS1 5 Timer1 Input Clock Prescale Select bit 1 BANK0:T1CON.T1CKPS0 4 Timer1 Input Clock Prescale Select bit 0 BANK0:T1CON.T1OSCEN 3 Timer1 Oscillator Enable Control bit BANK0:T1CON.T1SYNC 2 Timer1 External Clock Input Synchronization Control bit BANK0:T1CON.TMR1CS 1 Timer1 Clock Source Select bit BANK0:T1CON.TMR1ON 0 Timer1 On bit BANK0:TMR2 0x0011 Timer2 module's register BANK0:T2CON 0x0012 TIMER2 CONTROL REGISTER BANK0:T2CON.TOUTPS3 6 Timer2 Output Postscale Select bit 3 BANK0:T2CON.TOUTPS2 5 Timer2 Output Postscale Select bit 2 BANK0:T2CON.TOUTPS1 4 Timer2 Output Postscale Select bit 1 BANK0:T2CON.TOUTPS0 3 Timer2 Output Postscale Select bit 0 BANK0:T2CON.TMR2ON 2 Timer2 On bit BANK0:T2CON.T2CKPS1 1 Timer2 Clock Prescale Select bit 1 BANK0:T2CON.T2CKPS0 0 Timer2 Clock Prescale Select bit 0 BANK0:SSPBUF 0x0013 Synchronous Serial Port Receive Buffer/Transmit Register BANK0:SSPCON 0x0014 SYNC SERIAL PORT CONTROL REGISTER BANK0:SSPCON.WCOL 7 Write Collision Detect bit BANK0:SSPCON.SSPOV 6 Receive Overflow Indicator bit BANK0:SSPCON.SSPEN 5 Synchronous Serial Port Enable bit BANK0:SSPCON.CKP 4 Clock Polarity Select bit BANK0:SSPCON.SSPM3 3 Synchronous Serial Port Mode Select bit 3 BANK0:SSPCON.SSPM2 2 Synchronous Serial Port Mode Select bit 2 BANK0:SSPCON.SSPM1 1 Synchronous Serial Port Mode Select bit 1 BANK0:SSPCON.SSPM0 0 Synchronous Serial Port Mode Select bit 0 BANK0:CCPR1L 0x0015 Capture/Compare/PWM1 Register1 (LSB) BANK0:CCPR1H 0x0016 Capture/Compare/PWM1 Register1 (MSB) BANK0:CCP1CON 0x0017 CCP1CON REGISTER BANK0:CCP1CON.CCP1X 5 PWM Least Significant bit BANK0:CCP1CON.CCP1Y 4 PWM Least Significant bit BANK0:CCP1CON.CCP1M3 3 CCP1 Mode Select bit 3 BANK0:CCP1CON.CCP1M2 2 CCP1 Mode Select bit 2 BANK0:CCP1CON.CCP1M1 1 CCP1 Mode Select bit 1 BANK0:CCP1CON.CCP1M0 0 CCP1 Mode Select bit 0 BANK0:RCSTA 0x0018 RECEIVE STATUS AND CONTROL REGISTER BANK0:RCSTA.SPEN 7 Serial Port Enable bit BANK0:RCSTA.RX9 6 9-bit Receive Enable bit BANK0:RCSTA.SREN 5 Single Receive Enable bit BANK0:RCSTA.CREN 4 Continuous Receive Enable bit BANK0:RCSTA.FERR 2 Framing Error bit BANK0:RCSTA.OERR 1 Overrun Error bit BANK0:RCSTA.RX9D 0 9th bit of received data BANK0:TXREG 0x0019 USART Transmit Data Register BANK0:RCREG 0x001A USART Receive Data Register BANK0:CCPR2L 0x001B Capture/Compare/PWM2 Register2 (LSB) BANK0:CCPR2H 0x001C Capture/Compare/PWM2 Register2 (MSB) BANK0:CCP2CON 0x001D CCP2CON REGISTER BANK0:CCP2CON.CCP2X 5 PWM Least Significant bit BANK0:CCP2CON.CCP2Y 4 PWM Least Significant bit BANK0:CCP2CON.CCP2M3 3 CCP2 Mode Select bit 3 BANK0:CCP2CON.CCP2M2 2 CCP2 Mode Select bit 2 BANK0:CCP2CON.CCP2M1 1 CCP2 Mode Select bit 1 BANK0:CCP2CON.CCP2M0 0 CCP2 Mode Select bit 0 BANK0:ADRES 0x001E A/D Result Register Byte BANK0:ADCON0 0x001F ADCON0 REGISTER BANK0:ADCON0.ADCS1 7 A/D Conversion Clock Select bit 1 BANK0:ADCON0.ADCS0 6 A/D Conversion Clock Select bit 0 BANK0:ADCON0.CHS2 5 Analog Channel Select bit 2 BANK0:ADCON0.CHS1 4 Analog Channel Select bit 1 BANK0:ADCON0.CHS0 3 Analog Channel Select bit 0 BANK0:ADCON0.GO_DONE 2 A/D Conversion Status bit BANK0:ADCON0.ADON 0 A/D On bit ; BANK1 (0x0080:0x0100) BANK1:INDF 0x0080 INDF (not a physical register) BANK1:OPTION 0x0081 OPTION REGISTER BANK1:OPTION.RBPU 7 PORTB Pull-up Enable bit BANK1:OPTION.INTEDG 6 Interrupt Edge Select bit BANK1:OPTION.T0CS 5 TMR0 Clock Source Select bit BANK1:OPTION.T0SE 4 TMR0 Source Edge Select bit BANK1:OPTION.PSA 3 Prescaler Assignment bit BANK1:OPTION.PS2 2 Prescaler Rate Select bit 2 BANK1:OPTION.PS1 1 Prescaler Rate Select bit 1 BANK1:OPTION.PS0 0 Prescaler Rate Select bit 0 BANK1:PCL 0x0082 Program Counter's (PC) Least Significant Byte BANK1:STATUS 0x0083 STATUS REGISTER BANK1:STATUS.IRP 7 RegIster Bank Select bit BANK1:STATUS.RP1 6 Register Bank Select bit 1 BANK1:STATUS.RP0 5 Register Bank Select bit 0 BANK1:STATUS.TO 4 Time-out bit BANK1:STATUS.PD 3 Power-down bit BANK1:STATUS.Z 2 Zero bit BANK1:STATUS.DC 1 Digit carry/borrow bit BANK1:STATUS.C 0 Carry/borrow bit BANK1:FSR 0x0084 Indirect data memory address pointer BANK1:TRISA 0x0085 PORTA Data Direction Register BANK1:TRISA.TRISA5 5 PORTA Data Direction Register bit 5 BANK1:TRISA.TRISA4 4 PORTA Data Direction Register bit 4 BANK1:TRISA.TRISA3 3 PORTA Data Direction Register bit 3 BANK1:TRISA.TRISA2 2 PORTA Data Direction Register bit 2 BANK1:TRISA.TRISA1 1 PORTA Data Direction Register bit 1 BANK1:TRISA.TRISA0 0 PORTA Data Direction Register bit 0 BANK1:TRISB 0x0086 PORTB Data Direction Register BANK1:TRISB.TRISB7 7 PORTB Data Direction Register bit 7 BANK1:TRISB.TRISB6 6 PORTB Data Direction Register bit 6 BANK1:TRISB.TRISB5 5 PORTB Data Direction Register bit 5 BANK1:TRISB.TRISB4 4 PORTB Data Direction Register bit 4 BANK1:TRISB.TRISB3 3 PORTB Data Direction Register bit 3 BANK1:TRISB.TRISB2 2 PORTB Data Direction Register bit 2 BANK1:TRISB.TRISB1 1 PORTB Data Direction Register bit 1 BANK1:TRISB.TRISB0 0 PORTB Data Direction Register bit 0 BANK1:TRISC 0x0087 PORTC Data Direction Register BANK1:TRISC.TRISC7 7 PORTC Data Direction Register bit 7 BANK1:TRISC.TRISC6 6 PORTC Data Direction Register bit 6 BANK1:TRISC.TRISC5 5 PORTC Data Direction Register bit 5 BANK1:TRISC.TRISC4 4 PORTC Data Direction Register bit 4 BANK1:TRISC.TRISC3 3 PORTC Data Direction Register bit 3 BANK1:TRISC.TRISC2 2 PORTC Data Direction Register bit 2 BANK1:TRISC.TRISC1 1 PORTC Data Direction Register bit 1 BANK1:TRISC.TRISC0 0 PORTC Data Direction Register bit 0 BANK1:TRISD 0x0088 PORTD Data Direction Register (not implemented on the 28-pin devices) BANK1:TRISD.TRISD7 7 PORTD Data Direction Register bit 7 BANK1:TRISD.TRISD6 6 PORTD Data Direction Register bit 6 BANK1:TRISD.TRISD5 5 PORTD Data Direction Register bit 5 BANK1:TRISD.TRISD4 4 PORTD Data Direction Register bit 4 BANK1:TRISD.TRISD3 3 PORTD Data Direction Register bit 3 BANK1:TRISD.TRISD2 2 PORTD Data Direction Register bit 2 BANK1:TRISD.TRISD1 1 PORTD Data Direction Register bit 1 BANK1:TRISD.TRISD0 0 PORTD Data Direction Register bit 0 BANK1:TRISE 0x0089 PORTE Data Direction Bits (not implemented on the 28-pin devices) BANK1:TRISE.IBF 7 Input Buffer Full Status bit BANK1:TRISE.OBF 6 Output Buffer Full Status bit BANK1:TRISE.IBOV 5 Input Buffer Overflow Detect bit BANK1:TRISE.PSPMODE 4 Parallel Slave Port Mode Select bit BANK1:TRISE.TRISE2 2 Direction Control bit for pin RE2/CS/AN7 BANK1:TRISE.TRISE1 1 Direction Control bit for pin RE1/WR/AN6 BANK1:TRISE.TRISE0 0 Direction Control bit for pin RE0/RD/AN5 BANK1:PCLATH 0x008A Write Buffer for the upper 5 bits of the Program Counter BANK1:INTCON 0x008B INTCON REGISTER BANK1:INTCON.GIE 7 Global Interrupt Enable bit BANK1:INTCON.PEIE 6 Peripheral Interrupt Enable bit BANK1:INTCON.TMR0IE 5 TMR0 Overflow Interrupt Enable bit BANK1:INTCON.INTE 4 RB0/INT External Interrupt Enable bit BANK1:INTCON.RBIE 3 RB Port Change Interrupt Enable bit BANK1:INTCON.TMR0IF 2 TMR0 Overflow Interrupt Flag bit BANK1:INTCON.INTF 1 RB0/INT External Interrupt Flag bit BANK1:INTCON.RBIF 0 RB Port Change Interrupt Flag bit BANK1:PIE1 0x008C PIE1 REGISTER BANK1:PIE1.PSPIE 7 Parallel Slave Port Read/Write Interrupt Enable bit (reserved on the 28-pin devices) BANK1:PIE1.ADIE 6 BANK1:PIE1.RCIE 5 USART Receive Interrupt Enable bit BANK1:PIE1.TXIE 4 USART Transmit Interrupt Enable bit BANK1:PIE1.SSPIE 3 Synchronous Serial Port Interrupt Enable bit BANK1:PIE1.CCP1IE 2 CCP1 Interrupt Enable bit BANK1:PIE1.TMR2IE 1 TMR2 to PR2 Match Interrupt Enable bit BANK1:PIE1.TMR1IE 0 TMR1 Overflow Interrupt Enable bit BANK1:PIE2 0x008D PIE2 REGISTER BANK1:PIE2.CCP2IE 0 CCP2 Interrupt Enable bit BANK1:PCON 0x008E PCON REGISTER BANK1:PCON.POR 1 Power-on Reset Status bit BANK1:PCON.BOR 0 Brown-out Reset Status bit BANK1:RESERVED008F 0x008F RESERVED BANK1:RESERVED0090 0x0090 RESERVED BANK1:RESERVED0091 0x0091 RESERVED BANK1:PR2 0x0092 Timer2 Period Register BANK1:SSPADD 0x0093 Synchronous Serial Port (I2C mode) Address Register BANK1:SSPSTAT 0x0094 SYNC SERIAL PORT STATUS REGISTER BANK1:SSPSTAT.SMP 7 SPI data input sample phase BANK1:SSPSTAT.CKE 6 SPI Clock Edge Select BANK1:SSPSTAT.D_A 5 Data/Address bit (I2C mode only) BANK1:SSPSTAT.P 4 Stop bit (I2C mode only) BANK1:SSPSTAT.S 3 Start bit (I2C mode only) BANK1:SSPSTAT.R_W 2 Read/Write bit information (I2C mode only) BANK1:SSPSTAT.UA 1 Update Address (I2C mode only) BANK1:SSPSTAT.BF 0 Buffer Full Status bit BANK1:RESERVED0095 0x0095 RESERVED BANK1:RESERVED0096 0x0096 RESERVED BANK1:RESERVED0097 0x0097 RESERVED BANK1:TXSTA 0x0098 TRANSMIT STATUS AND CONTROL REGISTER BANK1:TXSTA.CSRC 7 Clock Source Select bit BANK1:TXSTA.TX9 6 9-bit Transmit Enable bit BANK1:TXSTA.TXEN 5 Transmit Enable bit BANK1:TXSTA.SYNC 4 USART Mode Select bit BANK1:TXSTA.BRGH 2 High Baud Rate Select bit BANK1:TXSTA.TRMT 1 Transmit Shift Register Status bit BANK1:TXSTA.TX9D 0 9th bit of transmit data BANK1:SPBRG 0x0099 Baud Rate Generator Register BANK1:RESERVED009A 0x009A RESERVED BANK1:RESERVED009B 0x009B RESERVED BANK1:RESERVED009C 0x009C RESERVED BANK1:RESERVED009D 0x009D RESERVED BANK1:RESERVED009E 0x009E RESERVED BANK1:ADCON1 0x009F ADCON1 REGISTER BANK1:ADCON1.PCFG2 2 A/D Port Configuration Control bit 2 BANK1:ADCON1.PCFG1 1 A/D Port Configuration Control bit 1 BANK1:ADCON1.PCFG0 0 A/D Port Configuration Control bit 0 ; BANK2 (0x0100:0x0180) BANK2:INDF 0x0100 INDF (not a physical register) BANK2:TMR0 0x0101 Timer0 module's register BANK2:PCL 0x0102 Program Counter's (PC) Least Significant Byte BANK2:STATUS 0x0103 STATUS REGISTER BANK2:STATUS.IRP 7 RegIster Bank Select bit BANK2:STATUS.RP1 6 Register Bank Select bit 1 BANK2:STATUS.RP0 5 Register Bank Select bit 0 BANK2:STATUS.TO 4 Time-out bit BANK2:STATUS.PD 3 Power-down bit BANK2:STATUS.Z 2 Zero bit BANK2:STATUS.DC 1 Digit carry/borrow bit BANK2:STATUS.C 0 Carry/borrow bit BANK2:FSR 0x0104 Indirect data memory address pointer BANK2:RESERVED0105 0x0105 RESERVED BANK2:PORTB 0x0106 PORTB register BANK2:PORTB.RB7 7 PORTB bit 7 BANK2:PORTB.RB6 6 PORTB bit 6 BANK2:PORTB.RB5 5 PORTB bit 5 BANK2:PORTB.RB4 4 PORTB bit 4 BANK2:PORTB.RB3 3 PORTB bit 3 BANK2:PORTB.RB2 2 PORTB bit 2 BANK2:PORTB.RB1 1 PORTB bit 1 BANK2:PORTB.RB0 0 PORTB bit 0 BANK2:RESERVED0107 0x0107 RESERVED BANK2:RESERVED0108 0x0108 RESERVED BANK2:RESERVED0109 0x0109 RESERVED BANK2:PCLATH 0x010A Write Buffer for the upper 5 bits of the Program Counter BANK2:INTCON 0x010B INTCON REGISTER BANK2:INTCON.GIE 7 Global Interrupt Enable bit BANK2:INTCON.PEIE 6 Peripheral Interrupt Enable bit BANK2:INTCON.TMR0IE 5 TMR0 Overflow Interrupt Enable bit BANK2:INTCON.INTE 4 RB0/INT External Interrupt Enable bit BANK2:INTCON.RBIE 3 RB Port Change Interrupt Enable bit BANK2:INTCON.TMR0IF 2 TMR0 Overflow Interrupt Flag bit BANK2:INTCON.INTF 1 RB0/INT External Interrupt Flag bit BANK2:INTCON.RBIF 0 RB Port Change Interrupt Flag bit BANK2:PMDATA 0x010C Data Register Low Byte BANK2:PMADR 0x010D Address Register Low Byte BANK2:PMDATH 0x010E Data Register High Byte BANK2:PMADRH 0x010F Address Register High Byte ; BANK3 (0x0180:0x0200) BANK3:INDF 0x0180 INDF (not a physical register) BANK3:OPTION 0x0181 OPTION REGISTER BANK3:OPTION.RBPU 7 PORTB Pull-up Enable bit BANK3:OPTION.INTEDG 6 Interrupt Edge Select bit BANK3:OPTION.T0CS 5 TMR0 Clock Source Select bit BANK3:OPTION.T0SE 4 TMR0 Source Edge Select bit BANK3:OPTION.PSA 3 Prescaler Assignment bit BANK3:OPTION.PS2 2 Prescaler Rate Select bit 2 BANK3:OPTION.PS1 1 Prescaler Rate Select bit 1 BANK3:OPTION.PS0 0 Prescaler Rate Select bit 0 BANK3:PCL 0x0182 Program Counter's (PC) Least Significant Byte BANK3:STATUS 0x0183 STATUS REGISTER BANK3:STATUS.IRP 7 RegIster Bank Select bit BANK3:STATUS.RP1 6 Register Bank Select bit 1 BANK3:STATUS.RP0 5 Register Bank Select bit 0 BANK3:STATUS.TO 4 Time-out bit BANK3:STATUS.PD 3 Power-down bit BANK3:STATUS.Z 2 Zero bit BANK3:STATUS.DC 1 Digit carry/borrow bit BANK3:STATUS.C 0 Carry/borrow bit BANK3:FSR 0x0184 Indirect data memory address pointer BANK3:RESERVED0185 0x0185 RESERVED BANK3:TRISB 0x0186 PORTB Data Direction Register BANK3:TRISB.TRISB7 7 PORTB Data Direction Register bit 7 BANK3:TRISB.TRISB6 6 PORTB Data Direction Register bit 6 BANK3:TRISB.TRISB5 5 PORTB Data Direction Register bit 5 BANK3:TRISB.TRISB4 4 PORTB Data Direction Register bit 4 BANK3:TRISB.TRISB3 3 PORTB Data Direction Register bit 3 BANK3:TRISB.TRISB2 2 PORTB Data Direction Register bit 2 BANK3:TRISB.TRISB1 1 PORTB Data Direction Register bit 1 BANK3:TRISB.TRISB0 0 PORTB Data Direction Register bit 0 BANK3:RESERVED0187 0x0187 RESERVED BANK3:RESERVED0188 0x0188 RESERVED BANK3:RESERVED0189 0x0189 RESERVED BANK3:PCLATH 0x018A Write Buffer for the upper 5 bits of the Program Counter BANK3:INTCON 0x018B INTCON REGISTER BANK3:INTCON.GIE 7 Global Interrupt Enable bit BANK3:INTCON.PEIE 6 Peripheral Interrupt Enable bit BANK3:INTCON.TMR0IE 5 TMR0 Overflow Interrupt Enable bit BANK3:INTCON.INTE 4 RB0/INT External Interrupt Enable bit BANK3:INTCON.RBIE 3 RB Port Change Interrupt Enable bit BANK3:INTCON.TMR0IF 2 TMR0 Overflow Interrupt Flag bit BANK3:INTCON.INTF 1 RB0/INT External Interrupt Flag bit BANK3:INTCON.RBIF 0 RB Port Change Interrupt Flag bit BANK3:PMCON1 0x018C PMCON1 REGISTER BANK3:PMCON1.RD 0 Read Control bit BANK3:RESERVED018D 0x018D RESERVED BANK3:RESERVED018E 0x018E RESERVED BANK3:RESERVED018F 0x018F RESERVED .16F74 ; http://www.microchip.com/download/lit/pline/picmicro/families/16f7x/30325b.pdf ; PIC16F73_4_6_7.pdf ; MEMORY MAP ; BANK_0 area DATA FSR_ 0x0000:0x0020 area DATA Gen_Purp 0x0020:0x0080 General Purpose Register area DATA MEM_Program0 0x0080:0x0800 On-chip Program Memory (Page 0) area DATA MEM_Program1 0x0800:0x1000 On-chip Program Memory (Page 1) ; BANK_1 ; area DATA FSR_ 0x0080:0x00A0 ; area DATA Gen_Purp 0x00A0:0x0100 General Purpose Register ; area DATA MEM_Program0 0x0100:0x0800 On-chip Program Memory (Page 0) ; area DATA MEM_Program1 0x0800:0x1000 On-chip Program Memory (Page 1) ; BANK_2 ; area DATA FSR_ 0x0100:0x0110 ; area BSS RESERVED 0x0110:0x0120 ; area DATA Gen_Purp_BANK0 0x0120:0x0180 accesses 20h-7Fh ; area DATA MEM_Program0 0x0180:0x0800 On-chip Program Memory (Page 0) ; area DATA MEM_Program1 0x0800:0x1000 On-chip Program Memory (Page 1) ; BANK_3 ; area DATA FSR_ 0x0180:0x0190 ; area BSS RESERVED 0x0190:0x01A0 ; area DATA Gen_Purp_BANK1 0x01A0:0x0200 accesses A0h-FFh ; area DATA MEM_Program0 0x0200:0x0800 On-chip Program Memory (Page 0) ; area DATA MEM_Program1 0x0800:0x1000 On-chip Program Memory (Page 1) ; Interrupt and reset vector assignments interrupt RESET 0x0000 RESET ; INPUT/OUTPUT PORTS ; BANK0 (0x0000:0x0080) BANK0:INDF 0x0000 INDF (not a physical register) BANK0:TMR0 0x0001 Timer0 module's register BANK0:PCL 0x0002 Program Counter's (PC) Least Significant Byte BANK0:STATUS 0x0003 STATUS REGISTER BANK0:STATUS.IRP 7 RegIster Bank Select bit BANK0:STATUS.RP1 6 Register Bank Select bit 1 BANK0:STATUS.RP0 5 Register Bank Select bit 0 BANK0:STATUS.TO 4 Time-out bit BANK0:STATUS.PD 3 Power-down bit BANK0:STATUS.Z 2 Zero bit BANK0:STATUS.DC 1 Digit carry/borrow bit BANK0:STATUS.C 0 Carry/borrow bit BANK0:FSR 0x0004 Indirect data memory address pointer BANK0:PORTA 0x0005 PORTA register BANK0:PORTA.RA5 5 PORTA bit 5 BANK0:PORTA.RA4 4 PORTA bit 4 BANK0:PORTA.RA3 3 PORTA bit 3 BANK0:PORTA.RA2 2 PORTA bit 2 BANK0:PORTA.RA1 1 PORTA bit 1 BANK0:PORTA.RA0 0 PORTA bit 0 BANK0:PORTB 0x0006 PORTB register BANK0:PORTB.RB7 7 PORTB bit 7 BANK0:PORTB.RB6 6 PORTB bit 6 BANK0:PORTB.RB5 5 PORTB bit 5 BANK0:PORTB.RB4 4 PORTB bit 4 BANK0:PORTB.RB3 3 PORTB bit 3 BANK0:PORTB.RB2 2 PORTB bit 2 BANK0:PORTB.RB1 1 PORTB bit 1 BANK0:PORTB.RB0 0 PORTB bit 0 BANK0:PORTC 0x0007 PORTC register BANK0:PORTC.RC7 7 PORTC bit 7 BANK0:PORTC.RC6 6 PORTC bit 6 BANK0:PORTC.RC5 5 PORTC bit 5 BANK0:PORTC.RC4 4 PORTC bit 4 BANK0:PORTC.RC3 3 PORTC bit 3 BANK0:PORTC.RC2 2 PORTC bit 2 BANK0:PORTC.RC1 1 PORTC bit 1 BANK0:PORTC.RC0 0 PORTC bit 0 BANK0:PORTD 0x0008 PORTD register (not implemented on the 28-pin devices) BANK0:PORTD.RD7 7 PORTD bit 7 BANK0:PORTD.RD6 6 PORTD bit 6 BANK0:PORTD.RD5 5 PORTD bit 5 BANK0:PORTD.RD4 4 PORTD bit 4 BANK0:PORTD.RD3 3 PORTD bit 3 BANK0:PORTD.RD2 2 PORTD bit 2 BANK0:PORTD.RD1 1 PORTD bit 1 BANK0:PORTD.RD0 0 PORTD bit 0 BANK0:PORTE 0x0009 PORTE register (not implemented on the 28-pin devices) BANK0:PORTE.RE2 2 PORTE bit 2 BANK0:PORTE.RE1 1 PORTE bit 1 BANK0:PORTE.RE0 0 PORTE bit 0 BANK0:PCLATH 0x000A Write Buffer for the upper 5 bits of the Program Counter BANK0:INTCON 0x000B INTCON REGISTER BANK0:INTCON.GIE 7 Global Interrupt Enable bit BANK0:INTCON.PEIE 6 Peripheral Interrupt Enable bit BANK0:INTCON.TMR0IE 5 TMR0 Overflow Interrupt Enable bit BANK0:INTCON.INTE 4 RB0/INT External Interrupt Enable bit BANK0:INTCON.RBIE 3 RB Port Change Interrupt Enable bit BANK0:INTCON.TMR0IF 2 TMR0 Overflow Interrupt Flag bit BANK0:INTCON.INTF 1 RB0/INT External Interrupt Flag bit BANK0:INTCON.RBIF 0 RB Port Change Interrupt Flag bit BANK0:PIR1 0x000C PIR1 REGISTER BANK0:PIR1.PSPIF 7 Parallel Slave Port Interrupt Flag bit (reserved on the 28-pin devices) BANK0:PIR1.ADIF 6 A/D Converter Interrupt Flag bit BANK0:PIR1.RCIF 5 USART Receive Interrupt Flag bit BANK0:PIR1.TXIF 4 USART Transmit Interrupt Flag bit BANK0:PIR1.SSPIF 3 Synchronous Serial Port Interrupt Flag bit BANK0:PIR1.CCP1IF 2 CCP1 Interrupt Flag bit BANK0:PIR1.TMR2IF 1 TMR2 to PR2 Match Interrupt Flag bit BANK0:PIR1.TMR1IF 0 TMR1 Overflow Interrupt Flag bit BANK0:PIR2 0x000D PIR2 REGISTER BANK0:PIR2.CCP2IF 0 CCP2 Interrupt Flag bit BANK0:TMR1L 0x000E Holding register for the Least Significant Byte of the 16-bit TMR1 register BANK0:TMR1H 0x000F Holding register for the Most Significant Byte of the 16-bit TMR1 register BANK0:T1CON 0x0010 TIMER1 CONTROL REGISTER BANK0:T1CON.T1CKPS1 5 Timer1 Input Clock Prescale Select bit 1 BANK0:T1CON.T1CKPS0 4 Timer1 Input Clock Prescale Select bit 0 BANK0:T1CON.T1OSCEN 3 Timer1 Oscillator Enable Control bit BANK0:T1CON.T1SYNC 2 Timer1 External Clock Input Synchronization Control bit BANK0:T1CON.TMR1CS 1 Timer1 Clock Source Select bit BANK0:T1CON.TMR1ON 0 Timer1 On bit BANK0:TMR2 0x0011 Timer2 module's register BANK0:T2CON 0x0012 TIMER2 CONTROL REGISTER BANK0:T2CON.TOUTPS3 6 Timer2 Output Postscale Select bit 3 BANK0:T2CON.TOUTPS2 5 Timer2 Output Postscale Select bit 2 BANK0:T2CON.TOUTPS1 4 Timer2 Output Postscale Select bit 1 BANK0:T2CON.TOUTPS0 3 Timer2 Output Postscale Select bit 0 BANK0:T2CON.TMR2ON 2 Timer2 On bit BANK0:T2CON.T2CKPS1 1 Timer2 Clock Prescale Select bit 1 BANK0:T2CON.T2CKPS0 0 Timer2 Clock Prescale Select bit 0 BANK0:SSPBUF 0x0013 Synchronous Serial Port Receive Buffer/Transmit Register BANK0:SSPCON 0x0014 SYNC SERIAL PORT CONTROL REGISTER BANK0:SSPCON.WCOL 7 Write Collision Detect bit BANK0:SSPCON.SSPOV 6 Receive Overflow Indicator bit BANK0:SSPCON.SSPEN 5 Synchronous Serial Port Enable bit BANK0:SSPCON.CKP 4 Clock Polarity Select bit BANK0:SSPCON.SSPM3 3 Synchronous Serial Port Mode Select bit 3 BANK0:SSPCON.SSPM2 2 Synchronous Serial Port Mode Select bit 2 BANK0:SSPCON.SSPM1 1 Synchronous Serial Port Mode Select bit 1 BANK0:SSPCON.SSPM0 0 Synchronous Serial Port Mode Select bit 0 BANK0:CCPR1L 0x0015 Capture/Compare/PWM1 Register1 (LSB) BANK0:CCPR1H 0x0016 Capture/Compare/PWM1 Register1 (MSB) BANK0:CCP1CON 0x0017 CCP1CON REGISTER BANK0:CCP1CON.CCP1X 5 PWM Least Significant bit BANK0:CCP1CON.CCP1Y 4 PWM Least Significant bit BANK0:CCP1CON.CCP1M3 3 CCP1 Mode Select bit 3 BANK0:CCP1CON.CCP1M2 2 CCP1 Mode Select bit 2 BANK0:CCP1CON.CCP1M1 1 CCP1 Mode Select bit 1 BANK0:CCP1CON.CCP1M0 0 CCP1 Mode Select bit 0 BANK0:RCSTA 0x0018 RECEIVE STATUS AND CONTROL REGISTER BANK0:RCSTA.SPEN 7 Serial Port Enable bit BANK0:RCSTA.RX9 6 9-bit Receive Enable bit BANK0:RCSTA.SREN 5 Single Receive Enable bit BANK0:RCSTA.CREN 4 Continuous Receive Enable bit BANK0:RCSTA.FERR 2 Framing Error bit BANK0:RCSTA.OERR 1 Overrun Error bit BANK0:RCSTA.RX9D 0 9th bit of received data BANK0:TXREG 0x0019 USART Transmit Data Register BANK0:RCREG 0x001A USART Receive Data Register BANK0:CCPR2L 0x001B Capture/Compare/PWM2 Register2 (LSB) BANK0:CCPR2H 0x001C Capture/Compare/PWM2 Register2 (MSB) BANK0:CCP2CON 0x001D CCP2CON REGISTER BANK0:CCP2CON.CCP2X 5 PWM Least Significant bit BANK0:CCP2CON.CCP2Y 4 PWM Least Significant bit BANK0:CCP2CON.CCP2M3 3 CCP2 Mode Select bit 3 BANK0:CCP2CON.CCP2M2 2 CCP2 Mode Select bit 2 BANK0:CCP2CON.CCP2M1 1 CCP2 Mode Select bit 1 BANK0:CCP2CON.CCP2M0 0 CCP2 Mode Select bit 0 BANK0:ADRES 0x001E A/D Result Register Byte BANK0:ADCON0 0x001F ADCON0 REGISTER BANK0:ADCON0.ADCS1 7 A/D Conversion Clock Select bit 1 BANK0:ADCON0.ADCS0 6 A/D Conversion Clock Select bit 0 BANK0:ADCON0.CHS2 5 Analog Channel Select bit 2 BANK0:ADCON0.CHS1 4 Analog Channel Select bit 1 BANK0:ADCON0.CHS0 3 Analog Channel Select bit 0 BANK0:ADCON0.GO_DONE 2 A/D Conversion Status bit BANK0:ADCON0.ADON 0 A/D On bit ; BANK1 (0x0080:0x0100) BANK1:INDF 0x0080 INDF (not a physical register) BANK1:OPTION 0x0081 OPTION REGISTER BANK1:OPTION.RBPU 7 PORTB Pull-up Enable bit BANK1:OPTION.INTEDG 6 Interrupt Edge Select bit BANK1:OPTION.T0CS 5 TMR0 Clock Source Select bit BANK1:OPTION.T0SE 4 TMR0 Source Edge Select bit BANK1:OPTION.PSA 3 Prescaler Assignment bit BANK1:OPTION.PS2 2 Prescaler Rate Select bit 2 BANK1:OPTION.PS1 1 Prescaler Rate Select bit 1 BANK1:OPTION.PS0 0 Prescaler Rate Select bit 0 BANK1:PCL 0x0082 Program Counter's (PC) Least Significant Byte BANK1:STATUS 0x0083 STATUS REGISTER BANK1:STATUS.IRP 7 RegIster Bank Select bit BANK1:STATUS.RP1 6 Register Bank Select bit 1 BANK1:STATUS.RP0 5 Register Bank Select bit 0 BANK1:STATUS.TO 4 Time-out bit BANK1:STATUS.PD 3 Power-down bit BANK1:STATUS.Z 2 Zero bit BANK1:STATUS.DC 1 Digit carry/borrow bit BANK1:STATUS.C 0 Carry/borrow bit BANK1:FSR 0x0084 Indirect data memory address pointer BANK1:TRISA 0x0085 PORTA Data Direction Register BANK1:TRISA.TRISA5 5 PORTA Data Direction Register bit 5 BANK1:TRISA.TRISA4 4 PORTA Data Direction Register bit 4 BANK1:TRISA.TRISA3 3 PORTA Data Direction Register bit 3 BANK1:TRISA.TRISA2 2 PORTA Data Direction Register bit 2 BANK1:TRISA.TRISA1 1 PORTA Data Direction Register bit 1 BANK1:TRISA.TRISA0 0 PORTA Data Direction Register bit 0 BANK1:TRISB 0x0086 PORTB Data Direction Register BANK1:TRISB.TRISB7 7 PORTB Data Direction Register bit 7 BANK1:TRISB.TRISB6 6 PORTB Data Direction Register bit 6 BANK1:TRISB.TRISB5 5 PORTB Data Direction Register bit 5 BANK1:TRISB.TRISB4 4 PORTB Data Direction Register bit 4 BANK1:TRISB.TRISB3 3 PORTB Data Direction Register bit 3 BANK1:TRISB.TRISB2 2 PORTB Data Direction Register bit 2 BANK1:TRISB.TRISB1 1 PORTB Data Direction Register bit 1 BANK1:TRISB.TRISB0 0 PORTB Data Direction Register bit 0 BANK1:TRISC 0x0087 PORTC Data Direction Register BANK1:TRISC.TRISC7 7 PORTC Data Direction Register bit 7 BANK1:TRISC.TRISC6 6 PORTC Data Direction Register bit 6 BANK1:TRISC.TRISC5 5 PORTC Data Direction Register bit 5 BANK1:TRISC.TRISC4 4 PORTC Data Direction Register bit 4 BANK1:TRISC.TRISC3 3 PORTC Data Direction Register bit 3 BANK1:TRISC.TRISC2 2 PORTC Data Direction Register bit 2 BANK1:TRISC.TRISC1 1 PORTC Data Direction Register bit 1 BANK1:TRISC.TRISC0 0 PORTC Data Direction Register bit 0 BANK1:TRISD 0x0088 PORTD Data Direction Register (not implemented on the 28-pin devices) BANK1:TRISD.TRISD7 7 PORTD Data Direction Register bit 7 BANK1:TRISD.TRISD6 6 PORTD Data Direction Register bit 6 BANK1:TRISD.TRISD5 5 PORTD Data Direction Register bit 5 BANK1:TRISD.TRISD4 4 PORTD Data Direction Register bit 4 BANK1:TRISD.TRISD3 3 PORTD Data Direction Register bit 3 BANK1:TRISD.TRISD2 2 PORTD Data Direction Register bit 2 BANK1:TRISD.TRISD1 1 PORTD Data Direction Register bit 1 BANK1:TRISD.TRISD0 0 PORTD Data Direction Register bit 0 BANK1:TRISE 0x0089 PORTE Data Direction Bits (not implemented on the 28-pin devices) BANK1:TRISE.IBF 7 Input Buffer Full Status bit BANK1:TRISE.OBF 6 Output Buffer Full Status bit BANK1:TRISE.IBOV 5 Input Buffer Overflow Detect bit BANK1:TRISE.PSPMODE 4 Parallel Slave Port Mode Select bit BANK1:TRISE.TRISE2 2 Direction Control bit for pin RE2/CS/AN7 BANK1:TRISE.TRISE1 1 Direction Control bit for pin RE1/WR/AN6 BANK1:TRISE.TRISE0 0 Direction Control bit for pin RE0/RD/AN5 BANK1:PCLATH 0x008A Write Buffer for the upper 5 bits of the Program Counter BANK1:INTCON 0x008B INTCON REGISTER BANK1:INTCON.GIE 7 Global Interrupt Enable bit BANK1:INTCON.PEIE 6 Peripheral Interrupt Enable bit BANK1:INTCON.TMR0IE 5 TMR0 Overflow Interrupt Enable bit BANK1:INTCON.INTE 4 RB0/INT External Interrupt Enable bit BANK1:INTCON.RBIE 3 RB Port Change Interrupt Enable bit BANK1:INTCON.TMR0IF 2 TMR0 Overflow Interrupt Flag bit BANK1:INTCON.INTF 1 RB0/INT External Interrupt Flag bit BANK1:INTCON.RBIF 0 RB Port Change Interrupt Flag bit BANK1:PIE1 0x008C PIE1 REGISTER BANK1:PIE1.PSPIE 7 Parallel Slave Port Read/Write Interrupt Enable bit (reserved on the 28-pin devices) BANK1:PIE1.ADIE 6 BANK1:PIE1.RCIE 5 USART Receive Interrupt Enable bit BANK1:PIE1.TXIE 4 USART Transmit Interrupt Enable bit BANK1:PIE1.SSPIE 3 Synchronous Serial Port Interrupt Enable bit BANK1:PIE1.CCP1IE 2 CCP1 Interrupt Enable bit BANK1:PIE1.TMR2IE 1 TMR2 to PR2 Match Interrupt Enable bit BANK1:PIE1.TMR1IE 0 TMR1 Overflow Interrupt Enable bit BANK1:PIE2 0x008D PIE2 REGISTER BANK1:PIE2.CCP2IE 0 CCP2 Interrupt Enable bit BANK1:PCON 0x008E PCON REGISTER BANK1:PCON.POR 1 Power-on Reset Status bit BANK1:PCON.BOR 0 Brown-out Reset Status bit BANK1:RESERVED008F 0x008F RESERVED BANK1:RESERVED0090 0x0090 RESERVED BANK1:RESERVED0091 0x0091 RESERVED BANK1:PR2 0x0092 Timer2 Period Register BANK1:SSPADD 0x0093 Synchronous Serial Port (I2C mode) Address Register BANK1:SSPSTAT 0x0094 SYNC SERIAL PORT STATUS REGISTER BANK1:SSPSTAT.SMP 7 SPI data input sample phase BANK1:SSPSTAT.CKE 6 SPI Clock Edge Select BANK1:SSPSTAT.D_A 5 Data/Address bit (I2C mode only) BANK1:SSPSTAT.P 4 Stop bit (I2C mode only) BANK1:SSPSTAT.S 3 Start bit (I2C mode only) BANK1:SSPSTAT.R_W 2 Read/Write bit information (I2C mode only) BANK1:SSPSTAT.UA 1 Update Address (I2C mode only) BANK1:SSPSTAT.BF 0 Buffer Full Status bit BANK1:RESERVED0095 0x0095 RESERVED BANK1:RESERVED0096 0x0096 RESERVED BANK1:RESERVED0097 0x0097 RESERVED BANK1:TXSTA 0x0098 TRANSMIT STATUS AND CONTROL REGISTER BANK1:TXSTA.CSRC 7 Clock Source Select bit BANK1:TXSTA.TX9 6 9-bit Transmit Enable bit BANK1:TXSTA.TXEN 5 Transmit Enable bit BANK1:TXSTA.SYNC 4 USART Mode Select bit BANK1:TXSTA.BRGH 2 High Baud Rate Select bit BANK1:TXSTA.TRMT 1 Transmit Shift Register Status bit BANK1:TXSTA.TX9D 0 9th bit of transmit data BANK1:SPBRG 0x0099 Baud Rate Generator Register BANK1:RESERVED009A 0x009A RESERVED BANK1:RESERVED009B 0x009B RESERVED BANK1:RESERVED009C 0x009C RESERVED BANK1:RESERVED009D 0x009D RESERVED BANK1:RESERVED009E 0x009E RESERVED BANK1:ADCON1 0x009F ADCON1 REGISTER BANK1:ADCON1.PCFG2 2 A/D Port Configuration Control bit 2 BANK1:ADCON1.PCFG1 1 A/D Port Configuration Control bit 1 BANK1:ADCON1.PCFG0 0 A/D Port Configuration Control bit 0 ; BANK2 (0x0100:0x0180) BANK2:INDF 0x0100 INDF (not a physical register) BANK2:TMR0 0x0101 Timer0 module's register BANK2:PCL 0x0102 Program Counter's (PC) Least Significant Byte BANK2:STATUS 0x0103 STATUS REGISTER BANK2:STATUS.IRP 7 RegIster Bank Select bit BANK2:STATUS.RP1 6 Register Bank Select bit 1 BANK2:STATUS.RP0 5 Register Bank Select bit 0 BANK2:STATUS.TO 4 Time-out bit BANK2:STATUS.PD 3 Power-down bit BANK2:STATUS.Z 2 Zero bit BANK2:STATUS.DC 1 Digit carry/borrow bit BANK2:STATUS.C 0 Carry/borrow bit BANK2:FSR 0x0104 Indirect data memory address pointer BANK2:RESERVED0105 0x0105 RESERVED BANK2:PORTB 0x0106 PORTB register BANK2:PORTB.RB7 7 PORTB bit 7 BANK2:PORTB.RB6 6 PORTB bit 6 BANK2:PORTB.RB5 5 PORTB bit 5 BANK2:PORTB.RB4 4 PORTB bit 4 BANK2:PORTB.RB3 3 PORTB bit 3 BANK2:PORTB.RB2 2 PORTB bit 2 BANK2:PORTB.RB1 1 PORTB bit 1 BANK2:PORTB.RB0 0 PORTB bit 0 BANK2:RESERVED0107 0x0107 RESERVED BANK2:RESERVED0108 0x0108 RESERVED BANK2:RESERVED0109 0x0109 RESERVED BANK2:PCLATH 0x010A Write Buffer for the upper 5 bits of the Program Counter BANK2:INTCON 0x010B INTCON REGISTER BANK2:INTCON.GIE 7 Global Interrupt Enable bit BANK2:INTCON.PEIE 6 Peripheral Interrupt Enable bit BANK2:INTCON.TMR0IE 5 TMR0 Overflow Interrupt Enable bit BANK2:INTCON.INTE 4 RB0/INT External Interrupt Enable bit BANK2:INTCON.RBIE 3 RB Port Change Interrupt Enable bit BANK2:INTCON.TMR0IF 2 TMR0 Overflow Interrupt Flag bit BANK2:INTCON.INTF 1 RB0/INT External Interrupt Flag bit BANK2:INTCON.RBIF 0 RB Port Change Interrupt Flag bit BANK2:PMDATA 0x010C Data Register Low Byte BANK2:PMADR 0x010D Address Register Low Byte BANK2:PMDATH 0x010E Data Register High Byte BANK2:PMADRH 0x010F Address Register High Byte ; BANK3 (0x0180:0x0200) BANK3:INDF 0x0180 INDF (not a physical register) BANK3:OPTION 0x0181 OPTION REGISTER BANK3:OPTION.RBPU 7 PORTB Pull-up Enable bit BANK3:OPTION.INTEDG 6 Interrupt Edge Select bit BANK3:OPTION.T0CS 5 TMR0 Clock Source Select bit BANK3:OPTION.T0SE 4 TMR0 Source Edge Select bit BANK3:OPTION.PSA 3 Prescaler Assignment bit BANK3:OPTION.PS2 2 Prescaler Rate Select bit 2 BANK3:OPTION.PS1 1 Prescaler Rate Select bit 1 BANK3:OPTION.PS0 0 Prescaler Rate Select bit 0 BANK3:PCL 0x0182 Program Counter's (PC) Least Significant Byte BANK3:STATUS 0x0183 STATUS REGISTER BANK3:STATUS.IRP 7 RegIster Bank Select bit BANK3:STATUS.RP1 6 Register Bank Select bit 1 BANK3:STATUS.RP0 5 Register Bank Select bit 0 BANK3:STATUS.TO 4 Time-out bit BANK3:STATUS.PD 3 Power-down bit BANK3:STATUS.Z 2 Zero bit BANK3:STATUS.DC 1 Digit carry/borrow bit BANK3:STATUS.C 0 Carry/borrow bit BANK3:FSR 0x0184 Indirect data memory address pointer BANK3:RESERVED0185 0x0185 RESERVED BANK3:TRISB 0x0186 PORTB Data Direction Register BANK3:TRISB.TRISB7 7 PORTB Data Direction Register bit 7 BANK3:TRISB.TRISB6 6 PORTB Data Direction Register bit 6 BANK3:TRISB.TRISB5 5 PORTB Data Direction Register bit 5 BANK3:TRISB.TRISB4 4 PORTB Data Direction Register bit 4 BANK3:TRISB.TRISB3 3 PORTB Data Direction Register bit 3 BANK3:TRISB.TRISB2 2 PORTB Data Direction Register bit 2 BANK3:TRISB.TRISB1 1 PORTB Data Direction Register bit 1 BANK3:TRISB.TRISB0 0 PORTB Data Direction Register bit 0 BANK3:RESERVED0187 0x0187 RESERVED BANK3:RESERVED0188 0x0188 RESERVED BANK3:RESERVED0189 0x0189 RESERVED BANK3:PCLATH 0x018A Write Buffer for the upper 5 bits of the Program Counter BANK3:INTCON 0x018B INTCON REGISTER BANK3:INTCON.GIE 7 Global Interrupt Enable bit BANK3:INTCON.PEIE 6 Peripheral Interrupt Enable bit BANK3:INTCON.TMR0IE 5 TMR0 Overflow Interrupt Enable bit BANK3:INTCON.INTE 4 RB0/INT External Interrupt Enable bit BANK3:INTCON.RBIE 3 RB Port Change Interrupt Enable bit BANK3:INTCON.TMR0IF 2 TMR0 Overflow Interrupt Flag bit BANK3:INTCON.INTF 1 RB0/INT External Interrupt Flag bit BANK3:INTCON.RBIF 0 RB Port Change Interrupt Flag bit BANK3:PMCON1 0x018C PMCON1 REGISTER BANK3:PMCON1.RD 0 Read Control bit BANK3:RESERVED018D 0x018D RESERVED BANK3:RESERVED018E 0x018E RESERVED BANK3:RESERVED018F 0x018F RESERVED .16F76 ; http://www.microchip.com/download/lit/pline/picmicro/families/16f7x/30325b.pdf ; PIC16F73_4_6_7.pdf ; MEMORY MAP ; BANK_0 area DATA FSR_ 0x0000:0x0020 area DATA Gen_Purp 0x0020:0x0080 General Purpose Register area DATA MEM_Program0 0x0080:0x0800 On-chip Program Memory (Page 0) area DATA MEM_Program1 0x0800:0x1000 On-chip Program Memory (Page 1) area DATA MEM_Program2 0x1000:0x1800 On-chip Program Memory (Page 2) area DATA MEM_Program3 0x1800:0x2000 On-chip Program Memory (Page 3) ; BANK_1 ; area DATA FSR_ 0x0080:0x00A0 ; area DATA Gen_Purp 0x00A0:0x00F0 General Purpose Register ; area DATA Gen_Purp_BANK0 0x00F0:0x0100 accesses 70h-7Fh ; area DATA MEM_Program0 0x0100:0x0800 On-chip Program Memory (Page 0) ; area DATA MEM_Program1 0x0800:0x1000 On-chip Program Memory (Page 1) ; area DATA MEM_Program2 0x1000:0x1800 On-chip Program Memory (Page 2) ; area DATA MEM_Program3 0x1800:0x2000 On-chip Program Memory (Page 3) ; BANK_2 ; area DATA FSR_ 0x0100:0x0110 ; area DATA Gen_Purp0 0x0110:0x0120 General Purpose Register 16 Bytes ; area DATA Gen_Purp1 0x0120:0x0170 General Purpose Register 80 Bytes ; area DATA Gen_Purp_BANK0 0x0170:0x0180 accesses 70h-7Fh ; area DATA MEM_Program0 0x0180:0x0800 On-chip Program Memory (Page 0) ; area DATA MEM_Program1 0x0800:0x1000 On-chip Program Memory (Page 1) ; area DATA MEM_Program2 0x1000:0x1800 On-chip Program Memory (Page 2) ; area DATA MEM_Program3 0x1800:0x2000 On-chip Program Memory (Page 3) ; BANK_3 ; area DATA FSR_ 0x0180:0x0190 ; area DATA Gen_Purp0 0x0190:0x01A0 General Purpose Register 16 Bytes ; area DATA Gen_Purp1 0x01A0:0x01F0 General Purpose Register 80 Bytes ; area DATA Gen_Purp_BANK0 0x01F0:0x0200 accesses 70h-7Fh in Bank 0 ; area DATA MEM_Program0 0x0200:0x0800 On-chip Program Memory (Page 0) ; area DATA MEM_Program1 0x0800:0x1000 On-chip Program Memory (Page 1) ; area DATA MEM_Program2 0x1000:0x1800 On-chip Program Memory (Page 2) ; area DATA MEM_Program3 0x1800:0x2000 On-chip Program Memory (Page 3) ; Interrupt and reset vector assignments interrupt RESET 0x0000 RESET ; INPUT/OUTPUT PORTS ; BANK0 (0x0000:0x0080) BANK0:INDF 0x0000 INDF (not a physical register) BANK0:TMR0 0x0001 Timer0 module's register BANK0:PCL 0x0002 Program Counter's (PC) Least Significant Byte BANK0:STATUS 0x0003 STATUS REGISTER BANK0:STATUS.IRP 7 RegIster Bank Select bit BANK0:STATUS.RP1 6 Register Bank Select bit 1 BANK0:STATUS.RP0 5 Register Bank Select bit 0 BANK0:STATUS.TO 4 Time-out bit BANK0:STATUS.PD 3 Power-down bit BANK0:STATUS.Z 2 Zero bit BANK0:STATUS.DC 1 Digit carry/borrow bit BANK0:STATUS.C 0 Carry/borrow bit BANK0:FSR 0x0004 Indirect data memory address pointer BANK0:PORTA 0x0005 PORTA register BANK0:PORTA.RA5 5 PORTA bit 5 BANK0:PORTA.RA4 4 PORTA bit 4 BANK0:PORTA.RA3 3 PORTA bit 3 BANK0:PORTA.RA2 2 PORTA bit 2 BANK0:PORTA.RA1 1 PORTA bit 1 BANK0:PORTA.RA0 0 PORTA bit 0 BANK0:PORTB 0x0006 PORTB register BANK0:PORTB.RB7 7 PORTB bit 7 BANK0:PORTB.RB6 6 PORTB bit 6 BANK0:PORTB.RB5 5 PORTB bit 5 BANK0:PORTB.RB4 4 PORTB bit 4 BANK0:PORTB.RB3 3 PORTB bit 3 BANK0:PORTB.RB2 2 PORTB bit 2 BANK0:PORTB.RB1 1 PORTB bit 1 BANK0:PORTB.RB0 0 PORTB bit 0 BANK0:PORTC 0x0007 PORTC register BANK0:PORTC.RC7 7 PORTC bit 7 BANK0:PORTC.RC6 6 PORTC bit 6 BANK0:PORTC.RC5 5 PORTC bit 5 BANK0:PORTC.RC4 4 PORTC bit 4 BANK0:PORTC.RC3 3 PORTC bit 3 BANK0:PORTC.RC2 2 PORTC bit 2 BANK0:PORTC.RC1 1 PORTC bit 1 BANK0:PORTC.RC0 0 PORTC bit 0 BANK0:PORTD 0x0008 PORTD register (not implemented on the 28-pin devices) BANK0:PORTD.RD7 7 PORTD bit 7 BANK0:PORTD.RD6 6 PORTD bit 6 BANK0:PORTD.RD5 5 PORTD bit 5 BANK0:PORTD.RD4 4 PORTD bit 4 BANK0:PORTD.RD3 3 PORTD bit 3 BANK0:PORTD.RD2 2 PORTD bit 2 BANK0:PORTD.RD1 1 PORTD bit 1 BANK0:PORTD.RD0 0 PORTD bit 0 BANK0:PORTE 0x0009 PORTE register (not implemented on the 28-pin devices) BANK0:PORTE.RE2 2 PORTE bit 2 BANK0:PORTE.RE1 1 PORTE bit 1 BANK0:PORTE.RE0 0 PORTE bit 0 BANK0:PCLATH 0x000A Write Buffer for the upper 5 bits of the Program Counter BANK0:INTCON 0x000B INTCON REGISTER BANK0:INTCON.GIE 7 Global Interrupt Enable bit BANK0:INTCON.PEIE 6 Peripheral Interrupt Enable bit BANK0:INTCON.TMR0IE 5 TMR0 Overflow Interrupt Enable bit BANK0:INTCON.INTE 4 RB0/INT External Interrupt Enable bit BANK0:INTCON.RBIE 3 RB Port Change Interrupt Enable bit BANK0:INTCON.TMR0IF 2 TMR0 Overflow Interrupt Flag bit BANK0:INTCON.INTF 1 RB0/INT External Interrupt Flag bit BANK0:INTCON.RBIF 0 RB Port Change Interrupt Flag bit BANK0:PIR1 0x000C PIR1 REGISTER BANK0:PIR1.PSPIF 7 Parallel Slave Port Interrupt Flag bit (reserved on the 28-pin devices) BANK0:PIR1.ADIF 6 A/D Converter Interrupt Flag bit BANK0:PIR1.RCIF 5 USART Receive Interrupt Flag bit BANK0:PIR1.TXIF 4 USART Transmit Interrupt Flag bit BANK0:PIR1.SSPIF 3 Synchronous Serial Port Interrupt Flag bit BANK0:PIR1.CCP1IF 2 CCP1 Interrupt Flag bit BANK0:PIR1.TMR2IF 1 TMR2 to PR2 Match Interrupt Flag bit BANK0:PIR1.TMR1IF 0 TMR1 Overflow Interrupt Flag bit BANK0:PIR2 0x000D PIR2 REGISTER BANK0:PIR2.CCP2IF 0 CCP2 Interrupt Flag bit BANK0:TMR1L 0x000E Holding register for the Least Significant Byte of the 16-bit TMR1 register BANK0:TMR1H 0x000F Holding register for the Most Significant Byte of the 16-bit TMR1 register BANK0:T1CON 0x0010 TIMER1 CONTROL REGISTER BANK0:T1CON.T1CKPS1 5 Timer1 Input Clock Prescale Select bit 1 BANK0:T1CON.T1CKPS0 4 Timer1 Input Clock Prescale Select bit 0 BANK0:T1CON.T1OSCEN 3 Timer1 Oscillator Enable Control bit BANK0:T1CON.T1SYNC 2 Timer1 External Clock Input Synchronization Control bit BANK0:T1CON.TMR1CS 1 Timer1 Clock Source Select bit BANK0:T1CON.TMR1ON 0 Timer1 On bit BANK0:TMR2 0x0011 Timer2 module's register BANK0:T2CON 0x0012 TIMER2 CONTROL REGISTER BANK0:T2CON.TOUTPS3 6 Timer2 Output Postscale Select bit 3 BANK0:T2CON.TOUTPS2 5 Timer2 Output Postscale Select bit 2 BANK0:T2CON.TOUTPS1 4 Timer2 Output Postscale Select bit 1 BANK0:T2CON.TOUTPS0 3 Timer2 Output Postscale Select bit 0 BANK0:T2CON.TMR2ON 2 Timer2 On bit BANK0:T2CON.T2CKPS1 1 Timer2 Clock Prescale Select bit 1 BANK0:T2CON.T2CKPS0 0 Timer2 Clock Prescale Select bit 0 BANK0:SSPBUF 0x0013 Synchronous Serial Port Receive Buffer/Transmit Register BANK0:SSPCON 0x0014 SYNC SERIAL PORT CONTROL REGISTER BANK0:SSPCON.WCOL 7 Write Collision Detect bit BANK0:SSPCON.SSPOV 6 Receive Overflow Indicator bit BANK0:SSPCON.SSPEN 5 Synchronous Serial Port Enable bit BANK0:SSPCON.CKP 4 Clock Polarity Select bit BANK0:SSPCON.SSPM3 3 Synchronous Serial Port Mode Select bit 3 BANK0:SSPCON.SSPM2 2 Synchronous Serial Port Mode Select bit 2 BANK0:SSPCON.SSPM1 1 Synchronous Serial Port Mode Select bit 1 BANK0:SSPCON.SSPM0 0 Synchronous Serial Port Mode Select bit 0 BANK0:CCPR1L 0x0015 Capture/Compare/PWM1 Register1 (LSB) BANK0:CCPR1H 0x0016 Capture/Compare/PWM1 Register1 (MSB) BANK0:CCP1CON 0x0017 CCP1CON REGISTER BANK0:CCP1CON.CCP1X 5 PWM Least Significant bit BANK0:CCP1CON.CCP1Y 4 PWM Least Significant bit BANK0:CCP1CON.CCP1M3 3 CCP1 Mode Select bit 3 BANK0:CCP1CON.CCP1M2 2 CCP1 Mode Select bit 2 BANK0:CCP1CON.CCP1M1 1 CCP1 Mode Select bit 1 BANK0:CCP1CON.CCP1M0 0 CCP1 Mode Select bit 0 BANK0:RCSTA 0x0018 RECEIVE STATUS AND CONTROL REGISTER BANK0:RCSTA.SPEN 7 Serial Port Enable bit BANK0:RCSTA.RX9 6 9-bit Receive Enable bit BANK0:RCSTA.SREN 5 Single Receive Enable bit BANK0:RCSTA.CREN 4 Continuous Receive Enable bit BANK0:RCSTA.FERR 2 Framing Error bit BANK0:RCSTA.OERR 1 Overrun Error bit BANK0:RCSTA.RX9D 0 9th bit of received data BANK0:TXREG 0x0019 USART Transmit Data Register BANK0:RCREG 0x001A USART Receive Data Register BANK0:CCPR2L 0x001B Capture/Compare/PWM2 Register2 (LSB) BANK0:CCPR2H 0x001C Capture/Compare/PWM2 Register2 (MSB) BANK0:CCP2CON 0x001D CCP2CON REGISTER BANK0:CCP2CON.CCP2X 5 PWM Least Significant bit BANK0:CCP2CON.CCP2Y 4 PWM Least Significant bit BANK0:CCP2CON.CCP2M3 3 CCP2 Mode Select bit 3 BANK0:CCP2CON.CCP2M2 2 CCP2 Mode Select bit 2 BANK0:CCP2CON.CCP2M1 1 CCP2 Mode Select bit 1 BANK0:CCP2CON.CCP2M0 0 CCP2 Mode Select bit 0 BANK0:ADRES 0x001E A/D Result Register Byte BANK0:ADCON0 0x001F ADCON0 REGISTER BANK0:ADCON0.ADCS1 7 A/D Conversion Clock Select bit 1 BANK0:ADCON0.ADCS0 6 A/D Conversion Clock Select bit 0 BANK0:ADCON0.CHS2 5 Analog Channel Select bit 2 BANK0:ADCON0.CHS1 4 Analog Channel Select bit 1 BANK0:ADCON0.CHS0 3 Analog Channel Select bit 0 BANK0:ADCON0.GO_DONE 2 A/D Conversion Status bit BANK0:ADCON0.ADON 0 A/D On bit ; BANK1 (0x0080:0x0100) BANK1:INDF 0x0080 INDF (not a physical register) BANK1:OPTION 0x0081 OPTION REGISTER BANK1:OPTION.RBPU 7 PORTB Pull-up Enable bit BANK1:OPTION.INTEDG 6 Interrupt Edge Select bit BANK1:OPTION.T0CS 5 TMR0 Clock Source Select bit BANK1:OPTION.T0SE 4 TMR0 Source Edge Select bit BANK1:OPTION.PSA 3 Prescaler Assignment bit BANK1:OPTION.PS2 2 Prescaler Rate Select bit 2 BANK1:OPTION.PS1 1 Prescaler Rate Select bit 1 BANK1:OPTION.PS0 0 Prescaler Rate Select bit 0 BANK1:PCL 0x0082 Program Counter's (PC) Least Significant Byte BANK1:STATUS 0x0083 STATUS REGISTER BANK1:STATUS.IRP 7 RegIster Bank Select bit BANK1:STATUS.RP1 6 Register Bank Select bit 1 BANK1:STATUS.RP0 5 Register Bank Select bit 0 BANK1:STATUS.TO 4 Time-out bit BANK1:STATUS.PD 3 Power-down bit BANK1:STATUS.Z 2 Zero bit BANK1:STATUS.DC 1 Digit carry/borrow bit BANK1:STATUS.C 0 Carry/borrow bit BANK1:FSR 0x0084 Indirect data memory address pointer BANK1:TRISA 0x0085 PORTA Data Direction Register BANK1:TRISA.TRISA5 5 PORTA Data Direction Register bit 5 BANK1:TRISA.TRISA4 4 PORTA Data Direction Register bit 4 BANK1:TRISA.TRISA3 3 PORTA Data Direction Register bit 3 BANK1:TRISA.TRISA2 2 PORTA Data Direction Register bit 2 BANK1:TRISA.TRISA1 1 PORTA Data Direction Register bit 1 BANK1:TRISA.TRISA0 0 PORTA Data Direction Register bit 0 BANK1:TRISB 0x0086 PORTB Data Direction Register BANK1:TRISB.TRISB7 7 PORTB Data Direction Register bit 7 BANK1:TRISB.TRISB6 6 PORTB Data Direction Register bit 6 BANK1:TRISB.TRISB5 5 PORTB Data Direction Register bit 5 BANK1:TRISB.TRISB4 4 PORTB Data Direction Register bit 4 BANK1:TRISB.TRISB3 3 PORTB Data Direction Register bit 3 BANK1:TRISB.TRISB2 2 PORTB Data Direction Register bit 2 BANK1:TRISB.TRISB1 1 PORTB Data Direction Register bit 1 BANK1:TRISB.TRISB0 0 PORTB Data Direction Register bit 0 BANK1:TRISC 0x0087 PORTC Data Direction Register BANK1:TRISC.TRISC7 7 PORTC Data Direction Register bit 7 BANK1:TRISC.TRISC6 6 PORTC Data Direction Register bit 6 BANK1:TRISC.TRISC5 5 PORTC Data Direction Register bit 5 BANK1:TRISC.TRISC4 4 PORTC Data Direction Register bit 4 BANK1:TRISC.TRISC3 3 PORTC Data Direction Register bit 3 BANK1:TRISC.TRISC2 2 PORTC Data Direction Register bit 2 BANK1:TRISC.TRISC1 1 PORTC Data Direction Register bit 1 BANK1:TRISC.TRISC0 0 PORTC Data Direction Register bit 0 BANK1:TRISD 0x0088 PORTD Data Direction Register (not implemented on the 28-pin devices) BANK1:TRISD.TRISD7 7 PORTD Data Direction Register bit 7 BANK1:TRISD.TRISD6 6 PORTD Data Direction Register bit 6 BANK1:TRISD.TRISD5 5 PORTD Data Direction Register bit 5 BANK1:TRISD.TRISD4 4 PORTD Data Direction Register bit 4 BANK1:TRISD.TRISD3 3 PORTD Data Direction Register bit 3 BANK1:TRISD.TRISD2 2 PORTD Data Direction Register bit 2 BANK1:TRISD.TRISD1 1 PORTD Data Direction Register bit 1 BANK1:TRISD.TRISD0 0 PORTD Data Direction Register bit 0 BANK1:TRISE 0x0089 PORTE Data Direction Bits (not implemented on the 28-pin devices) BANK1:TRISE.IBF 7 Input Buffer Full Status bit BANK1:TRISE.OBF 6 Output Buffer Full Status bit BANK1:TRISE.IBOV 5 Input Buffer Overflow Detect bit BANK1:TRISE.PSPMODE 4 Parallel Slave Port Mode Select bit BANK1:TRISE.TRISE2 2 Direction Control bit for pin RE2/CS/AN7 BANK1:TRISE.TRISE1 1 Direction Control bit for pin RE1/WR/AN6 BANK1:TRISE.TRISE0 0 Direction Control bit for pin RE0/RD/AN5 BANK1:PCLATH 0x008A Write Buffer for the upper 5 bits of the Program Counter BANK1:INTCON 0x008B INTCON REGISTER BANK1:INTCON.GIE 7 Global Interrupt Enable bit BANK1:INTCON.PEIE 6 Peripheral Interrupt Enable bit BANK1:INTCON.TMR0IE 5 TMR0 Overflow Interrupt Enable bit BANK1:INTCON.INTE 4 RB0/INT External Interrupt Enable bit BANK1:INTCON.RBIE 3 RB Port Change Interrupt Enable bit BANK1:INTCON.TMR0IF 2 TMR0 Overflow Interrupt Flag bit BANK1:INTCON.INTF 1 RB0/INT External Interrupt Flag bit BANK1:INTCON.RBIF 0 RB Port Change Interrupt Flag bit BANK1:PIE1 0x008C PIE1 REGISTER BANK1:PIE1.PSPIE 7 Parallel Slave Port Read/Write Interrupt Enable bit (reserved on the 28-pin devices) BANK1:PIE1.ADIE 6 BANK1:PIE1.RCIE 5 USART Receive Interrupt Enable bit BANK1:PIE1.TXIE 4 USART Transmit Interrupt Enable bit BANK1:PIE1.SSPIE 3 Synchronous Serial Port Interrupt Enable bit BANK1:PIE1.CCP1IE 2 CCP1 Interrupt Enable bit BANK1:PIE1.TMR2IE 1 TMR2 to PR2 Match Interrupt Enable bit BANK1:PIE1.TMR1IE 0 TMR1 Overflow Interrupt Enable bit BANK1:PIE2 0x008D PIE2 REGISTER BANK1:PIE2.CCP2IE 0 CCP2 Interrupt Enable bit BANK1:PCON 0x008E PCON REGISTER BANK1:PCON.POR 1 Power-on Reset Status bit BANK1:PCON.BOR 0 Brown-out Reset Status bit BANK1:RESERVED008F 0x008F RESERVED BANK1:RESERVED0090 0x0090 RESERVED BANK1:RESERVED0091 0x0091 RESERVED BANK1:PR2 0x0092 Timer2 Period Register BANK1:SSPADD 0x0093 Synchronous Serial Port (I2C mode) Address Register BANK1:SSPSTAT 0x0094 SYNC SERIAL PORT STATUS REGISTER BANK1:SSPSTAT.SMP 7 SPI data input sample phase BANK1:SSPSTAT.CKE 6 SPI Clock Edge Select BANK1:SSPSTAT.D_A 5 Data/Address bit (I2C mode only) BANK1:SSPSTAT.P 4 Stop bit (I2C mode only) BANK1:SSPSTAT.S 3 Start bit (I2C mode only) BANK1:SSPSTAT.R_W 2 Read/Write bit information (I2C mode only) BANK1:SSPSTAT.UA 1 Update Address (I2C mode only) BANK1:SSPSTAT.BF 0 Buffer Full Status bit BANK1:RESERVED0095 0x0095 RESERVED BANK1:RESERVED0096 0x0096 RESERVED BANK1:RESERVED0097 0x0097 RESERVED BANK1:TXSTA 0x0098 TRANSMIT STATUS AND CONTROL REGISTER BANK1:TXSTA.CSRC 7 Clock Source Select bit BANK1:TXSTA.TX9 6 9-bit Transmit Enable bit BANK1:TXSTA.TXEN 5 Transmit Enable bit BANK1:TXSTA.SYNC 4 USART Mode Select bit BANK1:TXSTA.BRGH 2 High Baud Rate Select bit BANK1:TXSTA.TRMT 1 Transmit Shift Register Status bit BANK1:TXSTA.TX9D 0 9th bit of transmit data BANK1:SPBRG 0x0099 Baud Rate Generator Register BANK1:RESERVED009A 0x009A RESERVED BANK1:RESERVED009B 0x009B RESERVED BANK1:RESERVED009C 0x009C RESERVED BANK1:RESERVED009D 0x009D RESERVED BANK1:RESERVED009E 0x009E RESERVED BANK1:ADCON1 0x009F ADCON1 REGISTER BANK1:ADCON1.PCFG2 2 A/D Port Configuration Control bit 2 BANK1:ADCON1.PCFG1 1 A/D Port Configuration Control bit 1 BANK1:ADCON1.PCFG0 0 A/D Port Configuration Control bit 0 ; BANK2 (0x0100:0x0180) BANK2:INDF 0x0100 INDF (not a physical register) BANK2:TMR0 0x0101 Timer0 module's register BANK2:PCL 0x0102 Program Counter's (PC) Least Significant Byte BANK2:STATUS 0x0103 STATUS REGISTER BANK2:STATUS.IRP 7 RegIster Bank Select bit BANK2:STATUS.RP1 6 Register Bank Select bit 1 BANK2:STATUS.RP0 5 Register Bank Select bit 0 BANK2:STATUS.TO 4 Time-out bit BANK2:STATUS.PD 3 Power-down bit BANK2:STATUS.Z 2 Zero bit BANK2:STATUS.DC 1 Digit carry/borrow bit BANK2:STATUS.C 0 Carry/borrow bit BANK2:FSR 0x0104 Indirect data memory address pointer BANK2:RESERVED0105 0x0105 RESERVED BANK2:PORTB 0x0106 PORTB register BANK2:PORTB.RB7 7 PORTB bit 7 BANK2:PORTB.RB6 6 PORTB bit 6 BANK2:PORTB.RB5 5 PORTB bit 5 BANK2:PORTB.RB4 4 PORTB bit 4 BANK2:PORTB.RB3 3 PORTB bit 3 BANK2:PORTB.RB2 2 PORTB bit 2 BANK2:PORTB.RB1 1 PORTB bit 1 BANK2:PORTB.RB0 0 PORTB bit 0 BANK2:RESERVED0107 0x0107 RESERVED BANK2:RESERVED0108 0x0108 RESERVED BANK2:RESERVED0109 0x0109 RESERVED BANK2:PCLATH 0x010A Write Buffer for the upper 5 bits of the Program Counter BANK2:INTCON 0x010B INTCON REGISTER BANK2:INTCON.GIE 7 Global Interrupt Enable bit BANK2:INTCON.PEIE 6 Peripheral Interrupt Enable bit BANK2:INTCON.TMR0IE 5 TMR0 Overflow Interrupt Enable bit BANK2:INTCON.INTE 4 RB0/INT External Interrupt Enable bit BANK2:INTCON.RBIE 3 RB Port Change Interrupt Enable bit BANK2:INTCON.TMR0IF 2 TMR0 Overflow Interrupt Flag bit BANK2:INTCON.INTF 1 RB0/INT External Interrupt Flag bit BANK2:INTCON.RBIF 0 RB Port Change Interrupt Flag bit BANK2:PMDATA 0x010C Data Register Low Byte BANK2:PMADR 0x010D Address Register Low Byte BANK2:PMDATH 0x010E Data Register High Byte BANK2:PMADRH 0x010F Address Register High Byte ; BANK3 (0x0180:0x0200) BANK3:INDF 0x0180 INDF (not a physical register) BANK3:OPTION 0x0181 OPTION REGISTER BANK3:OPTION.RBPU 7 PORTB Pull-up Enable bit BANK3:OPTION.INTEDG 6 Interrupt Edge Select bit BANK3:OPTION.T0CS 5 TMR0 Clock Source Select bit BANK3:OPTION.T0SE 4 TMR0 Source Edge Select bit BANK3:OPTION.PSA 3 Prescaler Assignment bit BANK3:OPTION.PS2 2 Prescaler Rate Select bit 2 BANK3:OPTION.PS1 1 Prescaler Rate Select bit 1 BANK3:OPTION.PS0 0 Prescaler Rate Select bit 0 BANK3:PCL 0x0182 Program Counter's (PC) Least Significant Byte BANK3:STATUS 0x0183 STATUS REGISTER BANK3:STATUS.IRP 7 RegIster Bank Select bit BANK3:STATUS.RP1 6 Register Bank Select bit 1 BANK3:STATUS.RP0 5 Register Bank Select bit 0 BANK3:STATUS.TO 4 Time-out bit BANK3:STATUS.PD 3 Power-down bit BANK3:STATUS.Z 2 Zero bit BANK3:STATUS.DC 1 Digit carry/borrow bit BANK3:STATUS.C 0 Carry/borrow bit BANK3:FSR 0x0184 Indirect data memory address pointer BANK3:RESERVED0185 0x0185 RESERVED BANK3:TRISB 0x0186 PORTB Data Direction Register BANK3:TRISB.TRISB7 7 PORTB Data Direction Register bit 7 BANK3:TRISB.TRISB6 6 PORTB Data Direction Register bit 6 BANK3:TRISB.TRISB5 5 PORTB Data Direction Register bit 5 BANK3:TRISB.TRISB4 4 PORTB Data Direction Register bit 4 BANK3:TRISB.TRISB3 3 PORTB Data Direction Register bit 3 BANK3:TRISB.TRISB2 2 PORTB Data Direction Register bit 2 BANK3:TRISB.TRISB1 1 PORTB Data Direction Register bit 1 BANK3:TRISB.TRISB0 0 PORTB Data Direction Register bit 0 BANK3:RESERVED0187 0x0187 RESERVED BANK3:RESERVED0188 0x0188 RESERVED BANK3:RESERVED0189 0x0189 RESERVED BANK3:PCLATH 0x018A Write Buffer for the upper 5 bits of the Program Counter BANK3:INTCON 0x018B INTCON REGISTER BANK3:INTCON.GIE 7 Global Interrupt Enable bit BANK3:INTCON.PEIE 6 Peripheral Interrupt Enable bit BANK3:INTCON.TMR0IE 5 TMR0 Overflow Interrupt Enable bit BANK3:INTCON.INTE 4 RB0/INT External Interrupt Enable bit BANK3:INTCON.RBIE 3 RB Port Change Interrupt Enable bit BANK3:INTCON.TMR0IF 2 TMR0 Overflow Interrupt Flag bit BANK3:INTCON.INTF 1 RB0/INT External Interrupt Flag bit BANK3:INTCON.RBIF 0 RB Port Change Interrupt Flag bit BANK3:PMCON1 0x018C PMCON1 REGISTER BANK3:PMCON1.RD 0 Read Control bit BANK3:RESERVED018D 0x018D RESERVED BANK3:RESERVED018E 0x018E RESERVED BANK3:RESERVED018F 0x018F RESERVED .16F77 ; http://www.microchip.com/download/lit/pline/picmicro/families/16f7x/30325b.pdf ; PIC16F73_4_6_7.pdf ; MEMORY MAP ; BANK_0 area DATA FSR_ 0x0000:0x0020 area DATA Gen_Purp 0x0020:0x0080 General Purpose Register area DATA MEM_Program0 0x0080:0x0800 On-chip Program Memory (Page 0) area DATA MEM_Program1 0x0800:0x1000 On-chip Program Memory (Page 1) area DATA MEM_Program2 0x1000:0x1800 On-chip Program Memory (Page 2) area DATA MEM_Program3 0x1800:0x2000 On-chip Program Memory (Page 3) ; BANK_1 ; area DATA FSR_ 0x0080:0x00A0 ; area DATA Gen_Purp 0x00A0:0x00F0 General Purpose Register ; area DATA Gen_Purp_BANK0 0x00F0:0x0100 accesses 70h-7Fh ; area DATA MEM_Program0 0x0100:0x0800 On-chip Program Memory (Page 0) ; area DATA MEM_Program1 0x0800:0x1000 On-chip Program Memory (Page 1) ; area DATA MEM_Program2 0x1000:0x1800 On-chip Program Memory (Page 2) ; area DATA MEM_Program3 0x1800:0x2000 On-chip Program Memory (Page 3) ; BANK_2 ; area DATA FSR_ 0x0100:0x0110 ; area DATA Gen_Purp0 0x0110:0x0120 General Purpose Register 16 Bytes ; area DATA Gen_Purp1 0x0120:0x0170 General Purpose Register 80 Bytes ; area DATA Gen_Purp_BANK0 0x0170:0x0180 accesses 70h-7Fh ; area DATA MEM_Program0 0x0180:0x0800 On-chip Program Memory (Page 0) ; area DATA MEM_Program1 0x0800:0x1000 On-chip Program Memory (Page 1) ; area DATA MEM_Program2 0x1000:0x1800 On-chip Program Memory (Page 2) ; area DATA MEM_Program3 0x1800:0x2000 On-chip Program Memory (Page 3) ; BANK_3 ; area DATA FSR_ 0x0180:0x0190 ; area DATA Gen_Purp0 0x0190:0x01A0 General Purpose Register 16 Bytes ; area DATA Gen_Purp1 0x01A0:0x01F0 General Purpose Register 80 Bytes ; area DATA Gen_Purp_BANK0 0x01F0:0x0200 accesses 70h-7Fh in Bank 0 ; area DATA MEM_Program0 0x0200:0x0800 On-chip Program Memory (Page 0) ; area DATA MEM_Program1 0x0800:0x1000 On-chip Program Memory (Page 1) ; area DATA MEM_Program2 0x1000:0x1800 On-chip Program Memory (Page 2) ; area DATA MEM_Program3 0x1800:0x2000 On-chip Program Memory (Page 3) ; Interrupt and reset vector assignments interrupt RESET 0x0000 RESET ; INPUT/OUTPUT PORTS ; BANK0 (0x0000:0x0080) BANK0:INDF 0x0000 INDF (not a physical register) BANK0:TMR0 0x0001 Timer0 module's register BANK0:PCL 0x0002 Program Counter's (PC) Least Significant Byte BANK0:STATUS 0x0003 STATUS REGISTER BANK0:STATUS.IRP 7 RegIster Bank Select bit BANK0:STATUS.RP1 6 Register Bank Select bit 1 BANK0:STATUS.RP0 5 Register Bank Select bit 0 BANK0:STATUS.TO 4 Time-out bit BANK0:STATUS.PD 3 Power-down bit BANK0:STATUS.Z 2 Zero bit BANK0:STATUS.DC 1 Digit carry/borrow bit BANK0:STATUS.C 0 Carry/borrow bit BANK0:FSR 0x0004 Indirect data memory address pointer BANK0:PORTA 0x0005 PORTA register BANK0:PORTA.RA5 5 PORTA bit 5 BANK0:PORTA.RA4 4 PORTA bit 4 BANK0:PORTA.RA3 3 PORTA bit 3 BANK0:PORTA.RA2 2 PORTA bit 2 BANK0:PORTA.RA1 1 PORTA bit 1 BANK0:PORTA.RA0 0 PORTA bit 0 BANK0:PORTB 0x0006 PORTB register BANK0:PORTB.RB7 7 PORTB bit 7 BANK0:PORTB.RB6 6 PORTB bit 6 BANK0:PORTB.RB5 5 PORTB bit 5 BANK0:PORTB.RB4 4 PORTB bit 4 BANK0:PORTB.RB3 3 PORTB bit 3 BANK0:PORTB.RB2 2 PORTB bit 2 BANK0:PORTB.RB1 1 PORTB bit 1 BANK0:PORTB.RB0 0 PORTB bit 0 BANK0:PORTC 0x0007 PORTC register BANK0:PORTC.RC7 7 PORTC bit 7 BANK0:PORTC.RC6 6 PORTC bit 6 BANK0:PORTC.RC5 5 PORTC bit 5 BANK0:PORTC.RC4 4 PORTC bit 4 BANK0:PORTC.RC3 3 PORTC bit 3 BANK0:PORTC.RC2 2 PORTC bit 2 BANK0:PORTC.RC1 1 PORTC bit 1 BANK0:PORTC.RC0 0 PORTC bit 0 BANK0:PORTD 0x0008 PORTD register (not implemented on the 28-pin devices) BANK0:PORTD.RD7 7 PORTD bit 7 BANK0:PORTD.RD6 6 PORTD bit 6 BANK0:PORTD.RD5 5 PORTD bit 5 BANK0:PORTD.RD4 4 PORTD bit 4 BANK0:PORTD.RD3 3 PORTD bit 3 BANK0:PORTD.RD2 2 PORTD bit 2 BANK0:PORTD.RD1 1 PORTD bit 1 BANK0:PORTD.RD0 0 PORTD bit 0 BANK0:PORTE 0x0009 PORTE register (not implemented on the 28-pin devices) BANK0:PORTE.RE2 2 PORTE bit 2 BANK0:PORTE.RE1 1 PORTE bit 1 BANK0:PORTE.RE0 0 PORTE bit 0 BANK0:PCLATH 0x000A Write Buffer for the upper 5 bits of the Program Counter BANK0:INTCON 0x000B INTCON REGISTER BANK0:INTCON.GIE 7 Global Interrupt Enable bit BANK0:INTCON.PEIE 6 Peripheral Interrupt Enable bit BANK0:INTCON.TMR0IE 5 TMR0 Overflow Interrupt Enable bit BANK0:INTCON.INTE 4 RB0/INT External Interrupt Enable bit BANK0:INTCON.RBIE 3 RB Port Change Interrupt Enable bit BANK0:INTCON.TMR0IF 2 TMR0 Overflow Interrupt Flag bit BANK0:INTCON.INTF 1 RB0/INT External Interrupt Flag bit BANK0:INTCON.RBIF 0 RB Port Change Interrupt Flag bit BANK0:PIR1 0x000C PIR1 REGISTER BANK0:PIR1.PSPIF 7 Parallel Slave Port Interrupt Flag bit (reserved on the 28-pin devices) BANK0:PIR1.ADIF 6 A/D Converter Interrupt Flag bit BANK0:PIR1.RCIF 5 USART Receive Interrupt Flag bit BANK0:PIR1.TXIF 4 USART Transmit Interrupt Flag bit BANK0:PIR1.SSPIF 3 Synchronous Serial Port Interrupt Flag bit BANK0:PIR1.CCP1IF 2 CCP1 Interrupt Flag bit BANK0:PIR1.TMR2IF 1 TMR2 to PR2 Match Interrupt Flag bit BANK0:PIR1.TMR1IF 0 TMR1 Overflow Interrupt Flag bit BANK0:PIR2 0x000D PIR2 REGISTER BANK0:PIR2.CCP2IF 0 CCP2 Interrupt Flag bit BANK0:TMR1L 0x000E Holding register for the Least Significant Byte of the 16-bit TMR1 register BANK0:TMR1H 0x000F Holding register for the Most Significant Byte of the 16-bit TMR1 register BANK0:T1CON 0x0010 TIMER1 CONTROL REGISTER BANK0:T1CON.T1CKPS1 5 Timer1 Input Clock Prescale Select bit 1 BANK0:T1CON.T1CKPS0 4 Timer1 Input Clock Prescale Select bit 0 BANK0:T1CON.T1OSCEN 3 Timer1 Oscillator Enable Control bit BANK0:T1CON.T1SYNC 2 Timer1 External Clock Input Synchronization Control bit BANK0:T1CON.TMR1CS 1 Timer1 Clock Source Select bit BANK0:T1CON.TMR1ON 0 Timer1 On bit BANK0:TMR2 0x0011 Timer2 module's register BANK0:T2CON 0x0012 TIMER2 CONTROL REGISTER BANK0:T2CON.TOUTPS3 6 Timer2 Output Postscale Select bit 3 BANK0:T2CON.TOUTPS2 5 Timer2 Output Postscale Select bit 2 BANK0:T2CON.TOUTPS1 4 Timer2 Output Postscale Select bit 1 BANK0:T2CON.TOUTPS0 3 Timer2 Output Postscale Select bit 0 BANK0:T2CON.TMR2ON 2 Timer2 On bit BANK0:T2CON.T2CKPS1 1 Timer2 Clock Prescale Select bit 1 BANK0:T2CON.T2CKPS0 0 Timer2 Clock Prescale Select bit 0 BANK0:SSPBUF 0x0013 Synchronous Serial Port Receive Buffer/Transmit Register BANK0:SSPCON 0x0014 SYNC SERIAL PORT CONTROL REGISTER BANK0:SSPCON.WCOL 7 Write Collision Detect bit BANK0:SSPCON.SSPOV 6 Receive Overflow Indicator bit BANK0:SSPCON.SSPEN 5 Synchronous Serial Port Enable bit BANK0:SSPCON.CKP 4 Clock Polarity Select bit BANK0:SSPCON.SSPM3 3 Synchronous Serial Port Mode Select bit 3 BANK0:SSPCON.SSPM2 2 Synchronous Serial Port Mode Select bit 2 BANK0:SSPCON.SSPM1 1 Synchronous Serial Port Mode Select bit 1 BANK0:SSPCON.SSPM0 0 Synchronous Serial Port Mode Select bit 0 BANK0:CCPR1L 0x0015 Capture/Compare/PWM1 Register1 (LSB) BANK0:CCPR1H 0x0016 Capture/Compare/PWM1 Register1 (MSB) BANK0:CCP1CON 0x0017 CCP1CON REGISTER BANK0:CCP1CON.CCP1X 5 PWM Least Significant bit BANK0:CCP1CON.CCP1Y 4 PWM Least Significant bit BANK0:CCP1CON.CCP1M3 3 CCP1 Mode Select bit 3 BANK0:CCP1CON.CCP1M2 2 CCP1 Mode Select bit 2 BANK0:CCP1CON.CCP1M1 1 CCP1 Mode Select bit 1 BANK0:CCP1CON.CCP1M0 0 CCP1 Mode Select bit 0 BANK0:RCSTA 0x0018 RECEIVE STATUS AND CONTROL REGISTER BANK0:RCSTA.SPEN 7 Serial Port Enable bit BANK0:RCSTA.RX9 6 9-bit Receive Enable bit BANK0:RCSTA.SREN 5 Single Receive Enable bit BANK0:RCSTA.CREN 4 Continuous Receive Enable bit BANK0:RCSTA.FERR 2 Framing Error bit BANK0:RCSTA.OERR 1 Overrun Error bit BANK0:RCSTA.RX9D 0 9th bit of received data BANK0:TXREG 0x0019 USART Transmit Data Register BANK0:RCREG 0x001A USART Receive Data Register BANK0:CCPR2L 0x001B Capture/Compare/PWM2 Register2 (LSB) BANK0:CCPR2H 0x001C Capture/Compare/PWM2 Register2 (MSB) BANK0:CCP2CON 0x001D CCP2CON REGISTER BANK0:CCP2CON.CCP2X 5 PWM Least Significant bit BANK0:CCP2CON.CCP2Y 4 PWM Least Significant bit BANK0:CCP2CON.CCP2M3 3 CCP2 Mode Select bit 3 BANK0:CCP2CON.CCP2M2 2 CCP2 Mode Select bit 2 BANK0:CCP2CON.CCP2M1 1 CCP2 Mode Select bit 1 BANK0:CCP2CON.CCP2M0 0 CCP2 Mode Select bit 0 BANK0:ADRES 0x001E A/D Result Register Byte BANK0:ADCON0 0x001F ADCON0 REGISTER BANK0:ADCON0.ADCS1 7 A/D Conversion Clock Select bit 1 BANK0:ADCON0.ADCS0 6 A/D Conversion Clock Select bit 0 BANK0:ADCON0.CHS2 5 Analog Channel Select bit 2 BANK0:ADCON0.CHS1 4 Analog Channel Select bit 1 BANK0:ADCON0.CHS0 3 Analog Channel Select bit 0 BANK0:ADCON0.GO_DONE 2 A/D Conversion Status bit BANK0:ADCON0.ADON 0 A/D On bit ; BANK1 (0x0080:0x0100) BANK1:INDF 0x0080 INDF (not a physical register) BANK1:OPTION 0x0081 OPTION REGISTER BANK1:OPTION.RBPU 7 PORTB Pull-up Enable bit BANK1:OPTION.INTEDG 6 Interrupt Edge Select bit BANK1:OPTION.T0CS 5 TMR0 Clock Source Select bit BANK1:OPTION.T0SE 4 TMR0 Source Edge Select bit BANK1:OPTION.PSA 3 Prescaler Assignment bit BANK1:OPTION.PS2 2 Prescaler Rate Select bit 2 BANK1:OPTION.PS1 1 Prescaler Rate Select bit 1 BANK1:OPTION.PS0 0 Prescaler Rate Select bit 0 BANK1:PCL 0x0082 Program Counter's (PC) Least Significant Byte BANK1:STATUS 0x0083 STATUS REGISTER BANK1:STATUS.IRP 7 RegIster Bank Select bit BANK1:STATUS.RP1 6 Register Bank Select bit 1 BANK1:STATUS.RP0 5 Register Bank Select bit 0 BANK1:STATUS.TO 4 Time-out bit BANK1:STATUS.PD 3 Power-down bit BANK1:STATUS.Z 2 Zero bit BANK1:STATUS.DC 1 Digit carry/borrow bit BANK1:STATUS.C 0 Carry/borrow bit BANK1:FSR 0x0084 Indirect data memory address pointer BANK1:TRISA 0x0085 PORTA Data Direction Register BANK1:TRISA.TRISA5 5 PORTA Data Direction Register bit 5 BANK1:TRISA.TRISA4 4 PORTA Data Direction Register bit 4 BANK1:TRISA.TRISA3 3 PORTA Data Direction Register bit 3 BANK1:TRISA.TRISA2 2 PORTA Data Direction Register bit 2 BANK1:TRISA.TRISA1 1 PORTA Data Direction Register bit 1 BANK1:TRISA.TRISA0 0 PORTA Data Direction Register bit 0 BANK1:TRISB 0x0086 PORTB Data Direction Register BANK1:TRISB.TRISB7 7 PORTB Data Direction Register bit 7 BANK1:TRISB.TRISB6 6 PORTB Data Direction Register bit 6 BANK1:TRISB.TRISB5 5 PORTB Data Direction Register bit 5 BANK1:TRISB.TRISB4 4 PORTB Data Direction Register bit 4 BANK1:TRISB.TRISB3 3 PORTB Data Direction Register bit 3 BANK1:TRISB.TRISB2 2 PORTB Data Direction Register bit 2 BANK1:TRISB.TRISB1 1 PORTB Data Direction Register bit 1 BANK1:TRISB.TRISB0 0 PORTB Data Direction Register bit 0 BANK1:TRISC 0x0087 PORTC Data Direction Register BANK1:TRISC.TRISC7 7 PORTC Data Direction Register bit 7 BANK1:TRISC.TRISC6 6 PORTC Data Direction Register bit 6 BANK1:TRISC.TRISC5 5 PORTC Data Direction Register bit 5 BANK1:TRISC.TRISC4 4 PORTC Data Direction Register bit 4 BANK1:TRISC.TRISC3 3 PORTC Data Direction Register bit 3 BANK1:TRISC.TRISC2 2 PORTC Data Direction Register bit 2 BANK1:TRISC.TRISC1 1 PORTC Data Direction Register bit 1 BANK1:TRISC.TRISC0 0 PORTC Data Direction Register bit 0 BANK1:TRISD 0x0088 PORTD Data Direction Register (not implemented on the 28-pin devices) BANK1:TRISD.TRISD7 7 PORTD Data Direction Register bit 7 BANK1:TRISD.TRISD6 6 PORTD Data Direction Register bit 6 BANK1:TRISD.TRISD5 5 PORTD Data Direction Register bit 5 BANK1:TRISD.TRISD4 4 PORTD Data Direction Register bit 4 BANK1:TRISD.TRISD3 3 PORTD Data Direction Register bit 3 BANK1:TRISD.TRISD2 2 PORTD Data Direction Register bit 2 BANK1:TRISD.TRISD1 1 PORTD Data Direction Register bit 1 BANK1:TRISD.TRISD0 0 PORTD Data Direction Register bit 0 BANK1:TRISE 0x0089 PORTE Data Direction Bits (not implemented on the 28-pin devices) BANK1:TRISE.IBF 7 Input Buffer Full Status bit BANK1:TRISE.OBF 6 Output Buffer Full Status bit BANK1:TRISE.IBOV 5 Input Buffer Overflow Detect bit BANK1:TRISE.PSPMODE 4 Parallel Slave Port Mode Select bit BANK1:TRISE.TRISE2 2 Direction Control bit for pin RE2/CS/AN7 BANK1:TRISE.TRISE1 1 Direction Control bit for pin RE1/WR/AN6 BANK1:TRISE.TRISE0 0 Direction Control bit for pin RE0/RD/AN5 BANK1:PCLATH 0x008A Write Buffer for the upper 5 bits of the Program Counter BANK1:INTCON 0x008B INTCON REGISTER BANK1:INTCON.GIE 7 Global Interrupt Enable bit BANK1:INTCON.PEIE 6 Peripheral Interrupt Enable bit BANK1:INTCON.TMR0IE 5 TMR0 Overflow Interrupt Enable bit BANK1:INTCON.INTE 4 RB0/INT External Interrupt Enable bit BANK1:INTCON.RBIE 3 RB Port Change Interrupt Enable bit BANK1:INTCON.TMR0IF 2 TMR0 Overflow Interrupt Flag bit BANK1:INTCON.INTF 1 RB0/INT External Interrupt Flag bit BANK1:INTCON.RBIF 0 RB Port Change Interrupt Flag bit BANK1:PIE1 0x008C PIE1 REGISTER BANK1:PIE1.PSPIE 7 Parallel Slave Port Read/Write Interrupt Enable bit (reserved on the 28-pin devices) BANK1:PIE1.ADIE 6 BANK1:PIE1.RCIE 5 USART Receive Interrupt Enable bit BANK1:PIE1.TXIE 4 USART Transmit Interrupt Enable bit BANK1:PIE1.SSPIE 3 Synchronous Serial Port Interrupt Enable bit BANK1:PIE1.CCP1IE 2 CCP1 Interrupt Enable bit BANK1:PIE1.TMR2IE 1 TMR2 to PR2 Match Interrupt Enable bit BANK1:PIE1.TMR1IE 0 TMR1 Overflow Interrupt Enable bit BANK1:PIE2 0x008D PIE2 REGISTER BANK1:PIE2.CCP2IE 0 CCP2 Interrupt Enable bit BANK1:PCON 0x008E PCON REGISTER BANK1:PCON.POR 1 Power-on Reset Status bit BANK1:PCON.BOR 0 Brown-out Reset Status bit BANK1:RESERVED008F 0x008F RESERVED BANK1:RESERVED0090 0x0090 RESERVED BANK1:RESERVED0091 0x0091 RESERVED BANK1:PR2 0x0092 Timer2 Period Register BANK1:SSPADD 0x0093 Synchronous Serial Port (I2C mode) Address Register BANK1:SSPSTAT 0x0094 SYNC SERIAL PORT STATUS REGISTER BANK1:SSPSTAT.SMP 7 SPI data input sample phase BANK1:SSPSTAT.CKE 6 SPI Clock Edge Select BANK1:SSPSTAT.D_A 5 Data/Address bit (I2C mode only) BANK1:SSPSTAT.P 4 Stop bit (I2C mode only) BANK1:SSPSTAT.S 3 Start bit (I2C mode only) BANK1:SSPSTAT.R_W 2 Read/Write bit information (I2C mode only) BANK1:SSPSTAT.UA 1 Update Address (I2C mode only) BANK1:SSPSTAT.BF 0 Buffer Full Status bit BANK1:RESERVED0095 0x0095 RESERVED BANK1:RESERVED0096 0x0096 RESERVED BANK1:RESERVED0097 0x0097 RESERVED BANK1:TXSTA 0x0098 TRANSMIT STATUS AND CONTROL REGISTER BANK1:TXSTA.CSRC 7 Clock Source Select bit BANK1:TXSTA.TX9 6 9-bit Transmit Enable bit BANK1:TXSTA.TXEN 5 Transmit Enable bit BANK1:TXSTA.SYNC 4 USART Mode Select bit BANK1:TXSTA.BRGH 2 High Baud Rate Select bit BANK1:TXSTA.TRMT 1 Transmit Shift Register Status bit BANK1:TXSTA.TX9D 0 9th bit of transmit data BANK1:SPBRG 0x0099 Baud Rate Generator Register BANK1:RESERVED009A 0x009A RESERVED BANK1:RESERVED009B 0x009B RESERVED BANK1:RESERVED009C 0x009C RESERVED BANK1:RESERVED009D 0x009D RESERVED BANK1:RESERVED009E 0x009E RESERVED BANK1:ADCON1 0x009F ADCON1 REGISTER BANK1:ADCON1.PCFG2 2 A/D Port Configuration Control bit 2 BANK1:ADCON1.PCFG1 1 A/D Port Configuration Control bit 1 BANK1:ADCON1.PCFG0 0 A/D Port Configuration Control bit 0 ; BANK2 (0x0100:0x0180) BANK2:INDF 0x0100 INDF (not a physical register) BANK2:TMR0 0x0101 Timer0 module's register BANK2:PCL 0x0102 Program Counter's (PC) Least Significant Byte BANK2:STATUS 0x0103 STATUS REGISTER BANK2:STATUS.IRP 7 RegIster Bank Select bit BANK2:STATUS.RP1 6 Register Bank Select bit 1 BANK2:STATUS.RP0 5 Register Bank Select bit 0 BANK2:STATUS.TO 4 Time-out bit BANK2:STATUS.PD 3 Power-down bit BANK2:STATUS.Z 2 Zero bit BANK2:STATUS.DC 1 Digit carry/borrow bit BANK2:STATUS.C 0 Carry/borrow bit BANK2:FSR 0x0104 Indirect data memory address pointer BANK2:RESERVED0105 0x0105 RESERVED BANK2:PORTB 0x0106 PORTB register BANK2:PORTB.RB7 7 PORTB bit 7 BANK2:PORTB.RB6 6 PORTB bit 6 BANK2:PORTB.RB5 5 PORTB bit 5 BANK2:PORTB.RB4 4 PORTB bit 4 BANK2:PORTB.RB3 3 PORTB bit 3 BANK2:PORTB.RB2 2 PORTB bit 2 BANK2:PORTB.RB1 1 PORTB bit 1 BANK2:PORTB.RB0 0 PORTB bit 0 BANK2:RESERVED0107 0x0107 RESERVED BANK2:RESERVED0108 0x0108 RESERVED BANK2:RESERVED0109 0x0109 RESERVED BANK2:PCLATH 0x010A Write Buffer for the upper 5 bits of the Program Counter BANK2:INTCON 0x010B INTCON REGISTER BANK2:INTCON.GIE 7 Global Interrupt Enable bit BANK2:INTCON.PEIE 6 Peripheral Interrupt Enable bit BANK2:INTCON.TMR0IE 5 TMR0 Overflow Interrupt Enable bit BANK2:INTCON.INTE 4 RB0/INT External Interrupt Enable bit BANK2:INTCON.RBIE 3 RB Port Change Interrupt Enable bit BANK2:INTCON.TMR0IF 2 TMR0 Overflow Interrupt Flag bit BANK2:INTCON.INTF 1 RB0/INT External Interrupt Flag bit BANK2:INTCON.RBIF 0 RB Port Change Interrupt Flag bit BANK2:PMDATA 0x010C Data Register Low Byte BANK2:PMADR 0x010D Address Register Low Byte BANK2:PMDATH 0x010E Data Register High Byte BANK2:PMADRH 0x010F Address Register High Byte ; BANK3 (0x0180:0x0200) BANK3:INDF 0x0180 INDF (not a physical register) BANK3:OPTION 0x0181 OPTION REGISTER BANK3:OPTION.RBPU 7 PORTB Pull-up Enable bit BANK3:OPTION.INTEDG 6 Interrupt Edge Select bit BANK3:OPTION.T0CS 5 TMR0 Clock Source Select bit BANK3:OPTION.T0SE 4 TMR0 Source Edge Select bit BANK3:OPTION.PSA 3 Prescaler Assignment bit BANK3:OPTION.PS2 2 Prescaler Rate Select bit 2 BANK3:OPTION.PS1 1 Prescaler Rate Select bit 1 BANK3:OPTION.PS0 0 Prescaler Rate Select bit 0 BANK3:PCL 0x0182 Program Counter's (PC) Least Significant Byte BANK3:STATUS 0x0183 STATUS REGISTER BANK3:STATUS.IRP 7 RegIster Bank Select bit BANK3:STATUS.RP1 6 Register Bank Select bit 1 BANK3:STATUS.RP0 5 Register Bank Select bit 0 BANK3:STATUS.TO 4 Time-out bit BANK3:STATUS.PD 3 Power-down bit BANK3:STATUS.Z 2 Zero bit BANK3:STATUS.DC 1 Digit carry/borrow bit BANK3:STATUS.C 0 Carry/borrow bit BANK3:FSR 0x0184 Indirect data memory address pointer BANK3:RESERVED0185 0x0185 RESERVED BANK3:TRISB 0x0186 PORTB Data Direction Register BANK3:TRISB.TRISB7 7 PORTB Data Direction Register bit 7 BANK3:TRISB.TRISB6 6 PORTB Data Direction Register bit 6 BANK3:TRISB.TRISB5 5 PORTB Data Direction Register bit 5 BANK3:TRISB.TRISB4 4 PORTB Data Direction Register bit 4 BANK3:TRISB.TRISB3 3 PORTB Data Direction Register bit 3 BANK3:TRISB.TRISB2 2 PORTB Data Direction Register bit 2 BANK3:TRISB.TRISB1 1 PORTB Data Direction Register bit 1 BANK3:TRISB.TRISB0 0 PORTB Data Direction Register bit 0 BANK3:RESERVED0187 0x0187 RESERVED BANK3:RESERVED0188 0x0188 RESERVED BANK3:RESERVED0189 0x0189 RESERVED BANK3:PCLATH 0x018A Write Buffer for the upper 5 bits of the Program Counter BANK3:INTCON 0x018B INTCON REGISTER BANK3:INTCON.GIE 7 Global Interrupt Enable bit BANK3:INTCON.PEIE 6 Peripheral Interrupt Enable bit BANK3:INTCON.TMR0IE 5 TMR0 Overflow Interrupt Enable bit BANK3:INTCON.INTE 4 RB0/INT External Interrupt Enable bit BANK3:INTCON.RBIE 3 RB Port Change Interrupt Enable bit BANK3:INTCON.TMR0IF 2 TMR0 Overflow Interrupt Flag bit BANK3:INTCON.INTF 1 RB0/INT External Interrupt Flag bit BANK3:INTCON.RBIF 0 RB Port Change Interrupt Flag bit BANK3:PMCON1 0x018C PMCON1 REGISTER BANK3:PMCON1.RD 0 Read Control bit BANK3:RESERVED018D 0x018D RESERVED BANK3:RESERVED018E 0x018E RESERVED BANK3:RESERVED018F 0x018F RESERVED .16F870 ; http://www.microchip.com/download/lit/pline/picmicro/families/16f87x/30569a.pdf ; PIC16F870_1.pdf ; MEMORY MAP ; BANK_0 area DATA FSR_ 0x0000:0x0020 area DATA Gen_Purp 0x0020:0x0080 General Purpose Register area DATA MEM_Program 0x0080:0x0800 On-chip Program Memory ; BANK_1 ; area DATA FSR_ 0x0080:0x00A0 ; area DATA Gen_Purp 0x00A0:0x00C0 General Purpose Register ; area BSS RESERVED 0x00C0:0x00F0 ; area DATA Gen_Purp_BANK0 0x00F0:0x0100 accesses 70h-7Fh ; area DATA MEM_Program 0x0100:0x0800 On-chip Program Memory ; BANK_2 ; area DATA FSR_ 0x0100:0x0110 ; area BSS RESERVED 0x0110:0x0120 ; area DATA Gen_Purp_BANK0 0x0120:0x0180 accesses 20h-7Fh ; area DATA MEM_Program 0x0180:0x0800 On-chip Program Memory ; BANK_3 ; area DATA FSR_ 0x0180:0x018E ; area BSS RESERVED 0x018E:0x01A0 ; area DATA Gen_Purp_BANK00 0x01A0:0x01C0 accesses A0h-BFh ; area BSS RESERVED 0x01C0:0x01F0 ; area DATA Gen_Purp_BANK01 0x01F0:0x0200 accesses 70h-7Fh ; area DATA MEM_Program 0x0200:0x0800 On-chip Program Memory ; Interrupt and reset vector assignments interrupt RESET 0x0000 RESET ; INPUT/OUTPUT PORTS ; BANK0 (0x0000:0x0080) BANK0:INDF 0x0000 INDF (not a physical register) BANK0:TMR0 0x0001 Timer0 module's register BANK0:PCL 0x0002 Program Counter's (PC) Least Significant Byte BANK0:STATUS 0x0003 STATUS REGISTER BANK0:STATUS.IRP 7 RegIster Bank Select bit BANK0:STATUS.RP1 6 Register Bank Select bit 1 BANK0:STATUS.RP0 5 Register Bank Select bit 0 BANK0:STATUS.TO 4 Time-out bit BANK0:STATUS.PD 3 Power-down bit BANK0:STATUS.Z 2 Zero bit BANK0:STATUS.DC 1 Digit carry/borrow bit BANK0:STATUS.C 0 Carry/borrow bit BANK0:FSR 0x0004 Indirect data memory address pointer BANK0:PORTA 0x0005 PORTA register BANK0:PORTA.RA5 5 PORTA bit 5 BANK0:PORTA.RA4 4 PORTA bit 4 BANK0:PORTA.RA3 3 PORTA bit 3 BANK0:PORTA.RA2 2 PORTA bit 2 BANK0:PORTA.RA1 1 PORTA bit 1 BANK0:PORTA.RA0 0 PORTA bit 0 BANK0:PORTB 0x0006 PORTB register BANK0:PORTB.RB7 7 PORTB bit 7 BANK0:PORTB.RB6 6 PORTB bit 6 BANK0:PORTB.RB5 5 PORTB bit 5 BANK0:PORTB.RB4 4 PORTB bit 4 BANK0:PORTB.RB3 3 PORTB bit 3 BANK0:PORTB.RB2 2 PORTB bit 2 BANK0:PORTB.RB1 1 PORTB bit 1 BANK0:PORTB.RB0 0 PORTB bit 0 BANK0:PORTC 0x0007 PORTC register BANK0:PORTC.RC7 7 PORTC bit 7 BANK0:PORTC.RC6 6 PORTC bit 6 BANK0:PORTC.RC5 5 PORTC bit 5 BANK0:PORTC.RC4 4 PORTC bit 4 BANK0:PORTC.RC3 3 PORTC bit 3 BANK0:PORTC.RC2 2 PORTC bit 2 BANK0:PORTC.RC1 1 PORTC bit 1 BANK0:PORTC.RC0 0 PORTC bit 0 BANK0:RESERVED0008 0x0008 RESERVED BANK0:RESERVED0009 0x0009 RESERVED BANK0:PCLATH 0x000A Write Buffer for the upper 5 bits of the Program Counter BANK0:INTCON 0x000B INTCON REGISTER BANK0:INTCON.GIE 7 Global Interrupt Enable bit BANK0:INTCON.PEIE 6 Peripheral Interrupt Enable bit BANK0:INTCON.T0IE 5 TMR0 Overflow Interrupt Enable bit BANK0:INTCON.INTE 4 RB0/INT External Interrupt Enable bit BANK0:INTCON.RBIE 3 RB Port Change Interrupt Enable bit BANK0:INTCON.T0IF 2 TMR0 Overflow Interrupt Flag bit BANK0:INTCON.INTF 1 RB0/INT External Interrupt Flag bit BANK0:INTCON.RBIF 0 RB Port Change Interrupt Flag bit BANK0:PIR1 0x000C PIR1 REGISTER BANK0:PIR1.PSPIF 7 Parallel Slave Port Interrupt Flag bit (reserved on the 28-pin devices) BANK0:PIR1.ADIF 6 A/D Converter Interrupt Flag bit BANK0:PIR1.RCIF 5 USART Receive Interrupt Flag bit BANK0:PIR1.TXIF 4 USART Transmit Interrupt Flag bit BANK0:PIR1.CCP1IF 2 CCP1 Interrupt Flag bit BANK0:PIR1.TMR2IF 1 TMR2 to PR2 Match Interrupt Flag bit BANK0:PIR1.TMR1IF 0 TMR1 Overflow Interrupt Flag bit BANK0:PIR2 0x000D PIR2 REGISTER BANK0:PIR2.EEIF 4 EEPROM Write Operation Interrupt Flag bit BANK0:TMR1L 0x000E Holding register for the Least Significant Byte of the 16-bit TMR1 register BANK0:TMR1H 0x000F Holding register for the Most Significant Byte of the 16-bit TMR1 register BANK0:T1CON 0x0010 TIMER1 CONTROL REGISTER BANK0:T1CON.T1CKPS1 5 Timer1 Input Clock Prescale Select bit 1 BANK0:T1CON.T1CKPS0 4 Timer1 Input Clock Prescale Select bit 0 BANK0:T1CON.T1OSCEN 3 Timer1 Oscillator Enable Control bit BANK0:T1CON.T1SYNC 2 Timer1 External Clock Input Synchronization Control bit BANK0:T1CON.TMR1CS 1 Timer1 Clock Source Select bit BANK0:T1CON.TMR1ON 0 Timer1 On bit BANK0:TMR2 0x0011 Timer2 module's register BANK0:T2CON 0x0012 TIMER2 CONTROL REGISTER BANK0:T2CON.TOUTPS3 6 Timer2 Output Postscale Select bit 3 BANK0:T2CON.TOUTPS2 5 Timer2 Output Postscale Select bit 2 BANK0:T2CON.TOUTPS1 4 Timer2 Output Postscale Select bit 1 BANK0:T2CON.TOUTPS0 3 Timer2 Output Postscale Select bit 0 BANK0:T2CON.TMR2ON 2 Timer2 On bit BANK0:T2CON.T2CKPS1 1 Timer2 Clock Prescale Select bit 1 BANK0:T2CON.T2CKPS0 0 Timer2 Clock Prescale Select bit 0 BANK0:RESERVED0013 0x0013 RESERVED BANK0:RESERVED0014 0x0014 RESERVED BANK0:CCPR1L 0x0015 Capture/Compare/PWM1 (LSB) BANK0:CCPR1H 0x0016 Capture/Compare/PWM1 (MSB) BANK0:CCP1CON 0x0017 CCP1CON REGISTER BANK0:CCP1CON.CCP1X 5 PWM Least Significant bit BANK0:CCP1CON.CCP1Y 4 PWM Least Significant bit BANK0:CCP1CON.CCP1M3 3 CCP1 Mode Select bit 3 BANK0:CCP1CON.CCP1M2 2 CCP1 Mode Select bit 2 BANK0:CCP1CON.CCP1M1 1 CCP1 Mode Select bit 1 BANK0:CCP1CON.CCP1M0 0 CCP1 Mode Select bit 0 BANK0:RCSTA 0x0018 RECEIVE STATUS AND CONTROL REGISTER BANK0:RCSTA.SPEN 7 Serial Port Enable bit BANK0:RCSTA.RX9 6 9-bit Receive Enable bit BANK0:RCSTA.SREN 5 Single Receive Enable bit BANK0:RCSTA.CREN 4 Continuous Receive Enable bit BANK0:RCSTA.ADDEN 3 Address Detect Enable bit BANK0:RCSTA.FERR 2 Framing Error bit BANK0:RCSTA.OERR 1 Overrun Error bit BANK0:RCSTA.RX9D 0 9th bit of received data BANK0:TXREG 0x0019 USART Transmit Data Register BANK0:RCREG 0x001A USART Receive Data Register BANK0:RESERVED001B 0x001B RESERVED BANK0:RESERVED001C 0x001C RESERVED BANK0:RESERVED001D 0x001D RESERVED BANK0:ADRESH 0x001E A/D Result Register High Byte BANK0:ADCON0 0x001F ADCON0 REGISTER BANK0:ADCON0.ADCS1 7 A/D Conversion Clock Select bit 1 BANK0:ADCON0.ADCS0 6 A/D Conversion Clock Select bit 0 BANK0:ADCON0.CHS2 5 Analog Channel Select bit 2 BANK0:ADCON0.CHS1 4 Analog Channel Select bit 1 BANK0:ADCON0.CHS0 3 Analog Channel Select bit 0 BANK0:ADCON0.GO_DONE 2 A/D Conversion Status bit BANK0:ADCON0.ADON 0 A/D On bit ; BANK1 (0x0080:0x0100) BANK1:INDF 0x0080 INDF (not a physical register) BANK1:OPTION 0x0081 OPTION REGISTER BANK1:OPTION.RBPU 7 PORTB Pull-up Enable bit BANK1:OPTION.INTEDG 6 Interrupt Edge Select bit BANK1:OPTION.T0CS 5 TMR0 Clock Source Select bit BANK1:OPTION.T0SE 4 TMR0 Source Edge Select bit BANK1:OPTION.PSA 3 Prescaler Assignment bit BANK1:OPTION.PS2 2 Prescaler Rate Select bit 2 BANK1:OPTION.PS1 1 Prescaler Rate Select bit 1 BANK1:OPTION.PS0 0 Prescaler Rate Select bit 0 BANK1:PCL 0x0082 Program Counter's (PC) Least Significant Byte BANK1:STATUS 0x0083 STATUS REGISTER BANK1:STATUS.IRP 7 RegIster Bank Select bit BANK1:STATUS.RP1 6 Register Bank Select bit 1 BANK1:STATUS.RP0 5 Register Bank Select bit 0 BANK1:STATUS.TO 4 Time-out bit BANK1:STATUS.PD 3 Power-down bit BANK1:STATUS.Z 2 Zero bit BANK1:STATUS.DC 1 Digit carry/borrow bit BANK1:STATUS.C 0 Carry/borrow bit BANK1:FSR 0x0084 Indirect data memory address pointer BANK1:TRISA 0x0085 PORTA Data Direction Register BANK1:TRISA.TRISA5 5 PORTA Data Direction Register bit 5 BANK1:TRISA.TRISA4 4 PORTA Data Direction Register bit 4 BANK1:TRISA.TRISA3 3 PORTA Data Direction Register bit 3 BANK1:TRISA.TRISA2 2 PORTA Data Direction Register bit 2 BANK1:TRISA.TRISA1 1 PORTA Data Direction Register bit 1 BANK1:TRISA.TRISA0 0 PORTA Data Direction Register bit 0 BANK1:TRISB 0x0086 PORTB Data Direction Register BANK1:TRISB.TRISB7 7 PORTB Data Direction Register bit 7 BANK1:TRISB.TRISB6 6 PORTB Data Direction Register bit 6 BANK1:TRISB.TRISB5 5 PORTB Data Direction Register bit 5 BANK1:TRISB.TRISB4 4 PORTB Data Direction Register bit 4 BANK1:TRISB.TRISB3 3 PORTB Data Direction Register bit 3 BANK1:TRISB.TRISB2 2 PORTB Data Direction Register bit 2 BANK1:TRISB.TRISB1 1 PORTB Data Direction Register bit 1 BANK1:TRISB.TRISB0 0 PORTB Data Direction Register bit 0 BANK1:TRISC 0x0087 PORTC Data Direction Register BANK1:TRISC.TRISC7 7 PORTC Data Direction Register bit 7 BANK1:TRISC.TRISC6 6 PORTC Data Direction Register bit 6 BANK1:TRISC.TRISC5 5 PORTC Data Direction Register bit 5 BANK1:TRISC.TRISC4 4 PORTC Data Direction Register bit 4 BANK1:TRISC.TRISC3 3 PORTC Data Direction Register bit 3 BANK1:TRISC.TRISC2 2 PORTC Data Direction Register bit 2 BANK1:TRISC.TRISC1 1 PORTC Data Direction Register bit 1 BANK1:TRISC.TRISC0 0 PORTC Data Direction Register bit 0 BANK1:RESERVED0088 0x0088 RESERVED BANK1:RESERVED0089 0x0089 RESERVED BANK1:PCLATH 0x008A Write Buffer for the upper 5 bits of the Program Counter BANK1:INTCON 0x008B INTCON REGISTER BANK1:INTCON.GIE 7 Global Interrupt Enable bit BANK1:INTCON.PEIE 6 Peripheral Interrupt Enable bit BANK1:INTCON.T0IE 5 TMR0 Overflow Interrupt Enable bit BANK1:INTCON.INTE 4 RB0/INT External Interrupt Enable bit BANK1:INTCON.RBIE 3 RB Port Change Interrupt Enable bit BANK1:INTCON.T0IF 2 TMR0 Overflow Interrupt Flag bit BANK1:INTCON.INTF 1 RB0/INT External Interrupt Flag bit BANK1:INTCON.RBIF 0 RB Port Change Interrupt Flag bit BANK1:PIE1 0x008C PIE1 REGISTER BANK1:PIE1.PSPIE 7 Parallel Slave Port Read/Write Interrupt Enable bit (reserved on the 28-pin devices) BANK1:PIE1.ADIE 6 A/D Converter Interrupt Enable bit BANK1:PIE1.RCIE 5 USART Receive Interrupt Enable bit BANK1:PIE1.TXIE 4 USART Transmit Interrupt Enable bit BANK1:PIE1.CCP1IE 2 CCP1 Interrupt Enable bit BANK1:PIE1.TMR2IE 1 TMR2 to PR2 Match Interrupt Enable bit BANK1:PIE1.TMR1IE 0 TMR1 Overflow Interrupt Enable bit BANK1:PIE2 0x008D PIE2 REGISTER BANK1:PIE2.EEIE 0 EEPROM Write Operation Interrupt Enable BANK1:PCON 0x008E PCON REGISTER BANK1:PCON.POR 1 Power-on Reset Status bit BANK1:PCON.BOR 0 Brown-out Reset Status bit BANK1:RESERVED008F 0x008F RESERVED BANK1:RESERVED0090 0x0090 RESERVED BANK1:RESERVED0091 0x0091 RESERVED BANK1:PR2 0x0092 Timer2 Period Register BANK1:RESERVED0093 0x0093 RESERVED BANK1:RESERVED0094 0x0094 RESERVED BANK1:RESERVED0095 0x0095 RESERVED BANK1:RESERVED0096 0x0096 RESERVED BANK1:RESERVED0097 0x0097 RESERVED BANK1:TXSTA 0x0098 TRANSMIT STATUS AND CONTROL REGISTER BANK1:TXSTA.CSRC 7 Clock Source Select bit BANK1:TXSTA.TX9 6 9-bit Transmit Enable bit BANK1:TXSTA.TXEN 5 Transmit Enable bit BANK1:TXSTA.SYNC 4 USART Mode Select bit BANK1:TXSTA.BRGH 2 High Baud Rate Select bit BANK1:TXSTA.TRMT 1 Transmit Shift Register Status bit BANK1:TXSTA.TX9D 0 9th bit of transmit data BANK1:SPBRG 0x0099 Baud Rate Generator Register BANK1:RESERVED009A 0x009A RESERVED BANK1:RESERVED009B 0x009B RESERVED BANK1:RESERVED009C 0x009C RESERVED BANK1:RESERVED009D 0x009D RESERVED BANK1:ADRESL 0x009E A/D Result Register Low Byte BANK1:ADCON1 0x009F ADCON1 REGISTER BANK1:ADCON1.ADFM 7 A/D Result format select BANK1:ADCON1.PCFG3 3 A/D Port Configuration Control bit 3 BANK1:ADCON1.PCFG2 2 A/D Port Configuration Control bit 2 BANK1:ADCON1.PCFG1 1 A/D Port Configuration Control bit 1 BANK1:ADCON1.PCFG0 0 A/D Port Configuration Control bit 0 ; BANK2 (0x0100:0x0180) BANK2:INDF 0x0100 INDF (not a physical register) BANK2:TMR0 0x0101 Timer0 module's register BANK2:PCL 0x0102 Program Counter's (PC) Least Significant Byte BANK2:STATUS 0x0103 STATUS REGISTER BANK2:STATUS.IRP 7 RegIster Bank Select bit BANK2:STATUS.RP1 6 Register Bank Select bit 1 BANK2:STATUS.RP0 5 Register Bank Select bit 0 BANK2:STATUS.TO 4 Time-out bit BANK2:STATUS.PD 3 Power-down bit BANK2:STATUS.Z 2 Zero bit BANK2:STATUS.DC 1 Digit carry/borrow bit BANK2:STATUS.C 0 Carry/borrow bit BANK2:FSR 0x0104 Indirect data memory address pointer BANK2:RESERVED0105 0x0105 RESERVED BANK2:PORTB 0x0106 PORTB register BANK2:PORTB.RB7 7 PORTB bit 7 BANK2:PORTB.RB6 6 PORTB bit 6 BANK2:PORTB.RB5 5 PORTB bit 5 BANK2:PORTB.RB4 4 PORTB bit 4 BANK2:PORTB.RB3 3 PORTB bit 3 BANK2:PORTB.RB2 2 PORTB bit 2 BANK2:PORTB.RB1 1 PORTB bit 1 BANK2:PORTB.RB0 0 PORTB bit 0 BANK2:RESERVED0107 0x0107 RESERVED BANK2:RESERVED0108 0x0108 RESERVED BANK2:RESERVED0109 0x0109 RESERVED BANK2:PCLATH 0x010A Write Buffer for the upper 5 bits of the Program Counter BANK2:INTCON 0x010B INTCON REGISTER BANK2:INTCON.GIE 7 Global Interrupt Enable bit BANK2:INTCON.PEIE 6 Peripheral Interrupt Enable bit BANK2:INTCON.T0IE 5 TMR0 Overflow Interrupt Enable bit BANK2:INTCON.INTE 4 RB0/INT External Interrupt Enable bit BANK2:INTCON.RBIE 3 RB Port Change Interrupt Enable bit BANK2:INTCON.T0IF 2 TMR0 Overflow Interrupt Flag bit BANK2:INTCON.INTF 1 RB0/INT External Interrupt Flag bit BANK2:INTCON.RBIF 0 RB Port Change Interrupt Flag bit BANK2:EEDATA 0x010C EEPROM data register BANK2:EEADR 0x010D EEPROM address register BANK2:EEDATH 0x010E EEPROM data register high byte BANK2:EEADRH 0x010F EEPROM address register high byte ; BANK3 (0x0180:0x0200) BANK3:INDF 0x0180 INDF (not a physical register) BANK3:OPTION 0x0181 OPTION REGISTER BANK3:OPTION.RBPU 7 PORTB Pull-up Enable bit BANK3:OPTION.INTEDG 6 Interrupt Edge Select bit BANK3:OPTION.T0CS 5 TMR0 Clock Source Select bit BANK3:OPTION.T0SE 4 TMR0 Source Edge Select bit BANK3:OPTION.PSA 3 Prescaler Assignment bit BANK3:OPTION.PS2 2 Prescaler Rate Select bit 2 BANK3:OPTION.PS1 1 Prescaler Rate Select bit 1 BANK3:OPTION.PS0 0 Prescaler Rate Select bit 0 BANK3:PCL 0x0182 Program Counter's (PC) Least Significant Byte BANK3:STATUS 0x0183 STATUS REGISTER BANK3:STATUS.IRP 7 RegIster Bank Select bit BANK3:STATUS.RP1 6 Register Bank Select bit 1 BANK3:STATUS.RP0 5 Register Bank Select bit 0 BANK3:STATUS.TO 4 Time-out bit BANK3:STATUS.PD 3 Power-down bit BANK3:STATUS.Z 2 Zero bit BANK3:STATUS.DC 1 Digit carry/borrow bit BANK3:STATUS.C 0 Carry/borrow bit BANK3:FSR 0x0184 Indirect data memory address pointer BANK3:RESERVED0185 0x0185 RESERVED BANK3:TRISB 0x0186 PORTB Data Direction Register BANK3:TRISB.TRISB7 7 PORTB Data Direction Register bit 7 BANK3:TRISB.TRISB6 6 PORTB Data Direction Register bit 6 BANK3:TRISB.TRISB5 5 PORTB Data Direction Register bit 5 BANK3:TRISB.TRISB4 4 PORTB Data Direction Register bit 4 BANK3:TRISB.TRISB3 3 PORTB Data Direction Register bit 3 BANK3:TRISB.TRISB2 2 PORTB Data Direction Register bit 2 BANK3:TRISB.TRISB1 1 PORTB Data Direction Register bit 1 BANK3:TRISB.TRISB0 0 PORTB Data Direction Register bit 0 BANK3:RESERVED0187 0x0187 RESERVED BANK3:RESERVED0188 0x0188 RESERVED BANK3:RESERVED0189 0x0189 RESERVED BANK3:PCLATH 0x018A Write Buffer for the upper 5 bits of the Program Counter BANK3:INTCON 0x018B INTCON REGISTER BANK3:INTCON.GIE 7 Global Interrupt Enable bit BANK3:INTCON.PEIE 6 Peripheral Interrupt Enable bit BANK3:INTCON.T0IE 5 TMR0 Overflow Interrupt Enable bit BANK3:INTCON.INTE 4 RB0/INT External Interrupt Enable bit BANK3:INTCON.RBIE 3 RB Port Change Interrupt Enable bit BANK3:INTCON.T0IF 2 TMR0 Overflow Interrupt Flag bit BANK3:INTCON.INTF 1 RB0/INT External Interrupt Flag bit BANK3:INTCON.RBIF 0 RB Port Change Interrupt Flag bit BANK3:EECON1 0x018C EECON1 REGISTER BANK3:EECON1.EEPGD 7 Program/Data EEPROM Select bit BANK3:EECON1.WRERR 3 EEPROM Error Flag bit BANK3:EECON1.WREN 2 EEPROM Write Enable bit BANK3:EECON1.WR 1 Write Control bit BANK3:EECON1.RD 0 Read Control bit BANK3:EECON2 0x018D EEPROM control register2 (not a physical register) .16F871 ; http://www.microchip.com/download/lit/pline/picmicro/families/16f87x/30569a.pdf ; PIC16F870_1.pdf ; MEMORY MAP ; BANK_0 area DATA FSR_ 0x0000:0x0020 area DATA Gen_Purp 0x0020:0x0080 General Purpose Register area DATA MEM_Program 0x0080:0x0800 On-chip Program Memory ; BANK_1 ; area DATA FSR_ 0x0080:0x00A0 ; area DATA Gen_Purp 0x00A0:0x00C0 General Purpose Register ; area BSS RESERVED 0x00C0:0x00F0 ; area DATA Gen_Purp_BANK0 0x00F0:0x0100 accesses 70h-7Fh ; area DATA MEM_Program 0x0100:0x0800 On-chip Program Memory ; BANK_2 ; area DATA FSR_ 0x0100:0x0110 ; area BSS RESERVED 0x0110:0x0120 ; area DATA Gen_Purp_BANK0 0x0120:0x0180 accesses 20h-7Fh ; area DATA MEM_Program 0x0180:0x0800 On-chip Program Memory ; BANK_3 ; area DATA FSR_ 0x0180:0x018E ; area BSS RESERVED 0x018E:0x01A0 ; area DATA Gen_Purp_BANK00 0x01A0:0x01C0 accesses A0h-BFh ; area BSS RESERVED 0x01C0:0x01F0 ; area DATA Gen_Purp_BANK01 0x01F0:0x0200 accesses 70h-7Fh ; area DATA MEM_Program 0x0200:0x0800 On-chip Program Memory ; Interrupt and reset vector assignments interrupt RESET 0x0000 RESET ; INPUT/OUTPUT PORTS ; BANK0 (0x0000:0x0080) BANK0:INDF 0x0000 INDF (not a physical register) BANK0:TMR0 0x0001 Timer0 module's register BANK0:PCL 0x0002 Program Counter's (PC) Least Significant Byte BANK0:STATUS 0x0003 STATUS REGISTER BANK0:STATUS.IRP 7 RegIster Bank Select bit BANK0:STATUS.RP1 6 Register Bank Select bit 1 BANK0:STATUS.RP0 5 Register Bank Select bit 0 BANK0:STATUS.TO 4 Time-out bit BANK0:STATUS.PD 3 Power-down bit BANK0:STATUS.Z 2 Zero bit BANK0:STATUS.DC 1 Digit carry/borrow bit BANK0:STATUS.C 0 Carry/borrow bit BANK0:FSR 0x0004 Indirect data memory address pointer BANK0:PORTA 0x0005 PORTA register BANK0:PORTA.RA5 5 PORTA bit 5 BANK0:PORTA.RA4 4 PORTA bit 4 BANK0:PORTA.RA3 3 PORTA bit 3 BANK0:PORTA.RA2 2 PORTA bit 2 BANK0:PORTA.RA1 1 PORTA bit 1 BANK0:PORTA.RA0 0 PORTA bit 0 BANK0:PORTB 0x0006 PORTB register BANK0:PORTB.RB7 7 PORTB bit 7 BANK0:PORTB.RB6 6 PORTB bit 6 BANK0:PORTB.RB5 5 PORTB bit 5 BANK0:PORTB.RB4 4 PORTB bit 4 BANK0:PORTB.RB3 3 PORTB bit 3 BANK0:PORTB.RB2 2 PORTB bit 2 BANK0:PORTB.RB1 1 PORTB bit 1 BANK0:PORTB.RB0 0 PORTB bit 0 BANK0:PORTC 0x0007 PORTC register BANK0:PORTC.RC7 7 PORTC bit 7 BANK0:PORTC.RC6 6 PORTC bit 6 BANK0:PORTC.RC5 5 PORTC bit 5 BANK0:PORTC.RC4 4 PORTC bit 4 BANK0:PORTC.RC3 3 PORTC bit 3 BANK0:PORTC.RC2 2 PORTC bit 2 BANK0:PORTC.RC1 1 PORTC bit 1 BANK0:PORTC.RC0 0 PORTC bit 0 BANK0:PORTD 0x0008 PORTD register (not implemented on the 28-pin devices) BANK0:PORTD.RD7 7 PORTD bit 7 BANK0:PORTD.RD6 6 PORTD bit 6 BANK0:PORTD.RD5 5 PORTD bit 5 BANK0:PORTD.RD4 4 PORTD bit 4 BANK0:PORTD.RD3 3 PORTD bit 3 BANK0:PORTD.RD2 2 PORTD bit 2 BANK0:PORTD.RD1 1 PORTD bit 1 BANK0:PORTD.RD0 0 PORTD bit 0 BANK0:PORTE 0x0009 PORTE register (not implemented on the 28-pin devices) BANK0:PORTE.RE2 2 PORTE bit 2 BANK0:PORTE.RE1 1 PORTE bit 1 BANK0:PORTE.RE0 0 PORTE bit 0 BANK0:PCLATH 0x000A Write Buffer for the upper 5 bits of the Program Counter BANK0:INTCON 0x000B INTCON REGISTER BANK0:INTCON.GIE 7 Global Interrupt Enable bit BANK0:INTCON.PEIE 6 Peripheral Interrupt Enable bit BANK0:INTCON.T0IE 5 TMR0 Overflow Interrupt Enable bit BANK0:INTCON.INTE 4 RB0/INT External Interrupt Enable bit BANK0:INTCON.RBIE 3 RB Port Change Interrupt Enable bit BANK0:INTCON.T0IF 2 TMR0 Overflow Interrupt Flag bit BANK0:INTCON.INTF 1 RB0/INT External Interrupt Flag bit BANK0:INTCON.RBIF 0 RB Port Change Interrupt Flag bit BANK0:PIR1 0x000C PIR1 REGISTER BANK0:PIR1.PSPIF 7 Parallel Slave Port Interrupt Flag bit (reserved on the 28-pin devices) BANK0:PIR1.ADIF 6 A/D Converter Interrupt Flag bit BANK0:PIR1.RCIF 5 USART Receive Interrupt Flag bit BANK0:PIR1.TXIF 4 USART Transmit Interrupt Flag bit BANK0:PIR1.CCP1IF 2 CCP1 Interrupt Flag bit BANK0:PIR1.TMR2IF 1 TMR2 to PR2 Match Interrupt Flag bit BANK0:PIR1.TMR1IF 0 TMR1 Overflow Interrupt Flag bit BANK0:PIR2 0x000D PIR2 REGISTER BANK0:PIR2.EEIF 4 EEPROM Write Operation Interrupt Flag bit BANK0:TMR1L 0x000E Holding register for the Least Significant Byte of the 16-bit TMR1 register BANK0:TMR1H 0x000F Holding register for the Most Significant Byte of the 16-bit TMR1 register BANK0:T1CON 0x0010 TIMER1 CONTROL REGISTER BANK0:T1CON.T1CKPS1 5 Timer1 Input Clock Prescale Select bit 1 BANK0:T1CON.T1CKPS0 4 Timer1 Input Clock Prescale Select bit 0 BANK0:T1CON.T1OSCEN 3 Timer1 Oscillator Enable Control bit BANK0:T1CON.T1SYNC 2 Timer1 External Clock Input Synchronization Control bit BANK0:T1CON.TMR1CS 1 Timer1 Clock Source Select bit BANK0:T1CON.TMR1ON 0 Timer1 On bit BANK0:TMR2 0x0011 Timer2 module's register BANK0:T2CON 0x0012 TIMER2 CONTROL REGISTER BANK0:T2CON.TOUTPS3 6 Timer2 Output Postscale Select bit 3 BANK0:T2CON.TOUTPS2 5 Timer2 Output Postscale Select bit 2 BANK0:T2CON.TOUTPS1 4 Timer2 Output Postscale Select bit 1 BANK0:T2CON.TOUTPS0 3 Timer2 Output Postscale Select bit 0 BANK0:T2CON.TMR2ON 2 Timer2 On bit BANK0:T2CON.T2CKPS1 1 Timer2 Clock Prescale Select bit 1 BANK0:T2CON.T2CKPS0 0 Timer2 Clock Prescale Select bit 0 BANK0:RESERVED0013 0x0013 RESERVED BANK0:RESERVED0014 0x0014 RESERVED BANK0:CCPR1L 0x0015 Capture/Compare/PWM1 (LSB) BANK0:CCPR1H 0x0016 Capture/Compare/PWM1 (MSB) BANK0:CCP1CON 0x0017 CCP1CON REGISTER BANK0:CCP1CON.CCP1X 5 PWM Least Significant bit BANK0:CCP1CON.CCP1Y 4 PWM Least Significant bit BANK0:CCP1CON.CCP1M3 3 CCP1 Mode Select bit 3 BANK0:CCP1CON.CCP1M2 2 CCP1 Mode Select bit 2 BANK0:CCP1CON.CCP1M1 1 CCP1 Mode Select bit 1 BANK0:CCP1CON.CCP1M0 0 CCP1 Mode Select bit 0 BANK0:RCSTA 0x0018 RECEIVE STATUS AND CONTROL REGISTER BANK0:RCSTA.SPEN 7 Serial Port Enable bit BANK0:RCSTA.RX9 6 9-bit Receive Enable bit BANK0:RCSTA.SREN 5 Single Receive Enable bit BANK0:RCSTA.CREN 4 Continuous Receive Enable bit BANK0:RCSTA.ADDEN 3 Address Detect Enable bit BANK0:RCSTA.FERR 2 Framing Error bit BANK0:RCSTA.OERR 1 Overrun Error bit BANK0:RCSTA.RX9D 0 9th bit of received data BANK0:TXREG 0x0019 USART Transmit Data Register BANK0:RCREG 0x001A USART Receive Data Register BANK0:RESERVED001B 0x001B RESERVED BANK0:RESERVED001C 0x001C RESERVED BANK0:RESERVED001D 0x001D RESERVED BANK0:ADRESH 0x001E A/D Result Register High Byte BANK0:ADCON0 0x001F ADCON0 REGISTER BANK0:ADCON0.ADCS1 7 A/D Conversion Clock Select bit 1 BANK0:ADCON0.ADCS0 6 A/D Conversion Clock Select bit 0 BANK0:ADCON0.CHS2 5 Analog Channel Select bit 2 BANK0:ADCON0.CHS1 4 Analog Channel Select bit 1 BANK0:ADCON0.CHS0 3 Analog Channel Select bit 0 BANK0:ADCON0.GO_DONE 2 A/D Conversion Status bit BANK0:ADCON0.ADON 0 A/D On bit ; BANK1 (0x0080:0x0100) BANK1:INDF 0x0080 INDF (not a physical register) BANK1:OPTION 0x0081 OPTION REGISTER BANK1:OPTION.RBPU 7 PORTB Pull-up Enable bit BANK1:OPTION.INTEDG 6 Interrupt Edge Select bit BANK1:OPTION.T0CS 5 TMR0 Clock Source Select bit BANK1:OPTION.T0SE 4 TMR0 Source Edge Select bit BANK1:OPTION.PSA 3 Prescaler Assignment bit BANK1:OPTION.PS2 2 Prescaler Rate Select bit 2 BANK1:OPTION.PS1 1 Prescaler Rate Select bit 1 BANK1:OPTION.PS0 0 Prescaler Rate Select bit 0 BANK1:PCL 0x0082 Program Counter's (PC) Least Significant Byte BANK1:STATUS 0x0083 STATUS REGISTER BANK1:STATUS.IRP 7 RegIster Bank Select bit BANK1:STATUS.RP1 6 Register Bank Select bit 1 BANK1:STATUS.RP0 5 Register Bank Select bit 0 BANK1:STATUS.TO 4 Time-out bit BANK1:STATUS.PD 3 Power-down bit BANK1:STATUS.Z 2 Zero bit BANK1:STATUS.DC 1 Digit carry/borrow bit BANK1:STATUS.C 0 Carry/borrow bit BANK1:FSR 0x0084 Indirect data memory address pointer BANK1:TRISA 0x0085 PORTA Data Direction Register BANK1:TRISA.TRISA5 5 PORTA Data Direction Register bit 5 BANK1:TRISA.TRISA4 4 PORTA Data Direction Register bit 4 BANK1:TRISA.TRISA3 3 PORTA Data Direction Register bit 3 BANK1:TRISA.TRISA2 2 PORTA Data Direction Register bit 2 BANK1:TRISA.TRISA1 1 PORTA Data Direction Register bit 1 BANK1:TRISA.TRISA0 0 PORTA Data Direction Register bit 0 BANK1:TRISB 0x0086 PORTB Data Direction Register BANK1:TRISB.TRISB7 7 PORTB Data Direction Register bit 7 BANK1:TRISB.TRISB6 6 PORTB Data Direction Register bit 6 BANK1:TRISB.TRISB5 5 PORTB Data Direction Register bit 5 BANK1:TRISB.TRISB4 4 PORTB Data Direction Register bit 4 BANK1:TRISB.TRISB3 3 PORTB Data Direction Register bit 3 BANK1:TRISB.TRISB2 2 PORTB Data Direction Register bit 2 BANK1:TRISB.TRISB1 1 PORTB Data Direction Register bit 1 BANK1:TRISB.TRISB0 0 PORTB Data Direction Register bit 0 BANK1:TRISC 0x0087 PORTC Data Direction Register BANK1:TRISC.TRISC7 7 PORTC Data Direction Register bit 7 BANK1:TRISC.TRISC6 6 PORTC Data Direction Register bit 6 BANK1:TRISC.TRISC5 5 PORTC Data Direction Register bit 5 BANK1:TRISC.TRISC4 4 PORTC Data Direction Register bit 4 BANK1:TRISC.TRISC3 3 PORTC Data Direction Register bit 3 BANK1:TRISC.TRISC2 2 PORTC Data Direction Register bit 2 BANK1:TRISC.TRISC1 1 PORTC Data Direction Register bit 1 BANK1:TRISC.TRISC0 0 PORTC Data Direction Register bit 0 BANK1:TRISD 0x0088 PORTD Data Direction Register (not implemented on the 28-pin devices) BANK1:TRISD.TRISD7 7 PORTD Data Direction Register bit 7 BANK1:TRISD.TRISD6 6 PORTD Data Direction Register bit 6 BANK1:TRISD.TRISD5 5 PORTD Data Direction Register bit 5 BANK1:TRISD.TRISD4 4 PORTD Data Direction Register bit 4 BANK1:TRISD.TRISD3 3 PORTD Data Direction Register bit 3 BANK1:TRISD.TRISD2 2 PORTD Data Direction Register bit 2 BANK1:TRISD.TRISD1 1 PORTD Data Direction Register bit 1 BANK1:TRISD.TRISD0 0 PORTD Data Direction Register bit 0 BANK1:TRISE 0x0089 PORTE Data Direction Bits (not implemented on the 28-pin devices) BANK1:TRISE.IBF 7 Input Buffer Full Status bit BANK1:TRISE.OBF 6 Output Buffer Full Status bit BANK1:TRISE.IBOV 5 Input Buffer Overflow Detect bit BANK1:TRISE.PSPMODE 4 Parallel Slave Port Mode Select bit BANK1:TRISE.TRISE2 2 Direction Control bit for pin RE2/CS BANK1:TRISE.TRISE1 1 Direction Control bit for pin RE1/WR BANK1:TRISE.TRISE0 0 Direction Control bit for pin RE0/RD BANK1:PCLATH 0x008A Write Buffer for the upper 5 bits of the Program Counter BANK1:INTCON 0x008B INTCON REGISTER BANK1:INTCON.GIE 7 Global Interrupt Enable bit BANK1:INTCON.PEIE 6 Peripheral Interrupt Enable bit BANK1:INTCON.T0IE 5 TMR0 Overflow Interrupt Enable bit BANK1:INTCON.INTE 4 RB0/INT External Interrupt Enable bit BANK1:INTCON.RBIE 3 RB Port Change Interrupt Enable bit BANK1:INTCON.T0IF 2 TMR0 Overflow Interrupt Flag bit BANK1:INTCON.INTF 1 RB0/INT External Interrupt Flag bit BANK1:INTCON.RBIF 0 RB Port Change Interrupt Flag bit BANK1:PIE1 0x008C PIE1 REGISTER BANK1:PIE1.PSPIE 7 Parallel Slave Port Read/Write Interrupt Enable bit (reserved on the 28-pin devices) BANK1:PIE1.ADIE 6 A/D Converter Interrupt Enable bit BANK1:PIE1.RCIE 5 USART Receive Interrupt Enable bit BANK1:PIE1.TXIE 4 USART Transmit Interrupt Enable bit BANK1:PIE1.CCP1IE 2 CCP1 Interrupt Enable bit BANK1:PIE1.TMR2IE 1 TMR2 to PR2 Match Interrupt Enable bit BANK1:PIE1.TMR1IE 0 TMR1 Overflow Interrupt Enable bit BANK1:PIE2 0x008D PIE2 REGISTER BANK1:PIE2.EEIE 0 EEPROM Write Operation Interrupt Enable BANK1:PCON 0x008E PCON REGISTER BANK1:PCON.POR 1 Power-on Reset Status bit BANK1:PCON.BOR 0 Brown-out Reset Status bit BANK1:RESERVED008F 0x008F RESERVED BANK1:RESERVED0090 0x0090 RESERVED BANK1:RESERVED0091 0x0091 RESERVED BANK1:PR2 0x0092 Timer2 Period Register BANK1:RESERVED0093 0x0093 RESERVED BANK1:RESERVED0094 0x0094 RESERVED BANK1:RESERVED0095 0x0095 RESERVED BANK1:RESERVED0096 0x0096 RESERVED BANK1:RESERVED0097 0x0097 RESERVED BANK1:TXSTA 0x0098 TRANSMIT STATUS AND CONTROL REGISTER BANK1:TXSTA.CSRC 7 Clock Source Select bit BANK1:TXSTA.TX9 6 9-bit Transmit Enable bit BANK1:TXSTA.TXEN 5 Transmit Enable bit BANK1:TXSTA.SYNC 4 USART Mode Select bit BANK1:TXSTA.BRGH 2 High Baud Rate Select bit BANK1:TXSTA.TRMT 1 Transmit Shift Register Status bit BANK1:TXSTA.TX9D 0 9th bit of transmit data BANK1:SPBRG 0x0099 Baud Rate Generator Register BANK1:RESERVED009A 0x009A RESERVED BANK1:RESERVED009B 0x009B RESERVED BANK1:RESERVED009C 0x009C RESERVED BANK1:RESERVED009D 0x009D RESERVED BANK1:ADRESL 0x009E A/D Result Register Low Byte BANK1:ADCON1 0x009F ADCON1 REGISTER BANK1:ADCON1.ADFM 7 A/D Result format select BANK1:ADCON1.PCFG3 3 A/D Port Configuration Control bit 3 BANK1:ADCON1.PCFG2 2 A/D Port Configuration Control bit 2 BANK1:ADCON1.PCFG1 1 A/D Port Configuration Control bit 1 BANK1:ADCON1.PCFG0 0 A/D Port Configuration Control bit 0 ; BANK2 (0x0100:0x0180) BANK2:INDF 0x0100 INDF (not a physical register) BANK2:TMR0 0x0101 Timer0 module's register BANK2:PCL 0x0102 Program Counter's (PC) Least Significant Byte BANK2:STATUS 0x0103 STATUS REGISTER BANK2:STATUS.IRP 7 RegIster Bank Select bit BANK2:STATUS.RP1 6 Register Bank Select bit 1 BANK2:STATUS.RP0 5 Register Bank Select bit 0 BANK2:STATUS.TO 4 Time-out bit BANK2:STATUS.PD 3 Power-down bit BANK2:STATUS.Z 2 Zero bit BANK2:STATUS.DC 1 Digit carry/borrow bit BANK2:STATUS.C 0 Carry/borrow bit BANK2:FSR 0x0104 Indirect data memory address pointer BANK2:RESERVED0105 0x0105 RESERVED BANK2:PORTB 0x0106 PORTB register BANK2:PORTB.RB7 7 PORTB bit 7 BANK2:PORTB.RB6 6 PORTB bit 6 BANK2:PORTB.RB5 5 PORTB bit 5 BANK2:PORTB.RB4 4 PORTB bit 4 BANK2:PORTB.RB3 3 PORTB bit 3 BANK2:PORTB.RB2 2 PORTB bit 2 BANK2:PORTB.RB1 1 PORTB bit 1 BANK2:PORTB.RB0 0 PORTB bit 0 BANK2:RESERVED0107 0x0107 RESERVED BANK2:RESERVED0108 0x0108 RESERVED BANK2:RESERVED0109 0x0109 RESERVED BANK2:PCLATH 0x010A Write Buffer for the upper 5 bits of the Program Counter BANK2:INTCON 0x010B INTCON REGISTER BANK2:INTCON.GIE 7 Global Interrupt Enable bit BANK2:INTCON.PEIE 6 Peripheral Interrupt Enable bit BANK2:INTCON.T0IE 5 TMR0 Overflow Interrupt Enable bit BANK2:INTCON.INTE 4 RB0/INT External Interrupt Enable bit BANK2:INTCON.RBIE 3 RB Port Change Interrupt Enable bit BANK2:INTCON.T0IF 2 TMR0 Overflow Interrupt Flag bit BANK2:INTCON.INTF 1 RB0/INT External Interrupt Flag bit BANK2:INTCON.RBIF 0 RB Port Change Interrupt Flag bit BANK2:EEDATA 0x010C EEPROM data register BANK2:EEADR 0x010D EEPROM address register BANK2:EEDATH 0x010E EEPROM data register high byte BANK2:EEADRH 0x010F EEPROM address register high byte ; BANK3 (0x0180:0x0200) BANK3:INDF 0x0180 INDF (not a physical register) BANK3:OPTION 0x0181 OPTION REGISTER BANK3:OPTION.RBPU 7 PORTB Pull-up Enable bit BANK3:OPTION.INTEDG 6 Interrupt Edge Select bit BANK3:OPTION.T0CS 5 TMR0 Clock Source Select bit BANK3:OPTION.T0SE 4 TMR0 Source Edge Select bit BANK3:OPTION.PSA 3 Prescaler Assignment bit BANK3:OPTION.PS2 2 Prescaler Rate Select bit 2 BANK3:OPTION.PS1 1 Prescaler Rate Select bit 1 BANK3:OPTION.PS0 0 Prescaler Rate Select bit 0 BANK3:PCL 0x0182 Program Counter's (PC) Least Significant Byte BANK3:STATUS 0x0183 STATUS REGISTER BANK3:STATUS.IRP 7 RegIster Bank Select bit BANK3:STATUS.RP1 6 Register Bank Select bit 1 BANK3:STATUS.RP0 5 Register Bank Select bit 0 BANK3:STATUS.TO 4 Time-out bit BANK3:STATUS.PD 3 Power-down bit BANK3:STATUS.Z 2 Zero bit BANK3:STATUS.DC 1 Digit carry/borrow bit BANK3:STATUS.C 0 Carry/borrow bit BANK3:FSR 0x0184 Indirect data memory address pointer BANK3:RESERVED0185 0x0185 RESERVED BANK3:TRISB 0x0186 PORTB Data Direction Register BANK3:TRISB.TRISB7 7 PORTB Data Direction Register bit 7 BANK3:TRISB.TRISB6 6 PORTB Data Direction Register bit 6 BANK3:TRISB.TRISB5 5 PORTB Data Direction Register bit 5 BANK3:TRISB.TRISB4 4 PORTB Data Direction Register bit 4 BANK3:TRISB.TRISB3 3 PORTB Data Direction Register bit 3 BANK3:TRISB.TRISB2 2 PORTB Data Direction Register bit 2 BANK3:TRISB.TRISB1 1 PORTB Data Direction Register bit 1 BANK3:TRISB.TRISB0 0 PORTB Data Direction Register bit 0 BANK3:RESERVED0187 0x0187 RESERVED BANK3:RESERVED0188 0x0188 RESERVED BANK3:RESERVED0189 0x0189 RESERVED BANK3:PCLATH 0x018A Write Buffer for the upper 5 bits of the Program Counter BANK3:INTCON 0x018B INTCON REGISTER BANK3:INTCON.GIE 7 Global Interrupt Enable bit BANK3:INTCON.PEIE 6 Peripheral Interrupt Enable bit BANK3:INTCON.T0IE 5 TMR0 Overflow Interrupt Enable bit BANK3:INTCON.INTE 4 RB0/INT External Interrupt Enable bit BANK3:INTCON.RBIE 3 RB Port Change Interrupt Enable bit BANK3:INTCON.T0IF 2 TMR0 Overflow Interrupt Flag bit BANK3:INTCON.INTF 1 RB0/INT External Interrupt Flag bit BANK3:INTCON.RBIF 0 RB Port Change Interrupt Flag bit BANK3:EECON1 0x018C EECON1 REGISTER BANK3:EECON1.EEPGD 7 Program/Data EEPROM Select bit BANK3:EECON1.WRERR 3 EEPROM Error Flag bit BANK3:EECON1.WREN 2 EEPROM Write Enable bit BANK3:EECON1.WR 1 Write Control bit BANK3:EECON1.RD 0 Read Control bit BANK3:EECON2 0x018D EEPROM control register2 (not a physical register) .16F873 ; http://www.microchip.com/download/lit/pline/picmicro/families/16f87x/30292c.pdf ; PIC16F873_4_6_7.pdf ; MEMORY MAP ; BANK_0 area DATA FSR_ 0x0000:0x0020 area DATA Gen_Purp 0x0020:0x0080 General Purpose Register area DATA MEM_Program0 0x0080:0x0800 On-chip Program Memory (Page 0) area DATA MEM_Program1 0x0800:0x1000 On-chip Program Memory (Page 1) ; BANK_1 ; area DATA FSR_ 0x0080:0x00A0 ; area DATA Gen_Purp 0x00A0:0x0100 General Purpose Register ; area DATA MEM_Program0 0x0100:0x0800 On-chip Program Memory (Page 0) ; area DATA MEM_Program1 0x0800:0x1000 On-chip Program Memory (Page 1) ; BANK_2 ; area DATA FSR_ 0x0100:0x0110 ; area BSS RESERVED 0x0110:0x0120 ; area DATA Gen_Purp_BANK0 0x0120:0x0180 accesses 20h-7Fh ; area DATA MEM_Program0 0x0180:0x0800 On-chip Program Memory (Page 0) ; area DATA MEM_Program1 0x0800:0x1000 On-chip Program Memory (Page 1) ; BANK_3 ; area DATA FSR_ 0x0180:0x0190 ; area BSS RESERVED 0x0190:0x01A0 ; area DATA Gen_Purp_BANK1 0x01A0:0x0200 accesses A0h-FFh ; area DATA MEM_Program0 0x0200:0x0800 On-chip Program Memory (Page 0) ; area DATA MEM_Program1 0x0800:0x1000 On-chip Program Memory (Page 1) ; Interrupt and reset vector assignments interrupt RESET 0x0000 RESET ; INPUT/OUTPUT PORTS ; BANK0 (0x0000:0x0080) BANK0:INDF 0x0000 INDF (not a physical register) BANK0:TMR0 0x0001 Timer0 module's register BANK0:PCL 0x0002 Program Counter (PC) Least Significant Byte BANK0:STATUS 0x0003 STATUS REGISTER BANK0:STATUS.IRP 7 RegIster Bank Select bit BANK0:STATUS.RP1 6 Register Bank Select bit 1 BANK0:STATUS.RP0 5 Register Bank Select bit 0 BANK0:STATUS.TO 4 Time-out bit BANK0:STATUS.PD 3 Power-down bit BANK0:STATUS.Z 2 Zero bit BANK0:STATUS.DC 1 Digit carry/borrow bit BANK0:STATUS.C 0 Carry/borrow bit BANK0:FSR 0x0004 Indirect data memory address pointer BANK0:PORTA 0x0005 PORTA register BANK0:PORTA.RA5 5 PORTA bit 5 BANK0:PORTA.RA4 4 PORTA bit 4 BANK0:PORTA.RA3 3 PORTA bit 3 BANK0:PORTA.RA2 2 PORTA bit 2 BANK0:PORTA.RA1 1 PORTA bit 1 BANK0:PORTA.RA0 0 PORTA bit 0 BANK0:PORTB 0x0006 PORTB register BANK0:PORTB.RB7 7 PORTB bit 7 BANK0:PORTB.RB6 6 PORTB bit 6 BANK0:PORTB.RB5 5 PORTB bit 5 BANK0:PORTB.RB4 4 PORTB bit 4 BANK0:PORTB.RB3 3 PORTB bit 3 BANK0:PORTB.RB2 2 PORTB bit 2 BANK0:PORTB.RB1 1 PORTB bit 1 BANK0:PORTB.RB0 0 PORTB bit 0 BANK0:PORTC 0x0007 PORTC register BANK0:PORTC.RC7 7 PORTC bit 7 BANK0:PORTC.RC6 6 PORTC bit 6 BANK0:PORTC.RC5 5 PORTC bit 5 BANK0:PORTC.RC4 4 PORTC bit 4 BANK0:PORTC.RC3 3 PORTC bit 3 BANK0:PORTC.RC2 2 PORTC bit 2 BANK0:PORTC.RC1 1 PORTC bit 1 BANK0:PORTC.RC0 0 PORTC bit 0 BANK0:RESERVED0008 0x0008 RESERVED BANK0:RESERVED0009 0x0009 RESERVED BANK0:PCLATH 0x000A Write Buffer for the upper 5 bits of the Program Counter BANK0:INTCON 0x000B INTCON REGISTER BANK0:INTCON.GIE 7 Global Interrupt Enable bit BANK0:INTCON.PEIE 6 Peripheral Interrupt Enable bit BANK0:INTCON.T0IE 5 TMR0 Overflow Interrupt Enable bit BANK0:INTCON.INTE 4 RB0/INT External Interrupt Enable bit BANK0:INTCON.RBIE 3 RB Port Change Interrupt Enable bit BANK0:INTCON.T0IF 2 TMR0 Overflow Interrupt Flag bit BANK0:INTCON.INTF 1 RB0/INT External Interrupt Flag bit BANK0:INTCON.RBIF 0 RB Port Change Interrupt Flag bit BANK0:PIR1 0x000C PIR1 REGISTER BANK0:PIR1.ADIF 6 A/D Converter Interrupt Flag bit BANK0:PIR1.RCIF 5 USART Receive Interrupt Flag bit BANK0:PIR1.TXIF 4 USART Transmit Interrupt Flag bit BANK0:PIR1.SSPIF 3 Synchronous Serial Port Interrupt Flag bit BANK0:PIR1.CCP1IF 2 CCP1 Interrupt Flag bit BANK0:PIR1.TMR2IF 1 TMR2 to PR2 Match Interrupt Flag bit BANK0:PIR1.TMR1IF 0 TMR1 Overflow Interrupt Flag bit BANK0:PIR2 0x000D PIR2 REGISTER BANK0:PIR2.EEIF 4 EEPROM Write Operation Interrupt Flag bit BANK0:PIR2.BCLIF 3 Bus Collision Interrupt Flag bit BANK0:PIR2.CCP2IF 0 CCP2 Interrupt Flag bit BANK0:TMR1L 0x000E Holding register for the Least Significant Byte of the 16-bit TMR1 register BANK0:TMR1H 0x000F Holding register for the Most Significant Byte of the 16-bit TMR1 register BANK0:T1CON 0x0010 TIMER1 CONTROL REGISTER BANK0:T1CON.T1CKPS1 5 Timer1 Input Clock Prescale Select bit 1 BANK0:T1CON.T1CKPS0 4 Timer1 Input Clock Prescale Select bit 0 BANK0:T1CON.T1OSCEN 3 Timer1 Oscillator Enable Control bit BANK0:T1CON.T1SYNC 2 Timer1 External Clock Input Synchronization Control bit BANK0:T1CON.TMR1CS 1 Timer1 Clock Source Select bit BANK0:T1CON.TMR1ON 0 Timer1 On bit BANK0:TMR2 0x0011 Timer2 module's register BANK0:T2CON 0x0012 TIMER2 CONTROL REGISTER BANK0:T2CON.TOUTPS3 6 Timer2 Output Postscale Select bit 3 BANK0:T2CON.TOUTPS2 5 Timer2 Output Postscale Select bit 2 BANK0:T2CON.TOUTPS1 4 Timer2 Output Postscale Select bit 1 BANK0:T2CON.TOUTPS0 3 Timer2 Output Postscale Select bit 0 BANK0:T2CON.TMR2ON 2 Timer2 On bit BANK0:T2CON.T2CKPS1 1 Timer2 Clock Prescale Select bit 1 BANK0:T2CON.T2CKPS0 0 Timer2 Clock Prescale Select bit 0 BANK0:SSPBUF 0x0013 Synchronous Serial Port Receive Buffer/Transmit Register BANK0:SSPCON 0x0014 SYNC SERIAL PORT CONTROL REGISTER BANK0:SSPCON.WCOL 7 Write Collision Detect bit BANK0:SSPCON.SSPOV 6 Receive Overflow Indicator bit BANK0:SSPCON.SSPEN 5 Synchronous Serial Port Enable bit BANK0:SSPCON.CKP 4 Clock Polarity Select bit BANK0:SSPCON.SSPM3 3 Synchronous Serial Port Mode Select bit 3 BANK0:SSPCON.SSPM2 2 Synchronous Serial Port Mode Select bit 2 BANK0:SSPCON.SSPM1 1 Synchronous Serial Port Mode Select bit 1 BANK0:SSPCON.SSPM0 0 Synchronous Serial Port Mode Select bit 0 BANK0:CCPR1L 0x0015 Capture/Compare/PWM1 Register1 (LSB) BANK0:CCPR1H 0x0016 Capture/Compare/PWM1 Register1 (MSB) BANK0:CCP1CON 0x0017 CCP1CON REGISTER BANK0:CCP1CON.CCP1X 5 PWM Least Significant bit BANK0:CCP1CON.CCP1Y 4 PWM Least Significant bit BANK0:CCP1CON.CCP1M3 3 CCP1 Mode Select bit 3 BANK0:CCP1CON.CCP1M2 2 CCP1 Mode Select bit 2 BANK0:CCP1CON.CCP1M1 1 CCP1 Mode Select bit 1 BANK0:CCP1CON.CCP1M0 0 CCP1 Mode Select bit 0 BANK0:RCSTA 0x0018 RECEIVE STATUS AND CONTROL REGISTER BANK0:RCSTA.SPEN 7 Serial Port Enable bit BANK0:RCSTA.RX9 6 9-bit Receive Enable bit BANK0:RCSTA.SREN 5 Single Receive Enable bit BANK0:RCSTA.CREN 4 Continuous Receive Enable bit BANK0:RCSTA.ADDEN 3 Address Detect Enable bit BANK0:RCSTA.FERR 2 Framing Error bit BANK0:RCSTA.OERR 1 Overrun Error bit BANK0:RCSTA.RX9D 0 9th bit of received data BANK0:TXREG 0x0019 USART Transmit Data Register BANK0:RCREG 0x001A USART Receive Data Register BANK0:CCPR2L 0x001B Capture/Compare/PWM2 Register2 (LSB) BANK0:CCPR2H 0x001C Capture/Compare/PWM2 Register2 (MSB) BANK0:CCP2CON 0x001D CCP2CON REGISTER BANK0:CCP2CON.CCP2X 5 PWM Least Significant bit BANK0:CCP2CON.CCP2Y 4 PWM Least Significant bit BANK0:CCP2CON.CCP2M3 3 CCP2 Mode Select bit 3 BANK0:CCP2CON.CCP2M2 2 CCP2 Mode Select bit 2 BANK0:CCP2CON.CCP2M1 1 CCP2 Mode Select bit 1 BANK0:CCP2CON.CCP2M0 0 CCP2 Mode Select bit 0 BANK0:ADRESH 0x001E A/D Result Register High Byte BANK0:ADCON0 0x001F ADCON0 REGISTER BANK0:ADCON0.ADCS1 7 A/D Conversion Clock Select bit 1 BANK0:ADCON0.ADCS0 6 A/D Conversion Clock Select bit 0 BANK0:ADCON0.CHS2 5 Analog Channel Select bit 2 BANK0:ADCON0.CHS1 4 Analog Channel Select bit 1 BANK0:ADCON0.CHS0 3 Analog Channel Select bit 0 BANK0:ADCON0.GO_DONE 2 A/D Conversion Status bit BANK0:ADCON0.ADON 0 A/D On bit ; BANK1 (0x0080:0x0100) BANK1:INDF 0x0080 INDF (not a physical register) BANK1:OPTION 0x0081 OPTION REGISTER BANK1:OPTION.RBPU 7 PORTB Pull-up Enable bit BANK1:OPTION.INTEDG 6 Interrupt Edge Select bit BANK1:OPTION.T0CS 5 TMR0 Clock Source Select bit BANK1:OPTION.T0SE 4 TMR0 Source Edge Select bit BANK1:OPTION.PSA 3 Prescaler Assignment bit BANK1:OPTION.PS2 2 Prescaler Rate Select bit 2 BANK1:OPTION.PS1 1 Prescaler Rate Select bit 1 BANK1:OPTION.PS0 0 Prescaler Rate Select bit 0 BANK1:PCL 0x0082 Program Counter's (PC) Least Significant Byte BANK1:STATUS 0x0083 STATUS REGISTER BANK1:STATUS.IRP 7 RegIster Bank Select bit BANK1:STATUS.RP1 6 Register Bank Select bit 1 BANK1:STATUS.RP0 5 Register Bank Select bit 0 BANK1:STATUS.TO 4 Time-out bit BANK1:STATUS.PD 3 Power-down bit BANK1:STATUS.Z 2 Zero bit BANK1:STATUS.DC 1 Digit carry/borrow bit BANK1:STATUS.C 0 Carry/borrow bit BANK1:FSR 0x0084 Indirect data memory address pointer BANK1:TRISA 0x0085 PORTA Data Direction Register BANK1:TRISA.TRISA5 5 PORTA Data Direction Register bit 5 BANK1:TRISA.TRISA4 4 PORTA Data Direction Register bit 4 BANK1:TRISA.TRISA3 3 PORTA Data Direction Register bit 3 BANK1:TRISA.TRISA2 2 PORTA Data Direction Register bit 2 BANK1:TRISA.TRISA1 1 PORTA Data Direction Register bit 1 BANK1:TRISA.TRISA0 0 PORTA Data Direction Register bit 0 BANK1:TRISB 0x0086 PORTB Data Direction Register BANK1:TRISB.TRISB7 7 PORTB Data Direction Register bit 7 BANK1:TRISB.TRISB6 6 PORTB Data Direction Register bit 6 BANK1:TRISB.TRISB5 5 PORTB Data Direction Register bit 5 BANK1:TRISB.TRISB4 4 PORTB Data Direction Register bit 4 BANK1:TRISB.TRISB3 3 PORTB Data Direction Register bit 3 BANK1:TRISB.TRISB2 2 PORTB Data Direction Register bit 2 BANK1:TRISB.TRISB1 1 PORTB Data Direction Register bit 1 BANK1:TRISB.TRISB0 0 PORTB Data Direction Register bit 0 BANK1:TRISC 0x0087 PORTC Data Direction Register BANK1:TRISC.TRISC7 7 PORTC Data Direction Register bit 7 BANK1:TRISC.TRISC6 6 PORTC Data Direction Register bit 6 BANK1:TRISC.TRISC5 5 PORTC Data Direction Register bit 5 BANK1:TRISC.TRISC4 4 PORTC Data Direction Register bit 4 BANK1:TRISC.TRISC3 3 PORTC Data Direction Register bit 3 BANK1:TRISC.TRISC2 2 PORTC Data Direction Register bit 2 BANK1:TRISC.TRISC1 1 PORTC Data Direction Register bit 1 BANK1:TRISC.TRISC0 0 PORTC Data Direction Register bit 0 BANK1:RESERVED0088 0x0088 RESERVED BANK1:RESERVED0089 0x0089 RESERVED BANK1:PCLATH 0x008A Write Buffer for the upper 5 bits of the Program Counter BANK1:INTCON 0x008B INTCON REGISTER BANK1:INTCON.GIE 7 Global Interrupt Enable bit BANK1:INTCON.PEIE 6 Peripheral Interrupt Enable bit BANK1:INTCON.T0IE 5 TMR0 Overflow Interrupt Enable bit BANK1:INTCON.INTE 4 RB0/INT External Interrupt Enable bit BANK1:INTCON.RBIE 3 RB Port Change Interrupt Enable bit BANK1:INTCON.T0IF 2 TMR0 Overflow Interrupt Flag bit BANK1:INTCON.INTF 1 RB0/INT External Interrupt Flag bit BANK1:INTCON.RBIF 0 RB Port Change Interrupt Flag bit BANK1:PIE1 0x008C PIE1 REGISTER BANK1:PIE1.ADIE 6 A/D Converter Interrupt Enable bit BANK1:PIE1.RCIE 5 USART Receive Interrupt Enable bit BANK1:PIE1.TXIE 4 USART Transmit Interrupt Enable bit BANK1:PIE1.SSPIE 3 Synchronous Serial Port Interrupt Enable bit BANK1:PIE1.CCP1IE 2 CCP1 Interrupt Enable bit BANK1:PIE1.TMR2IE 1 TMR2 to PR2 Match Interrupt Enable bit BANK1:PIE1.TMR1IE 0 TMR1 Overflow Interrupt Enable bit BANK1:PIE2 0x008D PIE2 REGISTER BANK1:PIE2.EEIE 4 EEPROM Write Operation Interrupt Enable BANK1:PIE2.BCLIE 3 Bus Collision Interrupt Enable BANK1:PIE2.CCP2IE 0 CCP2 Interrupt Enable bit BANK1:PCON 0x008E PCON REGISTER BANK1:PCON.POR 1 Power-on Reset Status bit BANK1:PCON.BOR 0 Brown-out Reset Status bit BANK1:RESERVED008F 0x008F RESERVED BANK1:RESERVED0090 0x0090 RESERVED BANK1:SSPCON2 0x0091 SYNC SERIAL PORT CONTROL REGISTER2 BANK1:SSPCON2.GCEN 7 General Call Enable bit (In I2C Slave mode only) BANK1:SSPCON2.ACKSTAT 6 Acknowledge Status bit (In I2C Master mode only) BANK1:SSPCON2.ACKDT 5 Acknowledge Data bit (In I2C Master mode only) BANK1:SSPCON2.ACKEN 4 Acknowledge Sequence Enable bit (In I2C Master mode only) BANK1:SSPCON2.RCEN 3 Receive Enable bit (In I2C Master mode only) BANK1:SSPCON2.PEN 2 STOP Condition Enable bit (In I2C Master mode only) BANK1:SSPCON2.RSEN 1 Repeated START Condition Enabled bit (In I2C Master mode only) BANK1:SSPCON2.SEN 0 START Condition Enabled bit (In I2C Master mode only) BANK1:PR2 0x0092 Timer2 Period Register BANK1:SSPADD 0x0093 Synchronous Serial Port (I2C mode) Address Register BANK1:SSPSTAT 0x0094 SYNC SERIAL PORT STATUS REGISTER BANK1:SSPSTAT.SMP 7 Sample bit BANK1:SSPSTAT.CKE 6 SPI Clock Edge Select bit BANK1:SSPSTAT.D_A 5 Data/Address bit (I2C mode only) BANK1:SSPSTAT.P 4 STOP bit (I2C mode only) BANK1:SSPSTAT.S 3 START bit (I2C mode only) BANK1:SSPSTAT.R_W 2 Read/Write bit information (I2C mode only) BANK1:SSPSTAT.UA 1 Update Address bit (10-bit I2C mode only) BANK1:SSPSTAT.BF 0 Buffer Full Status bit BANK1:RESERVED0095 0x0095 RESERVED BANK1:RESERVED0096 0x0096 RESERVED BANK1:RESERVED0097 0x0097 RESERVED BANK1:TXSTA 0x0098 TRANSMIT STATUS AND CONTROL REGISTER BANK1:TXSTA.CSRC 7 Clock Source Select bit BANK1:TXSTA.TX9 6 9-bit Transmit Enable bit BANK1:TXSTA.TXEN 5 Transmit Enable bit BANK1:TXSTA.SYNC 4 USART Mode Select bit BANK1:TXSTA.BRGH 2 High Baud Rate Select bit BANK1:TXSTA.TRMT 1 Transmit Shift Register Status bit BANK1:TXSTA.TX9D 0 9th bit of Transmit Data, can be parity bit BANK1:SPBRG 0x0099 Baud Rate Generator Register BANK1:RESERVED009A 0x009A RESERVED BANK1:RESERVED009B 0x009B RESERVED BANK1:RESERVED009C 0x009C RESERVED BANK1:RESERVED009D 0x009D RESERVED BANK1:ADRESL 0x009E A/D Result Register Low Byte BANK1:ADCON1 0x009F ADCON1 REGISTER BANK1:ADCON1.ADFM 7 A/D Result format select BANK1:ADCON1.PCFG3 3 A/D Port Configuration Control bit 3 BANK1:ADCON1.PCFG2 2 A/D Port Configuration Control bit 2 BANK1:ADCON1.PCFG1 1 A/D Port Configuration Control bit 1 BANK1:ADCON1.PCFG0 0 A/D Port Configuration Control bit 0 ; BANK2 (0x0100:0x0180) BANK2:INDF 0x0100 INDF (not a physical register) BANK2:TMR0 0x0101 Timer0 module's register BANK2:PCL 0x0102 Program Counter's (PC) Least Significant Byte BANK2:STATUS 0x0103 STATUS REGISTER BANK2:STATUS.IRP 7 RegIster Bank Select bit BANK2:STATUS.RP1 6 Register Bank Select bit 1 BANK2:STATUS.RP0 5 Register Bank Select bit 0 BANK2:STATUS.TO 4 Time-out bit BANK2:STATUS.PD 3 Power-down bit BANK2:STATUS.Z 2 Zero bit BANK2:STATUS.DC 1 Digit carry/borrow bit BANK2:STATUS.C 0 Carry/borrow bit BANK2:FSR 0x0104 Indirect data memory address pointer BANK2:RESERVED0105 0x0105 RESERVED BANK2:PORTB 0x0106 PORTB register BANK2:PORTB.RB7 7 PORTB bit 7 BANK2:PORTB.RB6 6 PORTB bit 6 BANK2:PORTB.RB5 5 PORTB bit 5 BANK2:PORTB.RB4 4 PORTB bit 4 BANK2:PORTB.RB3 3 PORTB bit 3 BANK2:PORTB.RB2 2 PORTB bit 2 BANK2:PORTB.RB1 1 PORTB bit 1 BANK2:PORTB.RB0 0 PORTB bit 0 BANK2:RESERVED0107 0x0107 RESERVED BANK2:RESERVED0108 0x0108 RESERVED BANK2:RESERVED0109 0x0109 RESERVED BANK2:PCLATH 0x010A Write Buffer for the upper 5 bits of the Program Counter BANK2:INTCON 0x010B INTCON REGISTER BANK2:INTCON.GIE 7 Global Interrupt Enable bit BANK2:INTCON.PEIE 6 Peripheral Interrupt Enable bit BANK2:INTCON.T0IE 5 TMR0 Overflow Interrupt Enable bit BANK2:INTCON.INTE 4 RB0/INT External Interrupt Enable bit BANK2:INTCON.RBIE 3 RB Port Change Interrupt Enable bit BANK2:INTCON.T0IF 2 TMR0 Overflow Interrupt Flag bit BANK2:INTCON.INTF 1 RB0/INT External Interrupt Flag bit BANK2:INTCON.RBIF 0 RB Port Change Interrupt Flag bit BANK2:EEDATA 0x010C EEPROM data register Low Byte BANK2:EEADR 0x010D EEPROM address register Low Byte BANK2:EEDATH 0x010E EEPROM data register high byte BANK2:EEADRH 0x010F EEPROM address register high byte ; BANK3 (0x0180:0x0200) BANK3:INDF 0x0180 INDF (not a physical register) BANK3:OPTION 0x0181 OPTION REGISTER BANK3:OPTION.RBPU 7 PORTB Pull-up Enable bit BANK3:OPTION.INTEDG 6 Interrupt Edge Select bit BANK3:OPTION.T0CS 5 TMR0 Clock Source Select bit BANK3:OPTION.T0SE 4 TMR0 Source Edge Select bit BANK3:OPTION.PSA 3 Prescaler Assignment bit BANK3:OPTION.PS2 2 Prescaler Rate Select bit 2 BANK3:OPTION.PS1 1 Prescaler Rate Select bit 1 BANK3:OPTION.PS0 0 Prescaler Rate Select bit 0 BANK3:PCL 0x0182 Program Counter's (PC) Least Significant Byte BANK3:STATUS 0x0183 STATUS REGISTER BANK3:STATUS.IRP 7 RegIster Bank Select bit BANK3:STATUS.RP1 6 Register Bank Select bit 1 BANK3:STATUS.RP0 5 Register Bank Select bit 0 BANK3:STATUS.TO 4 Time-out bit BANK3:STATUS.PD 3 Power-down bit BANK3:STATUS.Z 2 Zero bit BANK3:STATUS.DC 1 Digit carry/borrow bit BANK3:STATUS.C 0 Carry/borrow bit BANK3:FSR 0x0184 Indirect data memory address pointer BANK3:RESERVED0185 0x0185 RESERVED BANK3:TRISB 0x0186 PORTB Data Direction Register BANK3:TRISB.TRISB7 7 PORTB Data Direction Register bit 7 BANK3:TRISB.TRISB6 6 PORTB Data Direction Register bit 6 BANK3:TRISB.TRISB5 5 PORTB Data Direction Register bit 5 BANK3:TRISB.TRISB4 4 PORTB Data Direction Register bit 4 BANK3:TRISB.TRISB3 3 PORTB Data Direction Register bit 3 BANK3:TRISB.TRISB2 2 PORTB Data Direction Register bit 2 BANK3:TRISB.TRISB1 1 PORTB Data Direction Register bit 1 BANK3:TRISB.TRISB0 0 PORTB Data Direction Register bit 0 BANK3:RESERVED0187 0x0187 RESERVED BANK3:RESERVED0188 0x0188 RESERVED BANK3:RESERVED0189 0x0189 RESERVED BANK3:PCLATH 0x018A Write Buffer for the upper 5 bits of the Program Counter BANK3:INTCON 0x018B INTCON REGISTER BANK3:INTCON.GIE 7 Global Interrupt Enable bit BANK3:INTCON.PEIE 6 Peripheral Interrupt Enable bit BANK3:INTCON.T0IE 5 TMR0 Overflow Interrupt Enable bit BANK3:INTCON.INTE 4 RB0/INT External Interrupt Enable bit BANK3:INTCON.RBIE 3 RB Port Change Interrupt Enable bit BANK3:INTCON.T0IF 2 TMR0 Overflow Interrupt Flag bit BANK3:INTCON.INTF 1 RB0/INT External Interrupt Flag bit BANK3:INTCON.RBIF 0 RB Port Change Interrupt Flag bit BANK3:EECON1 0x018C EECON1 REGISTER BANK3:EECON1.EEPGD 7 Program/Data EEPROM Select bit BANK3:EECON1.WRERR 3 EEPROM Error Flag bit BANK3:EECON1.WREN 2 EEPROM Write Enable bit BANK3:EECON1.WR 1 Write Control bit BANK3:EECON1.RD 0 Read Control bit BANK3:EECON2 0x018D EEPROM control register2 (not a physical register) BANK3:RESERVED018E 0x018E RESERVED BANK3:RESERVED018F 0x018F RESERVED .16F874 ; http://www.microchip.com/download/lit/pline/picmicro/families/16f87x/30292c.pdf ; PIC16F873_4_6_7.pdf ; MEMORY MAP ; BANK_0 area DATA FSR_ 0x0000:0x0020 area DATA Gen_Purp 0x0020:0x0080 General Purpose Register area DATA MEM_Program0 0x0080:0x0800 On-chip Program Memory (Page 0) area DATA MEM_Program1 0x0800:0x1000 On-chip Program Memory (Page 1) ; BANK_1 ; area DATA FSR_ 0x0080:0x00A0 ; area DATA Gen_Purp 0x00A0:0x0100 General Purpose Register ; area DATA MEM_Program0 0x0100:0x0800 On-chip Program Memory (Page 0) ; area DATA MEM_Program1 0x0800:0x1000 On-chip Program Memory (Page 1) ; BANK_2 ; area DATA FSR_ 0x0100:0x0110 ; area BSS RESERVED 0x0110:0x0120 ; area DATA Gen_Purp_BANK0 0x0120:0x0180 accesses 20h-7Fh ; area DATA MEM_Program0 0x0180:0x0800 On-chip Program Memory (Page 0) ; area DATA MEM_Program1 0x0800:0x1000 On-chip Program Memory (Page 1) ; BANK_3 ; area DATA FSR_ 0x0180:0x0190 ; area BSS RESERVED 0x0190:0x01A0 ; area DATA Gen_Purp_BANK1 0x01A0:0x0200 accesses A0h-FFh ; area DATA MEM_Program0 0x0200:0x0800 On-chip Program Memory (Page 0) ; area DATA MEM_Program1 0x0800:0x1000 On-chip Program Memory (Page 1) ; Interrupt and reset vector assignments interrupt RESET 0x0000 RESET ; INPUT/OUTPUT PORTS ; BANK0 (0x0000:0x0080) BANK0:INDF 0x0000 INDF (not a physical register) BANK0:TMR0 0x0001 Timer0 module's register BANK0:PCL 0x0002 Program Counter (PC) Least Significant Byte BANK0:STATUS 0x0003 STATUS REGISTER BANK0:STATUS.IRP 7 RegIster Bank Select bit BANK0:STATUS.RP1 6 Register Bank Select bit 1 BANK0:STATUS.RP0 5 Register Bank Select bit 0 BANK0:STATUS.TO 4 Time-out bit BANK0:STATUS.PD 3 Power-down bit BANK0:STATUS.Z 2 Zero bit BANK0:STATUS.DC 1 Digit carry/borrow bit BANK0:STATUS.C 0 Carry/borrow bit BANK0:FSR 0x0004 Indirect data memory address pointer BANK0:PORTA 0x0005 PORTA register BANK0:PORTA.RA5 5 PORTA bit 5 BANK0:PORTA.RA4 4 PORTA bit 4 BANK0:PORTA.RA3 3 PORTA bit 3 BANK0:PORTA.RA2 2 PORTA bit 2 BANK0:PORTA.RA1 1 PORTA bit 1 BANK0:PORTA.RA0 0 PORTA bit 0 BANK0:PORTB 0x0006 PORTB register BANK0:PORTB.RB7 7 PORTB bit 7 BANK0:PORTB.RB6 6 PORTB bit 6 BANK0:PORTB.RB5 5 PORTB bit 5 BANK0:PORTB.RB4 4 PORTB bit 4 BANK0:PORTB.RB3 3 PORTB bit 3 BANK0:PORTB.RB2 2 PORTB bit 2 BANK0:PORTB.RB1 1 PORTB bit 1 BANK0:PORTB.RB0 0 PORTB bit 0 BANK0:PORTC 0x0007 PORTC register BANK0:PORTC.RC7 7 PORTC bit 7 BANK0:PORTC.RC6 6 PORTC bit 6 BANK0:PORTC.RC5 5 PORTC bit 5 BANK0:PORTC.RC4 4 PORTC bit 4 BANK0:PORTC.RC3 3 PORTC bit 3 BANK0:PORTC.RC2 2 PORTC bit 2 BANK0:PORTC.RC1 1 PORTC bit 1 BANK0:PORTC.RC0 0 PORTC bit 0 BANK0:PORTD 0x0008 PORTD register BANK0:PORTD.RD7 7 PORTD bit 7 BANK0:PORTD.RD6 6 PORTD bit 6 BANK0:PORTD.RD5 5 PORTD bit 5 BANK0:PORTD.RD4 4 PORTD bit 4 BANK0:PORTD.RD3 3 PORTD bit 3 BANK0:PORTD.RD2 2 PORTD bit 2 BANK0:PORTD.RD1 1 PORTD bit 1 BANK0:PORTD.RD0 0 PORTD bit 0 BANK0:PORTE 0x0009 PORTE register BANK0:PORTE.RE2 2 PORTE bit 2 BANK0:PORTE.RE1 1 PORTE bit 1 BANK0:PORTE.RE0 0 PORTE bit 0 BANK0:PCLATH 0x000A Write Buffer for the upper 5 bits of the Program Counter BANK0:INTCON 0x000B INTCON REGISTER BANK0:INTCON.GIE 7 Global Interrupt Enable bit BANK0:INTCON.PEIE 6 Peripheral Interrupt Enable bit BANK0:INTCON.T0IE 5 TMR0 Overflow Interrupt Enable bit BANK0:INTCON.INTE 4 RB0/INT External Interrupt Enable bit BANK0:INTCON.RBIE 3 RB Port Change Interrupt Enable bit BANK0:INTCON.T0IF 2 TMR0 Overflow Interrupt Flag bit BANK0:INTCON.INTF 1 RB0/INT External Interrupt Flag bit BANK0:INTCON.RBIF 0 RB Port Change Interrupt Flag bit BANK0:PIR1 0x000C PIR1 REGISTER BANK0:PIR1.PSPIF 7 Parallel Slave Port Interrupt Flag bit BANK0:PIR1.ADIF 6 A/D Converter Interrupt Flag bit BANK0:PIR1.RCIF 5 USART Receive Interrupt Flag bit BANK0:PIR1.TXIF 4 USART Transmit Interrupt Flag bit BANK0:PIR1.SSPIF 3 Synchronous Serial Port Interrupt Flag bit BANK0:PIR1.CCP1IF 2 CCP1 Interrupt Flag bit BANK0:PIR1.TMR2IF 1 TMR2 to PR2 Match Interrupt Flag bit BANK0:PIR1.TMR1IF 0 TMR1 Overflow Interrupt Flag bit BANK0:PIR2 0x000D PIR2 REGISTER BANK0:PIR2.EEIF 4 EEPROM Write Operation Interrupt Flag bit BANK0:PIR2.BCLIF 3 Bus Collision Interrupt Flag bit BANK0:PIR2.CCP2IF 0 CCP2 Interrupt Flag bit BANK0:TMR1L 0x000E Holding register for the Least Significant Byte of the 16-bit TMR1 register BANK0:TMR1H 0x000F Holding register for the Most Significant Byte of the 16-bit TMR1 register BANK0:T1CON 0x0010 TIMER1 CONTROL REGISTER BANK0:T1CON.T1CKPS1 5 Timer1 Input Clock Prescale Select bit 1 BANK0:T1CON.T1CKPS0 4 Timer1 Input Clock Prescale Select bit 0 BANK0:T1CON.T1OSCEN 3 Timer1 Oscillator Enable Control bit BANK0:T1CON.T1SYNC 2 Timer1 External Clock Input Synchronization Control bit BANK0:T1CON.TMR1CS 1 Timer1 Clock Source Select bit BANK0:T1CON.TMR1ON 0 Timer1 On bit BANK0:TMR2 0x0011 Timer2 module's register BANK0:T2CON 0x0012 TIMER2 CONTROL REGISTER BANK0:T2CON.TOUTPS3 6 Timer2 Output Postscale Select bit 3 BANK0:T2CON.TOUTPS2 5 Timer2 Output Postscale Select bit 2 BANK0:T2CON.TOUTPS1 4 Timer2 Output Postscale Select bit 1 BANK0:T2CON.TOUTPS0 3 Timer2 Output Postscale Select bit 0 BANK0:T2CON.TMR2ON 2 Timer2 On bit BANK0:T2CON.T2CKPS1 1 Timer2 Clock Prescale Select bit 1 BANK0:T2CON.T2CKPS0 0 Timer2 Clock Prescale Select bit 0 BANK0:SSPBUF 0x0013 Synchronous Serial Port Receive Buffer/Transmit Register BANK0:SSPCON 0x0014 SYNC SERIAL PORT CONTROL REGISTER BANK0:SSPCON.WCOL 7 Write Collision Detect bit BANK0:SSPCON.SSPOV 6 Receive Overflow Indicator bit BANK0:SSPCON.SSPEN 5 Synchronous Serial Port Enable bit BANK0:SSPCON.CKP 4 Clock Polarity Select bit BANK0:SSPCON.SSPM3 3 Synchronous Serial Port Mode Select bit 3 BANK0:SSPCON.SSPM2 2 Synchronous Serial Port Mode Select bit 2 BANK0:SSPCON.SSPM1 1 Synchronous Serial Port Mode Select bit 1 BANK0:SSPCON.SSPM0 0 Synchronous Serial Port Mode Select bit 0 BANK0:CCPR1L 0x0015 Capture/Compare/PWM1 Register1 (LSB) BANK0:CCPR1H 0x0016 Capture/Compare/PWM1 Register1 (MSB) BANK0:CCP1CON 0x0017 CCP1CON REGISTER BANK0:CCP1CON.CCP1X 5 PWM Least Significant bit BANK0:CCP1CON.CCP1Y 4 PWM Least Significant bit BANK0:CCP1CON.CCP1M3 3 CCP1 Mode Select bit 3 BANK0:CCP1CON.CCP1M2 2 CCP1 Mode Select bit 2 BANK0:CCP1CON.CCP1M1 1 CCP1 Mode Select bit 1 BANK0:CCP1CON.CCP1M0 0 CCP1 Mode Select bit 0 BANK0:RCSTA 0x0018 RECEIVE STATUS AND CONTROL REGISTER BANK0:RCSTA.SPEN 7 Serial Port Enable bit BANK0:RCSTA.RX9 6 9-bit Receive Enable bit BANK0:RCSTA.SREN 5 Single Receive Enable bit BANK0:RCSTA.CREN 4 Continuous Receive Enable bit BANK0:RCSTA.ADDEN 3 Address Detect Enable bit BANK0:RCSTA.FERR 2 Framing Error bit BANK0:RCSTA.OERR 1 Overrun Error bit BANK0:RCSTA.RX9D 0 9th bit of received data BANK0:TXREG 0x0019 USART Transmit Data Register BANK0:RCREG 0x001A USART Receive Data Register BANK0:CCPR2L 0x001B Capture/Compare/PWM2 Register2 (LSB) BANK0:CCPR2H 0x001C Capture/Compare/PWM2 Register2 (MSB) BANK0:CCP2CON 0x001D CCP2CON REGISTER BANK0:CCP2CON.CCP2X 5 PWM Least Significant bit BANK0:CCP2CON.CCP2Y 4 PWM Least Significant bit BANK0:CCP2CON.CCP2M3 3 CCP2 Mode Select bit 3 BANK0:CCP2CON.CCP2M2 2 CCP2 Mode Select bit 2 BANK0:CCP2CON.CCP2M1 1 CCP2 Mode Select bit 1 BANK0:CCP2CON.CCP2M0 0 CCP2 Mode Select bit 0 BANK0:ADRESH 0x001E A/D Result Register High Byte BANK0:ADCON0 0x001F ADCON0 REGISTER BANK0:ADCON0.ADCS1 7 A/D Conversion Clock Select bit 1 BANK0:ADCON0.ADCS0 6 A/D Conversion Clock Select bit 0 BANK0:ADCON0.CHS2 5 Analog Channel Select bit 2 BANK0:ADCON0.CHS1 4 Analog Channel Select bit 1 BANK0:ADCON0.CHS0 3 Analog Channel Select bit 0 BANK0:ADCON0.GO_DONE 2 A/D Conversion Status bit BANK0:ADCON0.ADON 0 A/D On bit ; BANK1 (0x0080:0x0100) BANK1:INDF 0x0080 INDF (not a physical register) BANK1:OPTION 0x0081 OPTION REGISTER BANK1:OPTION.RBPU 7 PORTB Pull-up Enable bit BANK1:OPTION.INTEDG 6 Interrupt Edge Select bit BANK1:OPTION.T0CS 5 TMR0 Clock Source Select bit BANK1:OPTION.T0SE 4 TMR0 Source Edge Select bit BANK1:OPTION.PSA 3 Prescaler Assignment bit BANK1:OPTION.PS2 2 Prescaler Rate Select bit 2 BANK1:OPTION.PS1 1 Prescaler Rate Select bit 1 BANK1:OPTION.PS0 0 Prescaler Rate Select bit 0 BANK1:PCL 0x0082 Program Counter's (PC) Least Significant Byte BANK1:STATUS 0x0083 STATUS REGISTER BANK1:STATUS.IRP 7 RegIster Bank Select bit BANK1:STATUS.RP1 6 Register Bank Select bit 1 BANK1:STATUS.RP0 5 Register Bank Select bit 0 BANK1:STATUS.TO 4 Time-out bit BANK1:STATUS.PD 3 Power-down bit BANK1:STATUS.Z 2 Zero bit BANK1:STATUS.DC 1 Digit carry/borrow bit BANK1:STATUS.C 0 Carry/borrow bit BANK1:FSR 0x0084 Indirect data memory address pointer BANK1:TRISA 0x0085 PORTA Data Direction Register BANK1:TRISA.TRISA5 5 PORTA Data Direction Register bit 5 BANK1:TRISA.TRISA4 4 PORTA Data Direction Register bit 4 BANK1:TRISA.TRISA3 3 PORTA Data Direction Register bit 3 BANK1:TRISA.TRISA2 2 PORTA Data Direction Register bit 2 BANK1:TRISA.TRISA1 1 PORTA Data Direction Register bit 1 BANK1:TRISA.TRISA0 0 PORTA Data Direction Register bit 0 BANK1:TRISB 0x0086 PORTB Data Direction Register BANK1:TRISB.TRISB7 7 PORTB Data Direction Register bit 7 BANK1:TRISB.TRISB6 6 PORTB Data Direction Register bit 6 BANK1:TRISB.TRISB5 5 PORTB Data Direction Register bit 5 BANK1:TRISB.TRISB4 4 PORTB Data Direction Register bit 4 BANK1:TRISB.TRISB3 3 PORTB Data Direction Register bit 3 BANK1:TRISB.TRISB2 2 PORTB Data Direction Register bit 2 BANK1:TRISB.TRISB1 1 PORTB Data Direction Register bit 1 BANK1:TRISB.TRISB0 0 PORTB Data Direction Register bit 0 BANK1:TRISC 0x0087 PORTC Data Direction Register BANK1:TRISC.TRISC7 7 PORTC Data Direction Register bit 7 BANK1:TRISC.TRISC6 6 PORTC Data Direction Register bit 6 BANK1:TRISC.TRISC5 5 PORTC Data Direction Register bit 5 BANK1:TRISC.TRISC4 4 PORTC Data Direction Register bit 4 BANK1:TRISC.TRISC3 3 PORTC Data Direction Register bit 3 BANK1:TRISC.TRISC2 2 PORTC Data Direction Register bit 2 BANK1:TRISC.TRISC1 1 PORTC Data Direction Register bit 1 BANK1:TRISC.TRISC0 0 PORTC Data Direction Register bit 0 BANK1:TRISD 0x0088 PORTD Data Direction Register BANK1:TRISD.TRISD7 7 PORTD Data Direction Register bit 7 BANK1:TRISD.TRISD6 6 PORTD Data Direction Register bit 6 BANK1:TRISD.TRISD5 5 PORTD Data Direction Register bit 5 BANK1:TRISD.TRISD4 4 PORTD Data Direction Register bit 4 BANK1:TRISD.TRISD3 3 PORTD Data Direction Register bit 3 BANK1:TRISD.TRISD2 2 PORTD Data Direction Register bit 2 BANK1:TRISD.TRISD1 1 PORTD Data Direction Register bit 1 BANK1:TRISD.TRISD0 0 PORTD Data Direction Register bit 0 BANK1:TRISE 0x0089 PORTE Data Direction Bits BANK1:TRISE.IBF 7 Input Buffer Full Status bit BANK1:TRISE.OBF 6 Output Buffer Full Status bit BANK1:TRISE.IBOV 5 Input Buffer Overflow Detect bit BANK1:TRISE.PSPMODE 4 Parallel Slave Port Mode Select bit BANK1:TRISE.TRISE2 2 Direction Control bit for pin RE2/CS BANK1:TRISE.TRISE1 1 Direction Control bit for pin RE1/WR BANK1:TRISE.TRISE0 0 Direction Control bit for pin RE0/RD BANK1:PCLATH 0x008A Write Buffer for the upper 5 bits of the Program Counter BANK1:INTCON 0x008B INTCON REGISTER BANK1:INTCON.GIE 7 Global Interrupt Enable bit BANK1:INTCON.PEIE 6 Peripheral Interrupt Enable bit BANK1:INTCON.T0IE 5 TMR0 Overflow Interrupt Enable bit BANK1:INTCON.INTE 4 RB0/INT External Interrupt Enable bit BANK1:INTCON.RBIE 3 RB Port Change Interrupt Enable bit BANK1:INTCON.T0IF 2 TMR0 Overflow Interrupt Flag bit BANK1:INTCON.INTF 1 RB0/INT External Interrupt Flag bit BANK1:INTCON.RBIF 0 RB Port Change Interrupt Flag bit BANK1:PIE1 0x008C PIE1 REGISTER BANK1:PIE1.PSPIE 7 Parallel Slave Port Read/Write Interrupt Enable bit BANK1:PIE1.ADIE 6 A/D Converter Interrupt Enable bit BANK1:PIE1.RCIE 5 USART Receive Interrupt Enable bit BANK1:PIE1.TXIE 4 USART Transmit Interrupt Enable bit BANK1:PIE1.SSPIE 3 Synchronous Serial Port Interrupt Enable bit BANK1:PIE1.CCP1IE 2 CCP1 Interrupt Enable bit BANK1:PIE1.TMR2IE 1 TMR2 to PR2 Match Interrupt Enable bit BANK1:PIE1.TMR1IE 0 TMR1 Overflow Interrupt Enable bit BANK1:PIE2 0x008D PIE2 REGISTER BANK1:PIE2.EEIE 4 EEPROM Write Operation Interrupt Enable BANK1:PIE2.BCLIE 3 Bus Collision Interrupt Enable BANK1:PIE2.CCP2IE 0 CCP2 Interrupt Enable bit BANK1:PCON 0x008E PCON REGISTER BANK1:PCON.POR 1 Power-on Reset Status bit BANK1:PCON.BOR 0 Brown-out Reset Status bit BANK1:RESERVED008F 0x008F RESERVED BANK1:RESERVED0090 0x0090 RESERVED BANK1:SSPCON2 0x0091 SYNC SERIAL PORT CONTROL REGISTER2 BANK1:SSPCON2.GCEN 7 General Call Enable bit (In I2C Slave mode only) BANK1:SSPCON2.ACKSTAT 6 Acknowledge Status bit (In I2C Master mode only) BANK1:SSPCON2.ACKDT 5 Acknowledge Data bit (In I2C Master mode only) BANK1:SSPCON2.ACKEN 4 Acknowledge Sequence Enable bit (In I2C Master mode only) BANK1:SSPCON2.RCEN 3 Receive Enable bit (In I2C Master mode only) BANK1:SSPCON2.PEN 2 STOP Condition Enable bit (In I2C Master mode only) BANK1:SSPCON2.RSEN 1 Repeated START Condition Enabled bit (In I2C Master mode only) BANK1:SSPCON2.SEN 0 START Condition Enabled bit (In I2C Master mode only) BANK1:PR2 0x0092 Timer2 Period Register BANK1:SSPADD 0x0093 Synchronous Serial Port (I2C mode) Address Register BANK1:SSPSTAT 0x0094 SYNC SERIAL PORT STATUS REGISTER BANK1:SSPSTAT.SMP 7 Sample bit BANK1:SSPSTAT.CKE 6 SPI Clock Edge Select bit BANK1:SSPSTAT.D_A 5 Data/Address bit (I2C mode only) BANK1:SSPSTAT.P 4 STOP bit (I2C mode only) BANK1:SSPSTAT.S 3 START bit (I2C mode only) BANK1:SSPSTAT.R_W 2 Read/Write bit information (I2C mode only) BANK1:SSPSTAT.UA 1 Update Address bit (10-bit I2C mode only) BANK1:SSPSTAT.BF 0 Buffer Full Status bit BANK1:RESERVED0095 0x0095 RESERVED BANK1:RESERVED0096 0x0096 RESERVED BANK1:RESERVED0097 0x0097 RESERVED BANK1:TXSTA 0x0098 TRANSMIT STATUS AND CONTROL REGISTER BANK1:TXSTA.CSRC 7 Clock Source Select bit BANK1:TXSTA.TX9 6 9-bit Transmit Enable bit BANK1:TXSTA.TXEN 5 Transmit Enable bit BANK1:TXSTA.SYNC 4 USART Mode Select bit BANK1:TXSTA.BRGH 2 High Baud Rate Select bit BANK1:TXSTA.TRMT 1 Transmit Shift Register Status bit BANK1:TXSTA.TX9D 0 9th bit of Transmit Data, can be parity bit BANK1:SPBRG 0x0099 Baud Rate Generator Register BANK1:RESERVED009A 0x009A RESERVED BANK1:RESERVED009B 0x009B RESERVED BANK1:RESERVED009C 0x009C RESERVED BANK1:RESERVED009D 0x009D RESERVED BANK1:ADRESL 0x009E A/D Result Register Low Byte BANK1:ADCON1 0x009F ADCON1 REGISTER BANK1:ADCON1.ADFM 7 A/D Result format select BANK1:ADCON1.PCFG3 3 A/D Port Configuration Control bit 3 BANK1:ADCON1.PCFG2 2 A/D Port Configuration Control bit 2 BANK1:ADCON1.PCFG1 1 A/D Port Configuration Control bit 1 BANK1:ADCON1.PCFG0 0 A/D Port Configuration Control bit 0 ; BANK2 (0x0100:0x0180) BANK2:INDF 0x0100 INDF (not a physical register) BANK2:TMR0 0x0101 Timer0 module's register BANK2:PCL 0x0102 Program Counter's (PC) Least Significant Byte BANK2:STATUS 0x0103 STATUS REGISTER BANK2:STATUS.IRP 7 RegIster Bank Select bit BANK2:STATUS.RP1 6 Register Bank Select bit 1 BANK2:STATUS.RP0 5 Register Bank Select bit 0 BANK2:STATUS.TO 4 Time-out bit BANK2:STATUS.PD 3 Power-down bit BANK2:STATUS.Z 2 Zero bit BANK2:STATUS.DC 1 Digit carry/borrow bit BANK2:STATUS.C 0 Carry/borrow bit BANK2:FSR 0x0104 Indirect data memory address pointer BANK2:RESERVED0105 0x0105 RESERVED BANK2:PORTB 0x0106 PORTB register BANK2:PORTB.RB7 7 PORTB bit 7 BANK2:PORTB.RB6 6 PORTB bit 6 BANK2:PORTB.RB5 5 PORTB bit 5 BANK2:PORTB.RB4 4 PORTB bit 4 BANK2:PORTB.RB3 3 PORTB bit 3 BANK2:PORTB.RB2 2 PORTB bit 2 BANK2:PORTB.RB1 1 PORTB bit 1 BANK2:PORTB.RB0 0 PORTB bit 0 BANK2:RESERVED0107 0x0107 RESERVED BANK2:RESERVED0108 0x0108 RESERVED BANK2:RESERVED0109 0x0109 RESERVED BANK2:PCLATH 0x010A Write Buffer for the upper 5 bits of the Program Counter BANK2:INTCON 0x010B INTCON REGISTER BANK2:INTCON.GIE 7 Global Interrupt Enable bit BANK2:INTCON.PEIE 6 Peripheral Interrupt Enable bit BANK2:INTCON.T0IE 5 TMR0 Overflow Interrupt Enable bit BANK2:INTCON.INTE 4 RB0/INT External Interrupt Enable bit BANK2:INTCON.RBIE 3 RB Port Change Interrupt Enable bit BANK2:INTCON.T0IF 2 TMR0 Overflow Interrupt Flag bit BANK2:INTCON.INTF 1 RB0/INT External Interrupt Flag bit BANK2:INTCON.RBIF 0 RB Port Change Interrupt Flag bit BANK2:EEDATA 0x010C EEPROM data register Low Byte BANK2:EEADR 0x010D EEPROM address register Low Byte BANK2:EEDATH 0x010E EEPROM data register high byte BANK2:EEADRH 0x010F EEPROM address register high byte ; BANK3 (0x0180:0x0200) BANK3:INDF 0x0180 INDF (not a physical register) BANK3:OPTION 0x0181 OPTION REGISTER BANK3:OPTION.RBPU 7 PORTB Pull-up Enable bit BANK3:OPTION.INTEDG 6 Interrupt Edge Select bit BANK3:OPTION.T0CS 5 TMR0 Clock Source Select bit BANK3:OPTION.T0SE 4 TMR0 Source Edge Select bit BANK3:OPTION.PSA 3 Prescaler Assignment bit BANK3:OPTION.PS2 2 Prescaler Rate Select bit 2 BANK3:OPTION.PS1 1 Prescaler Rate Select bit 1 BANK3:OPTION.PS0 0 Prescaler Rate Select bit 0 BANK3:PCL 0x0182 Program Counter's (PC) Least Significant Byte BANK3:STATUS 0x0183 STATUS REGISTER BANK3:STATUS.IRP 7 RegIster Bank Select bit BANK3:STATUS.RP1 6 Register Bank Select bit 1 BANK3:STATUS.RP0 5 Register Bank Select bit 0 BANK3:STATUS.TO 4 Time-out bit BANK3:STATUS.PD 3 Power-down bit BANK3:STATUS.Z 2 Zero bit BANK3:STATUS.DC 1 Digit carry/borrow bit BANK3:STATUS.C 0 Carry/borrow bit BANK3:FSR 0x0184 Indirect data memory address pointer BANK3:RESERVED0185 0x0185 RESERVED BANK3:TRISB 0x0186 PORTB Data Direction Register BANK3:TRISB.TRISB7 7 PORTB Data Direction Register bit 7 BANK3:TRISB.TRISB6 6 PORTB Data Direction Register bit 6 BANK3:TRISB.TRISB5 5 PORTB Data Direction Register bit 5 BANK3:TRISB.TRISB4 4 PORTB Data Direction Register bit 4 BANK3:TRISB.TRISB3 3 PORTB Data Direction Register bit 3 BANK3:TRISB.TRISB2 2 PORTB Data Direction Register bit 2 BANK3:TRISB.TRISB1 1 PORTB Data Direction Register bit 1 BANK3:TRISB.TRISB0 0 PORTB Data Direction Register bit 0 BANK3:RESERVED0187 0x0187 RESERVED BANK3:RESERVED0188 0x0188 RESERVED BANK3:RESERVED0189 0x0189 RESERVED BANK3:PCLATH 0x018A Write Buffer for the upper 5 bits of the Program Counter BANK3:INTCON 0x018B INTCON REGISTER BANK3:INTCON.GIE 7 Global Interrupt Enable bit BANK3:INTCON.PEIE 6 Peripheral Interrupt Enable bit BANK3:INTCON.T0IE 5 TMR0 Overflow Interrupt Enable bit BANK3:INTCON.INTE 4 RB0/INT External Interrupt Enable bit BANK3:INTCON.RBIE 3 RB Port Change Interrupt Enable bit BANK3:INTCON.T0IF 2 TMR0 Overflow Interrupt Flag bit BANK3:INTCON.INTF 1 RB0/INT External Interrupt Flag bit BANK3:INTCON.RBIF 0 RB Port Change Interrupt Flag bit BANK3:EECON1 0x018C EECON1 REGISTER BANK3:EECON1.EEPGD 7 Program/Data EEPROM Select bit BANK3:EECON1.WRERR 3 EEPROM Error Flag bit BANK3:EECON1.WREN 2 EEPROM Write Enable bit BANK3:EECON1.WR 1 Write Control bit BANK3:EECON1.RD 0 Read Control bit BANK3:EECON2 0x018D EEPROM control register2 (not a physical register) BANK3:RESERVED018E 0x018E RESERVED BANK3:RESERVED018F 0x018F RESERVED .16F876 ; http://www.microchip.com/download/lit/pline/picmicro/families/16f87x/30292c.pdf ; PIC16F873_4_6_7.pdf ; MEMORY MAP ; BANK_0 area DATA FSR_ 0x0000:0x0020 area DATA Gen_Purp 0x0020:0x0080 General Purpose Register area DATA MEM_Program0 0x0080:0x0800 On-chip Program Memory (Page 0) area DATA MEM_Program1 0x0800:0x1000 On-chip Program Memory (Page 1) area DATA MEM_Program2 0x1000:0x1800 On-chip Program Memory (Page 2) area DATA MEM_Program3 0x1800:0x2000 On-chip Program Memory (Page 3) ; BANK_1 ; area DATA FSR_ 0x0080:0x00A0 ; area DATA Gen_Purp 0x00A0:0x00F0 General Purpose Register ; area DATA Gen_Purp_BANK0 0x00F0:0x0100 accesses 70h-7Fh ; area DATA MEM_Program0 0x0100:0x0800 On-chip Program Memory (Page 0) ; area DATA MEM_Program1 0x0800:0x1000 On-chip Program Memory (Page 1) ; area DATA MEM_Program2 0x1000:0x1800 On-chip Program Memory (Page 2) ; area DATA MEM_Program3 0x1800:0x2000 On-chip Program Memory (Page 3) ; BANK_2 ; area DATA FSR_ 0x0100:0x0110 ; area DATA Gen_Purp0 0x0110:0x0120 General Purpose Register 16 Bytes ; area DATA Gen_Purp1 0x0120:0x0170 General Purpose Register 80 Bytes ; area DATA Gen_Purp_BANK0 0x0170:0x0180 accesses 70h-7Fh ; area DATA MEM_Program0 0x0180:0x0800 On-chip Program Memory (Page 0) ; area DATA MEM_Program1 0x0800:0x1000 On-chip Program Memory (Page 1) ; area DATA MEM_Program2 0x1000:0x1800 On-chip Program Memory (Page 2) ; area DATA MEM_Program3 0x1800:0x2000 On-chip Program Memory (Page 3) ; BANK_3 ; area DATA FSR_ 0x0180:0x0190 ; area DATA Gen_Purp0 0x0190:0x01A0 General Purpose Register 16 Bytes ; area DATA Gen_Purp1 0x01A0:0x01F0 General Purpose Register 80 Bytes ; area DATA Gen_Purp_BANK0 0x01F0:0x0200 accesses 70h-7Fh ; area DATA MEM_Program0 0x0200:0x0800 On-chip Program Memory (Page 0) ; area DATA MEM_Program1 0x0800:0x1000 On-chip Program Memory (Page 1) ; area DATA MEM_Program2 0x1000:0x1800 On-chip Program Memory (Page 2) ; area DATA MEM_Program3 0x1800:0x2000 On-chip Program Memory (Page 3) ; Interrupt and reset vector assignments interrupt RESET 0x0000 RESET ; INPUT/OUTPUT PORTS ; BANK0 (0x0000:0x0080) BANK0:INDF 0x0000 INDF (not a physical register) BANK0:TMR0 0x0001 Timer0 module's register BANK0:PCL 0x0002 Program Counter (PC) Least Significant Byte BANK0:STATUS 0x0003 STATUS REGISTER BANK0:STATUS.IRP 7 RegIster Bank Select bit BANK0:STATUS.RP1 6 Register Bank Select bit 1 BANK0:STATUS.RP0 5 Register Bank Select bit 0 BANK0:STATUS.TO 4 Time-out bit BANK0:STATUS.PD 3 Power-down bit BANK0:STATUS.Z 2 Zero bit BANK0:STATUS.DC 1 Digit carry/borrow bit BANK0:STATUS.C 0 Carry/borrow bit BANK0:FSR 0x0004 Indirect data memory address pointer BANK0:PORTA 0x0005 PORTA register BANK0:PORTA.RA5 5 PORTA bit 5 BANK0:PORTA.RA4 4 PORTA bit 4 BANK0:PORTA.RA3 3 PORTA bit 3 BANK0:PORTA.RA2 2 PORTA bit 2 BANK0:PORTA.RA1 1 PORTA bit 1 BANK0:PORTA.RA0 0 PORTA bit 0 BANK0:PORTB 0x0006 PORTB register BANK0:PORTB.RB7 7 PORTB bit 7 BANK0:PORTB.RB6 6 PORTB bit 6 BANK0:PORTB.RB5 5 PORTB bit 5 BANK0:PORTB.RB4 4 PORTB bit 4 BANK0:PORTB.RB3 3 PORTB bit 3 BANK0:PORTB.RB2 2 PORTB bit 2 BANK0:PORTB.RB1 1 PORTB bit 1 BANK0:PORTB.RB0 0 PORTB bit 0 BANK0:PORTC 0x0007 PORTC register BANK0:PORTC.RC7 7 PORTC bit 7 BANK0:PORTC.RC6 6 PORTC bit 6 BANK0:PORTC.RC5 5 PORTC bit 5 BANK0:PORTC.RC4 4 PORTC bit 4 BANK0:PORTC.RC3 3 PORTC bit 3 BANK0:PORTC.RC2 2 PORTC bit 2 BANK0:PORTC.RC1 1 PORTC bit 1 BANK0:PORTC.RC0 0 PORTC bit 0 BANK0:RESERVED0008 0x0008 RESERVED BANK0:RESERVED0009 0x0009 RESERVED BANK0:PCLATH 0x000A Write Buffer for the upper 5 bits of the Program Counter BANK0:INTCON 0x000B INTCON REGISTER BANK0:INTCON.GIE 7 Global Interrupt Enable bit BANK0:INTCON.PEIE 6 Peripheral Interrupt Enable bit BANK0:INTCON.T0IE 5 TMR0 Overflow Interrupt Enable bit BANK0:INTCON.INTE 4 RB0/INT External Interrupt Enable bit BANK0:INTCON.RBIE 3 RB Port Change Interrupt Enable bit BANK0:INTCON.T0IF 2 TMR0 Overflow Interrupt Flag bit BANK0:INTCON.INTF 1 RB0/INT External Interrupt Flag bit BANK0:INTCON.RBIF 0 RB Port Change Interrupt Flag bit BANK0:PIR1 0x000C PIR1 REGISTER BANK0:PIR1.ADIF 6 A/D Converter Interrupt Flag bit BANK0:PIR1.RCIF 5 USART Receive Interrupt Flag bit BANK0:PIR1.TXIF 4 USART Transmit Interrupt Flag bit BANK0:PIR1.SSPIF 3 Synchronous Serial Port Interrupt Flag bit BANK0:PIR1.CCP1IF 2 CCP1 Interrupt Flag bit BANK0:PIR1.TMR2IF 1 TMR2 to PR2 Match Interrupt Flag bit BANK0:PIR1.TMR1IF 0 TMR1 Overflow Interrupt Flag bit BANK0:PIR2 0x000D PIR2 REGISTER BANK0:PIR2.EEIF 4 EEPROM Write Operation Interrupt Flag bit BANK0:PIR2.BCLIF 3 Bus Collision Interrupt Flag bit BANK0:PIR2.CCP2IF 0 CCP2 Interrupt Flag bit BANK0:TMR1L 0x000E Holding register for the Least Significant Byte of the 16-bit TMR1 register BANK0:TMR1H 0x000F Holding register for the Most Significant Byte of the 16-bit TMR1 register BANK0:T1CON 0x0010 TIMER1 CONTROL REGISTER BANK0:T1CON.T1CKPS1 5 Timer1 Input Clock Prescale Select bit 1 BANK0:T1CON.T1CKPS0 4 Timer1 Input Clock Prescale Select bit 0 BANK0:T1CON.T1OSCEN 3 Timer1 Oscillator Enable Control bit BANK0:T1CON.T1SYNC 2 Timer1 External Clock Input Synchronization Control bit BANK0:T1CON.TMR1CS 1 Timer1 Clock Source Select bit BANK0:T1CON.TMR1ON 0 Timer1 On bit BANK0:TMR2 0x0011 Timer2 module's register BANK0:T2CON 0x0012 TIMER2 CONTROL REGISTER BANK0:T2CON.TOUTPS3 6 Timer2 Output Postscale Select bit 3 BANK0:T2CON.TOUTPS2 5 Timer2 Output Postscale Select bit 2 BANK0:T2CON.TOUTPS1 4 Timer2 Output Postscale Select bit 1 BANK0:T2CON.TOUTPS0 3 Timer2 Output Postscale Select bit 0 BANK0:T2CON.TMR2ON 2 Timer2 On bit BANK0:T2CON.T2CKPS1 1 Timer2 Clock Prescale Select bit 1 BANK0:T2CON.T2CKPS0 0 Timer2 Clock Prescale Select bit 0 BANK0:SSPBUF 0x0013 Synchronous Serial Port Receive Buffer/Transmit Register BANK0:SSPCON 0x0014 SYNC SERIAL PORT CONTROL REGISTER BANK0:SSPCON.WCOL 7 Write Collision Detect bit BANK0:SSPCON.SSPOV 6 Receive Overflow Indicator bit BANK0:SSPCON.SSPEN 5 Synchronous Serial Port Enable bit BANK0:SSPCON.CKP 4 Clock Polarity Select bit BANK0:SSPCON.SSPM3 3 Synchronous Serial Port Mode Select bit 3 BANK0:SSPCON.SSPM2 2 Synchronous Serial Port Mode Select bit 2 BANK0:SSPCON.SSPM1 1 Synchronous Serial Port Mode Select bit 1 BANK0:SSPCON.SSPM0 0 Synchronous Serial Port Mode Select bit 0 BANK0:CCPR1L 0x0015 Capture/Compare/PWM1 Register1 (LSB) BANK0:CCPR1H 0x0016 Capture/Compare/PWM1 Register1 (MSB) BANK0:CCP1CON 0x0017 CCP1CON REGISTER BANK0:CCP1CON.CCP1X 5 PWM Least Significant bit BANK0:CCP1CON.CCP1Y 4 PWM Least Significant bit BANK0:CCP1CON.CCP1M3 3 CCP1 Mode Select bit 3 BANK0:CCP1CON.CCP1M2 2 CCP1 Mode Select bit 2 BANK0:CCP1CON.CCP1M1 1 CCP1 Mode Select bit 1 BANK0:CCP1CON.CCP1M0 0 CCP1 Mode Select bit 0 BANK0:RCSTA 0x0018 RECEIVE STATUS AND CONTROL REGISTER BANK0:RCSTA.SPEN 7 Serial Port Enable bit BANK0:RCSTA.RX9 6 9-bit Receive Enable bit BANK0:RCSTA.SREN 5 Single Receive Enable bit BANK0:RCSTA.CREN 4 Continuous Receive Enable bit BANK0:RCSTA.ADDEN 3 Address Detect Enable bit BANK0:RCSTA.FERR 2 Framing Error bit BANK0:RCSTA.OERR 1 Overrun Error bit BANK0:RCSTA.RX9D 0 9th bit of received data BANK0:TXREG 0x0019 USART Transmit Data Register BANK0:RCREG 0x001A USART Receive Data Register BANK0:CCPR2L 0x001B Capture/Compare/PWM2 Register2 (LSB) BANK0:CCPR2H 0x001C Capture/Compare/PWM2 Register2 (MSB) BANK0:CCP2CON 0x001D CCP2CON REGISTER BANK0:CCP2CON.CCP2X 5 PWM Least Significant bit BANK0:CCP2CON.CCP2Y 4 PWM Least Significant bit BANK0:CCP2CON.CCP2M3 3 CCP2 Mode Select bit 3 BANK0:CCP2CON.CCP2M2 2 CCP2 Mode Select bit 2 BANK0:CCP2CON.CCP2M1 1 CCP2 Mode Select bit 1 BANK0:CCP2CON.CCP2M0 0 CCP2 Mode Select bit 0 BANK0:ADRESH 0x001E A/D Result Register High Byte BANK0:ADCON0 0x001F ADCON0 REGISTER BANK0:ADCON0.ADCS1 7 A/D Conversion Clock Select bit 1 BANK0:ADCON0.ADCS0 6 A/D Conversion Clock Select bit 0 BANK0:ADCON0.CHS2 5 Analog Channel Select bit 2 BANK0:ADCON0.CHS1 4 Analog Channel Select bit 1 BANK0:ADCON0.CHS0 3 Analog Channel Select bit 0 BANK0:ADCON0.GO_DONE 2 A/D Conversion Status bit BANK0:ADCON0.ADON 0 A/D On bit ; BANK1 (0x0080:0x0100) BANK1:INDF 0x0080 INDF (not a physical register) BANK1:OPTION 0x0081 OPTION REGISTER BANK1:OPTION.RBPU 7 PORTB Pull-up Enable bit BANK1:OPTION.INTEDG 6 Interrupt Edge Select bit BANK1:OPTION.T0CS 5 TMR0 Clock Source Select bit BANK1:OPTION.T0SE 4 TMR0 Source Edge Select bit BANK1:OPTION.PSA 3 Prescaler Assignment bit BANK1:OPTION.PS2 2 Prescaler Rate Select bit 2 BANK1:OPTION.PS1 1 Prescaler Rate Select bit 1 BANK1:OPTION.PS0 0 Prescaler Rate Select bit 0 BANK1:PCL 0x0082 Program Counter's (PC) Least Significant Byte BANK1:STATUS 0x0083 STATUS REGISTER BANK1:STATUS.IRP 7 RegIster Bank Select bit BANK1:STATUS.RP1 6 Register Bank Select bit 1 BANK1:STATUS.RP0 5 Register Bank Select bit 0 BANK1:STATUS.TO 4 Time-out bit BANK1:STATUS.PD 3 Power-down bit BANK1:STATUS.Z 2 Zero bit BANK1:STATUS.DC 1 Digit carry/borrow bit BANK1:STATUS.C 0 Carry/borrow bit BANK1:FSR 0x0084 Indirect data memory address pointer BANK1:TRISA 0x0085 PORTA Data Direction Register BANK1:TRISA.TRISA5 5 PORTA Data Direction Register bit 5 BANK1:TRISA.TRISA4 4 PORTA Data Direction Register bit 4 BANK1:TRISA.TRISA3 3 PORTA Data Direction Register bit 3 BANK1:TRISA.TRISA2 2 PORTA Data Direction Register bit 2 BANK1:TRISA.TRISA1 1 PORTA Data Direction Register bit 1 BANK1:TRISA.TRISA0 0 PORTA Data Direction Register bit 0 BANK1:TRISB 0x0086 PORTB Data Direction Register BANK1:TRISB.TRISB7 7 PORTB Data Direction Register bit 7 BANK1:TRISB.TRISB6 6 PORTB Data Direction Register bit 6 BANK1:TRISB.TRISB5 5 PORTB Data Direction Register bit 5 BANK1:TRISB.TRISB4 4 PORTB Data Direction Register bit 4 BANK1:TRISB.TRISB3 3 PORTB Data Direction Register bit 3 BANK1:TRISB.TRISB2 2 PORTB Data Direction Register bit 2 BANK1:TRISB.TRISB1 1 PORTB Data Direction Register bit 1 BANK1:TRISB.TRISB0 0 PORTB Data Direction Register bit 0 BANK1:TRISC 0x0087 PORTC Data Direction Register BANK1:TRISC.TRISC7 7 PORTC Data Direction Register bit 7 BANK1:TRISC.TRISC6 6 PORTC Data Direction Register bit 6 BANK1:TRISC.TRISC5 5 PORTC Data Direction Register bit 5 BANK1:TRISC.TRISC4 4 PORTC Data Direction Register bit 4 BANK1:TRISC.TRISC3 3 PORTC Data Direction Register bit 3 BANK1:TRISC.TRISC2 2 PORTC Data Direction Register bit 2 BANK1:TRISC.TRISC1 1 PORTC Data Direction Register bit 1 BANK1:TRISC.TRISC0 0 PORTC Data Direction Register bit 0 BANK1:RESERVED0088 0x0088 RESERVED BANK1:RESERVED0089 0x0089 RESERVED BANK1:PCLATH 0x008A Write Buffer for the upper 5 bits of the Program Counter BANK1:INTCON 0x008B INTCON REGISTER BANK1:INTCON.GIE 7 Global Interrupt Enable bit BANK1:INTCON.PEIE 6 Peripheral Interrupt Enable bit BANK1:INTCON.T0IE 5 TMR0 Overflow Interrupt Enable bit BANK1:INTCON.INTE 4 RB0/INT External Interrupt Enable bit BANK1:INTCON.RBIE 3 RB Port Change Interrupt Enable bit BANK1:INTCON.T0IF 2 TMR0 Overflow Interrupt Flag bit BANK1:INTCON.INTF 1 RB0/INT External Interrupt Flag bit BANK1:INTCON.RBIF 0 RB Port Change Interrupt Flag bit BANK1:PIE1 0x008C PIE1 REGISTER BANK1:PIE1.ADIE 6 A/D Converter Interrupt Enable bit BANK1:PIE1.RCIE 5 USART Receive Interrupt Enable bit BANK1:PIE1.TXIE 4 USART Transmit Interrupt Enable bit BANK1:PIE1.SSPIE 3 Synchronous Serial Port Interrupt Enable bit BANK1:PIE1.CCP1IE 2 CCP1 Interrupt Enable bit BANK1:PIE1.TMR2IE 1 TMR2 to PR2 Match Interrupt Enable bit BANK1:PIE1.TMR1IE 0 TMR1 Overflow Interrupt Enable bit BANK1:PIE2 0x008D PIE2 REGISTER BANK1:PIE2.EEIE 4 EEPROM Write Operation Interrupt Enable BANK1:PIE2.BCLIE 3 Bus Collision Interrupt Enable BANK1:PIE2.CCP2IE 0 CCP2 Interrupt Enable bit BANK1:PCON 0x008E PCON REGISTER BANK1:PCON.POR 1 Power-on Reset Status bit BANK1:PCON.BOR 0 Brown-out Reset Status bit BANK1:RESERVED008F 0x008F RESERVED BANK1:RESERVED0090 0x0090 RESERVED BANK1:SSPCON2 0x0091 SYNC SERIAL PORT CONTROL REGISTER2 BANK1:SSPCON2.GCEN 7 General Call Enable bit (In I2C Slave mode only) BANK1:SSPCON2.ACKSTAT 6 Acknowledge Status bit (In I2C Master mode only) BANK1:SSPCON2.ACKDT 5 Acknowledge Data bit (In I2C Master mode only) BANK1:SSPCON2.ACKEN 4 Acknowledge Sequence Enable bit (In I2C Master mode only) BANK1:SSPCON2.RCEN 3 Receive Enable bit (In I2C Master mode only) BANK1:SSPCON2.PEN 2 STOP Condition Enable bit (In I2C Master mode only) BANK1:SSPCON2.RSEN 1 Repeated START Condition Enabled bit (In I2C Master mode only) BANK1:SSPCON2.SEN 0 START Condition Enabled bit (In I2C Master mode only) BANK1:PR2 0x0092 Timer2 Period Register BANK1:SSPADD 0x0093 Synchronous Serial Port (I2C mode) Address Register BANK1:SSPSTAT 0x0094 SYNC SERIAL PORT STATUS REGISTER BANK1:SSPSTAT.SMP 7 Sample bit BANK1:SSPSTAT.CKE 6 SPI Clock Edge Select bit BANK1:SSPSTAT.D_A 5 Data/Address bit (I2C mode only) BANK1:SSPSTAT.P 4 STOP bit (I2C mode only) BANK1:SSPSTAT.S 3 START bit (I2C mode only) BANK1:SSPSTAT.R_W 2 Read/Write bit information (I2C mode only) BANK1:SSPSTAT.UA 1 Update Address bit (10-bit I2C mode only) BANK1:SSPSTAT.BF 0 Buffer Full Status bit BANK1:RESERVED0095 0x0095 RESERVED BANK1:RESERVED0096 0x0096 RESERVED BANK1:RESERVED0097 0x0097 RESERVED BANK1:TXSTA 0x0098 TRANSMIT STATUS AND CONTROL REGISTER BANK1:TXSTA.CSRC 7 Clock Source Select bit BANK1:TXSTA.TX9 6 9-bit Transmit Enable bit BANK1:TXSTA.TXEN 5 Transmit Enable bit BANK1:TXSTA.SYNC 4 USART Mode Select bit BANK1:TXSTA.BRGH 2 High Baud Rate Select bit BANK1:TXSTA.TRMT 1 Transmit Shift Register Status bit BANK1:TXSTA.TX9D 0 9th bit of Transmit Data, can be parity bit BANK1:SPBRG 0x0099 Baud Rate Generator Register BANK1:RESERVED009A 0x009A RESERVED BANK1:RESERVED009B 0x009B RESERVED BANK1:RESERVED009C 0x009C RESERVED BANK1:RESERVED009D 0x009D RESERVED BANK1:ADRESL 0x009E A/D Result Register Low Byte BANK1:ADCON1 0x009F ADCON1 REGISTER BANK1:ADCON1.ADFM 7 A/D Result format select BANK1:ADCON1.PCFG3 3 A/D Port Configuration Control bit 3 BANK1:ADCON1.PCFG2 2 A/D Port Configuration Control bit 2 BANK1:ADCON1.PCFG1 1 A/D Port Configuration Control bit 1 BANK1:ADCON1.PCFG0 0 A/D Port Configuration Control bit 0 ; BANK2 (0x0100:0x0180) BANK2:INDF 0x0100 INDF (not a physical register) BANK2:TMR0 0x0101 Timer0 module's register BANK2:PCL 0x0102 Program Counter's (PC) Least Significant Byte BANK2:STATUS 0x0103 STATUS REGISTER BANK2:STATUS.IRP 7 RegIster Bank Select bit BANK2:STATUS.RP1 6 Register Bank Select bit 1 BANK2:STATUS.RP0 5 Register Bank Select bit 0 BANK2:STATUS.TO 4 Time-out bit BANK2:STATUS.PD 3 Power-down bit BANK2:STATUS.Z 2 Zero bit BANK2:STATUS.DC 1 Digit carry/borrow bit BANK2:STATUS.C 0 Carry/borrow bit BANK2:FSR 0x0104 Indirect data memory address pointer BANK2:RESERVED0105 0x0105 RESERVED BANK2:PORTB 0x0106 PORTB register BANK2:PORTB.RB7 7 PORTB bit 7 BANK2:PORTB.RB6 6 PORTB bit 6 BANK2:PORTB.RB5 5 PORTB bit 5 BANK2:PORTB.RB4 4 PORTB bit 4 BANK2:PORTB.RB3 3 PORTB bit 3 BANK2:PORTB.RB2 2 PORTB bit 2 BANK2:PORTB.RB1 1 PORTB bit 1 BANK2:PORTB.RB0 0 PORTB bit 0 BANK2:RESERVED0107 0x0107 RESERVED BANK2:RESERVED0108 0x0108 RESERVED BANK2:RESERVED0109 0x0109 RESERVED BANK2:PCLATH 0x010A Write Buffer for the upper 5 bits of the Program Counter BANK2:INTCON 0x010B INTCON REGISTER BANK2:INTCON.GIE 7 Global Interrupt Enable bit BANK2:INTCON.PEIE 6 Peripheral Interrupt Enable bit BANK2:INTCON.T0IE 5 TMR0 Overflow Interrupt Enable bit BANK2:INTCON.INTE 4 RB0/INT External Interrupt Enable bit BANK2:INTCON.RBIE 3 RB Port Change Interrupt Enable bit BANK2:INTCON.T0IF 2 TMR0 Overflow Interrupt Flag bit BANK2:INTCON.INTF 1 RB0/INT External Interrupt Flag bit BANK2:INTCON.RBIF 0 RB Port Change Interrupt Flag bit BANK2:EEDATA 0x010C EEPROM data register Low Byte BANK2:EEADR 0x010D EEPROM address register Low Byte BANK2:EEDATH 0x010E EEPROM data register high byte BANK2:EEADRH 0x010F EEPROM address register high byte ; BANK3 (0x0180:0x0200) BANK3:INDF 0x0180 INDF (not a physical register) BANK3:OPTION 0x0181 OPTION REGISTER BANK3:OPTION.RBPU 7 PORTB Pull-up Enable bit BANK3:OPTION.INTEDG 6 Interrupt Edge Select bit BANK3:OPTION.T0CS 5 TMR0 Clock Source Select bit BANK3:OPTION.T0SE 4 TMR0 Source Edge Select bit BANK3:OPTION.PSA 3 Prescaler Assignment bit BANK3:OPTION.PS2 2 Prescaler Rate Select bit 2 BANK3:OPTION.PS1 1 Prescaler Rate Select bit 1 BANK3:OPTION.PS0 0 Prescaler Rate Select bit 0 BANK3:PCL 0x0182 Program Counter's (PC) Least Significant Byte BANK3:STATUS 0x0183 STATUS REGISTER BANK3:STATUS.IRP 7 RegIster Bank Select bit BANK3:STATUS.RP1 6 Register Bank Select bit 1 BANK3:STATUS.RP0 5 Register Bank Select bit 0 BANK3:STATUS.TO 4 Time-out bit BANK3:STATUS.PD 3 Power-down bit BANK3:STATUS.Z 2 Zero bit BANK3:STATUS.DC 1 Digit carry/borrow bit BANK3:STATUS.C 0 Carry/borrow bit BANK3:FSR 0x0184 Indirect data memory address pointer BANK3:RESERVED0185 0x0185 RESERVED BANK3:TRISB 0x0186 PORTB Data Direction Register BANK3:TRISB.TRISB7 7 PORTB Data Direction Register bit 7 BANK3:TRISB.TRISB6 6 PORTB Data Direction Register bit 6 BANK3:TRISB.TRISB5 5 PORTB Data Direction Register bit 5 BANK3:TRISB.TRISB4 4 PORTB Data Direction Register bit 4 BANK3:TRISB.TRISB3 3 PORTB Data Direction Register bit 3 BANK3:TRISB.TRISB2 2 PORTB Data Direction Register bit 2 BANK3:TRISB.TRISB1 1 PORTB Data Direction Register bit 1 BANK3:TRISB.TRISB0 0 PORTB Data Direction Register bit 0 BANK3:RESERVED0187 0x0187 RESERVED BANK3:RESERVED0188 0x0188 RESERVED BANK3:RESERVED0189 0x0189 RESERVED BANK3:PCLATH 0x018A Write Buffer for the upper 5 bits of the Program Counter BANK3:INTCON 0x018B INTCON REGISTER BANK3:INTCON.GIE 7 Global Interrupt Enable bit BANK3:INTCON.PEIE 6 Peripheral Interrupt Enable bit BANK3:INTCON.T0IE 5 TMR0 Overflow Interrupt Enable bit BANK3:INTCON.INTE 4 RB0/INT External Interrupt Enable bit BANK3:INTCON.RBIE 3 RB Port Change Interrupt Enable bit BANK3:INTCON.T0IF 2 TMR0 Overflow Interrupt Flag bit BANK3:INTCON.INTF 1 RB0/INT External Interrupt Flag bit BANK3:INTCON.RBIF 0 RB Port Change Interrupt Flag bit BANK3:EECON1 0x018C EECON1 REGISTER BANK3:EECON1.EEPGD 7 Program/Data EEPROM Select bit BANK3:EECON1.WRERR 3 EEPROM Error Flag bit BANK3:EECON1.WREN 2 EEPROM Write Enable bit BANK3:EECON1.WR 1 Write Control bit BANK3:EECON1.RD 0 Read Control bit BANK3:EECON2 0x018D EEPROM control register2 (not a physical register) BANK3:RESERVED018E 0x018E RESERVED BANK3:RESERVED018F 0x018F RESERVED .16F877 ; http://www.microchip.com/download/lit/pline/picmicro/families/16f87x/30292c.pdf ; PIC16F873_4_6_7.pdf ; MEMORY MAP ; BANK_0 area DATA FSR_ 0x0000:0x0020 area DATA Gen_Purp 0x0020:0x0080 General Purpose Register area DATA MEM_Program0 0x0080:0x0800 On-chip Program Memory (Page 0) area DATA MEM_Program1 0x0800:0x1000 On-chip Program Memory (Page 1) area DATA MEM_Program2 0x1000:0x1800 On-chip Program Memory (Page 2) area DATA MEM_Program3 0x1800:0x2000 On-chip Program Memory (Page 3) ; BANK_1 ; area DATA FSR_ 0x0080:0x00A0 ; area DATA Gen_Purp 0x00A0:0x00F0 General Purpose Register ; area DATA Gen_Purp_BANK0 0x00F0:0x0100 accesses 70h-7Fh ; area DATA MEM_Program0 0x0100:0x0800 On-chip Program Memory (Page 0) ; area DATA MEM_Program1 0x0800:0x1000 On-chip Program Memory (Page 1) ; area DATA MEM_Program2 0x1000:0x1800 On-chip Program Memory (Page 2) ; area DATA MEM_Program3 0x1800:0x2000 On-chip Program Memory (Page 3) ; BANK_2 ; area DATA FSR_ 0x0100:0x0110 ; area DATA Gen_Purp0 0x0110:0x0120 General Purpose Register 16 Bytes ; area DATA Gen_Purp1 0x0120:0x0170 General Purpose Register 80 Bytes ; area DATA Gen_Purp_BANK0 0x0170:0x0180 accesses 70h-7Fh ; area DATA MEM_Program0 0x0180:0x0800 On-chip Program Memory (Page 0) ; area DATA MEM_Program1 0x0800:0x1000 On-chip Program Memory (Page 1) ; area DATA MEM_Program2 0x1000:0x1800 On-chip Program Memory (Page 2) ; area DATA MEM_Program3 0x1800:0x2000 On-chip Program Memory (Page 3) ; BANK_3 ; area DATA FSR_ 0x0180:0x0190 ; area DATA Gen_Purp0 0x0190:0x01A0 General Purpose Register 16 Bytes ; area DATA Gen_Purp1 0x01A0:0x01F0 General Purpose Register 80 Bytes ; area DATA Gen_Purp_BANK0 0x01F0:0x0200 accesses 70h-7Fh ; area DATA MEM_Program0 0x0200:0x0800 On-chip Program Memory (Page 0) ; area DATA MEM_Program1 0x0800:0x1000 On-chip Program Memory (Page 1) ; area DATA MEM_Program2 0x1000:0x1800 On-chip Program Memory (Page 2) ; area DATA MEM_Program3 0x1800:0x2000 On-chip Program Memory (Page 3) ; Interrupt and reset vector assignments interrupt RESET 0x0000 RESET ; INPUT/OUTPUT PORTS ; BANK0 (0x0000:0x0080) BANK0:INDF 0x0000 INDF (not a physical register) BANK0:TMR0 0x0001 Timer0 module's register BANK0:PCL 0x0002 Program Counter (PC) Least Significant Byte BANK0:STATUS 0x0003 STATUS REGISTER BANK0:STATUS.IRP 7 RegIster Bank Select bit BANK0:STATUS.RP1 6 Register Bank Select bit 1 BANK0:STATUS.RP0 5 Register Bank Select bit 0 BANK0:STATUS.TO 4 Time-out bit BANK0:STATUS.PD 3 Power-down bit BANK0:STATUS.Z 2 Zero bit BANK0:STATUS.DC 1 Digit carry/borrow bit BANK0:STATUS.C 0 Carry/borrow bit BANK0:FSR 0x0004 Indirect data memory address pointer BANK0:PORTA 0x0005 PORTA register BANK0:PORTA.RA5 5 PORTA bit 5 BANK0:PORTA.RA4 4 PORTA bit 4 BANK0:PORTA.RA3 3 PORTA bit 3 BANK0:PORTA.RA2 2 PORTA bit 2 BANK0:PORTA.RA1 1 PORTA bit 1 BANK0:PORTA.RA0 0 PORTA bit 0 BANK0:PORTB 0x0006 PORTB register BANK0:PORTB.RB7 7 PORTB bit 7 BANK0:PORTB.RB6 6 PORTB bit 6 BANK0:PORTB.RB5 5 PORTB bit 5 BANK0:PORTB.RB4 4 PORTB bit 4 BANK0:PORTB.RB3 3 PORTB bit 3 BANK0:PORTB.RB2 2 PORTB bit 2 BANK0:PORTB.RB1 1 PORTB bit 1 BANK0:PORTB.RB0 0 PORTB bit 0 BANK0:PORTC 0x0007 PORTC register BANK0:PORTC.RC7 7 PORTC bit 7 BANK0:PORTC.RC6 6 PORTC bit 6 BANK0:PORTC.RC5 5 PORTC bit 5 BANK0:PORTC.RC4 4 PORTC bit 4 BANK0:PORTC.RC3 3 PORTC bit 3 BANK0:PORTC.RC2 2 PORTC bit 2 BANK0:PORTC.RC1 1 PORTC bit 1 BANK0:PORTC.RC0 0 PORTC bit 0 BANK0:PORTD 0x0008 PORTD register BANK0:PORTD.RD7 7 PORTD bit 7 BANK0:PORTD.RD6 6 PORTD bit 6 BANK0:PORTD.RD5 5 PORTD bit 5 BANK0:PORTD.RD4 4 PORTD bit 4 BANK0:PORTD.RD3 3 PORTD bit 3 BANK0:PORTD.RD2 2 PORTD bit 2 BANK0:PORTD.RD1 1 PORTD bit 1 BANK0:PORTD.RD0 0 PORTD bit 0 BANK0:PORTE 0x0009 PORTE register BANK0:PORTE.RE2 2 PORTE bit 2 BANK0:PORTE.RE1 1 PORTE bit 1 BANK0:PORTE.RE0 0 PORTE bit 0 BANK0:PCLATH 0x000A Write Buffer for the upper 5 bits of the Program Counter BANK0:INTCON 0x000B INTCON REGISTER BANK0:INTCON.GIE 7 Global Interrupt Enable bit BANK0:INTCON.PEIE 6 Peripheral Interrupt Enable bit BANK0:INTCON.T0IE 5 TMR0 Overflow Interrupt Enable bit BANK0:INTCON.INTE 4 RB0/INT External Interrupt Enable bit BANK0:INTCON.RBIE 3 RB Port Change Interrupt Enable bit BANK0:INTCON.T0IF 2 TMR0 Overflow Interrupt Flag bit BANK0:INTCON.INTF 1 RB0/INT External Interrupt Flag bit BANK0:INTCON.RBIF 0 RB Port Change Interrupt Flag bit BANK0:PIR1 0x000C PIR1 REGISTER BANK0:PIR1.PSPIF 7 Parallel Slave Port Interrupt Flag bit BANK0:PIR1.ADIF 6 A/D Converter Interrupt Flag bit BANK0:PIR1.RCIF 5 USART Receive Interrupt Flag bit BANK0:PIR1.TXIF 4 USART Transmit Interrupt Flag bit BANK0:PIR1.SSPIF 3 Synchronous Serial Port Interrupt Flag bit BANK0:PIR1.CCP1IF 2 CCP1 Interrupt Flag bit BANK0:PIR1.TMR2IF 1 TMR2 to PR2 Match Interrupt Flag bit BANK0:PIR1.TMR1IF 0 TMR1 Overflow Interrupt Flag bit BANK0:PIR2 0x000D PIR2 REGISTER BANK0:PIR2.EEIF 4 EEPROM Write Operation Interrupt Flag bit BANK0:PIR2.BCLIF 3 Bus Collision Interrupt Flag bit BANK0:PIR2.CCP2IF 0 CCP2 Interrupt Flag bit BANK0:TMR1L 0x000E Holding register for the Least Significant Byte of the 16-bit TMR1 register BANK0:TMR1H 0x000F Holding register for the Most Significant Byte of the 16-bit TMR1 register BANK0:T1CON 0x0010 TIMER1 CONTROL REGISTER BANK0:T1CON.T1CKPS1 5 Timer1 Input Clock Prescale Select bit 1 BANK0:T1CON.T1CKPS0 4 Timer1 Input Clock Prescale Select bit 0 BANK0:T1CON.T1OSCEN 3 Timer1 Oscillator Enable Control bit BANK0:T1CON.T1SYNC 2 Timer1 External Clock Input Synchronization Control bit BANK0:T1CON.TMR1CS 1 Timer1 Clock Source Select bit BANK0:T1CON.TMR1ON 0 Timer1 On bit BANK0:TMR2 0x0011 Timer2 module's register BANK0:T2CON 0x0012 TIMER2 CONTROL REGISTER BANK0:T2CON.TOUTPS3 6 Timer2 Output Postscale Select bit 3 BANK0:T2CON.TOUTPS2 5 Timer2 Output Postscale Select bit 2 BANK0:T2CON.TOUTPS1 4 Timer2 Output Postscale Select bit 1 BANK0:T2CON.TOUTPS0 3 Timer2 Output Postscale Select bit 0 BANK0:T2CON.TMR2ON 2 Timer2 On bit BANK0:T2CON.T2CKPS1 1 Timer2 Clock Prescale Select bit 1 BANK0:T2CON.T2CKPS0 0 Timer2 Clock Prescale Select bit 0 BANK0:SSPBUF 0x0013 Synchronous Serial Port Receive Buffer/Transmit Register BANK0:SSPCON 0x0014 SYNC SERIAL PORT CONTROL REGISTER BANK0:SSPCON.WCOL 7 Write Collision Detect bit BANK0:SSPCON.SSPOV 6 Receive Overflow Indicator bit BANK0:SSPCON.SSPEN 5 Synchronous Serial Port Enable bit BANK0:SSPCON.CKP 4 Clock Polarity Select bit BANK0:SSPCON.SSPM3 3 Synchronous Serial Port Mode Select bit 3 BANK0:SSPCON.SSPM2 2 Synchronous Serial Port Mode Select bit 2 BANK0:SSPCON.SSPM1 1 Synchronous Serial Port Mode Select bit 1 BANK0:SSPCON.SSPM0 0 Synchronous Serial Port Mode Select bit 0 BANK0:CCPR1L 0x0015 Capture/Compare/PWM1 Register1 (LSB) BANK0:CCPR1H 0x0016 Capture/Compare/PWM1 Register1 (MSB) BANK0:CCP1CON 0x0017 CCP1CON REGISTER BANK0:CCP1CON.CCP1X 5 PWM Least Significant bit BANK0:CCP1CON.CCP1Y 4 PWM Least Significant bit BANK0:CCP1CON.CCP1M3 3 CCP1 Mode Select bit 3 BANK0:CCP1CON.CCP1M2 2 CCP1 Mode Select bit 2 BANK0:CCP1CON.CCP1M1 1 CCP1 Mode Select bit 1 BANK0:CCP1CON.CCP1M0 0 CCP1 Mode Select bit 0 BANK0:RCSTA 0x0018 RECEIVE STATUS AND CONTROL REGISTER BANK0:RCSTA.SPEN 7 Serial Port Enable bit BANK0:RCSTA.RX9 6 9-bit Receive Enable bit BANK0:RCSTA.SREN 5 Single Receive Enable bit BANK0:RCSTA.CREN 4 Continuous Receive Enable bit BANK0:RCSTA.ADDEN 3 Address Detect Enable bit BANK0:RCSTA.FERR 2 Framing Error bit BANK0:RCSTA.OERR 1 Overrun Error bit BANK0:RCSTA.RX9D 0 9th bit of received data BANK0:TXREG 0x0019 USART Transmit Data Register BANK0:RCREG 0x001A USART Receive Data Register BANK0:CCPR2L 0x001B Capture/Compare/PWM2 Register2 (LSB) BANK0:CCPR2H 0x001C Capture/Compare/PWM2 Register2 (MSB) BANK0:CCP2CON 0x001D CCP2CON REGISTER BANK0:CCP2CON.CCP2X 5 PWM Least Significant bit BANK0:CCP2CON.CCP2Y 4 PWM Least Significant bit BANK0:CCP2CON.CCP2M3 3 CCP2 Mode Select bit 3 BANK0:CCP2CON.CCP2M2 2 CCP2 Mode Select bit 2 BANK0:CCP2CON.CCP2M1 1 CCP2 Mode Select bit 1 BANK0:CCP2CON.CCP2M0 0 CCP2 Mode Select bit 0 BANK0:ADRESH 0x001E A/D Result Register High Byte BANK0:ADCON0 0x001F ADCON0 REGISTER BANK0:ADCON0.ADCS1 7 A/D Conversion Clock Select bit 1 BANK0:ADCON0.ADCS0 6 A/D Conversion Clock Select bit 0 BANK0:ADCON0.CHS2 5 Analog Channel Select bit 2 BANK0:ADCON0.CHS1 4 Analog Channel Select bit 1 BANK0:ADCON0.CHS0 3 Analog Channel Select bit 0 BANK0:ADCON0.GO_DONE 2 A/D Conversion Status bit BANK0:ADCON0.ADON 0 A/D On bit ; BANK1 (0x0080:0x0100) BANK1:INDF 0x0080 INDF (not a physical register) BANK1:OPTION 0x0081 OPTION REGISTER BANK1:OPTION.RBPU 7 PORTB Pull-up Enable bit BANK1:OPTION.INTEDG 6 Interrupt Edge Select bit BANK1:OPTION.T0CS 5 TMR0 Clock Source Select bit BANK1:OPTION.T0SE 4 TMR0 Source Edge Select bit BANK1:OPTION.PSA 3 Prescaler Assignment bit BANK1:OPTION.PS2 2 Prescaler Rate Select bit 2 BANK1:OPTION.PS1 1 Prescaler Rate Select bit 1 BANK1:OPTION.PS0 0 Prescaler Rate Select bit 0 BANK1:PCL 0x0082 Program Counter's (PC) Least Significant Byte BANK1:STATUS 0x0083 STATUS REGISTER BANK1:STATUS.IRP 7 RegIster Bank Select bit BANK1:STATUS.RP1 6 Register Bank Select bit 1 BANK1:STATUS.RP0 5 Register Bank Select bit 0 BANK1:STATUS.TO 4 Time-out bit BANK1:STATUS.PD 3 Power-down bit BANK1:STATUS.Z 2 Zero bit BANK1:STATUS.DC 1 Digit carry/borrow bit BANK1:STATUS.C 0 Carry/borrow bit BANK1:FSR 0x0084 Indirect data memory address pointer BANK1:TRISA 0x0085 PORTA Data Direction Register BANK1:TRISA.TRISA5 5 PORTA Data Direction Register bit 5 BANK1:TRISA.TRISA4 4 PORTA Data Direction Register bit 4 BANK1:TRISA.TRISA3 3 PORTA Data Direction Register bit 3 BANK1:TRISA.TRISA2 2 PORTA Data Direction Register bit 2 BANK1:TRISA.TRISA1 1 PORTA Data Direction Register bit 1 BANK1:TRISA.TRISA0 0 PORTA Data Direction Register bit 0 BANK1:TRISB 0x0086 PORTB Data Direction Register BANK1:TRISB.TRISB7 7 PORTB Data Direction Register bit 7 BANK1:TRISB.TRISB6 6 PORTB Data Direction Register bit 6 BANK1:TRISB.TRISB5 5 PORTB Data Direction Register bit 5 BANK1:TRISB.TRISB4 4 PORTB Data Direction Register bit 4 BANK1:TRISB.TRISB3 3 PORTB Data Direction Register bit 3 BANK1:TRISB.TRISB2 2 PORTB Data Direction Register bit 2 BANK1:TRISB.TRISB1 1 PORTB Data Direction Register bit 1 BANK1:TRISB.TRISB0 0 PORTB Data Direction Register bit 0 BANK1:TRISC 0x0087 PORTC Data Direction Register BANK1:TRISC.TRISC7 7 PORTC Data Direction Register bit 7 BANK1:TRISC.TRISC6 6 PORTC Data Direction Register bit 6 BANK1:TRISC.TRISC5 5 PORTC Data Direction Register bit 5 BANK1:TRISC.TRISC4 4 PORTC Data Direction Register bit 4 BANK1:TRISC.TRISC3 3 PORTC Data Direction Register bit 3 BANK1:TRISC.TRISC2 2 PORTC Data Direction Register bit 2 BANK1:TRISC.TRISC1 1 PORTC Data Direction Register bit 1 BANK1:TRISC.TRISC0 0 PORTC Data Direction Register bit 0 BANK1:TRISD 0x0088 PORTD Data Direction Register BANK1:TRISD.TRISD7 7 PORTD Data Direction Register bit 7 BANK1:TRISD.TRISD6 6 PORTD Data Direction Register bit 6 BANK1:TRISD.TRISD5 5 PORTD Data Direction Register bit 5 BANK1:TRISD.TRISD4 4 PORTD Data Direction Register bit 4 BANK1:TRISD.TRISD3 3 PORTD Data Direction Register bit 3 BANK1:TRISD.TRISD2 2 PORTD Data Direction Register bit 2 BANK1:TRISD.TRISD1 1 PORTD Data Direction Register bit 1 BANK1:TRISD.TRISD0 0 PORTD Data Direction Register bit 0 BANK1:TRISE 0x0089 PORTE Data Direction Bits BANK1:TRISE.IBF 7 Input Buffer Full Status bit BANK1:TRISE.OBF 6 Output Buffer Full Status bit BANK1:TRISE.IBOV 5 Input Buffer Overflow Detect bit BANK1:TRISE.PSPMODE 4 Parallel Slave Port Mode Select bit BANK1:TRISE.TRISE2 2 Direction Control bit for pin RE2/CS BANK1:TRISE.TRISE1 1 Direction Control bit for pin RE1/WR BANK1:TRISE.TRISE0 0 Direction Control bit for pin RE0/RD BANK1:PCLATH 0x008A Write Buffer for the upper 5 bits of the Program Counter BANK1:INTCON 0x008B INTCON REGISTER BANK1:INTCON.GIE 7 Global Interrupt Enable bit BANK1:INTCON.PEIE 6 Peripheral Interrupt Enable bit BANK1:INTCON.T0IE 5 TMR0 Overflow Interrupt Enable bit BANK1:INTCON.INTE 4 RB0/INT External Interrupt Enable bit BANK1:INTCON.RBIE 3 RB Port Change Interrupt Enable bit BANK1:INTCON.T0IF 2 TMR0 Overflow Interrupt Flag bit BANK1:INTCON.INTF 1 RB0/INT External Interrupt Flag bit BANK1:INTCON.RBIF 0 RB Port Change Interrupt Flag bit BANK1:PIE1 0x008C PIE1 REGISTER BANK1:PIE1.PSPIE 7 Parallel Slave Port Read/Write Interrupt Enable bit BANK1:PIE1.ADIE 6 A/D Converter Interrupt Enable bit BANK1:PIE1.RCIE 5 USART Receive Interrupt Enable bit BANK1:PIE1.TXIE 4 USART Transmit Interrupt Enable bit BANK1:PIE1.SSPIE 3 Synchronous Serial Port Interrupt Enable bit BANK1:PIE1.CCP1IE 2 CCP1 Interrupt Enable bit BANK1:PIE1.TMR2IE 1 TMR2 to PR2 Match Interrupt Enable bit BANK1:PIE1.TMR1IE 0 TMR1 Overflow Interrupt Enable bit BANK1:PIE2 0x008D PIE2 REGISTER BANK1:PIE2.EEIE 4 EEPROM Write Operation Interrupt Enable BANK1:PIE2.BCLIE 3 Bus Collision Interrupt Enable BANK1:PIE2.CCP2IE 0 CCP2 Interrupt Enable bit BANK1:PCON 0x008E PCON REGISTER BANK1:PCON.POR 1 Power-on Reset Status bit BANK1:PCON.BOR 0 Brown-out Reset Status bit BANK1:RESERVED008F 0x008F RESERVED BANK1:RESERVED0090 0x0090 RESERVED BANK1:SSPCON2 0x0091 SYNC SERIAL PORT CONTROL REGISTER2 BANK1:SSPCON2.GCEN 7 General Call Enable bit (In I2C Slave mode only) BANK1:SSPCON2.ACKSTAT 6 Acknowledge Status bit (In I2C Master mode only) BANK1:SSPCON2.ACKDT 5 Acknowledge Data bit (In I2C Master mode only) BANK1:SSPCON2.ACKEN 4 Acknowledge Sequence Enable bit (In I2C Master mode only) BANK1:SSPCON2.RCEN 3 Receive Enable bit (In I2C Master mode only) BANK1:SSPCON2.PEN 2 STOP Condition Enable bit (In I2C Master mode only) BANK1:SSPCON2.RSEN 1 Repeated START Condition Enabled bit (In I2C Master mode only) BANK1:SSPCON2.SEN 0 START Condition Enabled bit (In I2C Master mode only) BANK1:PR2 0x0092 Timer2 Period Register BANK1:SSPADD 0x0093 Synchronous Serial Port (I2C mode) Address Register BANK1:SSPSTAT 0x0094 SYNC SERIAL PORT STATUS REGISTER BANK1:SSPSTAT.SMP 7 Sample bit BANK1:SSPSTAT.CKE 6 SPI Clock Edge Select bit BANK1:SSPSTAT.D_A 5 Data/Address bit (I2C mode only) BANK1:SSPSTAT.P 4 STOP bit (I2C mode only) BANK1:SSPSTAT.S 3 START bit (I2C mode only) BANK1:SSPSTAT.R_W 2 Read/Write bit information (I2C mode only) BANK1:SSPSTAT.UA 1 Update Address bit (10-bit I2C mode only) BANK1:SSPSTAT.BF 0 Buffer Full Status bit BANK1:RESERVED0095 0x0095 RESERVED BANK1:RESERVED0096 0x0096 RESERVED BANK1:RESERVED0097 0x0097 RESERVED BANK1:TXSTA 0x0098 TRANSMIT STATUS AND CONTROL REGISTER BANK1:TXSTA.CSRC 7 Clock Source Select bit BANK1:TXSTA.TX9 6 9-bit Transmit Enable bit BANK1:TXSTA.TXEN 5 Transmit Enable bit BANK1:TXSTA.SYNC 4 USART Mode Select bit BANK1:TXSTA.BRGH 2 High Baud Rate Select bit BANK1:TXSTA.TRMT 1 Transmit Shift Register Status bit BANK1:TXSTA.TX9D 0 9th bit of Transmit Data, can be parity bit BANK1:SPBRG 0x0099 Baud Rate Generator Register BANK1:RESERVED009A 0x009A RESERVED BANK1:RESERVED009B 0x009B RESERVED BANK1:RESERVED009C 0x009C RESERVED BANK1:RESERVED009D 0x009D RESERVED BANK1:ADRESL 0x009E A/D Result Register Low Byte BANK1:ADCON1 0x009F ADCON1 REGISTER BANK1:ADCON1.ADFM 7 A/D Result format select BANK1:ADCON1.PCFG3 3 A/D Port Configuration Control bit 3 BANK1:ADCON1.PCFG2 2 A/D Port Configuration Control bit 2 BANK1:ADCON1.PCFG1 1 A/D Port Configuration Control bit 1 BANK1:ADCON1.PCFG0 0 A/D Port Configuration Control bit 0 ; BANK2 (0x0100:0x0180) BANK2:INDF 0x0100 INDF (not a physical register) BANK2:TMR0 0x0101 Timer0 module's register BANK2:PCL 0x0102 Program Counter's (PC) Least Significant Byte BANK2:STATUS 0x0103 STATUS REGISTER BANK2:STATUS.IRP 7 RegIster Bank Select bit BANK2:STATUS.RP1 6 Register Bank Select bit 1 BANK2:STATUS.RP0 5 Register Bank Select bit 0 BANK2:STATUS.TO 4 Time-out bit BANK2:STATUS.PD 3 Power-down bit BANK2:STATUS.Z 2 Zero bit BANK2:STATUS.DC 1 Digit carry/borrow bit BANK2:STATUS.C 0 Carry/borrow bit BANK2:FSR 0x0104 Indirect data memory address pointer BANK2:RESERVED0105 0x0105 RESERVED BANK2:PORTB 0x0106 PORTB register BANK2:PORTB.RB7 7 PORTB bit 7 BANK2:PORTB.RB6 6 PORTB bit 6 BANK2:PORTB.RB5 5 PORTB bit 5 BANK2:PORTB.RB4 4 PORTB bit 4 BANK2:PORTB.RB3 3 PORTB bit 3 BANK2:PORTB.RB2 2 PORTB bit 2 BANK2:PORTB.RB1 1 PORTB bit 1 BANK2:PORTB.RB0 0 PORTB bit 0 BANK2:RESERVED0107 0x0107 RESERVED BANK2:RESERVED0108 0x0108 RESERVED BANK2:RESERVED0109 0x0109 RESERVED BANK2:PCLATH 0x010A Write Buffer for the upper 5 bits of the Program Counter BANK2:INTCON 0x010B INTCON REGISTER BANK2:INTCON.GIE 7 Global Interrupt Enable bit BANK2:INTCON.PEIE 6 Peripheral Interrupt Enable bit BANK2:INTCON.T0IE 5 TMR0 Overflow Interrupt Enable bit BANK2:INTCON.INTE 4 RB0/INT External Interrupt Enable bit BANK2:INTCON.RBIE 3 RB Port Change Interrupt Enable bit BANK2:INTCON.T0IF 2 TMR0 Overflow Interrupt Flag bit BANK2:INTCON.INTF 1 RB0/INT External Interrupt Flag bit BANK2:INTCON.RBIF 0 RB Port Change Interrupt Flag bit BANK2:EEDATA 0x010C EEPROM data register Low Byte BANK2:EEADR 0x010D EEPROM address register Low Byte BANK2:EEDATH 0x010E EEPROM data register high byte BANK2:EEADRH 0x010F EEPROM address register high byte ; BANK3 (0x0180:0x0200) BANK3:INDF 0x0180 INDF (not a physical register) BANK3:OPTION 0x0181 OPTION REGISTER BANK3:OPTION.RBPU 7 PORTB Pull-up Enable bit BANK3:OPTION.INTEDG 6 Interrupt Edge Select bit BANK3:OPTION.T0CS 5 TMR0 Clock Source Select bit BANK3:OPTION.T0SE 4 TMR0 Source Edge Select bit BANK3:OPTION.PSA 3 Prescaler Assignment bit BANK3:OPTION.PS2 2 Prescaler Rate Select bit 2 BANK3:OPTION.PS1 1 Prescaler Rate Select bit 1 BANK3:OPTION.PS0 0 Prescaler Rate Select bit 0 BANK3:PCL 0x0182 Program Counter's (PC) Least Significant Byte BANK3:STATUS 0x0183 STATUS REGISTER BANK3:STATUS.IRP 7 RegIster Bank Select bit BANK3:STATUS.RP1 6 Register Bank Select bit 1 BANK3:STATUS.RP0 5 Register Bank Select bit 0 BANK3:STATUS.TO 4 Time-out bit BANK3:STATUS.PD 3 Power-down bit BANK3:STATUS.Z 2 Zero bit BANK3:STATUS.DC 1 Digit carry/borrow bit BANK3:STATUS.C 0 Carry/borrow bit BANK3:FSR 0x0184 Indirect data memory address pointer BANK3:RESERVED0185 0x0185 RESERVED BANK3:TRISB 0x0186 PORTB Data Direction Register BANK3:TRISB.TRISB7 7 PORTB Data Direction Register bit 7 BANK3:TRISB.TRISB6 6 PORTB Data Direction Register bit 6 BANK3:TRISB.TRISB5 5 PORTB Data Direction Register bit 5 BANK3:TRISB.TRISB4 4 PORTB Data Direction Register bit 4 BANK3:TRISB.TRISB3 3 PORTB Data Direction Register bit 3 BANK3:TRISB.TRISB2 2 PORTB Data Direction Register bit 2 BANK3:TRISB.TRISB1 1 PORTB Data Direction Register bit 1 BANK3:TRISB.TRISB0 0 PORTB Data Direction Register bit 0 BANK3:RESERVED0187 0x0187 RESERVED BANK3:RESERVED0188 0x0188 RESERVED BANK3:RESERVED0189 0x0189 RESERVED BANK3:PCLATH 0x018A Write Buffer for the upper 5 bits of the Program Counter BANK3:INTCON 0x018B INTCON REGISTER BANK3:INTCON.GIE 7 Global Interrupt Enable bit BANK3:INTCON.PEIE 6 Peripheral Interrupt Enable bit BANK3:INTCON.T0IE 5 TMR0 Overflow Interrupt Enable bit BANK3:INTCON.INTE 4 RB0/INT External Interrupt Enable bit BANK3:INTCON.RBIE 3 RB Port Change Interrupt Enable bit BANK3:INTCON.T0IF 2 TMR0 Overflow Interrupt Flag bit BANK3:INTCON.INTF 1 RB0/INT External Interrupt Flag bit BANK3:INTCON.RBIF 0 RB Port Change Interrupt Flag bit BANK3:EECON1 0x018C EECON1 REGISTER BANK3:EECON1.EEPGD 7 Program/Data EEPROM Select bit BANK3:EECON1.WRERR 3 EEPROM Error Flag bit BANK3:EECON1.WREN 2 EEPROM Write Enable bit BANK3:EECON1.WR 1 Write Control bit BANK3:EECON1.RD 0 Read Control bit BANK3:EECON2 0x018D EEPROM control register2 (not a physical register) BANK3:RESERVED018E 0x018E RESERVED BANK3:RESERVED018F 0x018F RESERVED .16F873A ; http://www.microchip.com/download/lit/pline/picmicro/families/16f87x/39582a.pdf ; PIC16F87XA.pdf ; MEMORY MAP ; BANK_0 area DATA FSR_ 0x0000:0x0020 area DATA Gen_Purp 0x0020:0x0080 General Purpose Register area DATA MEM_Program0 0x0080:0x0800 On-chip Program Memory (Page 0) area DATA MEM_Program1 0x0800:0x1000 On-chip Program Memory (Page 1) ; BANK_1 ; area DATA FSR_ 0x0080:0x00A0 ; area DATA Gen_Purp 0x00A0:0x0100 General Purpose Register ; area DATA MEM_Program0 0x0100:0x0800 On-chip Program Memory (Page 0) ; area DATA MEM_Program1 0x0800:0x1000 On-chip Program Memory (Page 1) ; BANK_2 ; area DATA FSR_ 0x0100:0x0110 ; area BSS RESERVED 0x0110:0x0120 ; area DATA Gen_Purp_BANK0 0x0120:0x0180 accesses 20h-7Fh ; area DATA MEM_Program0 0x0180:0x0800 On-chip Program Memory (Page 0) ; area DATA MEM_Program1 0x0800:0x1000 On-chip Program Memory (Page 1) ; BANK_3 ; area DATA FSR_ 0x0180:0x0190 ; area BSS RESERVED 0x0190:0x01A0 ; area DATA Gen_Purp_BANK1 0x01A0:0x0200 accesses A0h-FFh ; area DATA MEM_Program0 0x0200:0x0800 On-chip Program Memory (Page 0) ; area DATA MEM_Program1 0x0800:0x1000 On-chip Program Memory (Page 1) ; Interrupt and reset vector assignments interrupt RESET 0x0000 RESET ; INPUT/OUTPUT PORTS ; BANK0 (0x0000:0x0080) BANK0:INDF 0x0000 INDF (not a physical register) BANK0:TMR0 0x0001 Timer0 module's register BANK0:PCL 0x0002 Program Counter (PC) Least Significant Byte BANK0:STATUS 0x0003 STATUS REGISTER BANK0:STATUS.IRP 7 RegIster Bank Select bit BANK0:STATUS.RP1 6 Register Bank Select bit 1 BANK0:STATUS.RP0 5 Register Bank Select bit 0 BANK0:STATUS.TO 4 Time-out bit BANK0:STATUS.PD 3 Power-down bit BANK0:STATUS.Z 2 Zero bit BANK0:STATUS.DC 1 Digit carry/borrow bit BANK0:STATUS.C 0 Carry/borrow bit BANK0:FSR 0x0004 Indirect data memory address pointer BANK0:PORTA 0x0005 PORTA register BANK0:PORTA.RA5 5 PORTA bit 5 BANK0:PORTA.RA4 4 PORTA bit 4 BANK0:PORTA.RA3 3 PORTA bit 3 BANK0:PORTA.RA2 2 PORTA bit 2 BANK0:PORTA.RA1 1 PORTA bit 1 BANK0:PORTA.RA0 0 PORTA bit 0 BANK0:PORTB 0x0006 PORTB register BANK0:PORTB.RB7 7 PORTB bit 7 BANK0:PORTB.RB6 6 PORTB bit 6 BANK0:PORTB.RB5 5 PORTB bit 5 BANK0:PORTB.RB4 4 PORTB bit 4 BANK0:PORTB.RB3 3 PORTB bit 3 BANK0:PORTB.RB2 2 PORTB bit 2 BANK0:PORTB.RB1 1 PORTB bit 1 BANK0:PORTB.RB0 0 PORTB bit 0 BANK0:PORTC 0x0007 PORTC register BANK0:PORTC.RC7 7 PORTC bit 7 BANK0:PORTC.RC6 6 PORTC bit 6 BANK0:PORTC.RC5 5 PORTC bit 5 BANK0:PORTC.RC4 4 PORTC bit 4 BANK0:PORTC.RC3 3 PORTC bit 3 BANK0:PORTC.RC2 2 PORTC bit 2 BANK0:PORTC.RC1 1 PORTC bit 1 BANK0:PORTC.RC0 0 PORTC bit 0 BANK0:RESERVED0008 0x0008 RESERVED BANK0:RESERVED0009 0x0009 RESERVED BANK0:PCLATH 0x000A Write Buffer for the upper 5 bits of the Program Counter BANK0:INTCON 0x000B INTCON REGISTER BANK0:INTCON.GIE 7 Global Interrupt Enable bit BANK0:INTCON.PEIE 6 Peripheral Interrupt Enable bit BANK0:INTCON.TMR0IE 5 TMR0 Overflow Interrupt Enable bit BANK0:INTCON.INTE 4 RB0/INT External Interrupt Enable bit BANK0:INTCON.RBIE 3 RB Port Change Interrupt Enable bit BANK0:INTCON.TMR0IF 2 TMR0 Overflow Interrupt Flag bit BANK0:INTCON.INTF 1 RB0/INT External Interrupt Flag bit BANK0:INTCON.RBIF 0 RB Port Change Interrupt Flag bit BANK0:PIR1 0x000C PIR1 REGISTER BANK0:PIR1.ADIF 6 A/D Converter Interrupt Flag bit BANK0:PIR1.RCIF 5 USART Receive Interrupt Flag bit BANK0:PIR1.TXIF 4 USART Transmit Interrupt Flag bit BANK0:PIR1.SSPIF 3 Synchronous Serial Port Interrupt Flag bit BANK0:PIR1.CCP1IF 2 CCP1 Interrupt Flag bit BANK0:PIR1.TMR2IF 1 TMR2 to PR2 Match Interrupt Flag bit BANK0:PIR1.TMR1IF 0 TMR1 Overflow Interrupt Flag bit BANK0:PIR2 0x000D PIR2 REGISTER BANK0:PIR2.CMIF 6 Comparator Interrupt Flag bit BANK0:PIR2.EEIF 4 EEPROM Write Operation Interrupt Flag bit BANK0:PIR2.BCLIF 3 Bus Collision Interrupt Flag bit BANK0:PIR2.CCP2IF 0 CCP2 Interrupt Flag bit BANK0:TMR1L 0x000E Holding register for the Least Significant Byte of the 16-bit TMR1 register BANK0:TMR1H 0x000F Holding register for the Most Significant Byte of the 16-bit TMR1 register BANK0:T1CON 0x0010 TIMER1 CONTROL REGISTER BANK0:T1CON.T1CKPS1 5 Timer1 Input Clock Prescale Select bit 1 BANK0:T1CON.T1CKPS0 4 Timer1 Input Clock Prescale Select bit 0 BANK0:T1CON.T1OSCEN 3 Timer1 Oscillator Enable Control bit BANK0:T1CON.T1SYNC 2 Timer1 External Clock Input Synchronization Control bit BANK0:T1CON.TMR1CS 1 Timer1 Clock Source Select bit BANK0:T1CON.TMR1ON 0 Timer1 On bit BANK0:TMR2 0x0011 Timer2 module register BANK0:T2CON 0x0012 TIMER2 CONTROL REGISTER BANK0:T2CON.TOUTPS3 6 Timer2 Output Postscale Select bit 3 BANK0:T2CON.TOUTPS2 5 Timer2 Output Postscale Select bit 2 BANK0:T2CON.TOUTPS1 4 Timer2 Output Postscale Select bit 1 BANK0:T2CON.TOUTPS0 3 Timer2 Output Postscale Select bit 0 BANK0:T2CON.TMR2ON 2 Timer2 On bit BANK0:T2CON.T2CKPS1 1 Timer2 Clock Prescale Select bit 1 BANK0:T2CON.T2CKPS0 0 Timer2 Clock Prescale Select bit 0 BANK0:SSPBUF 0x0013 Synchronous Serial Port Receive Buffer/Transmit Register BANK0:SSPCON 0x0014 SYNC SERIAL PORT CONTROL REGISTER BANK0:SSPCON.WCOL 7 Write Collision Detect bit BANK0:SSPCON.SSPOV 6 Receive Overflow Indicator bit BANK0:SSPCON.SSPEN 5 Synchronous Serial Port Enable bit BANK0:SSPCON.CKP 4 Clock Polarity Select bit BANK0:SSPCON.SSPM3 3 Synchronous Serial Port Mode Select bit 3 BANK0:SSPCON.SSPM2 2 Synchronous Serial Port Mode Select bit 2 BANK0:SSPCON.SSPM1 1 Synchronous Serial Port Mode Select bit 1 BANK0:SSPCON.SSPM0 0 Synchronous Serial Port Mode Select bit 0 BANK0:CCPR1L 0x0015 Capture/Compare/PWM1 Register1 (LSB) BANK0:CCPR1H 0x0016 Capture/Compare/PWM1 Register1 (MSB) BANK0:CCP1CON 0x0017 CCP1CON REGISTER BANK0:CCP1CON.CCP1X 5 PWM Least Significant bit BANK0:CCP1CON.CCP1Y 4 PWM Least Significant bit BANK0:CCP1CON.CCP1M3 3 CCP1 Mode Select bit 3 BANK0:CCP1CON.CCP1M2 2 CCP1 Mode Select bit 2 BANK0:CCP1CON.CCP1M1 1 CCP1 Mode Select bit 1 BANK0:CCP1CON.CCP1M0 0 CCP1 Mode Select bit 0 BANK0:RCSTA 0x0018 RECEIVE STATUS AND CONTROL REGISTER BANK0:RCSTA.SPEN 7 Serial Port Enable bit BANK0:RCSTA.RX9 6 9-bit Receive Enable bit BANK0:RCSTA.SREN 5 Single Receive Enable bit BANK0:RCSTA.CREN 4 Continuous Receive Enable bit BANK0:RCSTA.ADDEN 3 Address Detect Enable bit BANK0:RCSTA.FERR 2 Framing Error bit BANK0:RCSTA.OERR 1 Overrun Error bit BANK0:RCSTA.RX9D 0 9th bit of received data BANK0:TXREG 0x0019 USART Transmit Data Register BANK0:RCREG 0x001A USART Receive Data Register BANK0:CCPR2L 0x001B Capture/Compare/PWM2 Register2 (LSB) BANK0:CCPR2H 0x001C Capture/Compare/PWM2 Register2 (MSB) BANK0:CCP2CON 0x001D CCP2CON REGISTER BANK0:CCP2CON.CCP2X 5 PWM Least Significant bit BANK0:CCP2CON.CCP2Y 4 PWM Least Significant bit BANK0:CCP2CON.CCP2M3 3 CCP2 Mode Select bit 3 BANK0:CCP2CON.CCP2M2 2 CCP2 Mode Select bit 2 BANK0:CCP2CON.CCP2M1 1 CCP2 Mode Select bit 1 BANK0:CCP2CON.CCP2M0 0 CCP2 Mode Select bit 0 BANK0:ADRESH 0x001E A/D Result Register High Byte BANK0:ADCON0 0x001F ADCON0 REGISTER BANK0:ADCON0.ADCS1 7 A/D Conversion Clock Select bit 1 BANK0:ADCON0.ADCS0 6 A/D Conversion Clock Select bit 0 BANK0:ADCON0.CHS2 5 Analog Channel Select bit 2 BANK0:ADCON0.CHS1 4 Analog Channel Select bit 1 BANK0:ADCON0.CHS0 3 Analog Channel Select bit 0 BANK0:ADCON0.GO_DONE 2 A/D Conversion Status bit BANK0:ADCON0.ADON 0 A/D On bit ; BANK1 (0x0080:0x0100) BANK1:INDF 0x0080 INDF (not a physical register) BANK1:OPTION 0x0081 OPTION REGISTER BANK1:OPTION.RBPU 7 PORTB Pull-up Enable bit BANK1:OPTION.INTEDG 6 Interrupt Edge Select bit BANK1:OPTION.T0CS 5 TMR0 Clock Source Select bit BANK1:OPTION.T0SE 4 TMR0 Source Edge Select bit BANK1:OPTION.PSA 3 Prescaler Assignment bit BANK1:OPTION.PS2 2 Prescaler Rate Select bit 2 BANK1:OPTION.PS1 1 Prescaler Rate Select bit 1 BANK1:OPTION.PS0 0 Prescaler Rate Select bit 0 BANK1:PCL 0x0082 Program Counter's (PC) Least Significant Byte BANK1:STATUS 0x0083 STATUS REGISTER BANK1:STATUS.IRP 7 RegIster Bank Select bit BANK1:STATUS.RP1 6 Register Bank Select bit 1 BANK1:STATUS.RP0 5 Register Bank Select bit 0 BANK1:STATUS.TO 4 Time-out bit BANK1:STATUS.PD 3 Power-down bit BANK1:STATUS.Z 2 Zero bit BANK1:STATUS.DC 1 Digit carry/borrow bit BANK1:STATUS.C 0 Carry/borrow bit BANK1:FSR 0x0084 Indirect data memory address pointer BANK1:TRISA 0x0085 PORTA Data Direction Register BANK1:TRISA.TRISA5 5 PORTA Data Direction Register bit 5 BANK1:TRISA.TRISA4 4 PORTA Data Direction Register bit 4 BANK1:TRISA.TRISA3 3 PORTA Data Direction Register bit 3 BANK1:TRISA.TRISA2 2 PORTA Data Direction Register bit 2 BANK1:TRISA.TRISA1 1 PORTA Data Direction Register bit 1 BANK1:TRISA.TRISA0 0 PORTA Data Direction Register bit 0 BANK1:TRISB 0x0086 PORTB Data Direction Register BANK1:TRISB.TRISB7 7 PORTB Data Direction Register bit 7 BANK1:TRISB.TRISB6 6 PORTB Data Direction Register bit 6 BANK1:TRISB.TRISB5 5 PORTB Data Direction Register bit 5 BANK1:TRISB.TRISB4 4 PORTB Data Direction Register bit 4 BANK1:TRISB.TRISB3 3 PORTB Data Direction Register bit 3 BANK1:TRISB.TRISB2 2 PORTB Data Direction Register bit 2 BANK1:TRISB.TRISB1 1 PORTB Data Direction Register bit 1 BANK1:TRISB.TRISB0 0 PORTB Data Direction Register bit 0 BANK1:TRISC 0x0087 PORTC Data Direction Register BANK1:TRISC.TRISC7 7 PORTC Data Direction Register bit 7 BANK1:TRISC.TRISC6 6 PORTC Data Direction Register bit 6 BANK1:TRISC.TRISC5 5 PORTC Data Direction Register bit 5 BANK1:TRISC.TRISC4 4 PORTC Data Direction Register bit 4 BANK1:TRISC.TRISC3 3 PORTC Data Direction Register bit 3 BANK1:TRISC.TRISC2 2 PORTC Data Direction Register bit 2 BANK1:TRISC.TRISC1 1 PORTC Data Direction Register bit 1 BANK1:TRISC.TRISC0 0 PORTC Data Direction Register bit 0 BANK1:RESERVED0088 0x0088 RESERVED BANK1:RESERVED0089 0x0089 RESERVED BANK1:PCLATH 0x008A Write Buffer for the upper 5 bits of the Program Counter BANK1:INTCON 0x008B INTCON REGISTER BANK1:INTCON.GIE 7 Global Interrupt Enable bit BANK1:INTCON.PEIE 6 Peripheral Interrupt Enable bit BANK1:INTCON.TMR0IE 5 TMR0 Overflow Interrupt Enable bit BANK1:INTCON.INTE 4 RB0/INT External Interrupt Enable bit BANK1:INTCON.RBIE 3 RB Port Change Interrupt Enable bit BANK1:INTCON.TMR0IF 2 TMR0 Overflow Interrupt Flag bit BANK1:INTCON.INTF 1 RB0/INT External Interrupt Flag bit BANK1:INTCON.RBIF 0 RB Port Change Interrupt Flag bit BANK1:PIE1 0x008C PIE1 REGISTER BANK1:PIE1.ADIE 6 A/D Converter Interrupt Enable bit BANK1:PIE1.RCIE 5 USART Receive Interrupt Enable bit BANK1:PIE1.TXIE 4 USART Transmit Interrupt Enable bit BANK1:PIE1.SSPIE 3 Synchronous Serial Port Interrupt Enable bit BANK1:PIE1.CCP1IE 2 CCP1 Interrupt Enable bit BANK1:PIE1.TMR2IE 1 TMR2 to PR2 Match Interrupt Enable bit BANK1:PIE1.TMR1IE 0 TMR1 Overflow Interrupt Enable bit BANK1:PIE2 0x008D PIE2 REGISTER BANK1:PIE2.CMIE 6 Comparator Interrupt Enable bit BANK1:PIE2.EEIE 4 EEPROM Write Operation Interrupt Enable BANK1:PIE2.BCLIE 3 Bus Collision Interrupt Enable BANK1:PIE2.CCP2IE 0 CCP2 Interrupt Enable bit BANK1:PCON 0x008E PCON REGISTER BANK1:PCON.POR 1 Power-on Reset Status bit BANK1:PCON.BOR 0 Brown-out Reset Status bit BANK1:RESERVED008F 0x008F RESERVED BANK1:RESERVED0090 0x0090 RESERVED BANK1:SSPCON2 0x0091 SYNC SERIAL PORT CONTROL REGISTER2 BANK1:SSPCON2.GCEN 7 General Call Enable bit (In I2C Slave mode only) BANK1:SSPCON2.ACKSTAT 6 Acknowledge Status bit (In I2C Master mode only) BANK1:SSPCON2.ACKDT 5 Acknowledge Data bit (In I2C Master mode only) BANK1:SSPCON2.ACKEN 4 Acknowledge Sequence Enable bit (In I2C Master mode only) BANK1:SSPCON2.RCEN 3 Receive Enable bit (In I2C Master mode only) BANK1:SSPCON2.PEN 2 STOP Condition Enable bit (In I2C Master mode only) BANK1:SSPCON2.RSEN 1 Repeated START Condition Enabled bit (In I2C Master mode only) BANK1:SSPCON2.SEN 0 START Condition Enabled bit (In I2C Master mode only) BANK1:PR2 0x0092 Timer2 Period Register BANK1:SSPADD 0x0093 Synchronous Serial Port (I2C mode) Address Register BANK1:SSPSTAT 0x0094 SYNC SERIAL PORT STATUS REGISTER BANK1:SSPSTAT.SMP 7 Sample bit BANK1:SSPSTAT.CKE 6 SPI Clock Edge Select bit BANK1:SSPSTAT.D_A 5 Data/Address bit (I2C mode only) BANK1:SSPSTAT.P 4 STOP bit (I2C mode only) BANK1:SSPSTAT.S 3 START bit (I2C mode only) BANK1:SSPSTAT.R_W 2 Read/Write bit information (I2C mode only) BANK1:SSPSTAT.UA 1 Update Address bit (10-bit I2C mode only) BANK1:SSPSTAT.BF 0 Buffer Full Status bit BANK1:RESERVED0095 0x0095 RESERVED BANK1:RESERVED0096 0x0096 RESERVED BANK1:RESERVED0097 0x0097 RESERVED BANK1:TXSTA 0x0098 TRANSMIT STATUS AND CONTROL REGISTER BANK1:TXSTA.CSRC 7 Clock Source Select bit BANK1:TXSTA.TX9 6 9-bit Transmit Enable bit BANK1:TXSTA.TXEN 5 Transmit Enable bit BANK1:TXSTA.SYNC 4 USART Mode Select bit BANK1:TXSTA.BRGH 2 High Baud Rate Select bit BANK1:TXSTA.TRMT 1 Transmit Shift Register Status bit BANK1:TXSTA.TX9D 0 9th bit of Transmit Data, can be parity bit BANK1:SPBRG 0x0099 Baud Rate Generator Register BANK1:RESERVED009A 0x009A RESERVED BANK1:RESERVED009B 0x009B RESERVED BANK1:CMCON 0x009C CMCON REGISTER BANK1:CMCON.C2OUT 7 Comparator 2 Output bit BANK1:CMCON.C1OUT 6 Comparator 1 Output bit BANK1:CMCON.C2INV 5 Comparator 2 Output Inversion bit BANK1:CMCON.C1INV 4 Comparator 1 Output Inversion bit BANK1:CMCON.CIS 3 Comparator Input Switch bit BANK1:CMCON.CM2 2 Comparator Mode bit 2 BANK1:CMCON.CM1 1 Comparator Mode bit 1 BANK1:CMCON.CM0 0 Comparator Mode bit 0 BANK1:CVRCON 0x009D CVRCON CONTROL REGISTER BANK1:CVRCON.CVREN 7 Comparator Voltage Reference Enable bit BANK1:CVRCON.CVROE 6 Comparator VREF Output Enable bit BANK1:CVRCON.CVRR 5 Comparator VREF Range Selection bit BANK1:CVRCON.CVR3 3 Comparator VREF Value Selection bit 3 BANK1:CVRCON.CVR2 2 Comparator VREF Value Selection bit 2 BANK1:CVRCON.CVR1 1 Comparator VREF Value Selection bit 1 BANK1:CVRCON.CVR0 0 Comparator VREF Value Selection bit 0 BANK1:ADRESL 0x009E A/D Result Register Low Byte BANK1:ADCON1 0x009F ADCON1 REGISTER BANK1:ADCON1.ADFM 7 A/D Result format select BANK1:ADCON1.ADCS2 6 A/D Conversion Clock Select bit BANK1:ADCON1.PCFG3 3 A/D Port Configuration Control bit 3 BANK1:ADCON1.PCFG2 2 A/D Port Configuration Control bit 2 BANK1:ADCON1.PCFG1 1 A/D Port Configuration Control bit 1 BANK1:ADCON1.PCFG0 0 A/D Port Configuration Control bit 0 ; BANK2 (0x0100:0x0180) BANK2:INDF 0x0100 INDF (not a physical register) BANK2:TMR0 0x0101 Timer0 module's register BANK2:PCL 0x0102 Program Counter's (PC) Least Significant Byte BANK2:STATUS 0x0103 STATUS REGISTER BANK2:STATUS.IRP 7 RegIster Bank Select bit BANK2:STATUS.RP1 6 Register Bank Select bit 1 BANK2:STATUS.RP0 5 Register Bank Select bit 0 BANK2:STATUS.TO 4 Time-out bit BANK2:STATUS.PD 3 Power-down bit BANK2:STATUS.Z 2 Zero bit BANK2:STATUS.DC 1 Digit carry/borrow bit BANK2:STATUS.C 0 Carry/borrow bit BANK2:FSR 0x0104 Indirect data memory address pointer BANK2:RESERVED0105 0x0105 RESERVED BANK2:PORTB 0x0106 PORTB register BANK2:PORTB.RB7 7 PORTB bit 7 BANK2:PORTB.RB6 6 PORTB bit 6 BANK2:PORTB.RB5 5 PORTB bit 5 BANK2:PORTB.RB4 4 PORTB bit 4 BANK2:PORTB.RB3 3 PORTB bit 3 BANK2:PORTB.RB2 2 PORTB bit 2 BANK2:PORTB.RB1 1 PORTB bit 1 BANK2:PORTB.RB0 0 PORTB bit 0 BANK2:RESERVED0107 0x0107 RESERVED BANK2:RESERVED0108 0x0108 RESERVED BANK2:RESERVED0109 0x0109 RESERVED BANK2:PCLATH 0x010A Write Buffer for the upper 5 bits of the Program Counter BANK2:INTCON 0x010B INTCON REGISTER BANK2:INTCON.GIE 7 Global Interrupt Enable bit BANK2:INTCON.PEIE 6 Peripheral Interrupt Enable bit BANK2:INTCON.TMR0IE 5 TMR0 Overflow Interrupt Enable bit BANK2:INTCON.INTE 4 RB0/INT External Interrupt Enable bit BANK2:INTCON.RBIE 3 RB Port Change Interrupt Enable bit BANK2:INTCON.TMR0IF 2 TMR0 Overflow Interrupt Flag bit BANK2:INTCON.INTF 1 RB0/INT External Interrupt Flag bit BANK2:INTCON.RBIF 0 RB Port Change Interrupt Flag bit BANK2:EEDATA 0x010C EEPROM data register Low Byte BANK2:EEADR 0x010D EEPROM address register Low Byte BANK2:EEDATH 0x010E EEPROM data register high byte BANK2:EEADRH 0x010F EEPROM address register high byte ; BANK3 (0x0180:0x0200) BANK3:INDF 0x0180 INDF (not a physical register) BANK3:OPTION 0x0181 OPTION REGISTER BANK3:OPTION.RBPU 7 PORTB Pull-up Enable bit BANK3:OPTION.INTEDG 6 Interrupt Edge Select bit BANK3:OPTION.T0CS 5 TMR0 Clock Source Select bit BANK3:OPTION.T0SE 4 TMR0 Source Edge Select bit BANK3:OPTION.PSA 3 Prescaler Assignment bit BANK3:OPTION.PS2 2 Prescaler Rate Select bit 2 BANK3:OPTION.PS1 1 Prescaler Rate Select bit 1 BANK3:OPTION.PS0 0 Prescaler Rate Select bit 0 BANK3:PCL 0x0182 Program Counter's (PC) Least Significant Byte BANK3:STATUS 0x0183 STATUS REGISTER BANK3:STATUS.IRP 7 RegIster Bank Select bit BANK3:STATUS.RP1 6 Register Bank Select bit 1 BANK3:STATUS.RP0 5 Register Bank Select bit 0 BANK3:STATUS.TO 4 Time-out bit BANK3:STATUS.PD 3 Power-down bit BANK3:STATUS.Z 2 Zero bit BANK3:STATUS.DC 1 Digit carry/borrow bit BANK3:STATUS.C 0 Carry/borrow bit BANK3:FSR 0x0184 Indirect data memory address pointer BANK3:RESERVED0185 0x0185 RESERVED BANK3:TRISB 0x0186 PORTB Data Direction Register BANK3:TRISB.TRISB7 7 PORTB Data Direction Register bit 7 BANK3:TRISB.TRISB6 6 PORTB Data Direction Register bit 6 BANK3:TRISB.TRISB5 5 PORTB Data Direction Register bit 5 BANK3:TRISB.TRISB4 4 PORTB Data Direction Register bit 4 BANK3:TRISB.TRISB3 3 PORTB Data Direction Register bit 3 BANK3:TRISB.TRISB2 2 PORTB Data Direction Register bit 2 BANK3:TRISB.TRISB1 1 PORTB Data Direction Register bit 1 BANK3:TRISB.TRISB0 0 PORTB Data Direction Register bit 0 BANK3:RESERVED0187 0x0187 RESERVED BANK3:RESERVED0188 0x0188 RESERVED BANK3:RESERVED0189 0x0189 RESERVED BANK3:PCLATH 0x018A Write Buffer for the upper 5 bits of the Program Counter BANK3:INTCON 0x018B INTCON REGISTER BANK3:INTCON.GIE 7 Global Interrupt Enable bit BANK3:INTCON.PEIE 6 Peripheral Interrupt Enable bit BANK3:INTCON.TMR0IE 5 TMR0 Overflow Interrupt Enable bit BANK3:INTCON.INTE 4 RB0/INT External Interrupt Enable bit BANK3:INTCON.RBIE 3 RB Port Change Interrupt Enable bit BANK3:INTCON.TMR0IF 2 TMR0 Overflow Interrupt Flag bit BANK3:INTCON.INTF 1 RB0/INT External Interrupt Flag bit BANK3:INTCON.RBIF 0 RB Port Change Interrupt Flag bit BANK3:EECON1 0x018C EECON1 REGISTER BANK3:EECON1.EEPGD 7 Program/Data EEPROM Select bit BANK3:EECON1.WRERR 3 EEPROM Error Flag bit BANK3:EECON1.WREN 2 EEPROM Write Enable bit BANK3:EECON1.WR 1 Write Control bit BANK3:EECON1.RD 0 Read Control bit BANK3:EECON2 0x018D EEPROM control register2 (not a physical register) BANK3:RESERVED018E 0x018E RESERVED BANK3:RESERVED018F 0x018F RESERVED .16F874A ; http://www.microchip.com/download/lit/pline/picmicro/families/16f87x/39582a.pdf ; PIC16F87XA.pdf ; MEMORY MAP ; BANK_0 area DATA FSR_ 0x0000:0x0020 area DATA Gen_Purp 0x0020:0x0080 General Purpose Register area DATA MEM_Program0 0x0080:0x0800 On-chip Program Memory (Page 0) area DATA MEM_Program1 0x0800:0x1000 On-chip Program Memory (Page 1) ; BANK_1 ; area DATA FSR_ 0x0080:0x00A0 ; area DATA Gen_Purp 0x00A0:0x0100 General Purpose Register ; area DATA MEM_Program0 0x0100:0x0800 On-chip Program Memory (Page 0) ; area DATA MEM_Program1 0x0800:0x1000 On-chip Program Memory (Page 1) ; BANK_2 ; area DATA FSR_ 0x0100:0x0110 ; area BSS RESERVED 0x0110:0x0120 ; area DATA Gen_Purp_BANK0 0x0120:0x0180 accesses 20h-7Fh ; area DATA MEM_Program0 0x0180:0x0800 On-chip Program Memory (Page 0) ; area DATA MEM_Program1 0x0800:0x1000 On-chip Program Memory (Page 1) ; BANK_3 ; area DATA FSR_ 0x0180:0x0190 ; area BSS RESERVED 0x0190:0x01A0 ; area DATA Gen_Purp_BANK1 0x01A0:0x0200 accesses A0h-FFh ; area DATA MEM_Program0 0x0200:0x0800 On-chip Program Memory (Page 0) ; area DATA MEM_Program1 0x0800:0x1000 On-chip Program Memory (Page 1) ; Interrupt and reset vector assignments interrupt RESET 0x0000 RESET ; INPUT/OUTPUT PORTS ; BANK0 (0x0000:0x0080) BANK0:INDF 0x0000 INDF (not a physical register) BANK0:TMR0 0x0001 Timer0 module's register BANK0:PCL 0x0002 Program Counter (PC) Least Significant Byte BANK0:STATUS 0x0003 STATUS REGISTER BANK0:STATUS.IRP 7 RegIster Bank Select bit BANK0:STATUS.RP1 6 Register Bank Select bit 1 BANK0:STATUS.RP0 5 Register Bank Select bit 0 BANK0:STATUS.TO 4 Time-out bit BANK0:STATUS.PD 3 Power-down bit BANK0:STATUS.Z 2 Zero bit BANK0:STATUS.DC 1 Digit carry/borrow bit BANK0:STATUS.C 0 Carry/borrow bit BANK0:FSR 0x0004 Indirect data memory address pointer BANK0:PORTA 0x0005 PORTA register BANK0:PORTA.RA5 5 PORTA bit 5 BANK0:PORTA.RA4 4 PORTA bit 4 BANK0:PORTA.RA3 3 PORTA bit 3 BANK0:PORTA.RA2 2 PORTA bit 2 BANK0:PORTA.RA1 1 PORTA bit 1 BANK0:PORTA.RA0 0 PORTA bit 0 BANK0:PORTB 0x0006 PORTB register BANK0:PORTB.RB7 7 PORTB bit 7 BANK0:PORTB.RB6 6 PORTB bit 6 BANK0:PORTB.RB5 5 PORTB bit 5 BANK0:PORTB.RB4 4 PORTB bit 4 BANK0:PORTB.RB3 3 PORTB bit 3 BANK0:PORTB.RB2 2 PORTB bit 2 BANK0:PORTB.RB1 1 PORTB bit 1 BANK0:PORTB.RB0 0 PORTB bit 0 BANK0:PORTC 0x0007 PORTC register BANK0:PORTC.RC7 7 PORTC bit 7 BANK0:PORTC.RC6 6 PORTC bit 6 BANK0:PORTC.RC5 5 PORTC bit 5 BANK0:PORTC.RC4 4 PORTC bit 4 BANK0:PORTC.RC3 3 PORTC bit 3 BANK0:PORTC.RC2 2 PORTC bit 2 BANK0:PORTC.RC1 1 PORTC bit 1 BANK0:PORTC.RC0 0 PORTC bit 0 BANK0:PORTD 0x0008 PORTD register BANK0:PORTD.RD7 7 PORTD bit 7 BANK0:PORTD.RD6 6 PORTD bit 6 BANK0:PORTD.RD5 5 PORTD bit 5 BANK0:PORTD.RD4 4 PORTD bit 4 BANK0:PORTD.RD3 3 PORTD bit 3 BANK0:PORTD.RD2 2 PORTD bit 2 BANK0:PORTD.RD1 1 PORTD bit 1 BANK0:PORTD.RD0 0 PORTD bit 0 BANK0:PORTE 0x0009 PORTE register BANK0:PORTE.RE2 2 PORTE bit 2 BANK0:PORTE.RE1 1 PORTE bit 1 BANK0:PORTE.RE0 0 PORTE bit 0 BANK0:PCLATH 0x000A Write Buffer for the upper 5 bits of the Program Counter BANK0:INTCON 0x000B INTCON REGISTER BANK0:INTCON.GIE 7 Global Interrupt Enable bit BANK0:INTCON.PEIE 6 Peripheral Interrupt Enable bit BANK0:INTCON.TMR0IE 5 TMR0 Overflow Interrupt Enable bit BANK0:INTCON.INTE 4 RB0/INT External Interrupt Enable bit BANK0:INTCON.RBIE 3 RB Port Change Interrupt Enable bit BANK0:INTCON.TMR0IF 2 TMR0 Overflow Interrupt Flag bit BANK0:INTCON.INTF 1 RB0/INT External Interrupt Flag bit BANK0:INTCON.RBIF 0 RB Port Change Interrupt Flag bit BANK0:PIR1 0x000C PIR1 REGISTER BANK0:PIR1.PSPIF 7 Parallel Slave Port Interrupt Flag bit BANK0:PIR1.ADIF 6 A/D Converter Interrupt Flag bit BANK0:PIR1.RCIF 5 USART Receive Interrupt Flag bit BANK0:PIR1.TXIF 4 USART Transmit Interrupt Flag bit BANK0:PIR1.SSPIF 3 Synchronous Serial Port Interrupt Flag bit BANK0:PIR1.CCP1IF 2 CCP1 Interrupt Flag bit BANK0:PIR1.TMR2IF 1 TMR2 to PR2 Match Interrupt Flag bit BANK0:PIR1.TMR1IF 0 TMR1 Overflow Interrupt Flag bit BANK0:PIR2 0x000D PIR2 REGISTER BANK0:PIR2.CMIF 6 Comparator Interrupt Flag bit BANK0:PIR2.EEIF 4 EEPROM Write Operation Interrupt Flag bit BANK0:PIR2.BCLIF 3 Bus Collision Interrupt Flag bit BANK0:PIR2.CCP2IF 0 CCP2 Interrupt Flag bit BANK0:TMR1L 0x000E Holding register for the Least Significant Byte of the 16-bit TMR1 register BANK0:TMR1H 0x000F Holding register for the Most Significant Byte of the 16-bit TMR1 register BANK0:T1CON 0x0010 TIMER1 CONTROL REGISTER BANK0:T1CON.T1CKPS1 5 Timer1 Input Clock Prescale Select bit 1 BANK0:T1CON.T1CKPS0 4 Timer1 Input Clock Prescale Select bit 0 BANK0:T1CON.T1OSCEN 3 Timer1 Oscillator Enable Control bit BANK0:T1CON.T1SYNC 2 Timer1 External Clock Input Synchronization Control bit BANK0:T1CON.TMR1CS 1 Timer1 Clock Source Select bit BANK0:T1CON.TMR1ON 0 Timer1 On bit BANK0:TMR2 0x0011 Timer2 module register BANK0:T2CON 0x0012 TIMER2 CONTROL REGISTER BANK0:T2CON.TOUTPS3 6 Timer2 Output Postscale Select bit 3 BANK0:T2CON.TOUTPS2 5 Timer2 Output Postscale Select bit 2 BANK0:T2CON.TOUTPS1 4 Timer2 Output Postscale Select bit 1 BANK0:T2CON.TOUTPS0 3 Timer2 Output Postscale Select bit 0 BANK0:T2CON.TMR2ON 2 Timer2 On bit BANK0:T2CON.T2CKPS1 1 Timer2 Clock Prescale Select bit 1 BANK0:T2CON.T2CKPS0 0 Timer2 Clock Prescale Select bit 0 BANK0:SSPBUF 0x0013 Synchronous Serial Port Receive Buffer/Transmit Register BANK0:SSPCON 0x0014 SYNC SERIAL PORT CONTROL REGISTER BANK0:SSPCON.WCOL 7 Write Collision Detect bit BANK0:SSPCON.SSPOV 6 Receive Overflow Indicator bit BANK0:SSPCON.SSPEN 5 Synchronous Serial Port Enable bit BANK0:SSPCON.CKP 4 Clock Polarity Select bit BANK0:SSPCON.SSPM3 3 Synchronous Serial Port Mode Select bit 3 BANK0:SSPCON.SSPM2 2 Synchronous Serial Port Mode Select bit 2 BANK0:SSPCON.SSPM1 1 Synchronous Serial Port Mode Select bit 1 BANK0:SSPCON.SSPM0 0 Synchronous Serial Port Mode Select bit 0 BANK0:CCPR1L 0x0015 Capture/Compare/PWM1 Register1 (LSB) BANK0:CCPR1H 0x0016 Capture/Compare/PWM1 Register1 (MSB) BANK0:CCP1CON 0x0017 CCP1CON REGISTER BANK0:CCP1CON.CCP1X 5 PWM Least Significant bit BANK0:CCP1CON.CCP1Y 4 PWM Least Significant bit BANK0:CCP1CON.CCP1M3 3 CCP1 Mode Select bit 3 BANK0:CCP1CON.CCP1M2 2 CCP1 Mode Select bit 2 BANK0:CCP1CON.CCP1M1 1 CCP1 Mode Select bit 1 BANK0:CCP1CON.CCP1M0 0 CCP1 Mode Select bit 0 BANK0:RCSTA 0x0018 RECEIVE STATUS AND CONTROL REGISTER BANK0:RCSTA.SPEN 7 Serial Port Enable bit BANK0:RCSTA.RX9 6 9-bit Receive Enable bit BANK0:RCSTA.SREN 5 Single Receive Enable bit BANK0:RCSTA.CREN 4 Continuous Receive Enable bit BANK0:RCSTA.ADDEN 3 Address Detect Enable bit BANK0:RCSTA.FERR 2 Framing Error bit BANK0:RCSTA.OERR 1 Overrun Error bit BANK0:RCSTA.RX9D 0 9th bit of received data BANK0:TXREG 0x0019 USART Transmit Data Register BANK0:RCREG 0x001A USART Receive Data Register BANK0:CCPR2L 0x001B Capture/Compare/PWM2 Register2 (LSB) BANK0:CCPR2H 0x001C Capture/Compare/PWM2 Register2 (MSB) BANK0:CCP2CON 0x001D CCP2CON REGISTER BANK0:CCP2CON.CCP2X 5 PWM Least Significant bit BANK0:CCP2CON.CCP2Y 4 PWM Least Significant bit BANK0:CCP2CON.CCP2M3 3 CCP2 Mode Select bit 3 BANK0:CCP2CON.CCP2M2 2 CCP2 Mode Select bit 2 BANK0:CCP2CON.CCP2M1 1 CCP2 Mode Select bit 1 BANK0:CCP2CON.CCP2M0 0 CCP2 Mode Select bit 0 BANK0:ADRESH 0x001E A/D Result Register High Byte BANK0:ADCON0 0x001F ADCON0 REGISTER BANK0:ADCON0.ADCS1 7 A/D Conversion Clock Select bit 1 BANK0:ADCON0.ADCS0 6 A/D Conversion Clock Select bit 0 BANK0:ADCON0.CHS2 5 Analog Channel Select bit 2 BANK0:ADCON0.CHS1 4 Analog Channel Select bit 1 BANK0:ADCON0.CHS0 3 Analog Channel Select bit 0 BANK0:ADCON0.GO_DONE 2 A/D Conversion Status bit BANK0:ADCON0.ADON 0 A/D On bit ; BANK1 (0x0080:0x0100) BANK1:INDF 0x0080 INDF (not a physical register) BANK1:OPTION 0x0081 OPTION REGISTER BANK1:OPTION.RBPU 7 PORTB Pull-up Enable bit BANK1:OPTION.INTEDG 6 Interrupt Edge Select bit BANK1:OPTION.T0CS 5 TMR0 Clock Source Select bit BANK1:OPTION.T0SE 4 TMR0 Source Edge Select bit BANK1:OPTION.PSA 3 Prescaler Assignment bit BANK1:OPTION.PS2 2 Prescaler Rate Select bit 2 BANK1:OPTION.PS1 1 Prescaler Rate Select bit 1 BANK1:OPTION.PS0 0 Prescaler Rate Select bit 0 BANK1:PCL 0x0082 Program Counter's (PC) Least Significant Byte BANK1:STATUS 0x0083 STATUS REGISTER BANK1:STATUS.IRP 7 RegIster Bank Select bit BANK1:STATUS.RP1 6 Register Bank Select bit 1 BANK1:STATUS.RP0 5 Register Bank Select bit 0 BANK1:STATUS.TO 4 Time-out bit BANK1:STATUS.PD 3 Power-down bit BANK1:STATUS.Z 2 Zero bit BANK1:STATUS.DC 1 Digit carry/borrow bit BANK1:STATUS.C 0 Carry/borrow bit BANK1:FSR 0x0084 Indirect data memory address pointer BANK1:TRISA 0x0085 PORTA Data Direction Register BANK1:TRISA.TRISA5 5 PORTA Data Direction Register bit 5 BANK1:TRISA.TRISA4 4 PORTA Data Direction Register bit 4 BANK1:TRISA.TRISA3 3 PORTA Data Direction Register bit 3 BANK1:TRISA.TRISA2 2 PORTA Data Direction Register bit 2 BANK1:TRISA.TRISA1 1 PORTA Data Direction Register bit 1 BANK1:TRISA.TRISA0 0 PORTA Data Direction Register bit 0 BANK1:TRISB 0x0086 PORTB Data Direction Register BANK1:TRISB.TRISB7 7 PORTB Data Direction Register bit 7 BANK1:TRISB.TRISB6 6 PORTB Data Direction Register bit 6 BANK1:TRISB.TRISB5 5 PORTB Data Direction Register bit 5 BANK1:TRISB.TRISB4 4 PORTB Data Direction Register bit 4 BANK1:TRISB.TRISB3 3 PORTB Data Direction Register bit 3 BANK1:TRISB.TRISB2 2 PORTB Data Direction Register bit 2 BANK1:TRISB.TRISB1 1 PORTB Data Direction Register bit 1 BANK1:TRISB.TRISB0 0 PORTB Data Direction Register bit 0 BANK1:TRISC 0x0087 PORTC Data Direction Register BANK1:TRISC.TRISC7 7 PORTC Data Direction Register bit 7 BANK1:TRISC.TRISC6 6 PORTC Data Direction Register bit 6 BANK1:TRISC.TRISC5 5 PORTC Data Direction Register bit 5 BANK1:TRISC.TRISC4 4 PORTC Data Direction Register bit 4 BANK1:TRISC.TRISC3 3 PORTC Data Direction Register bit 3 BANK1:TRISC.TRISC2 2 PORTC Data Direction Register bit 2 BANK1:TRISC.TRISC1 1 PORTC Data Direction Register bit 1 BANK1:TRISC.TRISC0 0 PORTC Data Direction Register bit 0 BANK1:TRISD 0x0088 PORTD Data Direction Register BANK1:TRISD.TRISD7 7 PORTD Data Direction Register bit 7 BANK1:TRISD.TRISD6 6 PORTD Data Direction Register bit 6 BANK1:TRISD.TRISD5 5 PORTD Data Direction Register bit 5 BANK1:TRISD.TRISD4 4 PORTD Data Direction Register bit 4 BANK1:TRISD.TRISD3 3 PORTD Data Direction Register bit 3 BANK1:TRISD.TRISD2 2 PORTD Data Direction Register bit 2 BANK1:TRISD.TRISD1 1 PORTD Data Direction Register bit 1 BANK1:TRISD.TRISD0 0 PORTD Data Direction Register bit 0 BANK1:TRISE 0x0089 PORTE Data Direction Bits BANK1:TRISE.IBF 7 Input Buffer Full Status bit BANK1:TRISE.OBF 6 Output Buffer Full Status bit BANK1:TRISE.IBOV 5 Input Buffer Overflow Detect bit BANK1:TRISE.PSPMODE 4 Parallel Slave Port Mode Select bit BANK1:TRISE.TRISE2 2 Direction Control bit for pin RE2/CS BANK1:TRISE.TRISE1 1 Direction Control bit for pin RE1/WR BANK1:TRISE.TRISE0 0 Direction Control bit for pin RE0/RD BANK1:PCLATH 0x008A Write Buffer for the upper 5 bits of the Program Counter BANK1:INTCON 0x008B INTCON REGISTER BANK1:INTCON.GIE 7 Global Interrupt Enable bit BANK1:INTCON.PEIE 6 Peripheral Interrupt Enable bit BANK1:INTCON.TMR0IE 5 TMR0 Overflow Interrupt Enable bit BANK1:INTCON.INTE 4 RB0/INT External Interrupt Enable bit BANK1:INTCON.RBIE 3 RB Port Change Interrupt Enable bit BANK1:INTCON.TMR0IF 2 TMR0 Overflow Interrupt Flag bit BANK1:INTCON.INTF 1 RB0/INT External Interrupt Flag bit BANK1:INTCON.RBIF 0 RB Port Change Interrupt Flag bit BANK1:PIE1 0x008C PIE1 REGISTER BANK1:PIE1.PSPIE 7 Parallel Slave Port Read/Write Interrupt Enable bit BANK1:PIE1.ADIE 6 A/D Converter Interrupt Enable bit BANK1:PIE1.RCIE 5 USART Receive Interrupt Enable bit BANK1:PIE1.TXIE 4 USART Transmit Interrupt Enable bit BANK1:PIE1.SSPIE 3 Synchronous Serial Port Interrupt Enable bit BANK1:PIE1.CCP1IE 2 CCP1 Interrupt Enable bit BANK1:PIE1.TMR2IE 1 TMR2 to PR2 Match Interrupt Enable bit BANK1:PIE1.TMR1IE 0 TMR1 Overflow Interrupt Enable bit BANK1:PIE2 0x008D PIE2 REGISTER BANK1:PIE2.CMIE 6 Comparator Interrupt Enable bit BANK1:PIE2.EEIE 4 EEPROM Write Operation Interrupt Enable BANK1:PIE2.BCLIE 3 Bus Collision Interrupt Enable BANK1:PIE2.CCP2IE 0 CCP2 Interrupt Enable bit BANK1:PCON 0x008E PCON REGISTER BANK1:PCON.POR 1 Power-on Reset Status bit BANK1:PCON.BOR 0 Brown-out Reset Status bit BANK1:RESERVED008F 0x008F RESERVED BANK1:RESERVED0090 0x0090 RESERVED BANK1:SSPCON2 0x0091 SYNC SERIAL PORT CONTROL REGISTER2 BANK1:SSPCON2.GCEN 7 General Call Enable bit (In I2C Slave mode only) BANK1:SSPCON2.ACKSTAT 6 Acknowledge Status bit (In I2C Master mode only) BANK1:SSPCON2.ACKDT 5 Acknowledge Data bit (In I2C Master mode only) BANK1:SSPCON2.ACKEN 4 Acknowledge Sequence Enable bit (In I2C Master mode only) BANK1:SSPCON2.RCEN 3 Receive Enable bit (In I2C Master mode only) BANK1:SSPCON2.PEN 2 STOP Condition Enable bit (In I2C Master mode only) BANK1:SSPCON2.RSEN 1 Repeated START Condition Enabled bit (In I2C Master mode only) BANK1:SSPCON2.SEN 0 START Condition Enabled bit (In I2C Master mode only) BANK1:PR2 0x0092 Timer2 Period Register BANK1:SSPADD 0x0093 Synchronous Serial Port (I2C mode) Address Register BANK1:SSPSTAT 0x0094 SYNC SERIAL PORT STATUS REGISTER BANK1:SSPSTAT.SMP 7 Sample bit BANK1:SSPSTAT.CKE 6 SPI Clock Edge Select bit BANK1:SSPSTAT.D_A 5 Data/Address bit (I2C mode only) BANK1:SSPSTAT.P 4 STOP bit (I2C mode only) BANK1:SSPSTAT.S 3 START bit (I2C mode only) BANK1:SSPSTAT.R_W 2 Read/Write bit information (I2C mode only) BANK1:SSPSTAT.UA 1 Update Address bit (10-bit I2C mode only) BANK1:SSPSTAT.BF 0 Buffer Full Status bit BANK1:RESERVED0095 0x0095 RESERVED BANK1:RESERVED0096 0x0096 RESERVED BANK1:RESERVED0097 0x0097 RESERVED BANK1:TXSTA 0x0098 TRANSMIT STATUS AND CONTROL REGISTER BANK1:TXSTA.CSRC 7 Clock Source Select bit BANK1:TXSTA.TX9 6 9-bit Transmit Enable bit BANK1:TXSTA.TXEN 5 Transmit Enable bit BANK1:TXSTA.SYNC 4 USART Mode Select bit BANK1:TXSTA.BRGH 2 High Baud Rate Select bit BANK1:TXSTA.TRMT 1 Transmit Shift Register Status bit BANK1:TXSTA.TX9D 0 9th bit of Transmit Data, can be parity bit BANK1:SPBRG 0x0099 Baud Rate Generator Register BANK1:RESERVED009A 0x009A RESERVED BANK1:RESERVED009B 0x009B RESERVED BANK1:CMCON 0x009C CMCON REGISTER BANK1:CMCON.C2OUT 7 Comparator 2 Output bit BANK1:CMCON.C1OUT 6 Comparator 1 Output bit BANK1:CMCON.C2INV 5 Comparator 2 Output Inversion bit BANK1:CMCON.C1INV 4 Comparator 1 Output Inversion bit BANK1:CMCON.CIS 3 Comparator Input Switch bit BANK1:CMCON.CM2 2 Comparator Mode bit 2 BANK1:CMCON.CM1 1 Comparator Mode bit 1 BANK1:CMCON.CM0 0 Comparator Mode bit 0 BANK1:CVRCON 0x009D CVRCON CONTROL REGISTER BANK1:CVRCON.CVREN 7 Comparator Voltage Reference Enable bit BANK1:CVRCON.CVROE 6 Comparator VREF Output Enable bit BANK1:CVRCON.CVRR 5 Comparator VREF Range Selection bit BANK1:CVRCON.CVR3 3 Comparator VREF Value Selection bit 3 BANK1:CVRCON.CVR2 2 Comparator VREF Value Selection bit 2 BANK1:CVRCON.CVR1 1 Comparator VREF Value Selection bit 1 BANK1:CVRCON.CVR0 0 Comparator VREF Value Selection bit 0 BANK1:ADRESL 0x009E A/D Result Register Low Byte BANK1:ADCON1 0x009F ADCON1 REGISTER BANK1:ADCON1.ADFM 7 A/D Result format select BANK1:ADCON1.ADCS2 6 A/D Conversion Clock Select bit BANK1:ADCON1.PCFG3 3 A/D Port Configuration Control bit 3 BANK1:ADCON1.PCFG2 2 A/D Port Configuration Control bit 2 BANK1:ADCON1.PCFG1 1 A/D Port Configuration Control bit 1 BANK1:ADCON1.PCFG0 0 A/D Port Configuration Control bit 0 ; BANK2 (0x0100:0x0180) BANK2:INDF 0x0100 INDF (not a physical register) BANK2:TMR0 0x0101 Timer0 module's register BANK2:PCL 0x0102 Program Counter's (PC) Least Significant Byte BANK2:STATUS 0x0103 STATUS REGISTER BANK2:STATUS.IRP 7 RegIster Bank Select bit BANK2:STATUS.RP1 6 Register Bank Select bit 1 BANK2:STATUS.RP0 5 Register Bank Select bit 0 BANK2:STATUS.TO 4 Time-out bit BANK2:STATUS.PD 3 Power-down bit BANK2:STATUS.Z 2 Zero bit BANK2:STATUS.DC 1 Digit carry/borrow bit BANK2:STATUS.C 0 Carry/borrow bit BANK2:FSR 0x0104 Indirect data memory address pointer BANK2:RESERVED0105 0x0105 RESERVED BANK2:PORTB 0x0106 PORTB register BANK2:PORTB.RB7 7 PORTB bit 7 BANK2:PORTB.RB6 6 PORTB bit 6 BANK2:PORTB.RB5 5 PORTB bit 5 BANK2:PORTB.RB4 4 PORTB bit 4 BANK2:PORTB.RB3 3 PORTB bit 3 BANK2:PORTB.RB2 2 PORTB bit 2 BANK2:PORTB.RB1 1 PORTB bit 1 BANK2:PORTB.RB0 0 PORTB bit 0 BANK2:RESERVED0107 0x0107 RESERVED BANK2:RESERVED0108 0x0108 RESERVED BANK2:RESERVED0109 0x0109 RESERVED BANK2:PCLATH 0x010A Write Buffer for the upper 5 bits of the Program Counter BANK2:INTCON 0x010B INTCON REGISTER BANK2:INTCON.GIE 7 Global Interrupt Enable bit BANK2:INTCON.PEIE 6 Peripheral Interrupt Enable bit BANK2:INTCON.TMR0IE 5 TMR0 Overflow Interrupt Enable bit BANK2:INTCON.INTE 4 RB0/INT External Interrupt Enable bit BANK2:INTCON.RBIE 3 RB Port Change Interrupt Enable bit BANK2:INTCON.TMR0IF 2 TMR0 Overflow Interrupt Flag bit BANK2:INTCON.INTF 1 RB0/INT External Interrupt Flag bit BANK2:INTCON.RBIF 0 RB Port Change Interrupt Flag bit BANK2:EEDATA 0x010C EEPROM data register Low Byte BANK2:EEADR 0x010D EEPROM address register Low Byte BANK2:EEDATH 0x010E EEPROM data register high byte BANK2:EEADRH 0x010F EEPROM address register high byte ; BANK3 (0x0180:0x0200) BANK3:INDF 0x0180 INDF (not a physical register) BANK3:OPTION 0x0181 OPTION REGISTER BANK3:OPTION.RBPU 7 PORTB Pull-up Enable bit BANK3:OPTION.INTEDG 6 Interrupt Edge Select bit BANK3:OPTION.T0CS 5 TMR0 Clock Source Select bit BANK3:OPTION.T0SE 4 TMR0 Source Edge Select bit BANK3:OPTION.PSA 3 Prescaler Assignment bit BANK3:OPTION.PS2 2 Prescaler Rate Select bit 2 BANK3:OPTION.PS1 1 Prescaler Rate Select bit 1 BANK3:OPTION.PS0 0 Prescaler Rate Select bit 0 BANK3:PCL 0x0182 Program Counter's (PC) Least Significant Byte BANK3:STATUS 0x0183 STATUS REGISTER BANK3:STATUS.IRP 7 RegIster Bank Select bit BANK3:STATUS.RP1 6 Register Bank Select bit 1 BANK3:STATUS.RP0 5 Register Bank Select bit 0 BANK3:STATUS.TO 4 Time-out bit BANK3:STATUS.PD 3 Power-down bit BANK3:STATUS.Z 2 Zero bit BANK3:STATUS.DC 1 Digit carry/borrow bit BANK3:STATUS.C 0 Carry/borrow bit BANK3:FSR 0x0184 Indirect data memory address pointer BANK3:RESERVED0185 0x0185 RESERVED BANK3:TRISB 0x0186 PORTB Data Direction Register BANK3:TRISB.TRISB7 7 PORTB Data Direction Register bit 7 BANK3:TRISB.TRISB6 6 PORTB Data Direction Register bit 6 BANK3:TRISB.TRISB5 5 PORTB Data Direction Register bit 5 BANK3:TRISB.TRISB4 4 PORTB Data Direction Register bit 4 BANK3:TRISB.TRISB3 3 PORTB Data Direction Register bit 3 BANK3:TRISB.TRISB2 2 PORTB Data Direction Register bit 2 BANK3:TRISB.TRISB1 1 PORTB Data Direction Register bit 1 BANK3:TRISB.TRISB0 0 PORTB Data Direction Register bit 0 BANK3:RESERVED0187 0x0187 RESERVED BANK3:RESERVED0188 0x0188 RESERVED BANK3:RESERVED0189 0x0189 RESERVED BANK3:PCLATH 0x018A Write Buffer for the upper 5 bits of the Program Counter BANK3:INTCON 0x018B INTCON REGISTER BANK3:INTCON.GIE 7 Global Interrupt Enable bit BANK3:INTCON.PEIE 6 Peripheral Interrupt Enable bit BANK3:INTCON.TMR0IE 5 TMR0 Overflow Interrupt Enable bit BANK3:INTCON.INTE 4 RB0/INT External Interrupt Enable bit BANK3:INTCON.RBIE 3 RB Port Change Interrupt Enable bit BANK3:INTCON.TMR0IF 2 TMR0 Overflow Interrupt Flag bit BANK3:INTCON.INTF 1 RB0/INT External Interrupt Flag bit BANK3:INTCON.RBIF 0 RB Port Change Interrupt Flag bit BANK3:EECON1 0x018C EECON1 REGISTER BANK3:EECON1.EEPGD 7 Program/Data EEPROM Select bit BANK3:EECON1.WRERR 3 EEPROM Error Flag bit BANK3:EECON1.WREN 2 EEPROM Write Enable bit BANK3:EECON1.WR 1 Write Control bit BANK3:EECON1.RD 0 Read Control bit BANK3:EECON2 0x018D EEPROM control register2 (not a physical register) BANK3:RESERVED018E 0x018E RESERVED BANK3:RESERVED018F 0x018F RESERVED .16F876A ; http://www.microchip.com/download/lit/pline/picmicro/families/16f87x/39582a.pdf ; PIC16F87XA.pdf ; MEMORY MAP ; BANK_0 area DATA FSR_ 0x0000:0x0020 area DATA Gen_Purp 0x0020:0x0080 General Purpose Register area DATA MEM_Program0 0x0080:0x0800 On-chip Program Memory (Page 0) area DATA MEM_Program1 0x0800:0x1000 On-chip Program Memory (Page 1) area DATA MEM_Program2 0x1000:0x1800 On-chip Program Memory (Page 2) area DATA MEM_Program3 0x1800:0x2000 On-chip Program Memory (Page 3) ; BANK_1 ; area DATA FSR_ 0x0080:0x00A0 ; area DATA Gen_Purp 0x00A0:0x00F0 General Purpose Register ; area DATA Gen_Purp_BANK0 0x00F0:0x0100 accesses 70h-7Fh ; area DATA MEM_Program0 0x0100:0x0800 On-chip Program Memory (Page 0) ; area DATA MEM_Program1 0x0800:0x1000 On-chip Program Memory (Page 1) ; area DATA MEM_Program2 0x1000:0x1800 On-chip Program Memory (Page 2) ; area DATA MEM_Program3 0x1800:0x2000 On-chip Program Memory (Page 3) ; BANK_2 ; area DATA FSR_ 0x0100:0x0110 ; area DATA Gen_Purp0 0x0110:0x0120 General Purpose Register 16 Bytes ; area DATA Gen_Purp1 0x0120:0x0170 General Purpose Register 80 Bytes ; area DATA Gen_Purp_BANK0 0x0170:0x0180 accesses 70h-7Fh ; area DATA MEM_Program0 0x0180:0x0800 On-chip Program Memory (Page 0) ; area DATA MEM_Program1 0x0800:0x1000 On-chip Program Memory (Page 1) ; area DATA MEM_Program2 0x1000:0x1800 On-chip Program Memory (Page 2) ; area DATA MEM_Program3 0x1800:0x2000 On-chip Program Memory (Page 3) ; BANK_3 ; area DATA FSR_ 0x0180:0x0190 ; area DATA Gen_Purp0 0x0190:0x01A0 General Purpose Register 16 Bytes ; area DATA Gen_Purp1 0x01A0:0x01F0 General Purpose Register 80 Bytes ; area DATA Gen_Purp_BANK0 0x01F0:0x0200 accesses 70h-7Fh ; area DATA MEM_Program0 0x0200:0x0800 On-chip Program Memory (Page 0) ; area DATA MEM_Program1 0x0800:0x1000 On-chip Program Memory (Page 1) ; area DATA MEM_Program2 0x1000:0x1800 On-chip Program Memory (Page 2) ; area DATA MEM_Program3 0x1800:0x2000 On-chip Program Memory (Page 3) ; Interrupt and reset vector assignments interrupt RESET 0x0000 RESET ; INPUT/OUTPUT PORTS ; BANK0 (0x0000:0x0080) BANK0:INDF 0x0000 INDF (not a physical register) BANK0:TMR0 0x0001 Timer0 module's register BANK0:PCL 0x0002 Program Counter (PC) Least Significant Byte BANK0:STATUS 0x0003 STATUS REGISTER BANK0:STATUS.IRP 7 RegIster Bank Select bit BANK0:STATUS.RP1 6 Register Bank Select bit 1 BANK0:STATUS.RP0 5 Register Bank Select bit 0 BANK0:STATUS.TO 4 Time-out bit BANK0:STATUS.PD 3 Power-down bit BANK0:STATUS.Z 2 Zero bit BANK0:STATUS.DC 1 Digit carry/borrow bit BANK0:STATUS.C 0 Carry/borrow bit BANK0:FSR 0x0004 Indirect data memory address pointer BANK0:PORTA 0x0005 PORTA register BANK0:PORTA.RA5 5 PORTA bit 5 BANK0:PORTA.RA4 4 PORTA bit 4 BANK0:PORTA.RA3 3 PORTA bit 3 BANK0:PORTA.RA2 2 PORTA bit 2 BANK0:PORTA.RA1 1 PORTA bit 1 BANK0:PORTA.RA0 0 PORTA bit 0 BANK0:PORTB 0x0006 PORTB register BANK0:PORTB.RB7 7 PORTB bit 7 BANK0:PORTB.RB6 6 PORTB bit 6 BANK0:PORTB.RB5 5 PORTB bit 5 BANK0:PORTB.RB4 4 PORTB bit 4 BANK0:PORTB.RB3 3 PORTB bit 3 BANK0:PORTB.RB2 2 PORTB bit 2 BANK0:PORTB.RB1 1 PORTB bit 1 BANK0:PORTB.RB0 0 PORTB bit 0 BANK0:PORTC 0x0007 PORTC register BANK0:PORTC.RC7 7 PORTC bit 7 BANK0:PORTC.RC6 6 PORTC bit 6 BANK0:PORTC.RC5 5 PORTC bit 5 BANK0:PORTC.RC4 4 PORTC bit 4 BANK0:PORTC.RC3 3 PORTC bit 3 BANK0:PORTC.RC2 2 PORTC bit 2 BANK0:PORTC.RC1 1 PORTC bit 1 BANK0:PORTC.RC0 0 PORTC bit 0 BANK0:RESERVED0008 0x0008 RESERVED BANK0:RESERVED0009 0x0009 RESERVED BANK0:PCLATH 0x000A Write Buffer for the upper 5 bits of the Program Counter BANK0:INTCON 0x000B INTCON REGISTER BANK0:INTCON.GIE 7 Global Interrupt Enable bit BANK0:INTCON.PEIE 6 Peripheral Interrupt Enable bit BANK0:INTCON.TMR0IE 5 TMR0 Overflow Interrupt Enable bit BANK0:INTCON.INTE 4 RB0/INT External Interrupt Enable bit BANK0:INTCON.RBIE 3 RB Port Change Interrupt Enable bit BANK0:INTCON.TMR0IF 2 TMR0 Overflow Interrupt Flag bit BANK0:INTCON.INTF 1 RB0/INT External Interrupt Flag bit BANK0:INTCON.RBIF 0 RB Port Change Interrupt Flag bit BANK0:PIR1 0x000C PIR1 REGISTER BANK0:PIR1.ADIF 6 A/D Converter Interrupt Flag bit BANK0:PIR1.RCIF 5 USART Receive Interrupt Flag bit BANK0:PIR1.TXIF 4 USART Transmit Interrupt Flag bit BANK0:PIR1.SSPIF 3 Synchronous Serial Port Interrupt Flag bit BANK0:PIR1.CCP1IF 2 CCP1 Interrupt Flag bit BANK0:PIR1.TMR2IF 1 TMR2 to PR2 Match Interrupt Flag bit BANK0:PIR1.TMR1IF 0 TMR1 Overflow Interrupt Flag bit BANK0:PIR2 0x000D PIR2 REGISTER BANK0:PIR2.CMIF 6 Comparator Interrupt Flag bit BANK0:PIR2.EEIF 4 EEPROM Write Operation Interrupt Flag bit BANK0:PIR2.BCLIF 3 Bus Collision Interrupt Flag bit BANK0:PIR2.CCP2IF 0 CCP2 Interrupt Flag bit BANK0:TMR1L 0x000E Holding register for the Least Significant Byte of the 16-bit TMR1 register BANK0:TMR1H 0x000F Holding register for the Most Significant Byte of the 16-bit TMR1 register BANK0:T1CON 0x0010 TIMER1 CONTROL REGISTER BANK0:T1CON.T1CKPS1 5 Timer1 Input Clock Prescale Select bit 1 BANK0:T1CON.T1CKPS0 4 Timer1 Input Clock Prescale Select bit 0 BANK0:T1CON.T1OSCEN 3 Timer1 Oscillator Enable Control bit BANK0:T1CON.T1SYNC 2 Timer1 External Clock Input Synchronization Control bit BANK0:T1CON.TMR1CS 1 Timer1 Clock Source Select bit BANK0:T1CON.TMR1ON 0 Timer1 On bit BANK0:TMR2 0x0011 Timer2 module register BANK0:T2CON 0x0012 TIMER2 CONTROL REGISTER BANK0:T2CON.TOUTPS3 6 Timer2 Output Postscale Select bit 3 BANK0:T2CON.TOUTPS2 5 Timer2 Output Postscale Select bit 2 BANK0:T2CON.TOUTPS1 4 Timer2 Output Postscale Select bit 1 BANK0:T2CON.TOUTPS0 3 Timer2 Output Postscale Select bit 0 BANK0:T2CON.TMR2ON 2 Timer2 On bit BANK0:T2CON.T2CKPS1 1 Timer2 Clock Prescale Select bit 1 BANK0:T2CON.T2CKPS0 0 Timer2 Clock Prescale Select bit 0 BANK0:SSPBUF 0x0013 Synchronous Serial Port Receive Buffer/Transmit Register BANK0:SSPCON 0x0014 SYNC SERIAL PORT CONTROL REGISTER BANK0:SSPCON.WCOL 7 Write Collision Detect bit BANK0:SSPCON.SSPOV 6 Receive Overflow Indicator bit BANK0:SSPCON.SSPEN 5 Synchronous Serial Port Enable bit BANK0:SSPCON.CKP 4 Clock Polarity Select bit BANK0:SSPCON.SSPM3 3 Synchronous Serial Port Mode Select bit 3 BANK0:SSPCON.SSPM2 2 Synchronous Serial Port Mode Select bit 2 BANK0:SSPCON.SSPM1 1 Synchronous Serial Port Mode Select bit 1 BANK0:SSPCON.SSPM0 0 Synchronous Serial Port Mode Select bit 0 BANK0:CCPR1L 0x0015 Capture/Compare/PWM1 Register1 (LSB) BANK0:CCPR1H 0x0016 Capture/Compare/PWM1 Register1 (MSB) BANK0:CCP1CON 0x0017 CCP1CON REGISTER BANK0:CCP1CON.CCP1X 5 PWM Least Significant bit BANK0:CCP1CON.CCP1Y 4 PWM Least Significant bit BANK0:CCP1CON.CCP1M3 3 CCP1 Mode Select bit 3 BANK0:CCP1CON.CCP1M2 2 CCP1 Mode Select bit 2 BANK0:CCP1CON.CCP1M1 1 CCP1 Mode Select bit 1 BANK0:CCP1CON.CCP1M0 0 CCP1 Mode Select bit 0 BANK0:RCSTA 0x0018 RECEIVE STATUS AND CONTROL REGISTER BANK0:RCSTA.SPEN 7 Serial Port Enable bit BANK0:RCSTA.RX9 6 9-bit Receive Enable bit BANK0:RCSTA.SREN 5 Single Receive Enable bit BANK0:RCSTA.CREN 4 Continuous Receive Enable bit BANK0:RCSTA.ADDEN 3 Address Detect Enable bit BANK0:RCSTA.FERR 2 Framing Error bit BANK0:RCSTA.OERR 1 Overrun Error bit BANK0:RCSTA.RX9D 0 9th bit of received data BANK0:TXREG 0x0019 USART Transmit Data Register BANK0:RCREG 0x001A USART Receive Data Register BANK0:CCPR2L 0x001B Capture/Compare/PWM2 Register2 (LSB) BANK0:CCPR2H 0x001C Capture/Compare/PWM2 Register2 (MSB) BANK0:CCP2CON 0x001D CCP2CON REGISTER BANK0:CCP2CON.CCP2X 5 PWM Least Significant bit BANK0:CCP2CON.CCP2Y 4 PWM Least Significant bit BANK0:CCP2CON.CCP2M3 3 CCP2 Mode Select bit 3 BANK0:CCP2CON.CCP2M2 2 CCP2 Mode Select bit 2 BANK0:CCP2CON.CCP2M1 1 CCP2 Mode Select bit 1 BANK0:CCP2CON.CCP2M0 0 CCP2 Mode Select bit 0 BANK0:ADRESH 0x001E A/D Result Register High Byte BANK0:ADCON0 0x001F ADCON0 REGISTER BANK0:ADCON0.ADCS1 7 A/D Conversion Clock Select bit 1 BANK0:ADCON0.ADCS0 6 A/D Conversion Clock Select bit 0 BANK0:ADCON0.CHS2 5 Analog Channel Select bit 2 BANK0:ADCON0.CHS1 4 Analog Channel Select bit 1 BANK0:ADCON0.CHS0 3 Analog Channel Select bit 0 BANK0:ADCON0.GO_DONE 2 A/D Conversion Status bit BANK0:ADCON0.ADON 0 A/D On bit ; BANK1 (0x0080:0x0100) BANK1:INDF 0x0080 INDF (not a physical register) BANK1:OPTION 0x0081 OPTION REGISTER BANK1:OPTION.RBPU 7 PORTB Pull-up Enable bit BANK1:OPTION.INTEDG 6 Interrupt Edge Select bit BANK1:OPTION.T0CS 5 TMR0 Clock Source Select bit BANK1:OPTION.T0SE 4 TMR0 Source Edge Select bit BANK1:OPTION.PSA 3 Prescaler Assignment bit BANK1:OPTION.PS2 2 Prescaler Rate Select bit 2 BANK1:OPTION.PS1 1 Prescaler Rate Select bit 1 BANK1:OPTION.PS0 0 Prescaler Rate Select bit 0 BANK1:PCL 0x0082 Program Counter's (PC) Least Significant Byte BANK1:STATUS 0x0083 STATUS REGISTER BANK1:STATUS.IRP 7 RegIster Bank Select bit BANK1:STATUS.RP1 6 Register Bank Select bit 1 BANK1:STATUS.RP0 5 Register Bank Select bit 0 BANK1:STATUS.TO 4 Time-out bit BANK1:STATUS.PD 3 Power-down bit BANK1:STATUS.Z 2 Zero bit BANK1:STATUS.DC 1 Digit carry/borrow bit BANK1:STATUS.C 0 Carry/borrow bit BANK1:FSR 0x0084 Indirect data memory address pointer BANK1:TRISA 0x0085 PORTA Data Direction Register BANK1:TRISA.TRISA5 5 PORTA Data Direction Register bit 5 BANK1:TRISA.TRISA4 4 PORTA Data Direction Register bit 4 BANK1:TRISA.TRISA3 3 PORTA Data Direction Register bit 3 BANK1:TRISA.TRISA2 2 PORTA Data Direction Register bit 2 BANK1:TRISA.TRISA1 1 PORTA Data Direction Register bit 1 BANK1:TRISA.TRISA0 0 PORTA Data Direction Register bit 0 BANK1:TRISB 0x0086 PORTB Data Direction Register BANK1:TRISB.TRISB7 7 PORTB Data Direction Register bit 7 BANK1:TRISB.TRISB6 6 PORTB Data Direction Register bit 6 BANK1:TRISB.TRISB5 5 PORTB Data Direction Register bit 5 BANK1:TRISB.TRISB4 4 PORTB Data Direction Register bit 4 BANK1:TRISB.TRISB3 3 PORTB Data Direction Register bit 3 BANK1:TRISB.TRISB2 2 PORTB Data Direction Register bit 2 BANK1:TRISB.TRISB1 1 PORTB Data Direction Register bit 1 BANK1:TRISB.TRISB0 0 PORTB Data Direction Register bit 0 BANK1:TRISC 0x0087 PORTC Data Direction Register BANK1:TRISC.TRISC7 7 PORTC Data Direction Register bit 7 BANK1:TRISC.TRISC6 6 PORTC Data Direction Register bit 6 BANK1:TRISC.TRISC5 5 PORTC Data Direction Register bit 5 BANK1:TRISC.TRISC4 4 PORTC Data Direction Register bit 4 BANK1:TRISC.TRISC3 3 PORTC Data Direction Register bit 3 BANK1:TRISC.TRISC2 2 PORTC Data Direction Register bit 2 BANK1:TRISC.TRISC1 1 PORTC Data Direction Register bit 1 BANK1:TRISC.TRISC0 0 PORTC Data Direction Register bit 0 BANK1:RESERVED0088 0x0088 RESERVED BANK1:RESERVED0089 0x0089 RESERVED BANK1:PCLATH 0x008A Write Buffer for the upper 5 bits of the Program Counter BANK1:INTCON 0x008B INTCON REGISTER BANK1:INTCON.GIE 7 Global Interrupt Enable bit BANK1:INTCON.PEIE 6 Peripheral Interrupt Enable bit BANK1:INTCON.TMR0IE 5 TMR0 Overflow Interrupt Enable bit BANK1:INTCON.INTE 4 RB0/INT External Interrupt Enable bit BANK1:INTCON.RBIE 3 RB Port Change Interrupt Enable bit BANK1:INTCON.TMR0IF 2 TMR0 Overflow Interrupt Flag bit BANK1:INTCON.INTF 1 RB0/INT External Interrupt Flag bit BANK1:INTCON.RBIF 0 RB Port Change Interrupt Flag bit BANK1:PIE1 0x008C PIE1 REGISTER BANK1:PIE1.ADIE 6 A/D Converter Interrupt Enable bit BANK1:PIE1.RCIE 5 USART Receive Interrupt Enable bit BANK1:PIE1.TXIE 4 USART Transmit Interrupt Enable bit BANK1:PIE1.SSPIE 3 Synchronous Serial Port Interrupt Enable bit BANK1:PIE1.CCP1IE 2 CCP1 Interrupt Enable bit BANK1:PIE1.TMR2IE 1 TMR2 to PR2 Match Interrupt Enable bit BANK1:PIE1.TMR1IE 0 TMR1 Overflow Interrupt Enable bit BANK1:PIE2 0x008D PIE2 REGISTER BANK1:PIE2.CMIE 6 Comparator Interrupt Enable bit BANK1:PIE2.EEIE 4 EEPROM Write Operation Interrupt Enable BANK1:PIE2.BCLIE 3 Bus Collision Interrupt Enable BANK1:PIE2.CCP2IE 0 CCP2 Interrupt Enable bit BANK1:PCON 0x008E PCON REGISTER BANK1:PCON.POR 1 Power-on Reset Status bit BANK1:PCON.BOR 0 Brown-out Reset Status bit BANK1:RESERVED008F 0x008F RESERVED BANK1:RESERVED0090 0x0090 RESERVED BANK1:SSPCON2 0x0091 SYNC SERIAL PORT CONTROL REGISTER2 BANK1:SSPCON2.GCEN 7 General Call Enable bit (In I2C Slave mode only) BANK1:SSPCON2.ACKSTAT 6 Acknowledge Status bit (In I2C Master mode only) BANK1:SSPCON2.ACKDT 5 Acknowledge Data bit (In I2C Master mode only) BANK1:SSPCON2.ACKEN 4 Acknowledge Sequence Enable bit (In I2C Master mode only) BANK1:SSPCON2.RCEN 3 Receive Enable bit (In I2C Master mode only) BANK1:SSPCON2.PEN 2 STOP Condition Enable bit (In I2C Master mode only) BANK1:SSPCON2.RSEN 1 Repeated START Condition Enabled bit (In I2C Master mode only) BANK1:SSPCON2.SEN 0 START Condition Enabled bit (In I2C Master mode only) BANK1:PR2 0x0092 Timer2 Period Register BANK1:SSPADD 0x0093 Synchronous Serial Port (I2C mode) Address Register BANK1:SSPSTAT 0x0094 SYNC SERIAL PORT STATUS REGISTER BANK1:SSPSTAT.SMP 7 Sample bit BANK1:SSPSTAT.CKE 6 SPI Clock Edge Select bit BANK1:SSPSTAT.D_A 5 Data/Address bit (I2C mode only) BANK1:SSPSTAT.P 4 STOP bit (I2C mode only) BANK1:SSPSTAT.S 3 START bit (I2C mode only) BANK1:SSPSTAT.R_W 2 Read/Write bit information (I2C mode only) BANK1:SSPSTAT.UA 1 Update Address bit (10-bit I2C mode only) BANK1:SSPSTAT.BF 0 Buffer Full Status bit BANK1:RESERVED0095 0x0095 RESERVED BANK1:RESERVED0096 0x0096 RESERVED BANK1:RESERVED0097 0x0097 RESERVED BANK1:TXSTA 0x0098 TRANSMIT STATUS AND CONTROL REGISTER BANK1:TXSTA.CSRC 7 Clock Source Select bit BANK1:TXSTA.TX9 6 9-bit Transmit Enable bit BANK1:TXSTA.TXEN 5 Transmit Enable bit BANK1:TXSTA.SYNC 4 USART Mode Select bit BANK1:TXSTA.BRGH 2 High Baud Rate Select bit BANK1:TXSTA.TRMT 1 Transmit Shift Register Status bit BANK1:TXSTA.TX9D 0 9th bit of Transmit Data, can be parity bit BANK1:SPBRG 0x0099 Baud Rate Generator Register BANK1:RESERVED009A 0x009A RESERVED BANK1:RESERVED009B 0x009B RESERVED BANK1:CMCON 0x009C CMCON REGISTER BANK1:CMCON.C2OUT 7 Comparator 2 Output bit BANK1:CMCON.C1OUT 6 Comparator 1 Output bit BANK1:CMCON.C2INV 5 Comparator 2 Output Inversion bit BANK1:CMCON.C1INV 4 Comparator 1 Output Inversion bit BANK1:CMCON.CIS 3 Comparator Input Switch bit BANK1:CMCON.CM2 2 Comparator Mode bit 2 BANK1:CMCON.CM1 1 Comparator Mode bit 1 BANK1:CMCON.CM0 0 Comparator Mode bit 0 BANK1:CVRCON 0x009D CVRCON CONTROL REGISTER BANK1:CVRCON.CVREN 7 Comparator Voltage Reference Enable bit BANK1:CVRCON.CVROE 6 Comparator VREF Output Enable bit BANK1:CVRCON.CVRR 5 Comparator VREF Range Selection bit BANK1:CVRCON.CVR3 3 Comparator VREF Value Selection bit 3 BANK1:CVRCON.CVR2 2 Comparator VREF Value Selection bit 2 BANK1:CVRCON.CVR1 1 Comparator VREF Value Selection bit 1 BANK1:CVRCON.CVR0 0 Comparator VREF Value Selection bit 0 BANK1:ADRESL 0x009E A/D Result Register Low Byte BANK1:ADCON1 0x009F ADCON1 REGISTER BANK1:ADCON1.ADFM 7 A/D Result format select BANK1:ADCON1.ADCS2 6 A/D Conversion Clock Select bit BANK1:ADCON1.PCFG3 3 A/D Port Configuration Control bit 3 BANK1:ADCON1.PCFG2 2 A/D Port Configuration Control bit 2 BANK1:ADCON1.PCFG1 1 A/D Port Configuration Control bit 1 BANK1:ADCON1.PCFG0 0 A/D Port Configuration Control bit 0 ; BANK2 (0x0100:0x0180) BANK2:INDF 0x0100 INDF (not a physical register) BANK2:TMR0 0x0101 Timer0 module's register BANK2:PCL 0x0102 Program Counter's (PC) Least Significant Byte BANK2:STATUS 0x0103 STATUS REGISTER BANK2:STATUS.IRP 7 RegIster Bank Select bit BANK2:STATUS.RP1 6 Register Bank Select bit 1 BANK2:STATUS.RP0 5 Register Bank Select bit 0 BANK2:STATUS.TO 4 Time-out bit BANK2:STATUS.PD 3 Power-down bit BANK2:STATUS.Z 2 Zero bit BANK2:STATUS.DC 1 Digit carry/borrow bit BANK2:STATUS.C 0 Carry/borrow bit BANK2:FSR 0x0104 Indirect data memory address pointer BANK2:RESERVED0105 0x0105 RESERVED BANK2:PORTB 0x0106 PORTB register BANK2:PORTB.RB7 7 PORTB bit 7 BANK2:PORTB.RB6 6 PORTB bit 6 BANK2:PORTB.RB5 5 PORTB bit 5 BANK2:PORTB.RB4 4 PORTB bit 4 BANK2:PORTB.RB3 3 PORTB bit 3 BANK2:PORTB.RB2 2 PORTB bit 2 BANK2:PORTB.RB1 1 PORTB bit 1 BANK2:PORTB.RB0 0 PORTB bit 0 BANK2:RESERVED0107 0x0107 RESERVED BANK2:RESERVED0108 0x0108 RESERVED BANK2:RESERVED0109 0x0109 RESERVED BANK2:PCLATH 0x010A Write Buffer for the upper 5 bits of the Program Counter BANK2:INTCON 0x010B INTCON REGISTER BANK2:INTCON.GIE 7 Global Interrupt Enable bit BANK2:INTCON.PEIE 6 Peripheral Interrupt Enable bit BANK2:INTCON.TMR0IE 5 TMR0 Overflow Interrupt Enable bit BANK2:INTCON.INTE 4 RB0/INT External Interrupt Enable bit BANK2:INTCON.RBIE 3 RB Port Change Interrupt Enable bit BANK2:INTCON.TMR0IF 2 TMR0 Overflow Interrupt Flag bit BANK2:INTCON.INTF 1 RB0/INT External Interrupt Flag bit BANK2:INTCON.RBIF 0 RB Port Change Interrupt Flag bit BANK2:EEDATA 0x010C EEPROM data register Low Byte BANK2:EEADR 0x010D EEPROM address register Low Byte BANK2:EEDATH 0x010E EEPROM data register high byte BANK2:EEADRH 0x010F EEPROM address register high byte ; BANK3 (0x0180:0x0200) BANK3:INDF 0x0180 INDF (not a physical register) BANK3:OPTION 0x0181 OPTION REGISTER BANK3:OPTION.RBPU 7 PORTB Pull-up Enable bit BANK3:OPTION.INTEDG 6 Interrupt Edge Select bit BANK3:OPTION.T0CS 5 TMR0 Clock Source Select bit BANK3:OPTION.T0SE 4 TMR0 Source Edge Select bit BANK3:OPTION.PSA 3 Prescaler Assignment bit BANK3:OPTION.PS2 2 Prescaler Rate Select bit 2 BANK3:OPTION.PS1 1 Prescaler Rate Select bit 1 BANK3:OPTION.PS0 0 Prescaler Rate Select bit 0 BANK3:PCL 0x0182 Program Counter's (PC) Least Significant Byte BANK3:STATUS 0x0183 STATUS REGISTER BANK3:STATUS.IRP 7 RegIster Bank Select bit BANK3:STATUS.RP1 6 Register Bank Select bit 1 BANK3:STATUS.RP0 5 Register Bank Select bit 0 BANK3:STATUS.TO 4 Time-out bit BANK3:STATUS.PD 3 Power-down bit BANK3:STATUS.Z 2 Zero bit BANK3:STATUS.DC 1 Digit carry/borrow bit BANK3:STATUS.C 0 Carry/borrow bit BANK3:FSR 0x0184 Indirect data memory address pointer BANK3:RESERVED0185 0x0185 RESERVED BANK3:TRISB 0x0186 PORTB Data Direction Register BANK3:TRISB.TRISB7 7 PORTB Data Direction Register bit 7 BANK3:TRISB.TRISB6 6 PORTB Data Direction Register bit 6 BANK3:TRISB.TRISB5 5 PORTB Data Direction Register bit 5 BANK3:TRISB.TRISB4 4 PORTB Data Direction Register bit 4 BANK3:TRISB.TRISB3 3 PORTB Data Direction Register bit 3 BANK3:TRISB.TRISB2 2 PORTB Data Direction Register bit 2 BANK3:TRISB.TRISB1 1 PORTB Data Direction Register bit 1 BANK3:TRISB.TRISB0 0 PORTB Data Direction Register bit 0 BANK3:RESERVED0187 0x0187 RESERVED BANK3:RESERVED0188 0x0188 RESERVED BANK3:RESERVED0189 0x0189 RESERVED BANK3:PCLATH 0x018A Write Buffer for the upper 5 bits of the Program Counter BANK3:INTCON 0x018B INTCON REGISTER BANK3:INTCON.GIE 7 Global Interrupt Enable bit BANK3:INTCON.PEIE 6 Peripheral Interrupt Enable bit BANK3:INTCON.TMR0IE 5 TMR0 Overflow Interrupt Enable bit BANK3:INTCON.INTE 4 RB0/INT External Interrupt Enable bit BANK3:INTCON.RBIE 3 RB Port Change Interrupt Enable bit BANK3:INTCON.TMR0IF 2 TMR0 Overflow Interrupt Flag bit BANK3:INTCON.INTF 1 RB0/INT External Interrupt Flag bit BANK3:INTCON.RBIF 0 RB Port Change Interrupt Flag bit BANK3:EECON1 0x018C EECON1 REGISTER BANK3:EECON1.EEPGD 7 Program/Data EEPROM Select bit BANK3:EECON1.WRERR 3 EEPROM Error Flag bit BANK3:EECON1.WREN 2 EEPROM Write Enable bit BANK3:EECON1.WR 1 Write Control bit BANK3:EECON1.RD 0 Read Control bit BANK3:EECON2 0x018D EEPROM control register2 (not a physical register) BANK3:RESERVED018E 0x018E RESERVED BANK3:RESERVED018F 0x018F RESERVED .16F877A ; http://www.microchip.com/download/lit/pline/picmicro/families/16f87x/39582a.pdf ; PIC16F87XA.pdf ; MEMORY MAP ; BANK_0 area DATA FSR_ 0x0000:0x0020 area DATA Gen_Purp 0x0020:0x0080 General Purpose Register area DATA MEM_Program0 0x0080:0x0800 On-chip Program Memory (Page 0) area DATA MEM_Program1 0x0800:0x1000 On-chip Program Memory (Page 1) area DATA MEM_Program2 0x1000:0x1800 On-chip Program Memory (Page 2) area DATA MEM_Program3 0x1800:0x2000 On-chip Program Memory (Page 3) ; BANK_1 ; area DATA FSR_ 0x0080:0x00A0 ; area DATA Gen_Purp 0x00A0:0x00F0 General Purpose Register ; area DATA Gen_Purp_BANK0 0x00F0:0x0100 accesses 70h-7Fh ; area DATA MEM_Program0 0x0100:0x0800 On-chip Program Memory (Page 0) ; area DATA MEM_Program1 0x0800:0x1000 On-chip Program Memory (Page 1) ; area DATA MEM_Program2 0x1000:0x1800 On-chip Program Memory (Page 2) ; area DATA MEM_Program3 0x1800:0x2000 On-chip Program Memory (Page 3) ; BANK_2 ; area DATA FSR_ 0x0100:0x0110 ; area DATA Gen_Purp0 0x0110:0x0120 General Purpose Register 16 Bytes ; area DATA Gen_Purp1 0x0120:0x0170 General Purpose Register 80 Bytes ; area DATA Gen_Purp_BANK0 0x0170:0x0180 accesses 70h-7Fh ; area DATA MEM_Program0 0x0180:0x0800 On-chip Program Memory (Page 0) ; area DATA MEM_Program1 0x0800:0x1000 On-chip Program Memory (Page 1) ; area DATA MEM_Program2 0x1000:0x1800 On-chip Program Memory (Page 2) ; area DATA MEM_Program3 0x1800:0x2000 On-chip Program Memory (Page 3) ; BANK_3 ; area DATA FSR_ 0x0180:0x0190 ; area DATA Gen_Purp0 0x0190:0x01A0 General Purpose Register 16 Bytes ; area DATA Gen_Purp1 0x01A0:0x01F0 General Purpose Register 80 Bytes ; area DATA Gen_Purp_BANK0 0x01F0:0x0200 accesses 70h-7Fh ; area DATA MEM_Program0 0x0200:0x0800 On-chip Program Memory (Page 0) ; area DATA MEM_Program1 0x0800:0x1000 On-chip Program Memory (Page 1) ; area DATA MEM_Program2 0x1000:0x1800 On-chip Program Memory (Page 2) ; area DATA MEM_Program3 0x1800:0x2000 On-chip Program Memory (Page 3) ; Interrupt and reset vector assignments interrupt RESET 0x0000 RESET ; INPUT/OUTPUT PORTS ; BANK0 (0x0000:0x0080) BANK0:INDF 0x0000 INDF (not a physical register) BANK0:TMR0 0x0001 Timer0 module's register BANK0:PCL 0x0002 Program Counter (PC) Least Significant Byte BANK0:STATUS 0x0003 STATUS REGISTER BANK0:STATUS.IRP 7 RegIster Bank Select bit BANK0:STATUS.RP1 6 Register Bank Select bit 1 BANK0:STATUS.RP0 5 Register Bank Select bit 0 BANK0:STATUS.TO 4 Time-out bit BANK0:STATUS.PD 3 Power-down bit BANK0:STATUS.Z 2 Zero bit BANK0:STATUS.DC 1 Digit carry/borrow bit BANK0:STATUS.C 0 Carry/borrow bit BANK0:FSR 0x0004 Indirect data memory address pointer BANK0:PORTA 0x0005 PORTA register BANK0:PORTA.RA5 5 PORTA bit 5 BANK0:PORTA.RA4 4 PORTA bit 4 BANK0:PORTA.RA3 3 PORTA bit 3 BANK0:PORTA.RA2 2 PORTA bit 2 BANK0:PORTA.RA1 1 PORTA bit 1 BANK0:PORTA.RA0 0 PORTA bit 0 BANK0:PORTB 0x0006 PORTB register BANK0:PORTB.RB7 7 PORTB bit 7 BANK0:PORTB.RB6 6 PORTB bit 6 BANK0:PORTB.RB5 5 PORTB bit 5 BANK0:PORTB.RB4 4 PORTB bit 4 BANK0:PORTB.RB3 3 PORTB bit 3 BANK0:PORTB.RB2 2 PORTB bit 2 BANK0:PORTB.RB1 1 PORTB bit 1 BANK0:PORTB.RB0 0 PORTB bit 0 BANK0:PORTC 0x0007 PORTC register BANK0:PORTC.RC7 7 PORTC bit 7 BANK0:PORTC.RC6 6 PORTC bit 6 BANK0:PORTC.RC5 5 PORTC bit 5 BANK0:PORTC.RC4 4 PORTC bit 4 BANK0:PORTC.RC3 3 PORTC bit 3 BANK0:PORTC.RC2 2 PORTC bit 2 BANK0:PORTC.RC1 1 PORTC bit 1 BANK0:PORTC.RC0 0 PORTC bit 0 BANK0:PORTD 0x0008 PORTD register BANK0:PORTD.RD7 7 PORTD bit 7 BANK0:PORTD.RD6 6 PORTD bit 6 BANK0:PORTD.RD5 5 PORTD bit 5 BANK0:PORTD.RD4 4 PORTD bit 4 BANK0:PORTD.RD3 3 PORTD bit 3 BANK0:PORTD.RD2 2 PORTD bit 2 BANK0:PORTD.RD1 1 PORTD bit 1 BANK0:PORTD.RD0 0 PORTD bit 0 BANK0:PORTE 0x0009 PORTE register BANK0:PORTE.RE2 2 PORTE bit 2 BANK0:PORTE.RE1 1 PORTE bit 1 BANK0:PORTE.RE0 0 PORTE bit 0 BANK0:PCLATH 0x000A Write Buffer for the upper 5 bits of the Program Counter BANK0:INTCON 0x000B INTCON REGISTER BANK0:INTCON.GIE 7 Global Interrupt Enable bit BANK0:INTCON.PEIE 6 Peripheral Interrupt Enable bit BANK0:INTCON.TMR0IE 5 TMR0 Overflow Interrupt Enable bit BANK0:INTCON.INTE 4 RB0/INT External Interrupt Enable bit BANK0:INTCON.RBIE 3 RB Port Change Interrupt Enable bit BANK0:INTCON.TMR0IF 2 TMR0 Overflow Interrupt Flag bit BANK0:INTCON.INTF 1 RB0/INT External Interrupt Flag bit BANK0:INTCON.RBIF 0 RB Port Change Interrupt Flag bit BANK0:PIR1 0x000C PIR1 REGISTER BANK0:PIR1.PSPIF 7 Parallel Slave Port Interrupt Flag bit BANK0:PIR1.ADIF 6 A/D Converter Interrupt Flag bit BANK0:PIR1.RCIF 5 USART Receive Interrupt Flag bit BANK0:PIR1.TXIF 4 USART Transmit Interrupt Flag bit BANK0:PIR1.SSPIF 3 Synchronous Serial Port Interrupt Flag bit BANK0:PIR1.CCP1IF 2 CCP1 Interrupt Flag bit BANK0:PIR1.TMR2IF 1 TMR2 to PR2 Match Interrupt Flag bit BANK0:PIR1.TMR1IF 0 TMR1 Overflow Interrupt Flag bit BANK0:PIR2 0x000D PIR2 REGISTER BANK0:PIR2.CMIF 6 Comparator Interrupt Flag bit BANK0:PIR2.EEIF 4 EEPROM Write Operation Interrupt Flag bit BANK0:PIR2.BCLIF 3 Bus Collision Interrupt Flag bit BANK0:PIR2.CCP2IF 0 CCP2 Interrupt Flag bit BANK0:TMR1L 0x000E Holding register for the Least Significant Byte of the 16-bit TMR1 register BANK0:TMR1H 0x000F Holding register for the Most Significant Byte of the 16-bit TMR1 register BANK0:T1CON 0x0010 TIMER1 CONTROL REGISTER BANK0:T1CON.T1CKPS1 5 Timer1 Input Clock Prescale Select bit 1 BANK0:T1CON.T1CKPS0 4 Timer1 Input Clock Prescale Select bit 0 BANK0:T1CON.T1OSCEN 3 Timer1 Oscillator Enable Control bit BANK0:T1CON.T1SYNC 2 Timer1 External Clock Input Synchronization Control bit BANK0:T1CON.TMR1CS 1 Timer1 Clock Source Select bit BANK0:T1CON.TMR1ON 0 Timer1 On bit BANK0:TMR2 0x0011 Timer2 module register BANK0:T2CON 0x0012 TIMER2 CONTROL REGISTER BANK0:T2CON.TOUTPS3 6 Timer2 Output Postscale Select bit 3 BANK0:T2CON.TOUTPS2 5 Timer2 Output Postscale Select bit 2 BANK0:T2CON.TOUTPS1 4 Timer2 Output Postscale Select bit 1 BANK0:T2CON.TOUTPS0 3 Timer2 Output Postscale Select bit 0 BANK0:T2CON.TMR2ON 2 Timer2 On bit BANK0:T2CON.T2CKPS1 1 Timer2 Clock Prescale Select bit 1 BANK0:T2CON.T2CKPS0 0 Timer2 Clock Prescale Select bit 0 BANK0:SSPBUF 0x0013 Synchronous Serial Port Receive Buffer/Transmit Register BANK0:SSPCON 0x0014 SYNC SERIAL PORT CONTROL REGISTER BANK0:SSPCON.WCOL 7 Write Collision Detect bit BANK0:SSPCON.SSPOV 6 Receive Overflow Indicator bit BANK0:SSPCON.SSPEN 5 Synchronous Serial Port Enable bit BANK0:SSPCON.CKP 4 Clock Polarity Select bit BANK0:SSPCON.SSPM3 3 Synchronous Serial Port Mode Select bit 3 BANK0:SSPCON.SSPM2 2 Synchronous Serial Port Mode Select bit 2 BANK0:SSPCON.SSPM1 1 Synchronous Serial Port Mode Select bit 1 BANK0:SSPCON.SSPM0 0 Synchronous Serial Port Mode Select bit 0 BANK0:CCPR1L 0x0015 Capture/Compare/PWM1 Register1 (LSB) BANK0:CCPR1H 0x0016 Capture/Compare/PWM1 Register1 (MSB) BANK0:CCP1CON 0x0017 CCP1CON REGISTER BANK0:CCP1CON.CCP1X 5 PWM Least Significant bit BANK0:CCP1CON.CCP1Y 4 PWM Least Significant bit BANK0:CCP1CON.CCP1M3 3 CCP1 Mode Select bit 3 BANK0:CCP1CON.CCP1M2 2 CCP1 Mode Select bit 2 BANK0:CCP1CON.CCP1M1 1 CCP1 Mode Select bit 1 BANK0:CCP1CON.CCP1M0 0 CCP1 Mode Select bit 0 BANK0:RCSTA 0x0018 RECEIVE STATUS AND CONTROL REGISTER BANK0:RCSTA.SPEN 7 Serial Port Enable bit BANK0:RCSTA.RX9 6 9-bit Receive Enable bit BANK0:RCSTA.SREN 5 Single Receive Enable bit BANK0:RCSTA.CREN 4 Continuous Receive Enable bit BANK0:RCSTA.ADDEN 3 Address Detect Enable bit BANK0:RCSTA.FERR 2 Framing Error bit BANK0:RCSTA.OERR 1 Overrun Error bit BANK0:RCSTA.RX9D 0 9th bit of received data BANK0:TXREG 0x0019 USART Transmit Data Register BANK0:RCREG 0x001A USART Receive Data Register BANK0:CCPR2L 0x001B Capture/Compare/PWM2 Register2 (LSB) BANK0:CCPR2H 0x001C Capture/Compare/PWM2 Register2 (MSB) BANK0:CCP2CON 0x001D CCP2CON REGISTER BANK0:CCP2CON.CCP2X 5 PWM Least Significant bit BANK0:CCP2CON.CCP2Y 4 PWM Least Significant bit BANK0:CCP2CON.CCP2M3 3 CCP2 Mode Select bit 3 BANK0:CCP2CON.CCP2M2 2 CCP2 Mode Select bit 2 BANK0:CCP2CON.CCP2M1 1 CCP2 Mode Select bit 1 BANK0:CCP2CON.CCP2M0 0 CCP2 Mode Select bit 0 BANK0:ADRESH 0x001E A/D Result Register High Byte BANK0:ADCON0 0x001F ADCON0 REGISTER BANK0:ADCON0.ADCS1 7 A/D Conversion Clock Select bit 1 BANK0:ADCON0.ADCS0 6 A/D Conversion Clock Select bit 0 BANK0:ADCON0.CHS2 5 Analog Channel Select bit 2 BANK0:ADCON0.CHS1 4 Analog Channel Select bit 1 BANK0:ADCON0.CHS0 3 Analog Channel Select bit 0 BANK0:ADCON0.GO_DONE 2 A/D Conversion Status bit BANK0:ADCON0.ADON 0 A/D On bit ; BANK1 (0x0080:0x0100) BANK1:INDF 0x0080 INDF (not a physical register) BANK1:OPTION 0x0081 OPTION REGISTER BANK1:OPTION.RBPU 7 PORTB Pull-up Enable bit BANK1:OPTION.INTEDG 6 Interrupt Edge Select bit BANK1:OPTION.T0CS 5 TMR0 Clock Source Select bit BANK1:OPTION.T0SE 4 TMR0 Source Edge Select bit BANK1:OPTION.PSA 3 Prescaler Assignment bit BANK1:OPTION.PS2 2 Prescaler Rate Select bit 2 BANK1:OPTION.PS1 1 Prescaler Rate Select bit 1 BANK1:OPTION.PS0 0 Prescaler Rate Select bit 0 BANK1:PCL 0x0082 Program Counter's (PC) Least Significant Byte BANK1:STATUS 0x0083 STATUS REGISTER BANK1:STATUS.IRP 7 RegIster Bank Select bit BANK1:STATUS.RP1 6 Register Bank Select bit 1 BANK1:STATUS.RP0 5 Register Bank Select bit 0 BANK1:STATUS.TO 4 Time-out bit BANK1:STATUS.PD 3 Power-down bit BANK1:STATUS.Z 2 Zero bit BANK1:STATUS.DC 1 Digit carry/borrow bit BANK1:STATUS.C 0 Carry/borrow bit BANK1:FSR 0x0084 Indirect data memory address pointer BANK1:TRISA 0x0085 PORTA Data Direction Register BANK1:TRISA.TRISA5 5 PORTA Data Direction Register bit 5 BANK1:TRISA.TRISA4 4 PORTA Data Direction Register bit 4 BANK1:TRISA.TRISA3 3 PORTA Data Direction Register bit 3 BANK1:TRISA.TRISA2 2 PORTA Data Direction Register bit 2 BANK1:TRISA.TRISA1 1 PORTA Data Direction Register bit 1 BANK1:TRISA.TRISA0 0 PORTA Data Direction Register bit 0 BANK1:TRISB 0x0086 PORTB Data Direction Register BANK1:TRISB.TRISB7 7 PORTB Data Direction Register bit 7 BANK1:TRISB.TRISB6 6 PORTB Data Direction Register bit 6 BANK1:TRISB.TRISB5 5 PORTB Data Direction Register bit 5 BANK1:TRISB.TRISB4 4 PORTB Data Direction Register bit 4 BANK1:TRISB.TRISB3 3 PORTB Data Direction Register bit 3 BANK1:TRISB.TRISB2 2 PORTB Data Direction Register bit 2 BANK1:TRISB.TRISB1 1 PORTB Data Direction Register bit 1 BANK1:TRISB.TRISB0 0 PORTB Data Direction Register bit 0 BANK1:TRISC 0x0087 PORTC Data Direction Register BANK1:TRISC.TRISC7 7 PORTC Data Direction Register bit 7 BANK1:TRISC.TRISC6 6 PORTC Data Direction Register bit 6 BANK1:TRISC.TRISC5 5 PORTC Data Direction Register bit 5 BANK1:TRISC.TRISC4 4 PORTC Data Direction Register bit 4 BANK1:TRISC.TRISC3 3 PORTC Data Direction Register bit 3 BANK1:TRISC.TRISC2 2 PORTC Data Direction Register bit 2 BANK1:TRISC.TRISC1 1 PORTC Data Direction Register bit 1 BANK1:TRISC.TRISC0 0 PORTC Data Direction Register bit 0 BANK1:TRISD 0x0088 PORTD Data Direction Register BANK1:TRISD.TRISD7 7 PORTD Data Direction Register bit 7 BANK1:TRISD.TRISD6 6 PORTD Data Direction Register bit 6 BANK1:TRISD.TRISD5 5 PORTD Data Direction Register bit 5 BANK1:TRISD.TRISD4 4 PORTD Data Direction Register bit 4 BANK1:TRISD.TRISD3 3 PORTD Data Direction Register bit 3 BANK1:TRISD.TRISD2 2 PORTD Data Direction Register bit 2 BANK1:TRISD.TRISD1 1 PORTD Data Direction Register bit 1 BANK1:TRISD.TRISD0 0 PORTD Data Direction Register bit 0 BANK1:TRISE 0x0089 PORTE Data Direction Bits BANK1:TRISE.IBF 7 Input Buffer Full Status bit BANK1:TRISE.OBF 6 Output Buffer Full Status bit BANK1:TRISE.IBOV 5 Input Buffer Overflow Detect bit BANK1:TRISE.PSPMODE 4 Parallel Slave Port Mode Select bit BANK1:TRISE.TRISE2 2 Direction Control bit for pin RE2/CS BANK1:TRISE.TRISE1 1 Direction Control bit for pin RE1/WR BANK1:TRISE.TRISE0 0 Direction Control bit for pin RE0/RD BANK1:PCLATH 0x008A Write Buffer for the upper 5 bits of the Program Counter BANK1:INTCON 0x008B INTCON REGISTER BANK1:INTCON.GIE 7 Global Interrupt Enable bit BANK1:INTCON.PEIE 6 Peripheral Interrupt Enable bit BANK1:INTCON.TMR0IE 5 TMR0 Overflow Interrupt Enable bit BANK1:INTCON.INTE 4 RB0/INT External Interrupt Enable bit BANK1:INTCON.RBIE 3 RB Port Change Interrupt Enable bit BANK1:INTCON.TMR0IF 2 TMR0 Overflow Interrupt Flag bit BANK1:INTCON.INTF 1 RB0/INT External Interrupt Flag bit BANK1:INTCON.RBIF 0 RB Port Change Interrupt Flag bit BANK1:PIE1 0x008C PIE1 REGISTER BANK1:PIE1.PSPIE 7 Parallel Slave Port Read/Write Interrupt Enable bit BANK1:PIE1.ADIE 6 A/D Converter Interrupt Enable bit BANK1:PIE1.RCIE 5 USART Receive Interrupt Enable bit BANK1:PIE1.TXIE 4 USART Transmit Interrupt Enable bit BANK1:PIE1.SSPIE 3 Synchronous Serial Port Interrupt Enable bit BANK1:PIE1.CCP1IE 2 CCP1 Interrupt Enable bit BANK1:PIE1.TMR2IE 1 TMR2 to PR2 Match Interrupt Enable bit BANK1:PIE1.TMR1IE 0 TMR1 Overflow Interrupt Enable bit BANK1:PIE2 0x008D PIE2 REGISTER BANK1:PIE2.CMIE 6 Comparator Interrupt Enable bit BANK1:PIE2.EEIE 4 EEPROM Write Operation Interrupt Enable BANK1:PIE2.BCLIE 3 Bus Collision Interrupt Enable BANK1:PIE2.CCP2IE 0 CCP2 Interrupt Enable bit BANK1:PCON 0x008E PCON REGISTER BANK1:PCON.POR 1 Power-on Reset Status bit BANK1:PCON.BOR 0 Brown-out Reset Status bit BANK1:RESERVED008F 0x008F RESERVED BANK1:RESERVED0090 0x0090 RESERVED BANK1:SSPCON2 0x0091 SYNC SERIAL PORT CONTROL REGISTER2 BANK1:SSPCON2.GCEN 7 General Call Enable bit (In I2C Slave mode only) BANK1:SSPCON2.ACKSTAT 6 Acknowledge Status bit (In I2C Master mode only) BANK1:SSPCON2.ACKDT 5 Acknowledge Data bit (In I2C Master mode only) BANK1:SSPCON2.ACKEN 4 Acknowledge Sequence Enable bit (In I2C Master mode only) BANK1:SSPCON2.RCEN 3 Receive Enable bit (In I2C Master mode only) BANK1:SSPCON2.PEN 2 STOP Condition Enable bit (In I2C Master mode only) BANK1:SSPCON2.RSEN 1 Repeated START Condition Enabled bit (In I2C Master mode only) BANK1:SSPCON2.SEN 0 START Condition Enabled bit (In I2C Master mode only) BANK1:PR2 0x0092 Timer2 Period Register BANK1:SSPADD 0x0093 Synchronous Serial Port (I2C mode) Address Register BANK1:SSPSTAT 0x0094 SYNC SERIAL PORT STATUS REGISTER BANK1:SSPSTAT.SMP 7 Sample bit BANK1:SSPSTAT.CKE 6 SPI Clock Edge Select bit BANK1:SSPSTAT.D_A 5 Data/Address bit (I2C mode only) BANK1:SSPSTAT.P 4 STOP bit (I2C mode only) BANK1:SSPSTAT.S 3 START bit (I2C mode only) BANK1:SSPSTAT.R_W 2 Read/Write bit information (I2C mode only) BANK1:SSPSTAT.UA 1 Update Address bit (10-bit I2C mode only) BANK1:SSPSTAT.BF 0 Buffer Full Status bit BANK1:RESERVED0095 0x0095 RESERVED BANK1:RESERVED0096 0x0096 RESERVED BANK1:RESERVED0097 0x0097 RESERVED BANK1:TXSTA 0x0098 TRANSMIT STATUS AND CONTROL REGISTER BANK1:TXSTA.CSRC 7 Clock Source Select bit BANK1:TXSTA.TX9 6 9-bit Transmit Enable bit BANK1:TXSTA.TXEN 5 Transmit Enable bit BANK1:TXSTA.SYNC 4 USART Mode Select bit BANK1:TXSTA.BRGH 2 High Baud Rate Select bit BANK1:TXSTA.TRMT 1 Transmit Shift Register Status bit BANK1:TXSTA.TX9D 0 9th bit of Transmit Data, can be parity bit BANK1:SPBRG 0x0099 Baud Rate Generator Register BANK1:RESERVED009A 0x009A RESERVED BANK1:RESERVED009B 0x009B RESERVED BANK1:CMCON 0x009C CMCON REGISTER BANK1:CMCON.C2OUT 7 Comparator 2 Output bit BANK1:CMCON.C1OUT 6 Comparator 1 Output bit BANK1:CMCON.C2INV 5 Comparator 2 Output Inversion bit BANK1:CMCON.C1INV 4 Comparator 1 Output Inversion bit BANK1:CMCON.CIS 3 Comparator Input Switch bit BANK1:CMCON.CM2 2 Comparator Mode bit 2 BANK1:CMCON.CM1 1 Comparator Mode bit 1 BANK1:CMCON.CM0 0 Comparator Mode bit 0 BANK1:CVRCON 0x009D CVRCON CONTROL REGISTER BANK1:CVRCON.CVREN 7 Comparator Voltage Reference Enable bit BANK1:CVRCON.CVROE 6 Comparator VREF Output Enable bit BANK1:CVRCON.CVRR 5 Comparator VREF Range Selection bit BANK1:CVRCON.CVR3 3 Comparator VREF Value Selection bit 3 BANK1:CVRCON.CVR2 2 Comparator VREF Value Selection bit 2 BANK1:CVRCON.CVR1 1 Comparator VREF Value Selection bit 1 BANK1:CVRCON.CVR0 0 Comparator VREF Value Selection bit 0 BANK1:ADRESL 0x009E A/D Result Register Low Byte BANK1:ADCON1 0x009F ADCON1 REGISTER BANK1:ADCON1.ADFM 7 A/D Result format select BANK1:ADCON1.ADCS2 6 A/D Conversion Clock Select bit BANK1:ADCON1.PCFG3 3 A/D Port Configuration Control bit 3 BANK1:ADCON1.PCFG2 2 A/D Port Configuration Control bit 2 BANK1:ADCON1.PCFG1 1 A/D Port Configuration Control bit 1 BANK1:ADCON1.PCFG0 0 A/D Port Configuration Control bit 0 ; BANK2 (0x0100:0x0180) BANK2:INDF 0x0100 INDF (not a physical register) BANK2:TMR0 0x0101 Timer0 module's register BANK2:PCL 0x0102 Program Counter's (PC) Least Significant Byte BANK2:STATUS 0x0103 STATUS REGISTER BANK2:STATUS.IRP 7 RegIster Bank Select bit BANK2:STATUS.RP1 6 Register Bank Select bit 1 BANK2:STATUS.RP0 5 Register Bank Select bit 0 BANK2:STATUS.TO 4 Time-out bit BANK2:STATUS.PD 3 Power-down bit BANK2:STATUS.Z 2 Zero bit BANK2:STATUS.DC 1 Digit carry/borrow bit BANK2:STATUS.C 0 Carry/borrow bit BANK2:FSR 0x0104 Indirect data memory address pointer BANK2:RESERVED0105 0x0105 RESERVED BANK2:PORTB 0x0106 PORTB register BANK2:PORTB.RB7 7 PORTB bit 7 BANK2:PORTB.RB6 6 PORTB bit 6 BANK2:PORTB.RB5 5 PORTB bit 5 BANK2:PORTB.RB4 4 PORTB bit 4 BANK2:PORTB.RB3 3 PORTB bit 3 BANK2:PORTB.RB2 2 PORTB bit 2 BANK2:PORTB.RB1 1 PORTB bit 1 BANK2:PORTB.RB0 0 PORTB bit 0 BANK2:RESERVED0107 0x0107 RESERVED BANK2:RESERVED0108 0x0108 RESERVED BANK2:RESERVED0109 0x0109 RESERVED BANK2:PCLATH 0x010A Write Buffer for the upper 5 bits of the Program Counter BANK2:INTCON 0x010B INTCON REGISTER BANK2:INTCON.GIE 7 Global Interrupt Enable bit BANK2:INTCON.PEIE 6 Peripheral Interrupt Enable bit BANK2:INTCON.TMR0IE 5 TMR0 Overflow Interrupt Enable bit BANK2:INTCON.INTE 4 RB0/INT External Interrupt Enable bit BANK2:INTCON.RBIE 3 RB Port Change Interrupt Enable bit BANK2:INTCON.TMR0IF 2 TMR0 Overflow Interrupt Flag bit BANK2:INTCON.INTF 1 RB0/INT External Interrupt Flag bit BANK2:INTCON.RBIF 0 RB Port Change Interrupt Flag bit BANK2:EEDATA 0x010C EEPROM data register Low Byte BANK2:EEADR 0x010D EEPROM address register Low Byte BANK2:EEDATH 0x010E EEPROM data register high byte BANK2:EEADRH 0x010F EEPROM address register high byte ; BANK3 (0x0180:0x0200) BANK3:INDF 0x0180 INDF (not a physical register) BANK3:OPTION 0x0181 OPTION REGISTER BANK3:OPTION.RBPU 7 PORTB Pull-up Enable bit BANK3:OPTION.INTEDG 6 Interrupt Edge Select bit BANK3:OPTION.T0CS 5 TMR0 Clock Source Select bit BANK3:OPTION.T0SE 4 TMR0 Source Edge Select bit BANK3:OPTION.PSA 3 Prescaler Assignment bit BANK3:OPTION.PS2 2 Prescaler Rate Select bit 2 BANK3:OPTION.PS1 1 Prescaler Rate Select bit 1 BANK3:OPTION.PS0 0 Prescaler Rate Select bit 0 BANK3:PCL 0x0182 Program Counter's (PC) Least Significant Byte BANK3:STATUS 0x0183 STATUS REGISTER BANK3:STATUS.IRP 7 RegIster Bank Select bit BANK3:STATUS.RP1 6 Register Bank Select bit 1 BANK3:STATUS.RP0 5 Register Bank Select bit 0 BANK3:STATUS.TO 4 Time-out bit BANK3:STATUS.PD 3 Power-down bit BANK3:STATUS.Z 2 Zero bit BANK3:STATUS.DC 1 Digit carry/borrow bit BANK3:STATUS.C 0 Carry/borrow bit BANK3:FSR 0x0184 Indirect data memory address pointer BANK3:RESERVED0185 0x0185 RESERVED BANK3:TRISB 0x0186 PORTB Data Direction Register BANK3:TRISB.TRISB7 7 PORTB Data Direction Register bit 7 BANK3:TRISB.TRISB6 6 PORTB Data Direction Register bit 6 BANK3:TRISB.TRISB5 5 PORTB Data Direction Register bit 5 BANK3:TRISB.TRISB4 4 PORTB Data Direction Register bit 4 BANK3:TRISB.TRISB3 3 PORTB Data Direction Register bit 3 BANK3:TRISB.TRISB2 2 PORTB Data Direction Register bit 2 BANK3:TRISB.TRISB1 1 PORTB Data Direction Register bit 1 BANK3:TRISB.TRISB0 0 PORTB Data Direction Register bit 0 BANK3:RESERVED0187 0x0187 RESERVED BANK3:RESERVED0188 0x0188 RESERVED BANK3:RESERVED0189 0x0189 RESERVED BANK3:PCLATH 0x018A Write Buffer for the upper 5 bits of the Program Counter BANK3:INTCON 0x018B INTCON REGISTER BANK3:INTCON.GIE 7 Global Interrupt Enable bit BANK3:INTCON.PEIE 6 Peripheral Interrupt Enable bit BANK3:INTCON.TMR0IE 5 TMR0 Overflow Interrupt Enable bit BANK3:INTCON.INTE 4 RB0/INT External Interrupt Enable bit BANK3:INTCON.RBIE 3 RB Port Change Interrupt Enable bit BANK3:INTCON.TMR0IF 2 TMR0 Overflow Interrupt Flag bit BANK3:INTCON.INTF 1 RB0/INT External Interrupt Flag bit BANK3:INTCON.RBIF 0 RB Port Change Interrupt Flag bit BANK3:EECON1 0x018C EECON1 REGISTER BANK3:EECON1.EEPGD 7 Program/Data EEPROM Select bit BANK3:EECON1.WRERR 3 EEPROM Error Flag bit BANK3:EECON1.WREN 2 EEPROM Write Enable bit BANK3:EECON1.WR 1 Write Control bit BANK3:EECON1.RD 0 Read Control bit BANK3:EECON2 0x018D EEPROM control register2 (not a physical register) BANK3:RESERVED018E 0x018E RESERVED BANK3:RESERVED018F 0x018F RESERVED