; ; This file defines SFR names and bit names for Microchip's PIC14 processors. ; ; This file can be configured for different devices. ; At the beginning of the file there are definitions common for all devices ; Device-specific definitions are introduced by ; ; .devicename ; ; line. Also an optional directive ; ; .default devicename ; ; designates the default device name. ; ; ; It is allowed to have several mappings for the same port. For example: ; ; STATUS 0x03 ; STATUS 0x83 ; STATUS 0x103 ; STATUS 0x183 ; ; In this case IDA will redirect all memory references to the first definition. ; (all references to 0x83, 0x103, 0x183 will be rerouted to 0x03) ; .default 14000 .14000 ; http://www.microchip.com/download/lit/pline/picmicro/families/14c000/40122b.pdf ; PIC14000.pdf ; MEMORY MAP ; BANK_0 area DATA FSR_ 0x0000:0x0020 area DATA Gen_Purp 0x0020:0x0080 General Purpose Register area DATA MEM_Program0 0x0080:0x0800 On-chip Program Memory (Page 0) area DATA MEM_Program1 0x0800:0x0FC0 On-chip Program Memory (Page 1) area DATA CALIBR 0x0FC0:0x10000 Calibration Space ; BANK_1 ; area DATA FSR_ 0x0080:0x00A0 ; area DATA Gen_Purp 0x00A0:0x0100 General Purpose Register ; area DATA MEM_Program0 0x0100:0x0800 On-chip Program Memory (Page 0) ; area DATA MEM_Program1 0x0800:0x0FC0 On-chip Program Memory (Page 1) ; area DATA CALIBR 0x0FC0:0x10000 Calibration Space ; Interrupt and reset vector assignments interrupt RESET 0x0000 RESET ; INPUT/OUTPUT PORTS ; BANK_0 (0x0000:0x0080) BANK0:INDF 0x0000 INDF (not a physical register) BANK0:TMR0 0x0001 Timer0 data BANK0:PCL 0x0002 Program Counter's (PC's) least significant byte BANK0:STATUS 0x0003 STATUS REGISTER BANK0:STATUS.RP0 5 Register page select for direct addressing BANK0:STATUS.TO 4 Time-out bit BANK0:STATUS.PD 3 Power down bit BANK0:STATUS.Z 2 Zero bit BANK0:STATUS.DC 1 Digit carry / borrow bit BANK0:STATUS.C 0 Carry / borrow bit BANK0:FSR 0x0004 Indirect data memory address pointer BANK0:PORTA 0x0005 PORTA DATA REGISTER BANK0:PORTA.RA3_AN3 3 BANK0:PORTA.RA2_AN2 2 BANK0:PORTA.RA1_AN1 1 BANK0:PORTA.RA0_AN0 0 BANK0:RESERVED0006 0x0006 RESERVED BANK0:PORTC 0x0007 PORTC data latch BANK0:PORTC.RC7_SDAA 7 BANK0:PORTC.RC6_SCLA 6 BANK0:PORTC.RC5 5 BANK0:PORTC.RC4 4 BANK0:PORTC.RC3_T0CKI 3 BANK0:PORTC.RC2 2 BANK0:PORTC.RC1_CMPA 1 BANK0:PORTC.RC0_REFA 0 BANK0:PORTD 0x0008 PORTD DATA REGISTER BANK0:PORTD.RD7_AN7 7 BANK0:PORTD.RD6_AN6 6 BANK0:PORTD.RD5_AN5 5 BANK0:PORTD.RD4_AN4 4 BANK0:PORTD.RD3_REFB 3 BANK0:PORTD.RD2_CMPB 2 BANK0:PORTD.RD1_SDAB 1 BANK0:PORTD.RD0_SCLB 0 BANK0:RESERVED0009 0x0009 RESERVED BANK0:PCLATH 0x000A Buffered register for the upper 5 bits of the Program Counter (PC) BANK0:INTCON 0x000B INTCON REGISTER BANK0:INTCON.GIE 7 Global interrupt enable BANK0:INTCON.PEIE 6 Peripheral interrupt enable bit BANK0:INTCON.T0IE 5 TMR0 interrupt enable bit BANK0:INTCON.T0IF 2 TMR0 overflow interrupt flag BANK0:PIR1 0x000C PIR1 REGISTER BANK0:PIR1.CMIF 7 Programmable Reference Comparator Interrupt Flag BANK0:PIR1.PBIF 4 External Pushbutton Interrupt Flag BANK0:PIR1.I2CIF 3 I2C Port Interrupt Flag BANK0:PIR1.RCIF 2 PORTC Interrupt on Change Flag BANK0:PIR1.ADCIF 1 A/D Capture Interrupt Flag BANK0:PIR1.OVFIF 0 A/D counter Overflow Interrupt Flag BANK0:RESERVED000D 0x000D RESERVED BANK0:ADTMRL 0x000E A/D capture timer data least significant byte BANK0:ADTMRL.ADTMRL7 7 BANK0:ADTMRL.ADTMRL6 6 BANK0:ADTMRL.ADTMRL5 5 BANK0:ADTMRL.ADTMRL4 4 BANK0:ADTMRL.ADTMRL3 3 BANK0:ADTMRL.ADTMRL2 2 BANK0:ADTMRL.ADTMRL1 1 BANK0:ADTMRL.ADTMRL0 0 BANK0:ADTMRH 0x000F A/D capture timer data most significant byte BANK0:ADTMRH.ADTMRH15 7 BANK0:ADTMRH.ADTMRH14 6 BANK0:ADTMRH.ADTMRH13 5 BANK0:ADTMRH.ADTMRH12 4 BANK0:ADTMRH.ADTMRH11 3 BANK0:ADTMRH.ADTMRH10 2 BANK0:ADTMRH.ADTMRH9 1 BANK0:ADTMRH.ADTMRH8 0 BANK0:RESERVED0010 0x0010 RESERVED BANK0:RESERVED0011 0x0011 RESERVED BANK0:RESERVED0012 0x0012 RESERVED BANK0:I2CBUF 0x0013 I2C Serial Port Receive Buffer/Transmit Register BANK0:I2CCON 0x0014 I2C PORT CONTROL REGISTER BANK0:I2CCON.WCOL 7 Write collision detect BANK0:I2CCON.I2COV 6 Receive overflow flag BANK0:I2CCON.I2CEN 5 I2C enable BANK0:I2CCON.CKP 4 Clock polarity select BANK0:I2CCON.I2CM3 3 2Cmode select 3 BANK0:I2CCON.I2CM2 2 2Cmode select 2 BANK0:I2CCON.I2CM1 1 2Cmode select 1 BANK0:I2CCON.I2CM0 0 2Cmode select 0 BANK0:ADCAPL 0x0015 A/D capture latch least significant byte BANK0:ADCAPL.ADCAPL7 7 BANK0:ADCAPL.ADCAPL6 6 BANK0:ADCAPL.ADCAPL5 5 BANK0:ADCAPL.ADCAPL4 4 BANK0:ADCAPL.ADCAPL3 3 BANK0:ADCAPL.ADCAPL2 2 BANK0:ADCAPL.ADCAPL1 1 BANK0:ADCAPL.ADCAPL0 0 BANK0:ADCAPH 0x0016 A/D capture latch most significant byte BANK0:ADCAPH.ADCAPH15 7 BANK0:ADCAPH.ADCAPH14 6 BANK0:ADCAPH.ADCAPH13 5 BANK0:ADCAPH.ADCAPH12 4 BANK0:ADCAPH.ADCAPH11 3 BANK0:ADCAPH.ADCAPH10 2 BANK0:ADCAPH.ADCAPH9 1 BANK0:ADCAPH.ADCAPH8 0 BANK0:RESERVED0017 0x0017 RESERVED BANK0:RESERVED0018 0x0018 RESERVED BANK0:RESERVED0019 0x0019 RESERVED BANK0:RESERVED001A 0x001A RESERVED BANK0:RESERVED001B 0x001B RESERVED BANK0:RESERVED001C 0x001C RESERVED BANK0:RESERVED001D 0x001D RESERVED BANK0:RESERVED001E 0x001E RESERVED BANK0:ADCON0 0x001F A/D CONTROL AND STATUS REGISTER 0 BANK0:ADCON0.ADCS3 7 A/D Channel Selects 3 BANK0:ADCON0.ADCS2 6 A/D Channel Selects 2 BANK0:ADCON0.ADCS1 5 A/D Channel Selects 1 BANK0:ADCON0.ADCS0 4 A/D Channel Selects 0 BANK0:ADCON0.AMUXOE 2 Analog Mux Output Enable BANK0:ADCON0.ADRST 1 A/D Reset Control Bit BANK0:ADCON0.ADZERO 0 A/D Zero Select Control ; BANK_1 (0x0080:0x0100) BANK1:INDF 0x0080 INDF (not a physical register) BANK1:OPTION 0x0081 OPTION REGISTER BANK1:OPTION.RCPU 7 PORTC pull-up enable BANK1:OPTION.TOCS 5 TMR0 clock source BANK1:OPTION.TOSE 4 TMR0 source edge BANK1:OPTION.PSA 3 Prescaler assignment bit BANK1:OPTION.PS2 2 Prescaler select bit 2 BANK1:OPTION.PS1 1 Prescaler select bit 1 BANK1:OPTION.PS0 0 Prescaler select bit 0 BANK1:PCL 0x0082 Program Counter's (PC's) least significant byte BANK1:STATUS 0x0083 STATUS REGISTER BANK1:STATUS.RP0 5 Register page select for direct addressing BANK1:STATUS.TO 4 Time-out bit BANK1:STATUS.PD 3 Power down bit BANK1:STATUS.Z 2 Zero bit BANK1:STATUS.DC 1 Digit carry / borrow bit BANK1:STATUS.C 0 Carry / borrow bit BANK1:FSR 0x0084 Indirect data memory address pointer BANK1:TRISA 0x0085 PORTA Data Direction Register BANK1:RESERVED0086 0x0086 RESERVED BANK1:TRISC 0x0087 PORTC Data Direction Register BANK1:TRISC.TRISC7 7 Control direction on pin RC7/SDAA BANK1:TRISC.TRISC6 6 Control direction on pin RC6/SCLA BANK1:TRISC.TRISC5 5 Control direction on pin RC5 BANK1:TRISC.TRISC4 4 Control direction on pin RC4 BANK1:TRISC.TRISC3 3 Control direction on pin RC3 BANK1:TRISC.TRISC2 2 Control direction on pin RC2 BANK1:TRISC.TRISC1 1 Control direction on pin RC1/CMPA BANK1:TRISC.TRISC0 0 Control direction on pin RC0/REFA BANK1:TRISD 0x0088 PORTD Data Direction Register BANK1:TRISD.TRISD7 7 Control direction on pin RD7/AN7 BANK1:TRISD.TRISD6 6 Control direction on pin RD6/AN6 BANK1:TRISD.TRISD5 5 Control direction on pin RD5/AN5 BANK1:TRISD.TRISD4 4 Control direction on pin RD4/AN4 BANK1:TRISD.TRISD3 3 Control direction on pin RD3/REFB BANK1:TRISD.TRISD2 2 Control direction on pin RD2/CMPB BANK1:TRISD.TRISD1 1 Control direction on pin RD1/SDAB BANK1:TRISD.TRISD0 0 Control direction on pin RD0/SCLB BANK1:RESERVED0089 0x0089 RESERVED BANK1:PCLATH 0x008A Buffered register for the upper 5 bits of the Program Counter (PC) BANK1:INTCON 0x008B INTCON REGISTER BANK1:INTCON.GIE 7 Global interrupt enable BANK1:INTCON.PEIE 6 Peripheral interrupt enable bit BANK1:INTCON.T0IE 5 TMR0 interrupt enable bit BANK1:INTCON.T0IF 2 TMR0 overflow interrupt flag BANK1:PIE1 0x008C PIE1 REGISTER BANK1:PIE1.CMIE 7 Programmable Reference Comparator Interrupt Enable BANK1:PIE1.PBIE 4 External Pushbutton Interrupt Enable BANK1:PIE1.I2CIE 3 I2C Port Interrupt Enable BANK1:PIE1.RCIE 2 PORTC Interrupt on change Enable BANK1:PIE1.ADCIE 1 A/D Capture Interrupt Enable BANK1:PIE1.OVFIE 0 A/D Counter Overflow Interrupt Enable BANK1:RESERVED008D 0x008D RESERVED BANK1:PCON 0x008E PCON REGISTER BANK1:PCON.POR 1 Power on Reset Flag BANK1:PCON.LVD 0 Low Voltage Detect Flag BANK1:SLPCON 0x008F SLPCON REGISTER BANK1:SLPCON.HIBEN 7 Hibernate Mode Select BANK1:SLPCON.REFOFF 5 References Power Control BANK1:SLPCON.LSOFF 4 Level Shift Network Power Control BANK1:SLPCON.OSCOFF 3 Main Oscillator Power Control BANK1:SLPCON.CMOFF 2 Programmable Reference and Comparator Power Control BANK1:SLPCON.TEMPOFF 1 On-chip Temperature Sensor Power Control BANK1:SLPCON.ADOFF 0 A/D Module Power Control BANK1:RESERVED0090 0x0090 RESERVED BANK1:RESERVED0091 0x0091 RESERVED BANK1:RESERVED0092 0x0092 RESERVED BANK1:I2CADD 0x0093 I2C Synchronous Serial Port Address Register BANK1:I2CSTAT 0x0094 I2C PORT STATUS REGISTER BANK1:I2CSTAT.D_A 5 Data/Address bit BANK1:I2CSTAT.P 4 Stop bit BANK1:I2CSTAT.S 3 Start bit BANK1:I2CSTAT.R_W 2 Read/write bit information BANK1:I2CSTAT.UA 1 Update Address BANK1:I2CSTAT.BF 0 Buffer full BANK1:RESERVED0095 0x0095 RESERVED BANK1:RESERVED0096 0x0096 RESERVED BANK1:RESERVED0097 0x0097 RESERVED BANK1:RESERVED0098 0x0098 RESERVED BANK1:RESERVED0099 0x0099 RESERVED BANK1:RESERVED009A 0x009A RESERVED BANK1:PREFA 0x009B PREFA REGISTER BANK1:PREFA.PRA7 7 Programmable Reference A Voltage Select Bit 7 BANK1:PREFA.PRA6 6 Programmable Reference A Voltage Select Bit 6 BANK1:PREFA.PRA5 5 Programmable Reference A Voltage Select Bit 5 BANK1:PREFA.PRA4 4 Programmable Reference A Voltage Select Bit 4 BANK1:PREFA.PRA3 3 Programmable Reference A Voltage Select Bit 3 BANK1:PREFA.PRA2 2 Programmable Reference A Voltage Select Bit 2 BANK1:PREFA.PRA1 1 Programmable Reference A Voltage Select Bit 1 BANK1:PREFA.PRA0 0 Programmable Reference A Voltage Select Bit 0 BANK1:PREFB 0x009C PREFB REGISTER BANK1:PREFB.PRB7 7 Programmable Reference B Voltage Select Bit 7 BANK1:PREFB.PRB6 6 Programmable Reference B Voltage Select Bit 6 BANK1:PREFB.PRB5 5 Programmable Reference B Voltage Select Bit 5 BANK1:PREFB.PRB4 4 Programmable Reference B Voltage Select Bit 4 BANK1:PREFB.PRB3 3 Programmable Reference B Voltage Select Bit 3 BANK1:PREFB.PRB2 2 Programmable Reference B Voltage Select Bit 2 BANK1:PREFB.PRB1 1 Programmable Reference B Voltage Select Bit 1 BANK1:PREFB.PRB0 0 Programmable Reference B Voltage Select Bit 0 BANK1:CMCON 0x009D COMPARATOR CONTROL REGISTER BANK1:CMCON.CMBOUT 6 Comparator B Output BANK1:CMCON.CMBOE 5 Comparator B Output Enable BANK1:CMCON.CPOLB 4 Comparator B Polarity Bit BANK1:CMCON.CMAOUT 2 Comparator A Output BANK1:CMCON.CMAOE 1 Comparator A Output Enable BANK1:CMCON.CPOLA 0 Comparator A Polarity Bit BANK1:MISC 0x009E MISC REGISTER BANK1:MISC.SMHOG 7 SMHOG enable BANK1:MISC.SPGNDB 6 Serial Port Ground Select BANK1:MISC.SPGNDA 5 Serial Port Ground Select BANK1:MISC.I2CSEL 4 I2C Port select Bit BANK1:MISC.SMBUS 3 SMBus-Compatibility Select BANK1:MISC.INCLKEN 2 Oscillator Output Select (available in IN mode only) BANK1:MISC.OSC2 1 OSC2 output port bit (available in IN mode only) BANK1:MISC.OSC1 0 OSC1 input port bit (available in IN mode only) BANK1:ADCON1 0x009F A/D CONTROL AND STATUS REGISTER 1 BANK1:ADCON1.ADDAC3 7 A/D Current Source Selects 3 BANK1:ADCON1.ADDAC2 6 A/D Current Source Selects 2 BANK1:ADCON1.ADDAC1 5 A/D Current Source Selects 1 BANK1:ADCON1.ADDAC0 4 A/D Current Source Selects 0 BANK1:ADCON1.PCFG3 3 PORTD Configuration Selects 3 BANK1:ADCON1.PCFG2 2 PORTD Configuration Selects 2 BANK1:ADCON1.PCFG1 1 PORTA Configuration Selects 1 BANK1:ADCON1.PCFG0 0 PORTA Configuration Selects 0