.Z80180 ; Enhanced Z80 Megacell ; http://www.zilog.com/products/partdetails.asp?id=Z80180 ; INPUT/ OUTPUT PORTS CNTLA0 0x0000 ASCI Channel Control Register A 0 CNTLA0.MPE 7 Multi-Processor Mode Enable CNTLA0.RE 6 Receiver Enable CNTLA0.TE 5 Transmitter Enable CNTLA0._RTS0 4 Request to Send Channel 0 CNTLA0.MPBR_EFR 3 Multiprocessor Bit Receive/Error Flag Reset CNTLA0.MOD2 2 ASCI Data Format Mode 2 CNTLA0.MOD1 1 ASCI Data Format Mode 1 CNTLA0.MOD0 0 ASCI Data Format Mode 0 CNTLA1 0x0001 ASCI Channel Control Register A 0 CNTLA1.MPE 7 Multi-Processor Mode Enable CNTLA1.RE 6 Receiver Enable CNTLA1.TE 5 Transmitter Enable CNTLA1._RTS0 4 Request to Send Channel 0 CNTLA1.MPBR_EFR 3 Multiprocessor Bit Receive/Error Flag Reset CNTLA1.MOD2 2 ASCI Data Format Mode 2 CNTLA1.MOD1 1 ASCI Data Format Mode 1 CNTLA1.MOD0 0 ASCI Data Format Mode 0 CNTLB0 0x0002 ASCI Channel Control Register B 0 CNTLB0.MPBT 7 Multiprocessor Bit Transmit CNTLB0.MP 6 Multiprocessor Mode CNTLB0.__CTS_PS 5 Clear to Send/Prescale CNTLB0.PEO 4 Parity Even Odd CNTLB0.DR 3 Divide Ratio CNTLB0.SS2 2 Source/Speed Select 2 CNTLB0.SS1 1 Source/Speed Select 1 CNTLB0.SS0 0 Source/Speed Select 0 CNTLB1 0x0003 ASCI Channel Control Register B 1 CNTLB1.MPBT 7 Multiprocessor Bit Transmit CNTLB1.MP 6 Multiprocessor Mode CNTLB1.__CTS_PS 5 Clear to Send/Prescale CNTLB1.PEO 4 Parity Even Odd CNTLB1.DR 3 Divide Ratio CNTLB1.SS2 2 Source/Speed Select 2 CNTLB1.SS1 1 Source/Speed Select 1 CNTLB1.SS0 0 Source/Speed Select 0 STAT0 0x0004 ASCI Status Register 0 STAT0.RDRF 7 Receive Data Register Full STAT0.OVRN 6 Overrun Error STAT0.PE 5 Parity Error STAT0.FE 4 Framing Error STAT0.REI 3 Receive Interrupt Enable STAT0._DCD0 2 Data Carrier Detect STAT0.TDRE 1 Transmit Data Register Empty STAT0.TIE 0 Transmit Interrupt Enable STAT1 0x0005 ASCI Status Register 1 STAT1.RDRF 7 Receive Data Register Full STAT1.OVRN 6 Overrun Error STAT1.PE 5 Parity Error STAT1.FE 4 Framing Error STAT1.REI 3 Receive Interrupt Enable STAT1.TDRE 1 Transmit Data Register Empty STAT1.TIE 0 Transmit Interrupt Enable TDR0 0x0006 TDR1 0x0007 RDR0 0x0008 RDR1 0x0009 CNTR 0x000A CSIO Control/Status Register CNTR.EF 7 End Flag CNTR.EIE 6 End Interrupt Enable CNTR.RE 5 Receive Enable CNTR.TE 4 Transmit Enable CNTR.SS2 2 Speed Select 2 CNTR.SS1 1 Speed Select 1 CNTR.SS0 0 Speed Select 0 TRDR 0x000B CSIO Transmit/Receive Data Register TMDR0L 0x000C Timer Data Register Channel 0L TMDR0H 0x000D Timer Data Register Channel 0H RLDR0L 0x000E Timer Reload Register 0L RLDR0H 0x000F Timer Reload Register 0H TCR 0x0010 Timer Control Register TCR.TIF1 7 Timer Interrupt Flag 1 TCR.TIF0 6 Timer Interrupt Flag 0 TCR.TIE1 5 Timer Interrupt Enable 1 TCR.TIE0 4 Timer Interrupt Enable 0 TCR.TOC1 3 Timer Output Control TCR.TOC0 2 Timer Output Control TCR.TDE1 1 TCR.TDE0 0 TMDR1L 0x0014 Timer Data Register Channel 1L TMDR1H 0x0015 Timer Data Register Channel 1H RLDR1L 0x0016 Timer Reload Register 1L RLDR1H 0x0017 Timer Reload Register 1H FRC 0x0018 Free Running Counter SAR0L 0x0020 DMA Source Address Register Channel 0L SAR0H 0x0021 DMA Source Address Register Channel 0H SAR0B 0x0022 DMA Source Address Register Channel 0B DAR0L 0x0023 DMA Destination Address Register Channel 0L DAR0H 0x0024 DMA Destination Address Register Channel 0H DAR0B 0x0025 DMA Destination Address Register Channel 0B BCR0L 0x0026 DMA Byte Count Register Channel 0L BCR0H 0x0027 DMA Byte Count Register Channel 0H MAR1L 0x0028 DMA Memory Address Register, Channel 1L MAR1H 0x0029 DMA Memory Address Register, Channel 1H MAR1B 0x002A DMA Memory Address Register, Channel 1B IAR1L 0x002B DMA I/O Address Register Channel 1L IAR1H 0x002C DMA I/O Address Register Channel 1H BCR1L 0x002E DMA Byte Count Register Channel 1L BCR1H 0x002F DMA Byte Count Register Channel 1H DSTAT 0x0030 DMA Status Register DSTAT.DE1 7 DE1: DMA Enable Channel 1 DSTAT.DE0 6 DE0: DMA Enable Channel 0 DSTAT.DWE1 5 DE1 Bit WRITE Enable DSTAT.DWE0 4 DE0 Bit WRITE Enable DSTAT.DIE1 3 DMA Interrupt Enable Channel DSTAT.DIE0 2 DMA Interrupt Enable Channel DSTAT.DME 0 DMA Main Enable DMODE 0x0031 DMA Mode Register DMODE.DM1 5 Destination Mode Channel 0 DMODE.DM0 4 Destination Mode Channel 0 DMODE.SM1 3 Source Mode Channel 0 DMODE.SM0 2 Source Mode Channel 0 DMODE.MMOD 1 Memory Mode Channel 0 DCNTL 0x0032 DMA/WAIT Control Register DCNTL.MWI1 7 Memory Wait Insertion DCNTL.MWI0 6 Memory Wait Insertion DCNTL.IWI1 5 I/O Wait Insertion DCNTL.IWI0 4 I/O Wait Insertion DCNTL.DMS1 3 DMA Request Sense DCNTL.DMS0 2 DMA Request Sense DCNTL.DIM1 1 DMA Channel 1 I/O and Memory Mode DCNTL.DIM0 0 DMA Channel 1 I/O and Memory Mode IL 0x0033 Interrupt Vector Low Register IL.IL7 7 IL.IL6 6 IL.IL5 5 ITC 0x0034 Int/TRAP Control Register ITC.TRAP 7 ITC.UFO 6 Undefined Fetch Object ITC.ITE2 2 Interrupt Enable 2 ITC.ITE1 1 Interrupt Enable 1 ITC.ITE0 0 Interrupt Enable 0 RCR 0x0036 Refresh Control Register RCR.REFE 7 Refresh Enable RCR.REFW 6 Refresh Wait RCR.CYC1 1 Cycle Interval RCR.CYC0 0 Cycle Interval CBR 0x0038 MMU Common Base Register (CBR) CBR.CB7 7 CBR.CB6 6 CBR.CB5 5 CBR.CB4 4 CBR.CB3 3 CBR.CB2 2 CBR.CB1 1 CBR.CB0 0 BBR 0x0039 MMU Bank Base Register (BBR) BBR.BB7 7 BBR.BB6 6 BBR.BB5 5 BBR.BB4 4 BBR.BB3 3 BBR.BB2 2 BBR.BB1 1 BBR.BB0 0 CBAR 0x003A MMU Common/Bank Area Register (CBAR) CBAR.CA3 7 CBAR.CA2 6 CBAR.CA1 5 CBAR.CA0 4 CBAR.BA3 3 CBAR.BA2 2 CBAR.BA1 1 CBAR.BA0 0 OMCR 0x003E Operation Mode Control Register OMCR.MIE 7 OMCR._MITE 6 OMCR._IOC 5 ICR 0x003F I/O Control Register (ICR) ICR.IOA7 7 ICR.IOA6 6 ICR.IOSTP 5 .Z80181 ; Smart Access Controller .Z80182 ; ZiLOG Intelligent Peripheral (ZIPT) .Z80189 .Z8S180 ; + Parallel I/O .Z80195 ; Smart Peripheral Controller (ROMless) .Z80L183 ; Mixed-Signal Z183 Internet Processor .Z80S183 . Mixed-Signal Z183 Internet Processor .Z8L180 ; Enhanced Z80 Megacell .Z8L180 ; Low-Voltage Version (3.3 V) .Z8L182 ; ZiLOG Intelligent Peripheral (ZIPT) - Low Voltage Version .Z8S180 ; Enhanced Z80 Megacell .Z8L180 ; Low-Voltage Version (3.3 V)