; ; PowerPC special purpose registers ; ; For the device control registers (DCR), look into ppcdcr.cfg ; xer 1 Integer exception register lr 8 Link register ctr 9 Count register dsisr 18 DAE/source instruction service register dar 19 Data address register dec 22 Decrementer sdr1 25 SDR1 register srr0 26 Machine status save/restore register 0 srr1 27 Machine status save/restore register 1 eie 80 External interrupt enable eid 81 External interrupt disable nri 82 Non-recoverable interrupt cmpa 144 Comparator A value register cmpb 145 Comparator B value register cmpc 146 Comparator C value register cmpd 147 Comparator D value register ecr 148 Exception cause register der 149 Debug enable register counta 150 Breakpoint Counter A value and control register countb 151 Breakpoint Counter B value and control register cmpe 152 Comparator E value register cmpf 153 Comparator F value register cmpg 154 Comparator G value register cmph 155 Comparator H value register lctrl1 156 L-bus support control register 1 lctrl2 157 L-bus support control register 2 ictrl 158 I-bus support control register bar 159 Breakpoint address register tbl 268 Time base facility for reading (lower) tbu 269 Time base facility for reading (upper) sprg0 272 General special purpose register 0 sprg1 273 General special purpose register 1 sprg2 274 General special purpose register 2 sprg3 275 General special purpose register 3 asr 280 Address space register ear 282 External address register tblw 284 Time base facility for writing (lower) tbuw 285 Time base facility for writing (upper) pvr 287 Processor version register ibat0u 528 Instruction BAT register 0 (upper) ibat0l 529 Instruction BAT register 0 (lower) ibat1u 530 Instruction BAT register 1 (upper) ibat1l 531 Instruction BAT register 1 (lower) ibat2u 532 Instruction BAT register 2 (upper) ibat2l 533 Instruction BAT register 2 (lower) ibat3u 534 Instruction BAT register 3 (upper) ibat3l 535 Instruction BAT register 3 (lower) dbat0u 536 Data BAT register 0 (upper) dbat0l 537 Data BAT register 0 (lower) dbat1u 538 Data BAT register 1 (upper) dbat1l 539 Data BAT register 1 (lower) dbat2u 540 Data BAT register 2 (upper) dbat2l 541 Data BAT register 2 (lower) dbat3u 542 Data BAT register 3 (upper) dbat3l 543 Data BAT register 3 (lower) ;iccsr 560 I-cache control and status register ;icadr 561 I-cache address register ;icdat 562 I-cache data port (read only) dpdr 630 Development port data register sia 780 Sampled Instruction Address sda 781 Sampled Data Address ;pmc1 787 Performance Monitor Counter 1 (read only) ;pmc2 788 Performance Monitor Counter 2 (read only) ;pmc3 789 Performance Monitor Counter 3 (read only) ;pmc4 790 Performance Monitor Counter 4 (read only) ;pmc5 791 Performance Monitor Counter 5 (read only) ;pmc6 792 Performance Monitor Counter 6 (read only) ;pmc7 793 Performance Monitor Counter 7 (read only) ;pmc8 794 Performance Monitor Counter 8 (read only) ;mmcr0 795 Monitor Mode Control Regiater 0 (read only) ;mmcr1 798 Monitor Mode Control Regiater 1 (read only) hid0 1008 iabr 1010 dabr 1013 Data address breakpoint register buscsr 1016 l2cr 1017 l2sr 1018 fpecr 1022 Floating-point exception cause register pir 1023 ;-------------------------------------- ; MPC860 specifics Supervisor-Level SPR dpir 631 Development Port Instruction Register immr 638 Internal Memory Map register ic_csr 560 I-cache control and status register ic_adr 561 I-cache address register ic_dat 562 I-cache data port (read only) dc_cst 568 D-cache control and status register dc_adr 569 D-cache address register dc_dat 570 D-cache data port (read only) mi_ctr 784 I-MMU Control Register mi_ap 786 I-MMU Access Protect Register mi_epn 787 I-MMU Effective Page Number Register mi_twc 789 I-MMU Tablewalk Control Register mi_rpn 790 I-MMU Real Page Number Register mi_cam 816 I-MMU CAM Entry Read Register mi_ram0 817 I-MMU RAM Entry Read Register 0 mi_ram1 818 I-MMU RAM Entry Read Register 1 md_ctr 792 D-MMU Control Register m_casid 793 MMU Current Address Sapce ID Register md_ap 794 D-MMU Access Protect Register md_epn 795 D-MMU Effective Page Number Register m_twb 796 MMU Tablewalk Base Register md_twc 797 D-MMU Tablewalk Control Register md_rpn 798 D-MMU Real Page Number Register m_tw 799 MMU Tablewalk Special Register md_cam 824 D-MMU CAM Entry Read Register md_ram0 825 D-MMU RAM Entry Read Register 0 md_ram1 826 D-MMU RAM Entry Read Register 1 zpr 0x3b0 zone protection register (403GC) pid 0x3b1 process id register (403GC) smr 0x3b8 storage mem-coherent (not implemented) sgr 0x3b9 storage guarded register (403GC) dcwr 0x3ba data cache write-thru register (403GC) tbhu 0x3cc user-mode time base high (403GC) tblu 0x3cd user-mode time base low (403GC) icdbdr 0x3d3 instruction cache debug data reg (403GC) esr 0x3d4 execption syndrome register dear 0x3d5 data exeption address register evpr 0x3d6 exeption vector prefix register cdbcr 0x3d7 cache debug control register (403GC) tsr 0x3d8 timer status register tcr 0x3da timer control register pit 0x3db programmable interval timer tbhi 0x3dc time base high tblo 0x3dd time base low srr2 0x3de save/restore register 2 srr3 0x3df save/restore register 3 ;dbsr 0x3f0 debug status register ;dbcr 0x3f2 debug control register iac1 0x3f4 instruction address comparator 1 ;iac2 0x3f5 instruction address comparator 2 dac1 0x3f6 data address comparator 1 dac2 0x3f7 data address comparator 2 ;dccr 0x3fa data cache control register iccr 0x3fb instruction cache control register pbl1 0x3fc protection bound lower 1 pbu1 0x3fd protection bound upper 1 ;pbl2 0x3fe protection bound lower 2 ;pbu2 0x3ff protection bound upper 2