; The format of the input file: ; each device definition begins with a line like this: ; ; .devicename ; ; after it go the port definitions in this format: ; ; portname address ; ; the bit definitions (optional) are represented like this: ; ; portname.bitname bitnumber ; ; lines beginning with a space are ignored. ; comment lines should be started with ';' character. ; ; the default device is specified at the start of the file ; ; .default device_name ; ; all lines non conforming to the format are passed to the callback function ; ; MOTOROLA SPECIFIC LINES ;------------------------ ; ; the processor definition may include the memory configuration. ; the line format is: ; area CLASS AREA-NAME START:END ; ; where CLASS is anything, but please use one of CODE, DATA, BSS ; START and END are addresses, the end address is not included ; Interrupt vectors are declared in the following way: ; interrupt NAME ADDRESS COMMENT .default 68HC912DG128A .68HC912B32 ; ; M68HC12B.pdf ; MEMORY MAP area DATA FSR 0x0000:0x0200 REGISTERS 512 BYTES area BSS RESERVED 0x0200:0x0800 area DATA RAM 0x0800:0x0C00 1-KBYTE RAM area BSS RESERVED 0x0C00:0x0D00 area DATA EEPROM 0x0D00:0x1000 768 BYTES EEPROM area BSS RESERVED 0x1000:0x8000 area DATA EEPROM_ROM 0x8000:0xFFC0 FLASH EEPROM/ROM area DATA USER_VEC 0xFFC0:0x10000 ; Interrupt and reset vector assignments interrupt __RESET 0xFFFE Processor reset interrupt CME_FCME 0xFFFC COP clock monitor fail reset interrupt COP_FR 0xFFFA COP failure reset interrupt UIT 0xFFF8 Unimplemented instruction trap interrupt SWI 0xFFF6 SWI interrupt XIRQ 0xFFF4 XIRQ interrupt IRQEN 0xFFF2 IRQ interrupt RTIE 0xFFF0 Real-time interrupt interrupt C0I 0xFFEE Timer channel 0 interrupt C1I 0xFFEC Timer channel 1 interrupt C2I 0xFFEA Timer channel 2 interrupt C3I 0xFFE8 Timer channel 3 interrupt C4I 0xFFE6 Timer channel 4 interrupt C5I 0xFFE4 Timer channel 5 interrupt C6I 0xFFE2 Timer channel 6 interrupt C7I 0xFFE0 Timer channel 7 interrupt TOI 0xFFDE Timer overflow interrupt PAOVI 0xFFDC Pulse accumulator overflow interrupt PAI 0xFFDA Pulse accumulator input edge interrupt SPIE 0xFFD8 SPI serial transfer complete interrupt TIE_TCIE_RIE_ILIE 0xFFD6 SCI 0 interrupt ASCIE 0xFFD2 ATD interrupt IE 0xFFD0 BDLC interrupt MCZI 0xFFCC Modulus down counter underflow interrupt PBOVI 0xFFCA Pulse accumulator B overflow ; INPUT/ OUTPUT PORTS PORTA 0x0000 Port A Data Register PORTA.PA7 7 Port A Data Bit 7 PORTA.PA6 6 Port A Data Bit 6 PORTA.PA5 5 Port A Data Bit 5 PORTA.PA4 4 Port A Data Bit 4 PORTA.PA3 3 Port A Data Bit 3 PORTA.PA2 2 Port A Data Bit 2 PORTA.PA1 1 Port A Data Bit 1 PORTA.PA0 0 Port A Data Bit 0 PORTB 0x0001 Port B Data Register PORTB.PB7 7 Port B Data Bit 7 PORTB.PB6 6 Port B Data Bit 6 PORTB.PB5 5 Port B Data Bit 5 PORTB.PB4 4 Port B Data Bit 4 PORTB.PB3 3 Port B Data Bit 3 PORTB.PB2 2 Port B Data Bit 2 PORTB.PB1 1 Port B Data Bit 1 PORTB.PB0 0 Port B Data Bit 0 DDRA 0x0002 Data Direction Register A DDRA.DDA7 7 Data Direction Register A Bit 7 DDRA.DDA6 6 Data Direction Register A Bit 6 DDRA.DDA5 5 Data Direction Register A Bit 5 DDRA.DDA4 4 Data Direction Register A Bit 4 DDRA.DDA3 3 Data Direction Register A Bit 3 DDRA.DDA2 2 Data Direction Register A Bit 2 DDRA.DDA1 1 Data Direction Register A Bit 1 DDRA.DDA0 0 Data Direction Register A Bit 0 DDRB 0x0003 Data Direction Register B DDRB.DDB7 7 Data Direction Register B Bit 7 DDRB.DDB6 6 Data Direction Register B Bit 6 DDRB.DDB5 5 Data Direction Register B Bit 5 DDRB.DDB4 4 Data Direction Register B Bit 4 DDRB.DDB3 3 Data Direction Register B Bit 3 DDRB.DDB2 2 Data Direction Register B Bit 2 DDRB.DDB1 1 Data Direction Register B Bit 1 DDRB.DDB0 0 Data Direction Register B Bit 0 RESERVED00004 0x0004 RESERVED RESERVED00005 0x0005 RESERVED RESERVED00006 0x0006 RESERVED RESERVED00007 0x0007 RESERVED PORTE 0x0008 Port E Data Register PORTE.PE7 7 Port E Data Bit 7 PORTE.PE6 6 Port E Data Bit 6 PORTE.PE5 5 Port E Data Bit 5 PORTE.PE4 4 Port E Data Bit 4 PORTE.PE3 3 Port E Data Bit 3 PORTE.PE2 2 Port E Data Bit 2 PORTE.PE1 1 Port E Data Bit 1 PORTE.PE0 0 Port E Data Bit 0 DDRE 0x0009 Data Direction Register E DDRE.DDE7 7 Data Direction Register E Bit 7 DDRE.DDE6 6 Data Direction Register E Bit 6 DDRE.DDE5 5 Data Direction Register E Bit 5 DDRE.DDE4 4 Data Direction Register E Bit 4 DDRE.DDE3 3 Data Direction Register E Bit 3 DDRE.DDE2 2 Data Direction Register E Bit 2 DDRE.DDE1 1 Data Direction Register E Bit 1 DDRE.DDE0 0 Data Direction Register E Bit 0 PEAR 0x000A Port E Assignment Register PEAR.NDBE 7 No Data Bus Enable Bit PEAR.CGMTE 6 CGM Test Output Enable PEAR.PIPOE 5 Pipe Signal Output Enable Bit PEAR.NECLK 4 No External E Clock Bit PEAR.LSTRE 3 Low Strobe (LSTRB) Enable Bit PEAR.RDWE 2 Read/Write Enable Bit MODE 0x000B Mode Register MODE.SMODN 7 Mode Select Special MODE.MODB 6 Mode Select Special B Bit MODE.MODA 5 Mode Select Special A Bit MODE.ESTR 4 E Clock Stretch Enable Bit MODE.IVIS 3 Internal Visibility Bit MODE.EBSWAI 2 External Bus Module Stop in Wait Bit MODE.EME 0 Emulate Port E Bit PUCR 0x000C Pullup Control Register PUCR.PUPE 4 Pullup Port E Enable Bit PUCR.PUPB 1 Pullup Port B Enable Bit PUCR.PUPA 0 Pullup Port A Enable Bit RDRIV 0x000D Reduced Drive Register RDRIV.RDPE 3 Reduced Drive of Port E Bit RDRIV.RDPB 1 Reduced Drive of Port B Bit RDRIV.RDPA 0 Reduced Drive of Port A Bit RESERVED000E 0x000E RESERVED RESERVED000F 0x000F RESERVED INITRM 0x0010 RAM Initialization Register INITRM.RAM15 7 RAM Position Bit 15 INITRM.RAM14 6 RAM Position Bit 14 INITRM.RAM13 5 RAM Position Bit 13 INITRM.RAM12 4 RAM Position Bit 12 INITRM.RAM11 3 RAM Position Bit 11 INITRG 0x0011 Register Initialization Register INITRG.REG15 7 Register Position Bit 15 INITRG.REG14 6 Register Position Bit 14 INITRG.REG13 5 Register Position Bit 13 INITRG.REG12 4 Register Position Bit 12 INITRG.REG11 3 Register Position Bit 11 INITRG.MMSWAI 0 Memory Mapping Interface Stop in Wait Control Bit INITEE 0x0012 EEPROM Initialization Register INITEE.EE15 7 Internal EEPROM Position Bit 15 INITEE.EE14 6 Internal EEPROM Position Bit 14 INITEE.EE13 5 Internal EEPROM Position Bit 13 INITEE.EE12 4 Internal EEPROM Position Bit 12 INITEE.EEON 0 EEPROM On Bit MISC 0x0013 Miscellaneous Mapping Control Register MISC.NDRF 6 Narrow Data Bus for Register-Following Map Bit MISC.RFSTR1 5 Register-Following Stretch Bit 1 MISC.RFSTR0 4 Register-Following Stretch Bit 0 MISC.EXSTR1 3 External Access Stretch Bit 1 MISC.EXSTR0 2 External Access Stretch Bit 0 MISC.MAPROM 1 FLASH EEPROM/ROM Map Bit MISC.ROMON 0 FLASH EEPROM/ROM Enable Bit RTICTL 0x0014 Real-Time Interrupt Control Register RTICTL.RTIE 7 Real-Time Interrupt Enable Bit RTICTL.RSWAI 6 RTI and COP Stop While in Wait Bit RTICTL.RSBCK 5 RTI and COP Stop While in Background Debug Mode Bit RTICTL.RTBYP 3 Real-Time Interrupt Divider Chain Bypass Bit RTICTL.RTR2 2 Real-Time Interrupt Rate Select Bit 2 RTICTL.RTR1 1 Real-Time Interrupt Rate Select Bit 1 RTICTL.RTR0 0 Real-Time Interrupt Rate Select Bit 0 RTIFLG 0x0015 Real-Time Interrupt Flag Register RTIFLG.RTIF 7 Real-Time Interrupt Flag Bit COPCTL 0x0016 COP Control Register COPCTL.CME 7 Clock Monitor Enable Bit COPCTL.FCME 6 Force Clock Monitor Enable Bit COPCTL.FCM 5 Force Clock Monitor Reset Bit COPCTL.FCOP 4 Force COP Watchdog Reset Bit COPCTL.DISR 3 Disable Resets from COP Watchdog and Clock Monitor Bit COPCTL.CR2 2 COP Watchdog Timer Rate Select Bit 2 COPCTL.CR1 1 COP Watchdog Timer Rate Select Bit 1 COPCTL.CR0 0 COP Watchdog Timer Rate Select Bit 0 COPRST 0x0017 Arm/Reset COP Timer Register RESERVED0018 0x0018 RESERVED RESERVED0019 0x0019 RESERVED RESERVED001A 0x001A RESERVED RESERVED001B 0x001B RESERVED RESERVED001C 0x001C RESERVED RESERVED001D 0x001D RESERVED INTCR 0x001E Interrupt Control Register INTCR.IRQE 7 IRQ Edge-Sensitive Only Bit INTCR.IRQEN 6 External IRQ Enable Bit INTCR.DLY 5 Oscillator Startup Delay on Exit from Stop Mode Bit HPRIO 0x001F Highest Priority I Interrupt Register HPRIO.PSEL5 5 HPRIO.PSEL4 4 HPRIO.PSEL3 3 HPRIO.PSEL2 2 HPRIO.PSEL1 1 BRKCT0 0x0020 Breakpoint Control Register 0 BRKCT0.BKEN1 7 Breakpoint Mode Enable Bit 1 BRKCT0.BKEN0 6 Breakpoint Mode Enable Bit 0 BRKCT0.BKPM 5 Break on Program Addresses BRKCT0.BK1ALE 3 Breakpoint 1 Range Control Bit BRKCT0.BK0ALE 2 Breakpoint 0 Range Control Bit BRKCT1 0x0021 Breakpoint Control Register 1 BRKCT1.BKDBE 6 Enable Data Bus Bit BRKCT1.BKMBH 5 Breakpoint Mask High Bit BRKCT1.BKMBL 4 Breakpoint Mask Low Bit BRKCT1.BK1RWE 3 R/W Compare Enable Bit BRKCT1.BK1RW 2 R/W Compare Value Bit BRKCT1.BK0RWE 1 R/W Compare Enable Bit BRKCT1.BK0RW 0 R/W Compare Value Bit BRKAH 0x0022 Breakpoint Address Register High BRKAL 0x0023 Breakpoint Address Register Low BRKDH 0x0024 Breakpoint Data Register High BRKDL 0x0025 Breakpoint Data Register Low RESERVED0026 0x0026 RESERVED RESERVED0027 0x0027 RESERVED RESERVED0028 0x0028 RESERVED RESERVED0029 0x0029 RESERVED RESERVED002A 0x002A RESERVED RESERVED002B 0x002B RESERVED RESERVED002C 0x002C RESERVED RESERVED002D 0x002D RESERVED RESERVED002E 0x002E RESERVED RESERVED002F 0x002F RESERVED RESERVED0030 0x0030 RESERVED RESERVED0031 0x0031 RESERVED RESERVED0032 0x0032 RESERVED RESERVED0033 0x0033 RESERVED RESERVED0034 0x0034 RESERVED RESERVED0035 0x0035 RESERVED RESERVED0036 0x0036 RESERVED RESERVED0037 0x0037 RESERVED RESERVED0038 0x0038 RESERVED RESERVED0039 0x0039 RESERVED RESERVED003A 0x003A RESERVED RESERVED003B 0x003B RESERVED RESERVED003C 0x003C RESERVED RESERVED003D 0x003D RESERVED RESERVED003E 0x003E RESERVED RESERVED003F 0x003F RESERVED PWCLK 0x0040 PWM Clocks and Concatenate Register PWCLK.CON23 7 Concatenate PWM Channels 2 and 3 Bit PWCLK.CON01 6 Concatenate PWM Channels 0 and 1 Bit PWCLK.PCKA2 5 Prescaler for Clock A Bit 2 PWCLK.PCKA1 4 Prescaler for Clock A Bit 1 PWCLK.PCKA0 3 Prescaler for Clock A Bit 0 PWCLK.PCKB2 2 Prescaler for Clock B Bit 2 PWCLK.PCKB1 1 Prescaler for Clock B Bit 1 PWCLK.PCKB0 0 Prescaler for Clock B Bit 0 PWPOL 0x0041 PWM Clock Select and Polarity Register PWPOL.PCLK3 7 PWM Channel 3 Clock Select Bit PWPOL.PCLK2 6 PWM Channel 2 Clock Select Bit PWPOL.PCLK1 5 PWM Channel 1 Clock Select Bit PWPOL.PCLK0 4 PWM Channel 0 Clock Select Bit PWPOL.PPOL3 3 PWM Channel 3 Polarity Bit PWPOL.PPOL2 2 PWM Channel 2 Polarity Bit PWPOL.PPOL1 1 PWM Channel 1 Polarity Bit PWPOL.PPOL0 0 PWM Channel 0 Polarity Bit PWEN 0x0042 PWM Enable Register PWEN.PWEN3 3 PWM Channel 3 Enable Bit PWEN.PWEN2 2 PWM Channel 2 Enable Bit PWEN.PWEN1 1 PWM Channel 1 Enable Bit PWEN.PWEN0 0 PWM Channel 0 Enable Bit PWPRES 0x0043 PWM Prescaler Counter Register PWSCAL0 0x0044 PWM Scale Register 0 PWSCNT0 0x0045 PWM Scale Counter Register 0 PWSCAL1 0x0046 PWM Scale Register 1 PWSCNT1 0x0047 PWM Scale Counter Register 1 PWCNT0 0x0048 PWM Channel Counter Register 0 PWCNT1 0x0049 PWM Channel Counter Register 1 PWCNT2 0x004A PWM Channel Counter Register 2 PWCNT3 0x004B PWM Channel Counter Register 3 PWPER0 0x004C PWM Channel Period Register 0 PWPER1 0x004D PWM Channel Period Register 1 PWPER2 0x004E PWM Channel Period Register 2 PWPER3 0x004F PWM Channel Period Register 3 PWDTY0 0x0050 PWM Channel Duty Register 0 PWDTY1 0x0051 PWM Channel Duty Register 1 PWDTY2 0x0052 PWM Channel Duty Register 2 PWDTY3 0x0053 PWM Channel Duty Register 3 PWCTL 0x0054 PWM Control Register PWCTL.PSWAI 4 PWM Halts While in Wait Mode Bit PWCTL.CENTR 3 Center-Aligned Output Mode Bit PWCTL.RDPP 2 Reduced Drive of Port P Bit PWCTL.PUPP 1 Pullup Port P Enable Bit PWCTL.PSBCK 0 PWM Stops While in Background Mode Bit PWTST 0x0055 PWM Special Mode Register PWTST.DISCR 7 Disable Channel Counter Reset Bit PWTST.DISCP 6 Disable Compare Count Period Bit PWTST.DISCAL 5 Disable Scale Counter Loading Bit PORTP 0x0056 Port P Data Register PORTP.PP7 7 Port P Data Bit 7 PORTP.PP6 6 Port P Data Bit 6 PORTP.PP5 5 Port P Data Bit 5 PORTP.PP4 4 Port P Data Bit 4 PORTP.PP3 3 Port P Data Bit 3 PORTP.PP2 2 Port P Data Bit 2 PORTP.PP1 1 Port P Data Bit 1 PORTP.PP0 0 Port P Data Bit 0 DDRP 0x0057 Port P Data Direction Register DDRP.DDP7 7 Port P Data Direction Register Bit 7 DDRP.DDP6 6 Port P Data Direction Register Bit 6 DDRP.DDP5 5 Port P Data Direction Register Bit 5 DDRP.DDP4 4 Port P Data Direction Register Bit 4 DDRP.DDP3 3 Port P Data Direction Register Bit 3 DDRP.DDP2 2 Port P Data Direction Register Bit 2 DDRP.DDP1 1 Port P Data Direction Register Bit 1 DDRP.DDP0 0 Port P Data Direction Register Bit 0 RESERVED0058 0x0058 RESERVED RESERVED0059 0x0059 RESERVED RESERVED005A 0x005A RESERVED RESERVED005B 0x005B RESERVED RESERVED005C 0x005C RESERVED RESERVED005D 0x005D RESERVED RESERVED005E 0x005E RESERVED RESERVED005F 0x005F RESERVED ATDCTL0 0x0060 ATD Control Register 0 ATDCTL1 0x0061 ATD Control Register 1 ATDCTL2 0x0062 ATD Control Register 2 ATDCTL2.ADPU 7 ATD Disable Bit ATDCTL2.AFFC 6 ATD Fast Flag Clear Bit ATDCTL2.AWAI 5 ATD Stop in Wait Mode Bit ATDCTL2.ASCIE 1 ATD Sequence Complete Interrupt Enable Bit ATDCTL2.ASCIF 0 ATD Sequence Complete Interrupt Flag ATDCTL3 0x0063 ATD Control Register 3 ATDCTL3.FRZ1 1 Background Debug (Freeze) Enable Bit ATDCTL3.FRZ0 0 Background Debug (Freeze) Enable Bit ATDCTL4 0x0064 ATD Control Register 4 ATDCTL4.S10BM 7 ATD 10-Bit Mode Control Bit ATDCTL4.SMP1 6 Select Sample Time Bit 1 ATDCTL4.SMP0 5 Select Sample Time Bit 0 ATDCTL4.PRS4 4 Select Divide-By Factor for ATD P-Clock Prescaler Bit 4 ATDCTL4.PRS3 3 Select Divide-By Factor for ATD P-Clock Prescaler Bit 3 ATDCTL4.PRS2 2 Select Divide-By Factor for ATD P-Clock Prescaler Bit 2 ATDCTL4.PRS1 1 Select Divide-By Factor for ATD P-Clock Prescaler Bit 1 ATDCTL4.PRS0 0 Select Divide-By Factor for ATD P-Clock Prescaler Bit 0 ATDCTL5 0x0065 ATD Control Register 5 ATDCTL5.S8CM 6 Select 8 Channel Mode Bit ATDCTL5.SCAN 5 Enable Continuous Channel Scan Bit ATDCTL5.MULT 4 Enable Multichannel Conversion Bit ATDCTL5.CD 3 Channel Select for Conversion Bit ATDCTL5.CC 2 Channel Select for Conversion Bit ATDCTL5.CB 1 Channel Select for Conversion Bit ATDCTL5.CA 0 Channel Select for Conversion Bit ATDSTAT 0x0066 ATD Status Register ATDSTAT.SCF 7 Sequence Complete Flag ATDSTAT.CC2 2 Conversion Counter Bit 2 for Current 4 or 8 Conversions ATDSTAT.CC1 1 Conversion Counter Bit 1 for Current 4 or 8 Conversions ATDSTAT.CC0 0 Conversion Counter Bit 0 for Current 4 or 8 Conversions ATDSTATL 0x0067 ATD Status Register ATDSTATL.CCF7 7 Sequence Complete Flag 7 ATDSTATL.CCF6 6 Sequence Complete Flag 6 ATDSTATL.CCF5 5 Sequence Complete Flag 5 ATDSTATL.CCF4 4 Sequence Complete Flag 4 ATDSTATL.CCF3 3 Sequence Complete Flag 3 ATDSTATL.CCF2 2 Sequence Complete Flag 2 ATDSTATL.CCF1 1 Sequence Complete Flag 1 ATDSTATL.CCF0 0 Sequence Complete Flag 0 ATDTSTH 0x0068 ATD Test Register High ATDTSTH.SAR9 7 SAR Data Bit 9 ATDTSTH.SAR8 6 SAR Data Bit 8 ATDTSTH.SAR7 5 SAR Data Bit 7 ATDTSTH.SAR6 4 SAR Data Bit 6 ATDTSTH.SAR5 3 SAR Data Bit 5 ATDTSTH.SAR4 2 SAR Data Bit 4 ATDTSTH.SAR3 1 SAR Data Bit 3 ATDTSTH.SAR2 0 SAR Data Bit 2 ATDTSTL 0x0069 ATD Test Register Low ATDTSTL.SAR1 7 SAR Data Bit 1 ATDTSTL.SAR0 6 SAR Data Bit 0 ATDTSTL.RST 5 Module Reset Bit ATDTSTL.TSTOUT 4 Multiplex Output of TST3-TST0 (Factory Use) ATDTSTL.TST3 3 Test Bits 3 ATDTSTL.TST2 2 Test Bits 2 ATDTSTL.TST1 1 Test Bits 1 ATDTSTL.TST0 0 Test Bits 0 RESERVED006A 0x006A RESERVED RESERVED006B 0x006B RESERVED RESERVED006C 0x006C RESERVED RESERVED006D 0x006D RESERVED RESERVED006E 0x006E RESERVED PORTAD 0x006F Port AD Data Input Register PORTAD.PAD7 7 Port AD Data Input Bit 7 PORTAD.PAD6 6 Port AD Data Input Bit 6 PORTAD.PAD5 5 Port AD Data Input Bit 5 PORTAD.PAD4 4 Port AD Data Input Bit 4 PORTAD.PAD3 3 Port AD Data Input Bit 3 PORTAD.PAD2 2 Port AD Data Input Bit 2 PORTAD.PAD1 1 Port AD Data Input Bit 1 PORTAD.PAD0 0 Port AD Data Input Bit 0 ADRx0H 0x0070 ATD Result Register 0 High ADRx0H.ADRxH15 7 ATD Conversion Result Bit 15 ADRx0H.ADRxH14 6 ATD Conversion Result Bit 14 ADRx0H.ADRxH13 5 ATD Conversion Result Bit 13 ADRx0H.ADRxH12 4 ATD Conversion Result Bit 12 ADRx0H.ADRxH11 3 ATD Conversion Result Bit 11 ADRx0H.ADRxH10 2 ATD Conversion Result Bit 10 ADRx0H.ADRxH9 1 ATD Conversion Result Bit 9 ADRx0H.ADRxH8 0 ATD Conversion Result Bit 8 ADRx0L 0x0071 ATD Result Register 0 Low ADRx0L.ADRxHL7 7 ATD Conversion Result Bit 7 ADRx0L.ADRxHL6 6 ATD Conversion Result Bit 6 ADRx0L.ADRxHL5 5 ATD Conversion Result Bit 5 ADRx0L.ADRxHL4 4 ATD Conversion Result Bit 4 ADRx0L.ADRxHL3 3 ATD Conversion Result Bit 3 ADRx0L.ADRxHL2 2 ATD Conversion Result Bit 2 ADRx0L.ADRxHL1 1 ATD Conversion Result Bit 1 ADRx0L.ADRxHL0 0 ATD Conversion Result Bit 0 ADRx1H 0x0072 ATD Result Register 1 High ADRx1H.ADRxH15 7 ATD Conversion Result Bit 15 ADRx1H.ADRxH14 6 ATD Conversion Result Bit 14 ADRx1H.ADRxH13 5 ATD Conversion Result Bit 13 ADRx1H.ADRxH12 4 ATD Conversion Result Bit 12 ADRx1H.ADRxH11 3 ATD Conversion Result Bit 11 ADRx1H.ADRxH10 2 ATD Conversion Result Bit 10 ADRx1H.ADRxH9 1 ATD Conversion Result Bit 9 ADRx1H.ADRxH8 0 ATD Conversion Result Bit 8 ADRx1L 0x0073 ATD Result Register 1 Low ADRx1L.ADRxHL7 7 ATD Conversion Result Bit 7 ADRx1L.ADRxHL6 6 ATD Conversion Result Bit 6 ADRx1L.ADRxHL5 5 ATD Conversion Result Bit 5 ADRx1L.ADRxHL4 4 ATD Conversion Result Bit 4 ADRx1L.ADRxHL3 3 ATD Conversion Result Bit 3 ADRx1L.ADRxHL2 2 ATD Conversion Result Bit 2 ADRx1L.ADRxHL1 1 ATD Conversion Result Bit 1 ADRx1L.ADRxHL0 0 ATD Conversion Result Bit 0 ADRx2H 0x0074 ATD Result Register 2 High ADRx2H.ADRxH15 7 ATD Conversion Result Bit 15 ADRx2H.ADRxH14 6 ATD Conversion Result Bit 14 ADRx2H.ADRxH13 5 ATD Conversion Result Bit 13 ADRx2H.ADRxH12 4 ATD Conversion Result Bit 12 ADRx2H.ADRxH11 3 ATD Conversion Result Bit 11 ADRx2H.ADRxH10 2 ATD Conversion Result Bit 10 ADRx2H.ADRxH9 1 ATD Conversion Result Bit 9 ADRx2H.ADRxH8 0 ATD Conversion Result Bit 8 ADRx2L 0x0075 ATD Result Register 2 Low ADRx2L.ADRxHL7 7 ATD Conversion Result Bit 7 ADRx2L.ADRxHL6 6 ATD Conversion Result Bit 6 ADRx2L.ADRxHL5 5 ATD Conversion Result Bit 5 ADRx2L.ADRxHL4 4 ATD Conversion Result Bit 4 ADRx2L.ADRxHL3 3 ATD Conversion Result Bit 3 ADRx2L.ADRxHL2 2 ATD Conversion Result Bit 2 ADRx2L.ADRxHL1 1 ATD Conversion Result Bit 1 ADRx2L.ADRxHL0 0 ATD Conversion Result Bit 0 ADRx3H 0x0076 ATD Result Register 3 High ADRx3H.ADRxH15 7 ATD Conversion Result Bit 15 ADRx3H.ADRxH14 6 ATD Conversion Result Bit 14 ADRx3H.ADRxH13 5 ATD Conversion Result Bit 13 ADRx3H.ADRxH12 4 ATD Conversion Result Bit 12 ADRx3H.ADRxH11 3 ATD Conversion Result Bit 11 ADRx3H.ADRxH10 2 ATD Conversion Result Bit 10 ADRx3H.ADRxH9 1 ATD Conversion Result Bit 9 ADRx3H.ADRxH8 0 ATD Conversion Result Bit 8 ADRx3L 0x0077 ATD Result Register 3 Low ADRx3L.ADRxHL7 7 ATD Conversion Result Bit 7 ADRx3L.ADRxHL6 6 ATD Conversion Result Bit 6 ADRx3L.ADRxHL5 5 ATD Conversion Result Bit 5 ADRx3L.ADRxHL4 4 ATD Conversion Result Bit 4 ADRx3L.ADRxHL3 3 ATD Conversion Result Bit 3 ADRx3L.ADRxHL2 2 ATD Conversion Result Bit 2 ADRx3L.ADRxHL1 1 ATD Conversion Result Bit 1 ADRx3L.ADRxHL0 0 ATD Conversion Result Bit 0 ADRx4H 0x0078 ATD Result Register 4 High ADRx4H.ADRxH15 7 ATD Conversion Result Bit 15 ADRx4H.ADRxH14 6 ATD Conversion Result Bit 14 ADRx4H.ADRxH13 5 ATD Conversion Result Bit 13 ADRx4H.ADRxH12 4 ATD Conversion Result Bit 12 ADRx4H.ADRxH11 3 ATD Conversion Result Bit 11 ADRx4H.ADRxH10 2 ATD Conversion Result Bit 10 ADRx4H.ADRxH9 1 ATD Conversion Result Bit 9 ADRx4H.ADRxH8 0 ATD Conversion Result Bit 8 ADRx4L 0x0079 ATD Result Register 4 Low ADRx4L.ADRxHL7 7 ATD Conversion Result Bit 7 ADRx4L.ADRxHL6 6 ATD Conversion Result Bit 6 ADRx4L.ADRxHL5 5 ATD Conversion Result Bit 5 ADRx4L.ADRxHL4 4 ATD Conversion Result Bit 4 ADRx4L.ADRxHL3 3 ATD Conversion Result Bit 3 ADRx4L.ADRxHL2 2 ATD Conversion Result Bit 2 ADRx4L.ADRxHL1 1 ATD Conversion Result Bit 1 ADRx4L.ADRxHL0 0 ATD Conversion Result Bit 0 ADRx5H 0x007A ATD Result Register 5 High ADRx5H.ADRxH15 7 ATD Conversion Result Bit 15 ADRx5H.ADRxH14 6 ATD Conversion Result Bit 14 ADRx5H.ADRxH13 5 ATD Conversion Result Bit 13 ADRx5H.ADRxH12 4 ATD Conversion Result Bit 12 ADRx5H.ADRxH11 3 ATD Conversion Result Bit 11 ADRx5H.ADRxH10 2 ATD Conversion Result Bit 10 ADRx5H.ADRxH9 1 ATD Conversion Result Bit 9 ADRx5H.ADRxH8 0 ATD Conversion Result Bit 8 ADRx5L 0x007B ATD Result Register 5 Low ADRx5L.ADRxHL7 7 ATD Conversion Result Bit 7 ADRx5L.ADRxHL6 6 ATD Conversion Result Bit 6 ADRx5L.ADRxHL5 5 ATD Conversion Result Bit 5 ADRx5L.ADRxHL4 4 ATD Conversion Result Bit 4 ADRx5L.ADRxHL3 3 ATD Conversion Result Bit 3 ADRx5L.ADRxHL2 2 ATD Conversion Result Bit 2 ADRx5L.ADRxHL1 1 ATD Conversion Result Bit 1 ADRx5L.ADRxHL0 0 ATD Conversion Result Bit 0 ADRx6H 0x007C ATD Result Register 6 High ADRx6H.ADRxH15 7 ATD Conversion Result Bit 15 ADRx6H.ADRxH14 6 ATD Conversion Result Bit 14 ADRx6H.ADRxH13 5 ATD Conversion Result Bit 13 ADRx6H.ADRxH12 4 ATD Conversion Result Bit 12 ADRx6H.ADRxH11 3 ATD Conversion Result Bit 11 ADRx6H.ADRxH10 2 ATD Conversion Result Bit 10 ADRx6H.ADRxH9 1 ATD Conversion Result Bit 9 ADRx6H.ADRxH8 0 ATD Conversion Result Bit 8 ADRx6L 0x007D ATD Result Register 6 Low ADRx6L.ADRxHL7 7 ATD Conversion Result Bit 7 ADRx6L.ADRxHL6 6 ATD Conversion Result Bit 6 ADRx6L.ADRxHL5 5 ATD Conversion Result Bit 5 ADRx6L.ADRxHL4 4 ATD Conversion Result Bit 4 ADRx6L.ADRxHL3 3 ATD Conversion Result Bit 3 ADRx6L.ADRxHL2 2 ATD Conversion Result Bit 2 ADRx6L.ADRxHL1 1 ATD Conversion Result Bit 1 ADRx6L.ADRxHL0 0 ATD Conversion Result Bit 0 ADRx7H 0x007E ATD Result Register 7 High ADRx7H.ADRxH15 7 ATD Conversion Result Bit 15 ADRx7H.ADRxH14 6 ATD Conversion Result Bit 14 ADRx7H.ADRxH13 5 ATD Conversion Result Bit 13 ADRx7H.ADRxH12 4 ATD Conversion Result Bit 12 ADRx7H.ADRxH11 3 ATD Conversion Result Bit 11 ADRx7H.ADRxH10 2 ATD Conversion Result Bit 10 ADRx7H.ADRxH9 1 ATD Conversion Result Bit 9 ADRx7H.ADRxH8 0 ATD Conversion Result Bit 8 ADRx7L 0x007F ATD Result Register 7 Low ADRx7L.ADRxHL7 7 ATD Conversion Result Bit 7 ADRx7L.ADRxHL6 6 ATD Conversion Result Bit 6 ADRx7L.ADRxHL5 5 ATD Conversion Result Bit 5 ADRx7L.ADRxHL4 4 ATD Conversion Result Bit 4 ADRx7L.ADRxHL3 3 ATD Conversion Result Bit 3 ADRx7L.ADRxHL2 2 ATD Conversion Result Bit 2 ADRx7L.ADRxHL1 1 ATD Conversion Result Bit 1 ADRx7L.ADRxHL0 0 ATD Conversion Result Bit 0 TIOS 0x0080 Timer IC/OC Select Register TIOS.IOS7 7 Force Output Compare Action Bits for Channel 7 TIOS.IOS6 6 Force Output Compare Action Bits for Channel 6 TIOS.IOS5 5 Force Output Compare Action Bits for Channel 5 TIOS.IOS4 4 Force Output Compare Action Bits for Channel 4 TIOS.IOS3 3 Force Output Compare Action Bits for Channel 3 TIOS.IOS2 2 Force Output Compare Action Bits for Channel 2 TIOS.IOS1 1 Force Output Compare Action Bits for Channel 1 TIOS.IOS0 0 Force Output Compare Action Bits for Channel 0 CFORC 0x0081 Timer Compare Force Register CFORC.FOC7 7 Force Output Compare Action Bits for Channel 7 CFORC.FOC6 6 Force Output Compare Action Bits for Channel 6 CFORC.FOC5 5 Force Output Compare Action Bits for Channel 5 CFORC.FOC4 4 Force Output Compare Action Bits for Channel 4 CFORC.FOC3 3 Force Output Compare Action Bits for Channel 3 CFORC.FOC2 2 Force Output Compare Action Bits for Channel 2 CFORC.FOC1 1 Force Output Compare Action Bits for Channel 1 CFORC.FOC0 0 Force Output Compare Action Bits for Channel 0 OC7M 0x0082 Timer Output Compare 7 Mask Register OC7M.OC7M7 7 OC7M.OC7M6 6 OC7M.OC7M5 5 OC7M.OC7M4 4 OC7M.OC7M3 3 OC7M.OC7M2 2 OC7M.OC7M1 1 OC7M.OC7M0 0 OC7D 0x0083 Timer Output Compare 7 Data Register OC7D.OC7D7 7 OC7D.OC7D6 6 OC7D.OC7D5 5 OC7D.OC7D4 4 OC7D.OC7D3 3 OC7D.OC7D2 2 OC7D.OC7D1 1 OC7D.OC7D0 0 TCNTH 0x0084 Timer Count Register High TCNTL 0x0085 Timer Count Register Low TSCR 0x0086 Timer System Control Register TSCR.TEN 7 Timer Enable Bit TSCR.TSWAI 6 Timer Stops While in Wait Bit TSCR.TSBCK 5 Timer Stops While in Background Mode Bit TSCR.TFFCA 4 Timer Fast Flag Clear All Bit RESERVED0087 0x0087 RESERVED TCTL1 0x0088 Timer Control Register 1 TCTL1.OM7 7 Output mode 7 TCTL1.OL7 6 Output level 7 TCTL1.OM6 5 Output mode 6 TCTL1.OL6 4 Output level 6 TCTL1.OM5 3 Output mode 5 TCTL1.OL5 2 Output level 5 TCTL1.OM4 1 Output mode 4 TCTL1.OL4 0 Output level 4 TCTL2 0x0089 Timer Control Register 2 TCTL2.OM3 7 Output mode 3 TCTL2.OL3 6 Output level 3 TCTL2.OM2 5 Output mode 2 TCTL2.OL2 4 Output level 2 TCTL2.OM1 3 Output mode 1 TCTL2.OL1 2 Output level 1 TCTL2.OM0 1 Output mode 0 TCTL2.OL0 0 Output level 0 TCTL3 0x008A Timer Control Register 3 TCTL3.EDG7B 7 Input Capture Edge Control Bit 7B TCTL3.EDG7A 6 Input Capture Edge Control Bit 7A TCTL3.EDG6B 5 Input Capture Edge Control Bit 6B TCTL3.EDG6A 4 Input Capture Edge Control Bit 6A TCTL3.EDG5B 3 Input Capture Edge Control Bit 5B TCTL3.EDG5A 2 Input Capture Edge Control Bit 5A TCTL3.EDG4B 1 Input Capture Edge Control Bit 4B TCTL3.EDG4A 0 Input Capture Edge Control Bit 4A TCTL4 0x008B Timer Control Register 4 TCTL4.EDG3B 7 Input Capture Edge Control Bit 3B TCTL4.EDG3A 6 Input Capture Edge Control Bit 3A TCTL4.EDG2B 5 Input Capture Edge Control Bit 2B TCTL4.EDG2A 4 Input Capture Edge Control Bit 2A TCTL4.EDG1B 3 Input Capture Edge Control Bit 1B TCTL4.EDG1A 2 Input Capture Edge Control Bit 1A TCTL4.EDG0B 1 Input Capture Edge Control Bit 0B TCTL4.EDG0A 0 Input Capture Edge Control Bit 0A TMSK1 0x008C Timer Mask Register 1 TMSK1.C7I 7 Input Capture/Output Compare 1 Interrupt Enable Bit 7 TMSK1.C6I 6 Input Capture/Output Compare 1 Interrupt Enable Bit 6 TMSK1.C5I 5 Input Capture/Output Compare 1 Interrupt Enable Bit 5 TMSK1.C4I 4 Input Capture/Output Compare 1 Interrupt Enable Bit 4 TMSK1.C3I 3 Input Capture/Output Compare 1 Interrupt Enable Bit 3 TMSK1.C2I 2 Input Capture/Output Compare 1 Interrupt Enable Bit 2 TMSK1.C1I 1 Input Capture/Output Compare 1 Interrupt Enable Bit 1 TMSK1.C0I 0 Input Capture/Output Compare 1 Interrupt Enable Bit 0 TMSK2 0x008D Timer Mask Register 2 TMSK2.TOI 7 Timer Overflow Interrupt Enable Bit TMSK2.PUPT 5 Timer Pullup Resistor Enable Bit TMSK2.RDPT 4 Timer Drive Reduction Bit TMSK2.TCRE 3 Timer Counter Reset Enable Bit TMSK2.PR2 2 Timer Prescaler Select Bit 2 TMSK2.PR1 1 Timer Prescaler Select Bit 1 TMSK2.PR0 0 Timer Prescaler Select Bit 0 TFLG1 0x008E Timer Interrupt Flag Register 1 TFLG1.C7F 7 Input Capture/Output Compare Channel 7 Flag TFLG1.C6F 6 Input Capture/Output Compare Channel 6 Flag TFLG1.C5F 5 Input Capture/Output Compare Channel 5 Flag TFLG1.C4F 4 Input Capture/Output Compare Channel 4 Flag TFLG1.C3F 3 Input Capture/Output Compare Channel 3 Flag TFLG1.C2F 2 Input Capture/Output Compare Channel 2 Flag TFLG1.C1F 1 Input Capture/Output Compare Channel 1 Flag TFLG1.C0F 0 Input Capture/Output Compare Channel 0 Flag TFLG2 0x008F Timer Interrupt Flag Register 2 TFLG2.TOF 7 Timer Overflow Flag TC0H 0x0090 Timer Input Capture/Output Compare 0 Register High TC0L 0x0091 Timer Input Capture/Output Compare 0 Register Low TC1H 0x0092 Timer Input Capture/Output Compare 1 Register High TC1L 0x0093 Timer Input Capture/Output Compare 1 Register Low TC2H 0x0094 Timer Input Capture/Output Compare 2 Register High TC2L 0x0095 Timer Input Capture/Output Compare 2 Register Low TC3H 0x0096 Timer Input Capture/Output Compare 3 Register High TC3L 0x0097 Timer Input Capture/Output Compare 3 Register Low TC4H 0x0098 Timer Input Capture/Output Compare 4 Register High TC4L 0x0099 Timer Input Capture/Output Compare 4 Register Low TC5H 0x009A Timer Input Capture/Output Compare 5 Register High TC5L 0x009B Timer Input Capture/Output Compare 5 Register Low TC6H 0x009C Timer Input Capture/Output Compare 6 Register High TC6L 0x009D Timer Input Capture/Output Compare 6 Register Low TC7H 0x009E Timer Input Capture/Output Compare 7 Register High TC7L 0x009F Timer Input Capture/Output Compare 7 Register Low PACTL 0x00A0 Pulse Accumulator Control Register PACTL.PAEN 6 Pulse Accumulator System Enable Bit PACTL.PAMOD 5 Pulse Accumulator Mode Bit PACTL.PEDGE 4 Pulse Accumulator Edge Control Bit PACTL.CLK1 3 Clock Select Bit 1 PACTL.CLK0 2 Clock Select Bits 0 PACTL.PAOVI 1 Pulse Accumulator Overflow Interrupt Enable Bit PACTL.PAI 0 Pulse Accumulator Input Interrupt Enable Bit PAFLG 0x00A1 Pulse Accumulator Flag Register PAFLG.PAOVF 1 Pulse Accumulator Overflow Flag PAFLG.PAIF 0 Pulse Accumulator Input Edge Flag PACN3 0x00A2 Pulse Accumulator Count Register 3 PACN2 0x00A3 Pulse Accumulator Count Register 2 PACN1 0x00A4 Pulse Accumulator Count Register 1 PACN0 0x00A5 Pulse Accumulator Count Register 0 MCCTL 0x00A6 16-Bit Modulus Down-Counter Control Regster MCCTL.MCZI 7 Modulus Counter Underflow Interrupt Enable Bit MCCTL.MODMC 6 Modulus Mode Enable Bit MCCTL.RDMCL 5 Read Modulus Down-Counter Load Bit MCCTL.ICLAT 4 Input Capture Force Latch Action Bit MCCTL.FLMC 3 Force Load Register into the Modulus Counter Count Register Bit MCCTL.MCEN 2 Modulus Down-Counter Enable Bit MCCTL.MCPR1 1 Modulus Counter Prescaler Select Bit 1 MCCTL.MCPR0 0 Modulus Counter Prescaler Select Bit 0 MCFLG 0x00A7 16-Bit Modulus Down-Counter Flag Regster MCFLG.MCZF 7 Modulus Counter Underflow Interrupt Flag MCFLG.POLF3 3 First Input Capture Polarity Status Bit 3 MCFLG.POLF2 2 First Input Capture Polarity Status Bit 2 MCFLG.POLF1 1 First Input Capture Polarity Status Bit 1 MCFLG.POLF0 0 First Input Capture Polarity Status Bit 0 ICPACR 0x00A8 Input Control Pulse Accumulators Control Register ICPACR.PA3EN 3 8-Bit Pulse Accumulator 3 Enable Bit ICPACR.PA2EN 2 8-Bit Pulse Accumulator 2 Enable Bit ICPACR.PA1EN 1 8-Bit Pulse Accumulator 1 Enable Bit ICPACR.PA0EN 0 8-Bit Pulse Accumulator 0 Enable Bit DLYCT 0x00A9 Delay Counter Control Register DLYCT.DLY1 1 Delay Counter Select Bit 1 DLYCT.DLY0 0 Delay Counter Select Bit 0 ICOVW 0x00AA Input Control Overwrite Register ICOVW.NOVW7 7 No Input Capture Overwrite Bit 7 ICOVW.NOVW6 6 No Input Capture Overwrite Bit 6 ICOVW.NOVW5 5 No Input Capture Overwrite Bit 5 ICOVW.NOVW4 4 No Input Capture Overwrite Bit 4 ICOVW.NOVW3 3 No Input Capture Overwrite Bit 3 ICOVW.NOVW2 2 No Input Capture Overwrite Bit 2 ICOVW.NOVW1 1 No Input Capture Overwrite Bit 1 ICOVW.NOVW0 0 No Input Capture Overwrite Bit 0 ICSYS 0x00AB Input Control System Control Register ICSYS.SH37 7 Share Input Action of Input Capture Channels 3 and y Bit 7 ICSYS.SH26 6 Share Input Action of Input Capture Channels 2 and y Bit 6 ICSYS.SH15 5 Share Input Action of Input Capture Channels 1 and y Bit 5 ICSYS.SH04 4 Share Input Action of Input Capture Channels 0 and y Bit 4 ICSYS.TFMOD 3 Timer Flag-Setting Mode Bit ICSYS.PACMX 2 8-Bit Pulse Accumulators Maximum Count Bit ICSYS.BUFEN 1 IC Buffer Enable Bit ICSYS.LATQ 0 Input Control Latch or Queue Mode Enable Bit RESERVED00AC 0x00AC RESERVED TIMTST 0x00AD Timer Test Register TIMTST.TCBYP 1 Main Timer Divider Chain Bypass Bit TIMTST.PCBYP 0 PORTT 0x00AE Timer Port Data Register PORTT.PT7 7 Timer Port Data Register bit 7 PORTT.PT6 6 Timer Port Data Register bit 6 PORTT.PT5 5 Timer Port Data Register bit 5 PORTT.PT4 4 Timer Port Data Register bit 4 PORTT.PT3 3 Timer Port Data Register bit 3 PORTT.PT2 2 Timer Port Data Register bit 2 PORTT.PT1 1 Timer Port Data Register bit 1 PORTT.PT0 0 Timer Port Data Register bit 0 DDRT 0x00AF Data Direction Register for Timer Port DDRT.DDT7 7 Data Direction Register for Timer Port bit 7 DDRT.DDT6 6 Data Direction Register for Timer Port bit 6 DDRT.DDT5 5 Data Direction Register for Timer Port bit 5 DDRT.DDT4 4 Data Direction Register for Timer Port bit 4 DDRT.DDT3 3 Data Direction Register for Timer Port bit 3 DDRT.DDT2 2 Data Direction Register for Timer Port bit 2 DDRT.DDT1 1 Data Direction Register for Timer Port bit 1 DDRT.DDT0 0 Data Direction Register for Timer Port bit 0 PBCTL 0x00B0 16-Bit Pulse Accumulator B Control Register PBCTL.PBEN 6 Pulse Accumulator B System Enable Bit PBCTL.PBOVI 1 Pulse Accumulator B Overflow Interrupt Enable Bit PBFLG 0x00B1 Pulse Accumulator B Flag Register PBFLG.PBOVF 1 Pulse Accumulator B Overflow Flag PA3H 0x00B2 8-Bit Pulse Accumulator Holding Register 3 PA2H 0x00B3 8-Bit Pulse Accumulator Holding Register 2 PA1H 0x00B4 8-Bit Pulse Accumulator Holding Register 1 PA0H 0x00B5 8-Bit Pulse Accumulator Holding Register 0 MCCNTH 0x00B6 Modulus Down-Counter Count Register High MCCNTL 0x00B7 Modulus Down-Counter Count Register Low TC0HH 0x00B8 Timer Input Capture Holding Register 0 High TC0HL 0x00B9 Timer Input Capture Holding Register 0 Low TC1HH 0x00BA Timer Input Capture Holding Register 1 High TC1HL 0x00BB Timer Input Capture Holding Register 1 Low TC2HH 0x00BC Timer Input Capture Holding Register 2 High TC2HL 0x00BD Timer Input Capture Holding Register 2 Low TC3HH 0x00BE Timer Input Capture Holding Register 3 High TC3HL 0x00BF Timer Input Capture Holding Register 3 Low SC0BDH 0x00C0 SCI 0 Baud Rate Control Register High SC0BDH.BTST 7 SC0BDH.BSPL 6 SC0BDH.BRLD 5 SC0BDH.SBR12 4 SC0BDH.SBR11 3 SC0BDH.SBR10 2 SC0BDH.SBR9 1 SC0BDH.SBR8 0 SC0BDL 0x00C1 SCI 0 Baud Rate Control Register Low SC0BDL.SBR7 7 SC0BDL.SBR6 6 SC0BDL.SBR5 5 SC0BDL.SBR4 4 SC0BDL.SBR3 3 SC0BDL.SBR2 2 SC0BDL.SBR1 1 SC0BDL.SBR0 0 SC0CR1 0x00C2 SCI Control Register 1 SC0CR1.LOOPS 7 SCI LOOP Mode/Single-Wire Mode Enable Bit SC0CR1.WOMS 6 Wired-OR Mode for Serial Pins SC0CR1.RSRC 5 Receiver Source Bit SC0CR1.M 4 Mode Bit (select character format) SC0CR1.WAKE 3 Wakeup by Address Mark/Idle Bit SC0CR1.ILT 2 Idle Line Type Bit SC0CR1.PE 1 Parity Enable Bit SC0CR1.PT 0 Parity Type Bit SC0CR2 0x00C3 SCI Control Register 2 SC0CR2.TIE 7 Transmit Interrupt Enable Bit SC0CR2.TCIE 6 Transmit Complete Interrupt Enable Bit SC0CR2.RIE 5 Receiver Interrupt Enable Bit SC0CR2.ILIE 4 Idle Line Interrupt Enable Bit SC0CR2.TE 3 Transmitter Enable Bit SC0CR2.RE 2 Receiver Enable Bit SC0CR2.RWU 1 Receiver Wakeup Control Bit SC0CR2.SBK 0 Send Break Bit SC0SR1 0x00C4 SCI Status Register 1 SC0SR1.TDRE 7 Transmit Data Register Empty Flag SC0SR1.TC 6 Transmit Complete Flag SC0SR1.RDRF 5 Receive Data Register Full Flag SC0SR1.IDLE 4 Idle Line Detected Flag SC0SR1.OR 3 Overrun Error Flag SC0SR1.NF 2 Noise Error Flag SC0SR1.FE 1 Framing Error Flag SC0SR1.PF 0 Parity Error Flag SC0SR2 0x00C5 SCI Status Register 2 SC0SR2.RAF 0 Receiver Active Flag SC0DRH 0x00C6 SCI Data Register High SC0DRH.R8 7 Receive Bit 8 SC0DRH.T8 6 Transmit Bit 8 SC0DRL 0x00C7 SCI Data Register Low SC0DRL.R7T7 7 Receive/Transmit Data Bit 7 SC0DRL.R6T6 6 Receive/Transmit Data Bit 6 SC0DRL.R5T5 5 Receive/Transmit Data Bit 5 SC0DRL.R4T4 4 Receive/Transmit Data Bit 4 SC0DRL.R3T3 3 Receive/Transmit Data Bit 3 SC0DRL.R2T2 2 Receive/Transmit Data Bit 2 SC0DRL.R1T1 1 Receive/Transmit Data Bit 1 SC0DRL.R0T0 0 Receive/Transmit Data Bit 0 RESERVED00C8 0x00C8 RESERVED RESERVED00C9 0x00C9 RESERVED RESERVED00CA 0x00CA RESERVED RESERVED00CB 0x00CB RESERVED RESERVED00CC 0x00CC RESERVED RESERVED00CD 0x00CD RESERVED RESERVED00CE 0x00CE RESERVED RESERVED00CF 0x00CF RESERVED SP0CR1 0x00D0 SPI Control Register 1 SP0CR1.SPIE 7 SPI Interrupt Enable Bit SP0CR1.SPE 6 SPI System Enable Bit SP0CR1.SWOM 5 Port S Wired-OR Mode Bit SP0CR1.MSTR 4 SPI Master/Slave Mode Select Bit SP0CR1.CPOL 3 SPI Clock Polarity SP0CR1.CPHA 2 Clock Phase Bits SP0CR1.SSOE 1 Slave Select Output Enable Bit SP0CR1.LSBF 0 SPI LSB First Enable Bit SP0CR2 0x00D1 SPI Control Register 2 SP0CR2.PUPS 3 Pullup Port S Enable Bit SP0CR2.RDS 2 Reduce Drive of Port S Bit SP0CR2.SPC0 0 Serial Pin Control 0 Bit SP0BR 0x00D2 SPI Baud Rate Register SP0BR.SPR2 2 SPI Clock (SCK) Rate Select Bit 2 SP0BR.SPR1 1 SPI Clock (SCK) Rate Select Bit 1 SP0BR.SPR0 0 SPI Clock (SCK) Rate Select Bit 0 SP0SR 0x00D3 SPI Status Register SP0SR.SPIF 7 SPI Interrupt Request Bit SP0SR.WCOL 6 Write Collision Status Flag SP0SR.MODF 4 SPI Mode Error Interrupt Status Flag RESERVED00D4 0x00D4 RESERVED SP0DR 0x00D5 SPI Data Register PORTS 0x00D6 Port S Data Register PORTS.PS7 7 Port S Data Register Bit 7 PORTS.PS6 6 Port S Data Register Bit 6 PORTS.PS5 5 Port S Data Register Bit 5 PORTS.PS4 4 Port S Data Register Bit 4 PORTS.PS3 3 Port S Data Register Bit 3 PORTS.PS2 2 Port S Data Register Bit 2 PORTS.PS1 1 Port S Data Register Bit 1 PORTS.PS0 0 Port S Data Register Bit 0 DDRS 0x00D7 Port S Data Direction Register DDRS.DDS7 7 Port S Data Direction Register Bit 7 DDRS.DDS6 6 Port S Data Direction Register Bit 6 DDRS.DDS5 5 Port S Data Direction Register Bit 5 DDRS.DDS4 4 Port S Data Direction Register Bit 4 DDRS.DDS3 3 Port S Data Direction Register Bit 3 DDRS.DDS2 2 Port S Data Direction Register Bit 2 DDRS.DDS1 1 Port S Data Direction Register Bit 1 DDRS.DDS0 0 Port S Data Direction Register Bit 0 RESERVED00D8 0x00D8 RESERVED RESERVED00D9 0x00D9 RESERVED RESERVED00DA 0x00DA RESERVED PURDS 0x00DB Port S Pullup/Reduced Drive Register PURDS.RDPS2 6 Reduce Drive of PS7-PS4 PURDS.RDPS1 5 Reduce Drive of PS3 and PS2 PURDS.RDPS0 4 Reduce Drive of PS1 and PS0 PURDS.PUPS2 2 Pullup Port S Enable PS7-PS4 PURDS.PUPS1 1 Pullup Port S Enable PS3 and PS2 Bit PURDS.PUPS0 0 Pullup Port S Enable PS1 and PS0 Bit RESERVED00DC 0x00DC RESERVED RESERVED00DD 0x00DD RESERVED RESERVED00DE 0x00DE RESERVED RESERVED00DF 0x00DF RESERVED SLOW 0x00E0 Slow Mode Divider Register SLOW.SLDV2 2 Slow Mode Divisor Selector Bit 2 SLOW.SLDV1 1 Slow Mode Divisor Selector Bit 1 SLOW.SLDV0 0 Slow Mode Divisor Selector Bit 0 RESERVED00E1 0x00E1 RESERVED RESERVED00E2 0x00E2 RESERVED RESERVED00E3 0x00E3 RESERVED RESERVED00E4 0x00E4 RESERVED RESERVED00E5 0x00E5 RESERVED RESERVED00E6 0x00E6 RESERVED RESERVED00E7 0x00E7 RESERVED RESERVED00E8 0x00E8 RESERVED RESERVED00E9 0x00E9 RESERVED RESERVED00EA 0x00EA RESERVED RESERVED00EB 0x00EB RESERVED RESERVED00EC 0x00EC RESERVED RESERVED00ED 0x00ED RESERVED RESERVED00EE 0x00EE RESERVED RESERVED00EF 0x00EF RESERVED EEMCR 0x00F0 EEPROM Configuration Register EEMCR.EESWAI 2 EEPROM Stops in Wait Mode Bit EEMCR.PROTLCK 1 Block Protect Write Lock Bit EEMCR.EERC 0 EEPROM Charge Pump Clock Bit EEPROT 0x00F1 EEPROM Block Protect Register EEPROT.BRPROT4 4 EEPROM Block Protection Bit 4 EEPROT.BRPROT3 3 EEPROM Block Protection Bit 3 EEPROT.BRPROT2 2 EEPROM Block Protection Bit 2 EEPROT.BRPROT1 1 EEPROM Block Protection Bit 1 EEPROT.BRPROT0 0 EEPROM Block Protection Bit 0 EETST 0x00F2 EEPROM Test Register EETST.EEODD 7 Odd Row Programming Bit EETST.EEVEN 6 Even Row Programming Bit EETST.MARG 5 Program and Erase Voltage Margin Test Enable Bit EETST.EECPD 4 Charge Pump Disable Bit EETST.EECPRD 3 Charge Pump Ramp Disable Bit EETST.EECPM 1 Charge Pump Monitor Enable Bit EEPROG 0x00F3 EEPROM Control Register EEPROG.BULKP 7 Bulk Erase Protection Bit EEPROG.BYTE 4 Byte and Aligned Word Erase Bit EEPROG.ROW 3 Row or Bulk Erase Bit EEPROG.ERASE 2 Erase Control Bit EEPROG.EELAT 1 EEPROM Latch Control Bit EEPROG.EEPGM 0 Program and Erase Enable Bit FEELCK 0x00F4 FLASH EEPROM Lock Control Register FEELCK.LOCK 0 Lock Register Bit FEEMCR 0x00F5 FLASH EEPROM Configuration Register FEEMCR.BOOTP 0 Boot Protect Bit FEETST 0x00F6 FLASH EEPROM Test Register FEETST.FSTE 7 Stress Test Enable Bit FEETST.GADR 6 Gate/Drain Stress Test Select Bit FEETST.HVT 5 Stress Test High Voltage Status Bit FEETST.FENLV 4 Enable Low Voltage Bit FEETST.FDISVFP 3 Disable Status V FP Voltage Lock Bit FEETST.VTCK 2 V T Check Test Enable Bit FEETST.STRE 1 Spare Test Row Enable Bit FEETST.MWPR 0 Multiple Word Programming Bit FEECTL 0x00F7 FLASH EEPROM Control Register FEECTL.FEESWAI 4 FLASH EEPROM Stop in Wait Control Bit FEECTL.SVFP 3 Status V FP Voltage Bit FEECTL.ERAS 2 Erase Control Bit FEECTL.LAT 1 Latch Control Bit FEECTL.ENPE 0 Enable Programming/Erase Bit BCR1 0x00F8 BDLC Control Register 1 BCR1.IMSG 7 Ignore Message Bit BCR1.CLKS 6 Clock Select Bit BCR1.R1 5 Rate Select Bit 1 BCR1.R0 4 Rate Select Bit 0 BCR1.IE 1 Interrupt Enable Bit BCR1.WCM 0 Wait Clock Mode Bit BSVR 0x00F9 BDLC State Vector Register BSVR.I3 5 Interrupt Source Bit 3 BSVR.I2 4 Interrupt Source Bit 2 BSVR.I1 3 Interrupt Source Bit 1 BSVR.I0 2 Interrupt Source Bit 0 BCR2 0x00FA BDLC Control Register 2 BCR2.ALOOP 7 Analog Loopback Mode Bit BCR2.DLOOP 6 Digital Loopback Mode Bit BCR2.RX4XE 5 Receive 4X Enable Bit BCR2.NBFS 4 Normalization Bit Format Select Bit BCR2.TEOD 3 Transmit End of Data Bit BCR2.TSIFR 2 Transmit In-Frame Response Bit BCR2.TMIFR1 1 Transmit In-Frame Response Bit 1 BCR2.TMIFR0 0 Transmit In-Frame Response Bit 0 BDR 0x00FB BDLC Data Register BDR.BD7 7 BDR.BD6 6 BDR.BD5 5 BDR.BD4 4 BDR.BD3 3 BDR.BD2 2 BDR.BD1 1 BDR.BD0 0 BARD 0x00FC BDLC Analog Roundtrip Delay Register BARD.ATE 7 Analog Transceiver Enable Bit BARD.RXPOL 6 Receive Pin Polarity Bit BARD.BO3 3 BARD Offset Bit 3 BARD.BO2 2 BARD Offset Bit 2 BARD.BO1 1 BARD Offset Bit 1 BARD.BO0 0 BARD Offset Bit 0 DLCSCR 0x00FD Port DLC Control Register DLCSCR.BDLCEN 2 BDLC Enable Bit DLCSCR.PUPDLC 1 BDLC Pullup Enable Bit DLCSCR.RDPDLC 0 BDLC Reduced Drive Bit PORTDLC 0x00FE Port DLC Data Register PORTDLC.PDLC6 6 Port DLC Data Register Bit 6 PORTDLC.PDLC5 5 Port DLC Data Register Bit 5 PORTDLC.PDLC4 4 Port DLC Data Register Bit 4 PORTDLC.PDLC3 3 Port DLC Data Register Bit 3 PORTDLC.PDLC2 2 Port DLC Data Register Bit 2 PORTDLC.PDLC1 1 Port DLC Data Register Bit 1 PORTDLC.PDLC0 0 Port DLC Data Register Bit 0 DDRDLC 0x00FF Port DLC Data Direction Register DDRDLC.DDDLC6 6 Data Direction Port DLC Bit 6 DDRDLC.DDDLC5 5 Data Direction Port DLC Bit 5 DDRDLC.DDDLC4 4 Data Direction Port DLC Bit 4 DDRDLC.DDDLC3 3 Data Direction Port DLC Bit 3 DDRDLC.DDDLC2 2 Data Direction Port DLC Bit 2 DDRDLC.DDDLC1 1 Data Direction Port DLC Bit 1 DDRDLC.DDDLC0 0 Data Direction Port DLC Bit 0 ; CAN RESERVED0100 0x0100 RESERVED RESERVED0101 0x0101 RESERVED RESERVED0102 0x0102 RESERVED RESERVED0103 0x0103 RESERVED RESERVED0104 0x0104 RESERVED RESERVED0105 0x0105 RESERVED RESERVED0106 0x0106 RESERVED RESERVED0107 0x0107 RESERVED RESERVED0108 0x0108 RESERVED RESERVED0109 0x0109 RESERVED RESERVED010A 0x010A RESERVED RESERVED010B 0x010B RESERVED RESERVED010C 0x010C RESERVED RESERVED010D 0x010D RESERVED RESERVED010E 0x010E RESERVED RESERVED010F 0x010F RESERVED RESERVED0110 0x0110 RESERVED RESERVED0111 0x0111 RESERVED RESERVED0112 0x0112 RESERVED RESERVED0113 0x0113 RESERVED RESERVED0114 0x0114 RESERVED RESERVED0115 0x0115 RESERVED RESERVED0116 0x0116 RESERVED RESERVED0117 0x0117 RESERVED RESERVED0118 0x0118 RESERVED RESERVED0119 0x0119 RESERVED RESERVED011A 0x011A RESERVED RESERVED011B 0x011B RESERVED RESERVED011C 0x011C RESERVED RESERVED011D 0x011D RESERVED RESERVED011E 0x011E RESERVED RESERVED011F 0x011F RESERVED RESERVED0120 0x0120 RESERVED RESERVED0121 0x0121 RESERVED RESERVED0122 0x0122 RESERVED RESERVED0123 0x0123 RESERVED RESERVED0124 0x0124 RESERVED RESERVED0125 0x0125 RESERVED RESERVED0126 0x0126 RESERVED RESERVED0127 0x0127 RESERVED RESERVED0128 0x0128 RESERVED RESERVED0129 0x0129 RESERVED RESERVED012A 0x012A RESERVED RESERVED012B 0x012B RESERVED RESERVED012C 0x012C RESERVED RESERVED012D 0x012D RESERVED RESERVED012E 0x012E RESERVED RESERVED012F 0x012F RESERVED RESERVED0130 0x0130 RESERVED RESERVED0131 0x0131 RESERVED RESERVED0132 0x0132 RESERVED RESERVED0133 0x0133 RESERVED RESERVED0134 0x0134 RESERVED RESERVED0135 0x0135 RESERVED RESERVED0136 0x0136 RESERVED RESERVED0137 0x0137 RESERVED RESERVED0138 0x0138 RESERVED RESERVED0139 0x0139 RESERVED RESERVED013A 0x013A RESERVED RESERVED013B 0x013B RESERVED RESERVED013C 0x013C RESERVED RESERVED013D 0x013D RESERVED RESERVED013E 0x013E RESERVED RESERVED013F 0x013F RESERVED .68HC912BC32 ; ; M68HC12B.pdf ; MEMORY MAP area DATA FSR 0x0000:0x0200 REGISTERS 512 BYTES area BSS RESERVED 0x0200:0x0800 area DATA RAM 0x0800:0x0C00 1-KBYTE RAM area BSS RESERVED 0x0C00:0x0D00 area DATA EEPROM 0x0D00:0x1000 768 BYTES EEPROM area BSS RESERVED 0x1000:0x8000 area DATA EEPROM_ROM 0x8000:0xFFC0 FLASH EEPROM/ROM area DATA USER_VEC 0xFFC0:0x10000 ; Interrupt and reset vector assignments interrupt __RESET 0xFFFE Processor reset interrupt CME_FCME 0xFFFC COP clock monitor fail reset interrupt COP_FR 0xFFFA COP failure reset interrupt UIT 0xFFF8 Unimplemented instruction trap interrupt SWI 0xFFF6 SWI interrupt XIRQ 0xFFF4 XIRQ interrupt IRQEN 0xFFF2 IRQ interrupt RTIE 0xFFF0 Real-time interrupt interrupt C0I 0xFFEE Timer channel 0 interrupt C1I 0xFFEC Timer channel 1 interrupt C2I 0xFFEA Timer channel 2 interrupt C3I 0xFFE8 Timer channel 3 interrupt C4I 0xFFE6 Timer channel 4 interrupt C5I 0xFFE4 Timer channel 5 interrupt C6I 0xFFE2 Timer channel 6 interrupt C7I 0xFFE0 Timer channel 7 interrupt TOI 0xFFDE Timer overflow interrupt PAOVI 0xFFDC Pulse accumulator overflow interrupt PAI 0xFFDA Pulse accumulator input edge interrupt SPIE 0xFFD8 SPI serial transfer complete interrupt TIE_TCIE_RIE_ILIE 0xFFD6 SCI 0 interrupt ASCIE 0xFFD2 ATD interrupt WUPIE 0xFFD0 MSCAN wakeup interrupt MSCAN_ER 0xFFC8 MSCAN errors interrupt RXFIE 0xFFC6 MSCAN receive interrupt TXEIE 0xFFC4 MSCAN transmit ; INPUT/ OUTPUT PORTS PORTA 0x0000 Port A Data Register PORTA.PA7 7 Port A Data Bit 7 PORTA.PA6 6 Port A Data Bit 6 PORTA.PA5 5 Port A Data Bit 5 PORTA.PA4 4 Port A Data Bit 4 PORTA.PA3 3 Port A Data Bit 3 PORTA.PA2 2 Port A Data Bit 2 PORTA.PA1 1 Port A Data Bit 1 PORTA.PA0 0 Port A Data Bit 0 PORTB 0x0001 Port B Data Register PORTB.PB7 7 Port B Data Bit 7 PORTB.PB6 6 Port B Data Bit 6 PORTB.PB5 5 Port B Data Bit 5 PORTB.PB4 4 Port B Data Bit 4 PORTB.PB3 3 Port B Data Bit 3 PORTB.PB2 2 Port B Data Bit 2 PORTB.PB1 1 Port B Data Bit 1 PORTB.PB0 0 Port B Data Bit 0 DDRA 0x0002 Data Direction Register A DDRA.DDA7 7 Data Direction Register A Bit 7 DDRA.DDA6 6 Data Direction Register A Bit 6 DDRA.DDA5 5 Data Direction Register A Bit 5 DDRA.DDA4 4 Data Direction Register A Bit 4 DDRA.DDA3 3 Data Direction Register A Bit 3 DDRA.DDA2 2 Data Direction Register A Bit 2 DDRA.DDA1 1 Data Direction Register A Bit 1 DDRA.DDA0 0 Data Direction Register A Bit 0 DDRB 0x0003 Data Direction Register B DDRB.DDB7 7 Data Direction Register B Bit 7 DDRB.DDB6 6 Data Direction Register B Bit 6 DDRB.DDB5 5 Data Direction Register B Bit 5 DDRB.DDB4 4 Data Direction Register B Bit 4 DDRB.DDB3 3 Data Direction Register B Bit 3 DDRB.DDB2 2 Data Direction Register B Bit 2 DDRB.DDB1 1 Data Direction Register B Bit 1 DDRB.DDB0 0 Data Direction Register B Bit 0 RESERVED00004 0x0004 RESERVED RESERVED00005 0x0005 RESERVED RESERVED00006 0x0006 RESERVED RESERVED00007 0x0007 RESERVED PORTE 0x0008 Port E Data Register PORTE.PE7 7 Port E Data Bit 7 PORTE.PE6 6 Port E Data Bit 6 PORTE.PE5 5 Port E Data Bit 5 PORTE.PE4 4 Port E Data Bit 4 PORTE.PE3 3 Port E Data Bit 3 PORTE.PE2 2 Port E Data Bit 2 PORTE.PE1 1 Port E Data Bit 1 PORTE.PE0 0 Port E Data Bit 0 DDRE 0x0009 Data Direction Register E DDRE.DDE7 7 Data Direction Register E Bit 7 DDRE.DDE6 6 Data Direction Register E Bit 6 DDRE.DDE5 5 Data Direction Register E Bit 5 DDRE.DDE4 4 Data Direction Register E Bit 4 DDRE.DDE3 3 Data Direction Register E Bit 3 DDRE.DDE2 2 Data Direction Register E Bit 2 DDRE.DDE1 1 Data Direction Register E Bit 1 DDRE.DDE0 0 Data Direction Register E Bit 0 PEAR 0x000A Port E Assignment Register PEAR.NDBE 7 No Data Bus Enable Bit PEAR.CGMTE 6 CGM Test Output Enable PEAR.PIPOE 5 Pipe Signal Output Enable Bit PEAR.NECLK 4 No External E Clock Bit PEAR.LSTRE 3 Low Strobe (LSTRB) Enable Bit PEAR.RDWE 2 Read/Write Enable Bit MODE 0x000B Mode Register MODE.SMODN 7 Mode Select Special MODE.MODB 6 Mode Select Special B Bit MODE.MODA 5 Mode Select Special A Bit MODE.ESTR 4 E Clock Stretch Enable Bit MODE.IVIS 3 Internal Visibility Bit MODE.EBSWAI 2 External Bus Module Stop in Wait Bit MODE.EME 0 Emulate Port E Bit PUCR 0x000C Pullup Control Register PUCR.PUPE 4 Pullup Port E Enable Bit PUCR.PUPB 1 Pullup Port B Enable Bit PUCR.PUPA 0 Pullup Port A Enable Bit RDRIV 0x000D Reduced Drive Register RDRIV.RDPE 3 Reduced Drive of Port E Bit RDRIV.RDPB 1 Reduced Drive of Port B Bit RDRIV.RDPA 0 Reduced Drive of Port A Bit RESERVED000E 0x000E RESERVED RESERVED000F 0x000F RESERVED INITRM 0x0010 RAM Initialization Register INITRM.RAM15 7 RAM Position Bit 15 INITRM.RAM14 6 RAM Position Bit 14 INITRM.RAM13 5 RAM Position Bit 13 INITRM.RAM12 4 RAM Position Bit 12 INITRM.RAM11 3 RAM Position Bit 11 INITRG 0x0011 Register Initialization Register INITRG.REG15 7 Register Position Bit 15 INITRG.REG14 6 Register Position Bit 14 INITRG.REG13 5 Register Position Bit 13 INITRG.REG12 4 Register Position Bit 12 INITRG.REG11 3 Register Position Bit 11 INITRG.MMSWAI 0 Memory Mapping Interface Stop in Wait Control Bit INITEE 0x0012 EEPROM Initialization Register INITEE.EE15 7 Internal EEPROM Position Bit 15 INITEE.EE14 6 Internal EEPROM Position Bit 14 INITEE.EE13 5 Internal EEPROM Position Bit 13 INITEE.EE12 4 Internal EEPROM Position Bit 12 INITEE.EEON 0 EEPROM On Bit MISC 0x0013 Miscellaneous Mapping Control Register MISC.NDRF 6 Narrow Data Bus for Register-Following Map Bit MISC.RFSTR1 5 Register-Following Stretch Bit 1 MISC.RFSTR0 4 Register-Following Stretch Bit 0 MISC.EXSTR1 3 External Access Stretch Bit 1 MISC.EXSTR0 2 External Access Stretch Bit 0 MISC.MAPROM 1 FLASH EEPROM/ROM Map Bit MISC.ROMON 0 FLASH EEPROM/ROM Enable Bit RTICTL 0x0014 Real-Time Interrupt Control Register RTICTL.RTIE 7 Real-Time Interrupt Enable Bit RTICTL.RSWAI 6 RTI and COP Stop While in Wait Bit RTICTL.RSBCK 5 RTI and COP Stop While in Background Debug Mode Bit RTICTL.RTBYP 3 Real-Time Interrupt Divider Chain Bypass Bit RTICTL.RTR2 2 Real-Time Interrupt Rate Select Bit 2 RTICTL.RTR1 1 Real-Time Interrupt Rate Select Bit 1 RTICTL.RTR0 0 Real-Time Interrupt Rate Select Bit 0 RTIFLG 0x0015 Real-Time Interrupt Flag Register RTIFLG.RTIF 7 Real-Time Interrupt Flag Bit COPCTL 0x0016 COP Control Register COPCTL.CME 7 Clock Monitor Enable Bit COPCTL.FCME 6 Force Clock Monitor Enable Bit COPCTL.FCM 5 Force Clock Monitor Reset Bit COPCTL.FCOP 4 Force COP Watchdog Reset Bit COPCTL.DISR 3 Disable Resets from COP Watchdog and Clock Monitor Bit COPCTL.CR2 2 COP Watchdog Timer Rate Select Bit 2 COPCTL.CR1 1 COP Watchdog Timer Rate Select Bit 1 COPCTL.CR0 0 COP Watchdog Timer Rate Select Bit 0 COPRST 0x0017 Arm/Reset COP Timer Register RESERVED0018 0x0018 RESERVED RESERVED0019 0x0019 RESERVED RESERVED001A 0x001A RESERVED RESERVED001B 0x001B RESERVED RESERVED001C 0x001C RESERVED RESERVED001D 0x001D RESERVED INTCR 0x001E Interrupt Control Register INTCR.IRQE 7 IRQ Edge-Sensitive Only Bit INTCR.IRQEN 6 External IRQ Enable Bit INTCR.DLY 5 Oscillator Startup Delay on Exit from Stop Mode Bit HPRIO 0x001F Highest Priority I Interrupt Register HPRIO.PSEL5 5 HPRIO.PSEL4 4 HPRIO.PSEL3 3 HPRIO.PSEL2 2 HPRIO.PSEL1 1 BRKCT0 0x0020 Breakpoint Control Register 0 BRKCT0.BKEN1 7 Breakpoint Mode Enable Bit 1 BRKCT0.BKEN0 6 Breakpoint Mode Enable Bit 0 BRKCT0.BKPM 5 Break on Program Addresses BRKCT0.BK1ALE 3 Breakpoint 1 Range Control Bit BRKCT0.BK0ALE 2 Breakpoint 0 Range Control Bit BRKCT1 0x0021 Breakpoint Control Register 1 BRKCT1.BKDBE 6 Enable Data Bus Bit BRKCT1.BKMBH 5 Breakpoint Mask High Bit BRKCT1.BKMBL 4 Breakpoint Mask Low Bit BRKCT1.BK1RWE 3 R/W Compare Enable Bit BRKCT1.BK1RW 2 R/W Compare Value Bit BRKCT1.BK0RWE 1 R/W Compare Enable Bit BRKCT1.BK0RW 0 R/W Compare Value Bit BRKAH 0x0022 Breakpoint Address Register High BRKAL 0x0023 Breakpoint Address Register Low BRKDH 0x0024 Breakpoint Data Register High BRKDL 0x0025 Breakpoint Data Register Low RESERVED0026 0x0026 RESERVED RESERVED0027 0x0027 RESERVED RESERVED0028 0x0028 RESERVED RESERVED0029 0x0029 RESERVED RESERVED002A 0x002A RESERVED RESERVED002B 0x002B RESERVED RESERVED002C 0x002C RESERVED RESERVED002D 0x002D RESERVED RESERVED002E 0x002E RESERVED RESERVED002F 0x002F RESERVED RESERVED0030 0x0030 RESERVED RESERVED0031 0x0031 RESERVED RESERVED0032 0x0032 RESERVED RESERVED0033 0x0033 RESERVED RESERVED0034 0x0034 RESERVED RESERVED0035 0x0035 RESERVED RESERVED0036 0x0036 RESERVED RESERVED0037 0x0037 RESERVED RESERVED0038 0x0038 RESERVED RESERVED0039 0x0039 RESERVED RESERVED003A 0x003A RESERVED RESERVED003B 0x003B RESERVED RESERVED003C 0x003C RESERVED RESERVED003D 0x003D RESERVED RESERVED003E 0x003E RESERVED RESERVED003F 0x003F RESERVED PWCLK 0x0040 PWM Clocks and Concatenate Register PWCLK.CON23 7 Concatenate PWM Channels 2 and 3 Bit PWCLK.CON01 6 Concatenate PWM Channels 0 and 1 Bit PWCLK.PCKA2 5 Prescaler for Clock A Bit 2 PWCLK.PCKA1 4 Prescaler for Clock A Bit 1 PWCLK.PCKA0 3 Prescaler for Clock A Bit 0 PWCLK.PCKB2 2 Prescaler for Clock B Bit 2 PWCLK.PCKB1 1 Prescaler for Clock B Bit 1 PWCLK.PCKB0 0 Prescaler for Clock B Bit 0 PWPOL 0x0041 PWM Clock Select and Polarity Register PWPOL.PCLK3 7 PWM Channel 3 Clock Select Bit PWPOL.PCLK2 6 PWM Channel 2 Clock Select Bit PWPOL.PCLK1 5 PWM Channel 1 Clock Select Bit PWPOL.PCLK0 4 PWM Channel 0 Clock Select Bit PWPOL.PPOL3 3 PWM Channel 3 Polarity Bit PWPOL.PPOL2 2 PWM Channel 2 Polarity Bit PWPOL.PPOL1 1 PWM Channel 1 Polarity Bit PWPOL.PPOL0 0 PWM Channel 0 Polarity Bit PWEN 0x0042 PWM Enable Register PWEN.PWEN3 3 PWM Channel 3 Enable Bit PWEN.PWEN2 2 PWM Channel 2 Enable Bit PWEN.PWEN1 1 PWM Channel 1 Enable Bit PWEN.PWEN0 0 PWM Channel 0 Enable Bit PWPRES 0x0043 PWM Prescaler Counter Register PWSCAL0 0x0044 PWM Scale Register 0 PWSCNT0 0x0045 PWM Scale Counter Register 0 PWSCAL1 0x0046 PWM Scale Register 1 PWSCNT1 0x0047 PWM Scale Counter Register 1 PWCNT0 0x0048 PWM Channel Counter Register 0 PWCNT1 0x0049 PWM Channel Counter Register 1 PWCNT2 0x004A PWM Channel Counter Register 2 PWCNT3 0x004B PWM Channel Counter Register 3 PWPER0 0x004C PWM Channel Period Register 0 PWPER1 0x004D PWM Channel Period Register 1 PWPER2 0x004E PWM Channel Period Register 2 PWPER3 0x004F PWM Channel Period Register 3 PWDTY0 0x0050 PWM Channel Duty Register 0 PWDTY1 0x0051 PWM Channel Duty Register 1 PWDTY2 0x0052 PWM Channel Duty Register 2 PWDTY3 0x0053 PWM Channel Duty Register 3 PWCTL 0x0054 PWM Control Register PWCTL.PSWAI 4 PWM Halts While in Wait Mode Bit PWCTL.CENTR 3 Center-Aligned Output Mode Bit PWCTL.RDPP 2 Reduced Drive of Port P Bit PWCTL.PUPP 1 Pullup Port P Enable Bit PWCTL.PSBCK 0 PWM Stops While in Background Mode Bit PWTST 0x0055 PWM Special Mode Register PWTST.DISCR 7 Disable Channel Counter Reset Bit PWTST.DISCP 6 Disable Compare Count Period Bit PWTST.DISCAL 5 Disable Scale Counter Loading Bit PORTP 0x0056 Port P Data Register PORTP.PP7 7 Port P Data Bit 7 PORTP.PP6 6 Port P Data Bit 6 PORTP.PP5 5 Port P Data Bit 5 PORTP.PP4 4 Port P Data Bit 4 PORTP.PP3 3 Port P Data Bit 3 PORTP.PP2 2 Port P Data Bit 2 PORTP.PP1 1 Port P Data Bit 1 PORTP.PP0 0 Port P Data Bit 0 DDRP 0x0057 Port P Data Direction Register DDRP.DDP7 7 Port P Data Direction Register Bit 7 DDRP.DDP6 6 Port P Data Direction Register Bit 6 DDRP.DDP5 5 Port P Data Direction Register Bit 5 DDRP.DDP4 4 Port P Data Direction Register Bit 4 DDRP.DDP3 3 Port P Data Direction Register Bit 3 DDRP.DDP2 2 Port P Data Direction Register Bit 2 DDRP.DDP1 1 Port P Data Direction Register Bit 1 DDRP.DDP0 0 Port P Data Direction Register Bit 0 RESERVED0058 0x0058 RESERVED RESERVED0059 0x0059 RESERVED RESERVED005A 0x005A RESERVED RESERVED005B 0x005B RESERVED RESERVED005C 0x005C RESERVED RESERVED005D 0x005D RESERVED RESERVED005E 0x005E RESERVED RESERVED005F 0x005F RESERVED ATDCTL0 0x0060 ATD Control Register 0 ATDCTL1 0x0061 ATD Control Register 1 ATDCTL2 0x0062 ATD Control Register 2 ATDCTL2.ADPU 7 ATD Disable Bit ATDCTL2.AFFC 6 ATD Fast Flag Clear Bit ATDCTL2.AWAI 5 ATD Stop in Wait Mode Bit ATDCTL2.ASCIE 1 ATD Sequence Complete Interrupt Enable Bit ATDCTL2.ASCIF 0 ATD Sequence Complete Interrupt Flag ATDCTL3 0x0063 ATD Control Register 3 ATDCTL3.FRZ1 1 Background Debug (Freeze) Enable Bit ATDCTL3.FRZ0 0 Background Debug (Freeze) Enable Bit ATDCTL4 0x0064 ATD Control Register 4 ATDCTL4.S10BM 7 ATD 10-Bit Mode Control Bit ATDCTL4.SMP1 6 Select Sample Time Bit 1 ATDCTL4.SMP0 5 Select Sample Time Bit 0 ATDCTL4.PRS4 4 Select Divide-By Factor for ATD P-Clock Prescaler Bit 4 ATDCTL4.PRS3 3 Select Divide-By Factor for ATD P-Clock Prescaler Bit 3 ATDCTL4.PRS2 2 Select Divide-By Factor for ATD P-Clock Prescaler Bit 2 ATDCTL4.PRS1 1 Select Divide-By Factor for ATD P-Clock Prescaler Bit 1 ATDCTL4.PRS0 0 Select Divide-By Factor for ATD P-Clock Prescaler Bit 0 ATDCTL5 0x0065 ATD Control Register 5 ATDCTL5.S8CM 6 Select 8 Channel Mode Bit ATDCTL5.SCAN 5 Enable Continuous Channel Scan Bit ATDCTL5.MULT 4 Enable Multichannel Conversion Bit ATDCTL5.CD 3 Channel Select for Conversion Bit ATDCTL5.CC 2 Channel Select for Conversion Bit ATDCTL5.CB 1 Channel Select for Conversion Bit ATDCTL5.CA 0 Channel Select for Conversion Bit ATDSTAT 0x0066 ATD Status Register ATDSTAT.SCF 7 Sequence Complete Flag ATDSTAT.CC2 2 Conversion Counter Bit 2 for Current 4 or 8 Conversions ATDSTAT.CC1 1 Conversion Counter Bit 1 for Current 4 or 8 Conversions ATDSTAT.CC0 0 Conversion Counter Bit 0 for Current 4 or 8 Conversions ATDSTATL 0x0067 ATD Status Register ATDSTATL.CCF7 7 Sequence Complete Flag 7 ATDSTATL.CCF6 6 Sequence Complete Flag 6 ATDSTATL.CCF5 5 Sequence Complete Flag 5 ATDSTATL.CCF4 4 Sequence Complete Flag 4 ATDSTATL.CCF3 3 Sequence Complete Flag 3 ATDSTATL.CCF2 2 Sequence Complete Flag 2 ATDSTATL.CCF1 1 Sequence Complete Flag 1 ATDSTATL.CCF0 0 Sequence Complete Flag 0 ATDTSTH 0x0068 ATD Test Register High ATDTSTH.SAR9 7 SAR Data Bit 9 ATDTSTH.SAR8 6 SAR Data Bit 8 ATDTSTH.SAR7 5 SAR Data Bit 7 ATDTSTH.SAR6 4 SAR Data Bit 6 ATDTSTH.SAR5 3 SAR Data Bit 5 ATDTSTH.SAR4 2 SAR Data Bit 4 ATDTSTH.SAR3 1 SAR Data Bit 3 ATDTSTH.SAR2 0 SAR Data Bit 2 ATDTSTL 0x0069 ATD Test Register Low ATDTSTL.SAR1 7 SAR Data Bit 1 ATDTSTL.SAR0 6 SAR Data Bit 0 ATDTSTL.RST 5 Module Reset Bit ATDTSTL.TSTOUT 4 Multiplex Output of TST3-TST0 (Factory Use) ATDTSTL.TST3 3 Test Bits 3 ATDTSTL.TST2 2 Test Bits 2 ATDTSTL.TST1 1 Test Bits 1 ATDTSTL.TST0 0 Test Bits 0 RESERVED006A 0x006A RESERVED RESERVED006B 0x006B RESERVED RESERVED006C 0x006C RESERVED RESERVED006D 0x006D RESERVED RESERVED006E 0x006E RESERVED PORTAD 0x006F Port AD Data Input Register PORTAD.PAD7 7 Port AD Data Input Bit 7 PORTAD.PAD6 6 Port AD Data Input Bit 6 PORTAD.PAD5 5 Port AD Data Input Bit 5 PORTAD.PAD4 4 Port AD Data Input Bit 4 PORTAD.PAD3 3 Port AD Data Input Bit 3 PORTAD.PAD2 2 Port AD Data Input Bit 2 PORTAD.PAD1 1 Port AD Data Input Bit 1 PORTAD.PAD0 0 Port AD Data Input Bit 0 ADRx0H 0x0070 ATD Result Register 0 High ADRx0H.ADRxH15 7 ATD Conversion Result Bit 15 ADRx0H.ADRxH14 6 ATD Conversion Result Bit 14 ADRx0H.ADRxH13 5 ATD Conversion Result Bit 13 ADRx0H.ADRxH12 4 ATD Conversion Result Bit 12 ADRx0H.ADRxH11 3 ATD Conversion Result Bit 11 ADRx0H.ADRxH10 2 ATD Conversion Result Bit 10 ADRx0H.ADRxH9 1 ATD Conversion Result Bit 9 ADRx0H.ADRxH8 0 ATD Conversion Result Bit 8 ADRx0L 0x0071 ATD Result Register 0 Low ADRx0L.ADRxHL7 7 ATD Conversion Result Bit 7 ADRx0L.ADRxHL6 6 ATD Conversion Result Bit 6 ADRx0L.ADRxHL5 5 ATD Conversion Result Bit 5 ADRx0L.ADRxHL4 4 ATD Conversion Result Bit 4 ADRx0L.ADRxHL3 3 ATD Conversion Result Bit 3 ADRx0L.ADRxHL2 2 ATD Conversion Result Bit 2 ADRx0L.ADRxHL1 1 ATD Conversion Result Bit 1 ADRx0L.ADRxHL0 0 ATD Conversion Result Bit 0 ADRx1H 0x0072 ATD Result Register 1 High ADRx1H.ADRxH15 7 ATD Conversion Result Bit 15 ADRx1H.ADRxH14 6 ATD Conversion Result Bit 14 ADRx1H.ADRxH13 5 ATD Conversion Result Bit 13 ADRx1H.ADRxH12 4 ATD Conversion Result Bit 12 ADRx1H.ADRxH11 3 ATD Conversion Result Bit 11 ADRx1H.ADRxH10 2 ATD Conversion Result Bit 10 ADRx1H.ADRxH9 1 ATD Conversion Result Bit 9 ADRx1H.ADRxH8 0 ATD Conversion Result Bit 8 ADRx1L 0x0073 ATD Result Register 1 Low ADRx1L.ADRxHL7 7 ATD Conversion Result Bit 7 ADRx1L.ADRxHL6 6 ATD Conversion Result Bit 6 ADRx1L.ADRxHL5 5 ATD Conversion Result Bit 5 ADRx1L.ADRxHL4 4 ATD Conversion Result Bit 4 ADRx1L.ADRxHL3 3 ATD Conversion Result Bit 3 ADRx1L.ADRxHL2 2 ATD Conversion Result Bit 2 ADRx1L.ADRxHL1 1 ATD Conversion Result Bit 1 ADRx1L.ADRxHL0 0 ATD Conversion Result Bit 0 ADRx2H 0x0074 ATD Result Register 2 High ADRx2H.ADRxH15 7 ATD Conversion Result Bit 15 ADRx2H.ADRxH14 6 ATD Conversion Result Bit 14 ADRx2H.ADRxH13 5 ATD Conversion Result Bit 13 ADRx2H.ADRxH12 4 ATD Conversion Result Bit 12 ADRx2H.ADRxH11 3 ATD Conversion Result Bit 11 ADRx2H.ADRxH10 2 ATD Conversion Result Bit 10 ADRx2H.ADRxH9 1 ATD Conversion Result Bit 9 ADRx2H.ADRxH8 0 ATD Conversion Result Bit 8 ADRx2L 0x0075 ATD Result Register 2 Low ADRx2L.ADRxHL7 7 ATD Conversion Result Bit 7 ADRx2L.ADRxHL6 6 ATD Conversion Result Bit 6 ADRx2L.ADRxHL5 5 ATD Conversion Result Bit 5 ADRx2L.ADRxHL4 4 ATD Conversion Result Bit 4 ADRx2L.ADRxHL3 3 ATD Conversion Result Bit 3 ADRx2L.ADRxHL2 2 ATD Conversion Result Bit 2 ADRx2L.ADRxHL1 1 ATD Conversion Result Bit 1 ADRx2L.ADRxHL0 0 ATD Conversion Result Bit 0 ADRx3H 0x0076 ATD Result Register 3 High ADRx3H.ADRxH15 7 ATD Conversion Result Bit 15 ADRx3H.ADRxH14 6 ATD Conversion Result Bit 14 ADRx3H.ADRxH13 5 ATD Conversion Result Bit 13 ADRx3H.ADRxH12 4 ATD Conversion Result Bit 12 ADRx3H.ADRxH11 3 ATD Conversion Result Bit 11 ADRx3H.ADRxH10 2 ATD Conversion Result Bit 10 ADRx3H.ADRxH9 1 ATD Conversion Result Bit 9 ADRx3H.ADRxH8 0 ATD Conversion Result Bit 8 ADRx3L 0x0077 ATD Result Register 3 Low ADRx3L.ADRxHL7 7 ATD Conversion Result Bit 7 ADRx3L.ADRxHL6 6 ATD Conversion Result Bit 6 ADRx3L.ADRxHL5 5 ATD Conversion Result Bit 5 ADRx3L.ADRxHL4 4 ATD Conversion Result Bit 4 ADRx3L.ADRxHL3 3 ATD Conversion Result Bit 3 ADRx3L.ADRxHL2 2 ATD Conversion Result Bit 2 ADRx3L.ADRxHL1 1 ATD Conversion Result Bit 1 ADRx3L.ADRxHL0 0 ATD Conversion Result Bit 0 ADRx4H 0x0078 ATD Result Register 4 High ADRx4H.ADRxH15 7 ATD Conversion Result Bit 15 ADRx4H.ADRxH14 6 ATD Conversion Result Bit 14 ADRx4H.ADRxH13 5 ATD Conversion Result Bit 13 ADRx4H.ADRxH12 4 ATD Conversion Result Bit 12 ADRx4H.ADRxH11 3 ATD Conversion Result Bit 11 ADRx4H.ADRxH10 2 ATD Conversion Result Bit 10 ADRx4H.ADRxH9 1 ATD Conversion Result Bit 9 ADRx4H.ADRxH8 0 ATD Conversion Result Bit 8 ADRx4L 0x0079 ATD Result Register 4 Low ADRx4L.ADRxHL7 7 ATD Conversion Result Bit 7 ADRx4L.ADRxHL6 6 ATD Conversion Result Bit 6 ADRx4L.ADRxHL5 5 ATD Conversion Result Bit 5 ADRx4L.ADRxHL4 4 ATD Conversion Result Bit 4 ADRx4L.ADRxHL3 3 ATD Conversion Result Bit 3 ADRx4L.ADRxHL2 2 ATD Conversion Result Bit 2 ADRx4L.ADRxHL1 1 ATD Conversion Result Bit 1 ADRx4L.ADRxHL0 0 ATD Conversion Result Bit 0 ADRx5H 0x007A ATD Result Register 5 High ADRx5H.ADRxH15 7 ATD Conversion Result Bit 15 ADRx5H.ADRxH14 6 ATD Conversion Result Bit 14 ADRx5H.ADRxH13 5 ATD Conversion Result Bit 13 ADRx5H.ADRxH12 4 ATD Conversion Result Bit 12 ADRx5H.ADRxH11 3 ATD Conversion Result Bit 11 ADRx5H.ADRxH10 2 ATD Conversion Result Bit 10 ADRx5H.ADRxH9 1 ATD Conversion Result Bit 9 ADRx5H.ADRxH8 0 ATD Conversion Result Bit 8 ADRx5L 0x007B ATD Result Register 5 Low ADRx5L.ADRxHL7 7 ATD Conversion Result Bit 7 ADRx5L.ADRxHL6 6 ATD Conversion Result Bit 6 ADRx5L.ADRxHL5 5 ATD Conversion Result Bit 5 ADRx5L.ADRxHL4 4 ATD Conversion Result Bit 4 ADRx5L.ADRxHL3 3 ATD Conversion Result Bit 3 ADRx5L.ADRxHL2 2 ATD Conversion Result Bit 2 ADRx5L.ADRxHL1 1 ATD Conversion Result Bit 1 ADRx5L.ADRxHL0 0 ATD Conversion Result Bit 0 ADRx6H 0x007C ATD Result Register 6 High ADRx6H.ADRxH15 7 ATD Conversion Result Bit 15 ADRx6H.ADRxH14 6 ATD Conversion Result Bit 14 ADRx6H.ADRxH13 5 ATD Conversion Result Bit 13 ADRx6H.ADRxH12 4 ATD Conversion Result Bit 12 ADRx6H.ADRxH11 3 ATD Conversion Result Bit 11 ADRx6H.ADRxH10 2 ATD Conversion Result Bit 10 ADRx6H.ADRxH9 1 ATD Conversion Result Bit 9 ADRx6H.ADRxH8 0 ATD Conversion Result Bit 8 ADRx6L 0x007D ATD Result Register 6 Low ADRx6L.ADRxHL7 7 ATD Conversion Result Bit 7 ADRx6L.ADRxHL6 6 ATD Conversion Result Bit 6 ADRx6L.ADRxHL5 5 ATD Conversion Result Bit 5 ADRx6L.ADRxHL4 4 ATD Conversion Result Bit 4 ADRx6L.ADRxHL3 3 ATD Conversion Result Bit 3 ADRx6L.ADRxHL2 2 ATD Conversion Result Bit 2 ADRx6L.ADRxHL1 1 ATD Conversion Result Bit 1 ADRx6L.ADRxHL0 0 ATD Conversion Result Bit 0 ADRx7H 0x007E ATD Result Register 7 High ADRx7H.ADRxH15 7 ATD Conversion Result Bit 15 ADRx7H.ADRxH14 6 ATD Conversion Result Bit 14 ADRx7H.ADRxH13 5 ATD Conversion Result Bit 13 ADRx7H.ADRxH12 4 ATD Conversion Result Bit 12 ADRx7H.ADRxH11 3 ATD Conversion Result Bit 11 ADRx7H.ADRxH10 2 ATD Conversion Result Bit 10 ADRx7H.ADRxH9 1 ATD Conversion Result Bit 9 ADRx7H.ADRxH8 0 ATD Conversion Result Bit 8 ADRx7L 0x007F ATD Result Register 7 Low ADRx7L.ADRxHL7 7 ATD Conversion Result Bit 7 ADRx7L.ADRxHL6 6 ATD Conversion Result Bit 6 ADRx7L.ADRxHL5 5 ATD Conversion Result Bit 5 ADRx7L.ADRxHL4 4 ATD Conversion Result Bit 4 ADRx7L.ADRxHL3 3 ATD Conversion Result Bit 3 ADRx7L.ADRxHL2 2 ATD Conversion Result Bit 2 ADRx7L.ADRxHL1 1 ATD Conversion Result Bit 1 ADRx7L.ADRxHL0 0 ATD Conversion Result Bit 0 TIOS 0x0080 Timer IC/OC Select Register TIOS.IOS7 7 Force Output Compare Action Bits for Channel 7 TIOS.IOS6 6 Force Output Compare Action Bits for Channel 6 TIOS.IOS5 5 Force Output Compare Action Bits for Channel 5 TIOS.IOS4 4 Force Output Compare Action Bits for Channel 4 TIOS.IOS3 3 Force Output Compare Action Bits for Channel 3 TIOS.IOS2 2 Force Output Compare Action Bits for Channel 2 TIOS.IOS1 1 Force Output Compare Action Bits for Channel 1 TIOS.IOS0 0 Force Output Compare Action Bits for Channel 0 CFORC 0x0081 Timer Compare Force Register CFORC.FOC7 7 Force Output Compare Action Bits for Channel 7 CFORC.FOC6 6 Force Output Compare Action Bits for Channel 6 CFORC.FOC5 5 Force Output Compare Action Bits for Channel 5 CFORC.FOC4 4 Force Output Compare Action Bits for Channel 4 CFORC.FOC3 3 Force Output Compare Action Bits for Channel 3 CFORC.FOC2 2 Force Output Compare Action Bits for Channel 2 CFORC.FOC1 1 Force Output Compare Action Bits for Channel 1 CFORC.FOC0 0 Force Output Compare Action Bits for Channel 0 OC7M 0x0082 Timer Output Compare 7 Mask Register OC7M.OC7M7 7 OC7M.OC7M6 6 OC7M.OC7M5 5 OC7M.OC7M4 4 OC7M.OC7M3 3 OC7M.OC7M2 2 OC7M.OC7M1 1 OC7M.OC7M0 0 OC7D 0x0083 Timer Output Compare 7 Data Register OC7D.OC7D7 7 OC7D.OC7D6 6 OC7D.OC7D5 5 OC7D.OC7D4 4 OC7D.OC7D3 3 OC7D.OC7D2 2 OC7D.OC7D1 1 OC7D.OC7D0 0 TCNTH 0x0084 Timer Count Register High TCNTL 0x0085 Timer Count Register Low TSCR 0x0086 Timer System Control Register TSCR.TEN 7 Timer Enable Bit TSCR.TSWAI 6 Timer Stops While in Wait Bit TSCR.TSBCK 5 Timer Stops While in Background Mode Bit TSCR.TFFCA 4 Timer Fast Flag Clear All Bit RESERVED0087 0x0087 RESERVED TCTL1 0x0088 Timer Control Register 1 TCTL1.OM7 7 Output mode 7 TCTL1.OL7 6 Output level 7 TCTL1.OM6 5 Output mode 6 TCTL1.OL6 4 Output level 6 TCTL1.OM5 3 Output mode 5 TCTL1.OL5 2 Output level 5 TCTL1.OM4 1 Output mode 4 TCTL1.OL4 0 Output level 4 TCTL2 0x0089 Timer Control Register 2 TCTL2.OM3 7 Output mode 3 TCTL2.OL3 6 Output level 3 TCTL2.OM2 5 Output mode 2 TCTL2.OL2 4 Output level 2 TCTL2.OM1 3 Output mode 1 TCTL2.OL1 2 Output level 1 TCTL2.OM0 1 Output mode 0 TCTL2.OL0 0 Output level 0 TCTL3 0x008A Timer Control Register 3 TCTL3.EDG7B 7 Input Capture Edge Control Bit 7B TCTL3.EDG7A 6 Input Capture Edge Control Bit 7A TCTL3.EDG6B 5 Input Capture Edge Control Bit 6B TCTL3.EDG6A 4 Input Capture Edge Control Bit 6A TCTL3.EDG5B 3 Input Capture Edge Control Bit 5B TCTL3.EDG5A 2 Input Capture Edge Control Bit 5A TCTL3.EDG4B 1 Input Capture Edge Control Bit 4B TCTL3.EDG4A 0 Input Capture Edge Control Bit 4A TCTL4 0x008B Timer Control Register 4 TCTL4.EDG3B 7 Input Capture Edge Control Bit 3B TCTL4.EDG3A 6 Input Capture Edge Control Bit 3A TCTL4.EDG2B 5 Input Capture Edge Control Bit 2B TCTL4.EDG2A 4 Input Capture Edge Control Bit 2A TCTL4.EDG1B 3 Input Capture Edge Control Bit 1B TCTL4.EDG1A 2 Input Capture Edge Control Bit 1A TCTL4.EDG0B 1 Input Capture Edge Control Bit 0B TCTL4.EDG0A 0 Input Capture Edge Control Bit 0A TMSK1 0x008C Timer Mask Register 1 TMSK1.C7I 7 Input Capture/Output Compare 1 Interrupt Enable Bit 7 TMSK1.C6I 6 Input Capture/Output Compare 1 Interrupt Enable Bit 6 TMSK1.C5I 5 Input Capture/Output Compare 1 Interrupt Enable Bit 5 TMSK1.C4I 4 Input Capture/Output Compare 1 Interrupt Enable Bit 4 TMSK1.C3I 3 Input Capture/Output Compare 1 Interrupt Enable Bit 3 TMSK1.C2I 2 Input Capture/Output Compare 1 Interrupt Enable Bit 2 TMSK1.C1I 1 Input Capture/Output Compare 1 Interrupt Enable Bit 1 TMSK1.C0I 0 Input Capture/Output Compare 1 Interrupt Enable Bit 0 TMSK2 0x008D Timer Mask Register 2 TMSK2.TOI 7 Timer Overflow Interrupt Enable Bit TMSK2.PUPT 5 Timer Pullup Resistor Enable Bit TMSK2.RDPT 4 Timer Drive Reduction Bit TMSK2.TCRE 3 Timer Counter Reset Enable Bit TMSK2.PR2 2 Timer Prescaler Select Bit 2 TMSK2.PR1 1 Timer Prescaler Select Bit 1 TMSK2.PR0 0 Timer Prescaler Select Bit 0 TFLG1 0x008E Timer Interrupt Flag Register 1 TFLG1.C7F 7 Input Capture/Output Compare Channel 7 Flag TFLG1.C6F 6 Input Capture/Output Compare Channel 6 Flag TFLG1.C5F 5 Input Capture/Output Compare Channel 5 Flag TFLG1.C4F 4 Input Capture/Output Compare Channel 4 Flag TFLG1.C3F 3 Input Capture/Output Compare Channel 3 Flag TFLG1.C2F 2 Input Capture/Output Compare Channel 2 Flag TFLG1.C1F 1 Input Capture/Output Compare Channel 1 Flag TFLG1.C0F 0 Input Capture/Output Compare Channel 0 Flag TFLG2 0x008F Timer Interrupt Flag Register 2 TFLG2.TOF 7 Timer Overflow Flag TC0H 0x0090 Timer Input Capture/Output Compare 0 Register High TC0L 0x0091 Timer Input Capture/Output Compare 0 Register Low TC1H 0x0092 Timer Input Capture/Output Compare 1 Register High TC1L 0x0093 Timer Input Capture/Output Compare 1 Register Low TC2H 0x0094 Timer Input Capture/Output Compare 2 Register High TC2L 0x0095 Timer Input Capture/Output Compare 2 Register Low TC3H 0x0096 Timer Input Capture/Output Compare 3 Register High TC3L 0x0097 Timer Input Capture/Output Compare 3 Register Low TC4H 0x0098 Timer Input Capture/Output Compare 4 Register High TC4L 0x0099 Timer Input Capture/Output Compare 4 Register Low TC5H 0x009A Timer Input Capture/Output Compare 5 Register High TC5L 0x009B Timer Input Capture/Output Compare 5 Register Low TC6H 0x009C Timer Input Capture/Output Compare 6 Register High TC6L 0x009D Timer Input Capture/Output Compare 6 Register Low TC7H 0x009E Timer Input Capture/Output Compare 7 Register High TC7L 0x009F Timer Input Capture/Output Compare 7 Register Low PACTL 0x00A0 Pulse Accumulator Control Register PACTL.PAEN 6 Pulse Accumulator System Enable Bit PACTL.PAMOD 5 Pulse Accumulator Mode Bit PACTL.PEDGE 4 Pulse Accumulator Edge Control Bit PACTL.CLK1 3 Clock Select Bit 1 PACTL.CLK0 2 Clock Select Bits 0 PACTL.PAOVI 1 Pulse Accumulator Overflow Interrupt Enable Bit PACTL.PAI 0 Pulse Accumulator Input Interrupt Enable Bit PAFLG 0x00A1 Pulse Accumulator Flag Register PAFLG.PAOVF 1 Pulse Accumulator Overflow Flag PAFLG.PAIF 0 Pulse Accumulator Input Edge Flag PACN3 0x00A2 Pulse Accumulator Count Register 3 PACN2 0x00A3 Pulse Accumulator Count Register 2 PACN1 0x00A4 Pulse Accumulator Count Register 1 PACN0 0x00A5 Pulse Accumulator Count Register 0 MCCTL 0x00A6 16-Bit Modulus Down-Counter Control Regster MCCTL.MCZI 7 Modulus Counter Underflow Interrupt Enable Bit MCCTL.MODMC 6 Modulus Mode Enable Bit MCCTL.RDMCL 5 Read Modulus Down-Counter Load Bit MCCTL.ICLAT 4 Input Capture Force Latch Action Bit MCCTL.FLMC 3 Force Load Register into the Modulus Counter Count Register Bit MCCTL.MCEN 2 Modulus Down-Counter Enable Bit MCCTL.MCPR1 1 Modulus Counter Prescaler Select Bit 1 MCCTL.MCPR0 0 Modulus Counter Prescaler Select Bit 0 MCFLG 0x00A7 16-Bit Modulus Down-Counter Flag Regster MCFLG.MCZF 7 Modulus Counter Underflow Interrupt Flag MCFLG.POLF3 3 First Input Capture Polarity Status Bit 3 MCFLG.POLF2 2 First Input Capture Polarity Status Bit 2 MCFLG.POLF1 1 First Input Capture Polarity Status Bit 1 MCFLG.POLF0 0 First Input Capture Polarity Status Bit 0 ICPACR 0x00A8 Input Control Pulse Accumulators Control Register ICPACR.PA3EN 3 8-Bit Pulse Accumulator 3 Enable Bit ICPACR.PA2EN 2 8-Bit Pulse Accumulator 2 Enable Bit ICPACR.PA1EN 1 8-Bit Pulse Accumulator 1 Enable Bit ICPACR.PA0EN 0 8-Bit Pulse Accumulator 0 Enable Bit DLYCT 0x00A9 Delay Counter Control Register DLYCT.DLY1 1 Delay Counter Select Bit 1 DLYCT.DLY0 0 Delay Counter Select Bit 0 ICOVW 0x00AA Input Control Overwrite Register ICOVW.NOVW7 7 No Input Capture Overwrite Bit 7 ICOVW.NOVW6 6 No Input Capture Overwrite Bit 6 ICOVW.NOVW5 5 No Input Capture Overwrite Bit 5 ICOVW.NOVW4 4 No Input Capture Overwrite Bit 4 ICOVW.NOVW3 3 No Input Capture Overwrite Bit 3 ICOVW.NOVW2 2 No Input Capture Overwrite Bit 2 ICOVW.NOVW1 1 No Input Capture Overwrite Bit 1 ICOVW.NOVW0 0 No Input Capture Overwrite Bit 0 ICSYS 0x00AB Input Control System Control Register ICSYS.SH37 7 Share Input Action of Input Capture Channels 3 and y Bit 7 ICSYS.SH26 6 Share Input Action of Input Capture Channels 2 and y Bit 6 ICSYS.SH15 5 Share Input Action of Input Capture Channels 1 and y Bit 5 ICSYS.SH04 4 Share Input Action of Input Capture Channels 0 and y Bit 4 ICSYS.TFMOD 3 Timer Flag-Setting Mode Bit ICSYS.PACMX 2 8-Bit Pulse Accumulators Maximum Count Bit ICSYS.BUFEN 1 IC Buffer Enable Bit ICSYS.LATQ 0 Input Control Latch or Queue Mode Enable Bit RESERVED00AC 0x00AC RESERVED TIMTST 0x00AD Timer Test Register TIMTST.TCBYP 1 Main Timer Divider Chain Bypass Bit TIMTST.PCBYP 0 PORTT 0x00AE Timer Port Data Register PORTT.PT7 7 Timer Port Data Register bit 7 PORTT.PT6 6 Timer Port Data Register bit 6 PORTT.PT5 5 Timer Port Data Register bit 5 PORTT.PT4 4 Timer Port Data Register bit 4 PORTT.PT3 3 Timer Port Data Register bit 3 PORTT.PT2 2 Timer Port Data Register bit 2 PORTT.PT1 1 Timer Port Data Register bit 1 PORTT.PT0 0 Timer Port Data Register bit 0 DDRT 0x00AF Data Direction Register for Timer Port DDRT.DDT7 7 Data Direction Register for Timer Port bit 7 DDRT.DDT6 6 Data Direction Register for Timer Port bit 6 DDRT.DDT5 5 Data Direction Register for Timer Port bit 5 DDRT.DDT4 4 Data Direction Register for Timer Port bit 4 DDRT.DDT3 3 Data Direction Register for Timer Port bit 3 DDRT.DDT2 2 Data Direction Register for Timer Port bit 2 DDRT.DDT1 1 Data Direction Register for Timer Port bit 1 DDRT.DDT0 0 Data Direction Register for Timer Port bit 0 PBCTL 0x00B0 16-Bit Pulse Accumulator B Control Register PBCTL.PBEN 6 Pulse Accumulator B System Enable Bit PBCTL.PBOVI 1 Pulse Accumulator B Overflow Interrupt Enable Bit PBFLG 0x00B1 Pulse Accumulator B Flag Register PBFLG.PBOVF 1 Pulse Accumulator B Overflow Flag PA3H 0x00B2 8-Bit Pulse Accumulator Holding Register 3 PA2H 0x00B3 8-Bit Pulse Accumulator Holding Register 2 PA1H 0x00B4 8-Bit Pulse Accumulator Holding Register 1 PA0H 0x00B5 8-Bit Pulse Accumulator Holding Register 0 MCCNTH 0x00B6 Modulus Down-Counter Count Register High MCCNTL 0x00B7 Modulus Down-Counter Count Register Low TC0HH 0x00B8 Timer Input Capture Holding Register 0 High TC0HL 0x00B9 Timer Input Capture Holding Register 0 Low TC1HH 0x00BA Timer Input Capture Holding Register 1 High TC1HL 0x00BB Timer Input Capture Holding Register 1 Low TC2HH 0x00BC Timer Input Capture Holding Register 2 High TC2HL 0x00BD Timer Input Capture Holding Register 2 Low TC3HH 0x00BE Timer Input Capture Holding Register 3 High TC3HL 0x00BF Timer Input Capture Holding Register 3 Low SC0BDH 0x00C0 SCI 0 Baud Rate Control Register High SC0BDH.BTST 7 SC0BDH.BSPL 6 SC0BDH.BRLD 5 SC0BDH.SBR12 4 SC0BDH.SBR11 3 SC0BDH.SBR10 2 SC0BDH.SBR9 1 SC0BDH.SBR8 0 SC0BDL 0x00C1 SCI 0 Baud Rate Control Register Low SC0BDL.SBR7 7 SC0BDL.SBR6 6 SC0BDL.SBR5 5 SC0BDL.SBR4 4 SC0BDL.SBR3 3 SC0BDL.SBR2 2 SC0BDL.SBR1 1 SC0BDL.SBR0 0 SC0CR1 0x00C2 SCI Control Register 1 SC0CR1.LOOPS 7 SCI LOOP Mode/Single-Wire Mode Enable Bit SC0CR1.WOMS 6 Wired-OR Mode for Serial Pins SC0CR1.RSRC 5 Receiver Source Bit SC0CR1.M 4 Mode Bit (select character format) SC0CR1.WAKE 3 Wakeup by Address Mark/Idle Bit SC0CR1.ILT 2 Idle Line Type Bit SC0CR1.PE 1 Parity Enable Bit SC0CR1.PT 0 Parity Type Bit SC0CR2 0x00C3 SCI Control Register 2 SC0CR2.TIE 7 Transmit Interrupt Enable Bit SC0CR2.TCIE 6 Transmit Complete Interrupt Enable Bit SC0CR2.RIE 5 Receiver Interrupt Enable Bit SC0CR2.ILIE 4 Idle Line Interrupt Enable Bit SC0CR2.TE 3 Transmitter Enable Bit SC0CR2.RE 2 Receiver Enable Bit SC0CR2.RWU 1 Receiver Wakeup Control Bit SC0CR2.SBK 0 Send Break Bit SC0SR1 0x00C4 SCI Status Register 1 SC0SR1.TDRE 7 Transmit Data Register Empty Flag SC0SR1.TC 6 Transmit Complete Flag SC0SR1.RDRF 5 Receive Data Register Full Flag SC0SR1.IDLE 4 Idle Line Detected Flag SC0SR1.OR 3 Overrun Error Flag SC0SR1.NF 2 Noise Error Flag SC0SR1.FE 1 Framing Error Flag SC0SR1.PF 0 Parity Error Flag SC0SR2 0x00C5 SCI Status Register 2 SC0SR2.RAF 0 Receiver Active Flag SC0DRH 0x00C6 SCI Data Register High SC0DRH.R8 7 Receive Bit 8 SC0DRH.T8 6 Transmit Bit 8 SC0DRL 0x00C7 SCI Data Register Low SC0DRL.R7T7 7 Receive/Transmit Data Bit 7 SC0DRL.R6T6 6 Receive/Transmit Data Bit 6 SC0DRL.R5T5 5 Receive/Transmit Data Bit 5 SC0DRL.R4T4 4 Receive/Transmit Data Bit 4 SC0DRL.R3T3 3 Receive/Transmit Data Bit 3 SC0DRL.R2T2 2 Receive/Transmit Data Bit 2 SC0DRL.R1T1 1 Receive/Transmit Data Bit 1 SC0DRL.R0T0 0 Receive/Transmit Data Bit 0 RESERVED00C8 0x00C8 RESERVED RESERVED00C9 0x00C9 RESERVED RESERVED00CA 0x00CA RESERVED RESERVED00CB 0x00CB RESERVED RESERVED00CC 0x00CC RESERVED RESERVED00CD 0x00CD RESERVED RESERVED00CE 0x00CE RESERVED RESERVED00CF 0x00CF RESERVED SP0CR1 0x00D0 SPI Control Register 1 SP0CR1.SPIE 7 SPI Interrupt Enable Bit SP0CR1.SPE 6 SPI System Enable Bit SP0CR1.SWOM 5 Port S Wired-OR Mode Bit SP0CR1.MSTR 4 SPI Master/Slave Mode Select Bit SP0CR1.CPOL 3 SPI Clock Polarity SP0CR1.CPHA 2 Clock Phase Bits SP0CR1.SSOE 1 Slave Select Output Enable Bit SP0CR1.LSBF 0 SPI LSB First Enable Bit SP0CR2 0x00D1 SPI Control Register 2 SP0CR2.PUPS 3 Pullup Port S Enable Bit SP0CR2.RDS 2 Reduce Drive of Port S Bit SP0CR2.SPC0 0 Serial Pin Control 0 Bit SP0BR 0x00D2 SPI Baud Rate Register SP0BR.SPR2 2 SPI Clock (SCK) Rate Select Bit 2 SP0BR.SPR1 1 SPI Clock (SCK) Rate Select Bit 1 SP0BR.SPR0 0 SPI Clock (SCK) Rate Select Bit 0 SP0SR 0x00D3 SPI Status Register SP0SR.SPIF 7 SPI Interrupt Request Bit SP0SR.WCOL 6 Write Collision Status Flag SP0SR.MODF 4 SPI Mode Error Interrupt Status Flag RESERVED00D4 0x00D4 RESERVED SP0DR 0x00D5 SPI Data Register PORTS 0x00D6 Port S Data Register PORTS.PS7 7 Port S Data Register Bit 7 PORTS.PS6 6 Port S Data Register Bit 6 PORTS.PS5 5 Port S Data Register Bit 5 PORTS.PS4 4 Port S Data Register Bit 4 PORTS.PS3 3 Port S Data Register Bit 3 PORTS.PS2 2 Port S Data Register Bit 2 PORTS.PS1 1 Port S Data Register Bit 1 PORTS.PS0 0 Port S Data Register Bit 0 DDRS 0x00D7 Port S Data Direction Register DDRS.DDS7 7 Port S Data Direction Register Bit 7 DDRS.DDS6 6 Port S Data Direction Register Bit 6 DDRS.DDS5 5 Port S Data Direction Register Bit 5 DDRS.DDS4 4 Port S Data Direction Register Bit 4 DDRS.DDS3 3 Port S Data Direction Register Bit 3 DDRS.DDS2 2 Port S Data Direction Register Bit 2 DDRS.DDS1 1 Port S Data Direction Register Bit 1 DDRS.DDS0 0 Port S Data Direction Register Bit 0 RESERVED00D8 0x00D8 RESERVED RESERVED00D9 0x00D9 RESERVED RESERVED00DA 0x00DA RESERVED PURDS 0x00DB Port S Pullup/Reduced Drive Register PURDS.RDPS2 6 Reduce Drive of PS7-PS4 PURDS.RDPS1 5 Reduce Drive of PS3 and PS2 PURDS.RDPS0 4 Reduce Drive of PS1 and PS0 PURDS.PUPS2 2 Pullup Port S Enable PS7-PS4 PURDS.PUPS1 1 Pullup Port S Enable PS3 and PS2 Bit PURDS.PUPS0 0 Pullup Port S Enable PS1 and PS0 Bit RESERVED00DC 0x00DC RESERVED RESERVED00DD 0x00DD RESERVED RESERVED00DE 0x00DE RESERVED RESERVED00DF 0x00DF RESERVED SLOW 0x00E0 Slow Mode Divider Register SLOW.SLDV2 2 Slow Mode Divisor Selector Bit 2 SLOW.SLDV1 1 Slow Mode Divisor Selector Bit 1 SLOW.SLDV0 0 Slow Mode Divisor Selector Bit 0 RESERVED00E1 0x00E1 RESERVED RESERVED00E2 0x00E2 RESERVED RESERVED00E3 0x00E3 RESERVED RESERVED00E4 0x00E4 RESERVED RESERVED00E5 0x00E5 RESERVED RESERVED00E6 0x00E6 RESERVED RESERVED00E7 0x00E7 RESERVED RESERVED00E8 0x00E8 RESERVED RESERVED00E9 0x00E9 RESERVED RESERVED00EA 0x00EA RESERVED RESERVED00EB 0x00EB RESERVED RESERVED00EC 0x00EC RESERVED RESERVED00ED 0x00ED RESERVED RESERVED00EE 0x00EE RESERVED RESERVED00EF 0x00EF RESERVED EEMCR 0x00F0 EEPROM Configuration Register EEMCR.EESWAI 2 EEPROM Stops in Wait Mode Bit EEMCR.PROTLCK 1 Block Protect Write Lock Bit EEMCR.EERC 0 EEPROM Charge Pump Clock Bit EEPROT 0x00F1 EEPROM Block Protect Register EEPROT.BRPROT4 4 EEPROM Block Protection Bit 4 EEPROT.BRPROT3 3 EEPROM Block Protection Bit 3 EEPROT.BRPROT2 2 EEPROM Block Protection Bit 2 EEPROT.BRPROT1 1 EEPROM Block Protection Bit 1 EEPROT.BRPROT0 0 EEPROM Block Protection Bit 0 EETST 0x00F2 EEPROM Test Register EETST.EEODD 7 Odd Row Programming Bit EETST.EEVEN 6 Even Row Programming Bit EETST.MARG 5 Program and Erase Voltage Margin Test Enable Bit EETST.EECPD 4 Charge Pump Disable Bit EETST.EECPRD 3 Charge Pump Ramp Disable Bit EETST.EECPM 1 Charge Pump Monitor Enable Bit EEPROG 0x00F3 EEPROM Control Register EEPROG.BULKP 7 Bulk Erase Protection Bit EEPROG.BYTE 4 Byte and Aligned Word Erase Bit EEPROG.ROW 3 Row or Bulk Erase Bit EEPROG.ERASE 2 Erase Control Bit EEPROG.EELAT 1 EEPROM Latch Control Bit EEPROG.EEPGM 0 Program and Erase Enable Bit FEELCK 0x00F4 FLASH EEPROM Lock Control Register FEELCK.LOCK 0 Lock Register Bit FEEMCR 0x00F5 FLASH EEPROM Configuration Register FEEMCR.BOOTP 0 Boot Protect Bit FEETST 0x00F6 FLASH EEPROM Test Register FEETST.FSTE 7 Stress Test Enable Bit FEETST.GADR 6 Gate/Drain Stress Test Select Bit FEETST.HVT 5 Stress Test High Voltage Status Bit FEETST.FENLV 4 Enable Low Voltage Bit FEETST.FDISVFP 3 Disable Status V FP Voltage Lock Bit FEETST.VTCK 2 V T Check Test Enable Bit FEETST.STRE 1 Spare Test Row Enable Bit FEETST.MWPR 0 Multiple Word Programming Bit FEECTL 0x00F7 FLASH EEPROM Control Register FEECTL.FEESWAI 4 FLASH EEPROM Stop in Wait Control Bit FEECTL.SVFP 3 Status V FP Voltage Bit FEECTL.ERAS 2 Erase Control Bit FEECTL.LAT 1 Latch Control Bit FEECTL.ENPE 0 Enable Programming/Erase Bit RESERVED00F8 0x00F8 RESERVED RESERVED00F9 0x00F9 RESERVED RESERVED00FA 0x00FA RESERVED RESERVED00FB 0x00FB RESERVED RESERVED00FC 0x00FC RESERVED RESERVED00FD 0x00FD RESERVED RESERVED00FE 0x00FE RESERVED RESERVED00FF 0x00FF RESERVED ; CAN CMCR0 0x0100 msCAN12 Module Control Register 0 CMCR0.CSWAI 5 CAN Stops in Wait Mode Bit CMCR0.SYNCH 4 Synchronized Status Bit CMCR0.TLNKEN 3 Timer Enable Flag CMCR0.SLPAK 2 Sleep Mode Acknowledge Flag CMCR0.SLPRQ 1 Sleep Request, Go To Sleep Mode Flag CMCR0.SFTRES 0 Soft-Reset Bit CMCR1 0x0101 msCAN12 Module Control Register 1 CMCR1.LOOPB 2 Loop Back Self-Test Mode Bit CMCR1.WUPM 1 Wakeup Mode Flag CMCR1.CLKSRC 0 msCAN12 Clock Source Flag CBTR0 0x0102 msCAN12 Bus Timing Register 0 CBTR0.SJW1 7 Synchronization Jump Width Bit 1 CBTR0.SJW0 6 Synchronization Jump Width Bit 0 CBTR0.BRP5 5 Baud Rate Prescaler Bit 5 CBTR0.BRP4 4 Baud Rate Prescaler Bit 4 CBTR0.BRP3 3 Baud Rate Prescaler Bit 3 CBTR0.BRP2 2 Baud Rate Prescaler Bit 2 CBTR0.BRP1 1 Baud Rate Prescaler Bit 1 CBTR0.BRP0 0 Baud Rate Prescaler Bit 0 CBTR1 0x0103 msCAN12 Bus Timing Register 1 CBTR1.SAMP 7 Sampling Bit CBTR1.TSEG22 6 Time Segment Bit 22 CBTR1.TSEG21 5 Time Segment Bit 21 CBTR1.TSEG20 4 Time Segment Bit 20 CBTR1.TSEG13 3 Time Segment Bit 13 CBTR1.TSEG12 2 Time Segment Bit 12 CBTR1.TSEG11 1 Time Segment Bit 11 CBTR1.TSEG10 0 Time Segment Bit 10 CRFLG 0x0104 msCAN12 Receiver Flag Register CRFLG.WUPIF 7 Wakeup Interrupt Flag CRFLG.RWRNIF 6 Receiver Warning Interrupt Flag CRFLG.TWRNIF 5 Transmitter Warning Interrupt Flag CRFLG.RERRIF 4 Receiver Error Passive Interrupt Flag CRFLG.TERRIF 3 Transmitter Error Passive Interrupt Flag CRFLG.BOFFIF 2 Bus-Off Interrupt Flag CRFLG.OVRIF 1 Overrun Interrupt Flag CRFLG.RXF 0 Receive Buffer Full Flag CRIER 0x0105 msCAN12 Receiver Interrupt Enable Register CRIER.WUPIE 7 Wakeup Interrupt Enable Bit CRIER.RWRNIE 6 Receiver Warning Interrupt Enable Bit CRIER.TWRNIE 5 Transmitter Warning Interrupt Enable Bit CRIER.RERRIE 4 Receiver Error Passive Interrupt Enable Bit CRIER.TERRIE 3 Transmitter Error Passive Interrupt Enable Bit CRIER.BOFFIE 2 Bus-Off Interrupt Enable Bit CRIER.OVRIE 1 Overrun Interrupt Enable Bit CRIER.RXFIE 0 Receiver Full Interrupt Enable Bit CTFLG 0x0106 msCAN12 Transmitter Flag Register CTFLG.ABTAK2 6 Abort Acknowledge Flag 2 CTFLG.ABTAK1 5 Abort Acknowledge Flag 1 CTFLG.ABTAK0 4 Abort Acknowledge Flag 0 CTFLG.TXE2 2 Transmitter Buffer Empty Flag 2 CTFLG.TXE1 1 Transmitter Buffer Empty Flag 1 CTFLG.TXE0 0 Transmitter Buffer Empty Flag 0 CTCR 0x0107 msCAN12 Transmitter Control Register CTCR.ABTRQ2 6 Abort Request Bit 2 CTCR.ABTRQ1 5 Abort Request Bit 1 CTCR.ABTRQ0 4 Abort Request Bit 0 CTCR.TXEIE2 2 Transmitter Empty Interrupt Enable Bit 2 CTCR.TXEIE1 1 Transmitter Empty Interrupt Enable Bit 1 CTCR.TXEIE0 0 Transmitter Empty Interrupt Enable Bit 0 CIDAC 0x0108 msCAN12 Identifier Acceptance Control Register CIDAC.IDAM1 5 Identifier Acceptance Mode Flag 1 CIDAC.IDAM0 4 Identifier Acceptance Mode Flag 0 CIDAC.IDHIT2 2 Identifier Acceptance Hit Indicator Flag 2 CIDAC.IDHIT1 1 Identifier Acceptance Hit Indicator Flag 1 CIDAC.IDHIT0 0 Identifier Acceptance Hit Indicator Flag 0 RESERVED0109 0x0109 RESERVED RESERVED010A 0x010A RESERVED RESERVED010B 0x010B RESERVED RESERVED010C 0x010C RESERVED RESERVED010D 0x010D RESERVED CRXERR 0x010E msCAN12 Receive Error Counter CRXERR.RXERR7 7 CRXERR.RXERR6 6 CRXERR.RXERR5 5 CRXERR.RXERR4 4 CRXERR.RXERR3 3 CRXERR.RXERR2 2 CRXERR.RXERR1 1 CRXERR.RXERR0 0 CTXERR 0x010F msCAN12 Transmit Error Counter CTXERR.TXERR7 7 CTXERR.TXERR6 6 CTXERR.TXERR5 5 CTXERR.TXERR4 4 CTXERR.TXERR3 3 CTXERR.TXERR2 2 CTXERR.TXERR1 1 CTXERR.TXERR0 0 CIDAR0 0x0110 msCAN12 Identifier Acceptance Register 0 CIDAR0.AC7 7 Acceptance Code Bit 7 CIDAR0.AC6 6 Acceptance Code Bit 6 CIDAR0.AC5 5 Acceptance Code Bit 5 CIDAR0.AC4 4 Acceptance Code Bit 4 CIDAR0.AC3 3 Acceptance Code Bit 3 CIDAR0.AC2 2 Acceptance Code Bit 2 CIDAR0.AC1 1 Acceptance Code Bit 1 CIDAR0.AC0 0 Acceptance Code Bit 0 CIDAR1 0x0111 msCAN12 Identifier Acceptance Register 1 CIDAR1.AC7 7 Acceptance Code Bit 7 CIDAR1.AC6 6 Acceptance Code Bit 6 CIDAR1.AC5 5 Acceptance Code Bit 5 CIDAR1.AC4 4 Acceptance Code Bit 4 CIDAR1.AC3 3 Acceptance Code Bit 3 CIDAR1.AC2 2 Acceptance Code Bit 2 CIDAR1.AC1 1 Acceptance Code Bit 1 CIDAR1.AC0 0 Acceptance Code Bit 0 CIDAR2 0x0112 msCAN12 Identifier Acceptance Register 2 CIDAR2.AC7 7 Acceptance Code Bit 7 CIDAR2.AC6 6 Acceptance Code Bit 6 CIDAR2.AC5 5 Acceptance Code Bit 5 CIDAR2.AC4 4 Acceptance Code Bit 4 CIDAR2.AC3 3 Acceptance Code Bit 3 CIDAR2.AC2 2 Acceptance Code Bit 2 CIDAR2.AC1 1 Acceptance Code Bit 1 CIDAR2.AC0 0 Acceptance Code Bit 0 CIDAR3 0x0113 msCAN12 Identifier Acceptance Register 3 CIDAR3.AC7 7 Acceptance Code Bit 7 CIDAR3.AC6 6 Acceptance Code Bit 6 CIDAR3.AC5 5 Acceptance Code Bit 5 CIDAR3.AC4 4 Acceptance Code Bit 4 CIDAR3.AC3 3 Acceptance Code Bit 3 CIDAR3.AC2 2 Acceptance Code Bit 2 CIDAR3.AC1 1 Acceptance Code Bit 1 CIDAR3.AC0 0 Acceptance Code Bit 0 CIDMR0 0x0114 msCAN12 Identifier Mask Register 0 CIDMR0.AM7 7 Acceptance Mask Bit 7 CIDMR0.AM6 6 Acceptance Mask Bit 6 CIDMR0.AM5 5 Acceptance Mask Bit 5 CIDMR0.AM4 4 Acceptance Mask Bit 4 CIDMR0.AM3 3 Acceptance Mask Bit 3 CIDMR0.AM2 2 Acceptance Mask Bit 2 CIDMR0.AM1 1 Acceptance Mask Bit 1 CIDMR0.AM0 0 Acceptance Mask Bit 0 CIDMR1 0x0115 msCAN12 Identifier Mask Register 1 CIDMR1.AM7 7 Acceptance Mask Bit 7 CIDMR1.AM6 6 Acceptance Mask Bit 6 CIDMR1.AM5 5 Acceptance Mask Bit 5 CIDMR1.AM4 4 Acceptance Mask Bit 4 CIDMR1.AM3 3 Acceptance Mask Bit 3 CIDMR1.AM2 2 Acceptance Mask Bit 2 CIDMR1.AM1 1 Acceptance Mask Bit 1 CIDMR1.AM0 0 Acceptance Mask Bit 0 CIDMR2 0x0116 msCAN12 Identifier Mask Register 2 CIDMR2.AM7 7 Acceptance Mask Bit 7 CIDMR2.AM6 6 Acceptance Mask Bit 6 CIDMR2.AM5 5 Acceptance Mask Bit 5 CIDMR2.AM4 4 Acceptance Mask Bit 4 CIDMR2.AM3 3 Acceptance Mask Bit 3 CIDMR2.AM2 2 Acceptance Mask Bit 2 CIDMR2.AM1 1 Acceptance Mask Bit 1 CIDMR2.AM0 0 Acceptance Mask Bit 0 CIDMR3 0x0117 msCAN12 Identifier Mask Register 3 CIDMR3.AM7 7 Acceptance Mask Bit 7 CIDMR3.AM6 6 Acceptance Mask Bit 6 CIDMR3.AM5 5 Acceptance Mask Bit 5 CIDMR3.AM4 4 Acceptance Mask Bit 4 CIDMR3.AM3 3 Acceptance Mask Bit 3 CIDMR3.AM2 2 Acceptance Mask Bit 2 CIDMR3.AM1 1 Acceptance Mask Bit 1 CIDMR3.AM0 0 Acceptance Mask Bit 0 CIDAR4 0x0118 msCAN12 Identifier Acceptance Register 4 CIDAR4.AC7 7 Acceptance Code Bit 7 CIDAR4.AC6 6 Acceptance Code Bit 6 CIDAR4.AC5 5 Acceptance Code Bit 5 CIDAR4.AC4 4 Acceptance Code Bit 4 CIDAR4.AC3 3 Acceptance Code Bit 3 CIDAR4.AC2 2 Acceptance Code Bit 2 CIDAR4.AC1 1 Acceptance Code Bit 1 CIDAR4.AC0 0 Acceptance Code Bit 0 CIDAR5 0x0119 msCAN12 Identifier Acceptance Register 5 CIDAR5.AC7 7 Acceptance Code Bit 7 CIDAR5.AC6 6 Acceptance Code Bit 6 CIDAR5.AC5 5 Acceptance Code Bit 5 CIDAR5.AC4 4 Acceptance Code Bit 4 CIDAR5.AC3 3 Acceptance Code Bit 3 CIDAR5.AC2 2 Acceptance Code Bit 2 CIDAR5.AC1 1 Acceptance Code Bit 1 CIDAR5.AC0 0 Acceptance Code Bit 0 CIDAR6 0x011A msCAN12 Identifier Acceptance Register 6 CIDAR6.AC7 7 Acceptance Code Bit 7 CIDAR6.AC6 6 Acceptance Code Bit 6 CIDAR6.AC5 5 Acceptance Code Bit 5 CIDAR6.AC4 4 Acceptance Code Bit 4 CIDAR6.AC3 3 Acceptance Code Bit 3 CIDAR6.AC2 2 Acceptance Code Bit 2 CIDAR6.AC1 1 Acceptance Code Bit 1 CIDAR6.AC0 0 Acceptance Code Bit 0 CIDAR7 0x011B msCAN12 Identifier Acceptance Register 7 CIDAR7.AC7 7 Acceptance Code Bit 7 CIDAR7.AC6 6 Acceptance Code Bit 6 CIDAR7.AC5 5 Acceptance Code Bit 5 CIDAR7.AC4 4 Acceptance Code Bit 4 CIDAR7.AC3 3 Acceptance Code Bit 3 CIDAR7.AC2 2 Acceptance Code Bit 2 CIDAR7.AC1 1 Acceptance Code Bit 1 CIDAR7.AC0 0 Acceptance Code Bit 0 CIDMR4 0x011C msCAN12 Identifier Mask Register 4 CIDMR4.AM7 7 Acceptance Mask Bit 7 CIDMR4.AM6 6 Acceptance Mask Bit 6 CIDMR4.AM5 5 Acceptance Mask Bit 5 CIDMR4.AM4 4 Acceptance Mask Bit 4 CIDMR4.AM3 3 Acceptance Mask Bit 3 CIDMR4.AM2 2 Acceptance Mask Bit 2 CIDMR4.AM1 1 Acceptance Mask Bit 1 CIDMR4.AM0 0 Acceptance Mask Bit 0 CIDMR5 0x011D msCAN12 Identifier Mask Register 5 CIDMR5.AM7 7 Acceptance Mask Bit 7 CIDMR5.AM6 6 Acceptance Mask Bit 6 CIDMR5.AM5 5 Acceptance Mask Bit 5 CIDMR5.AM4 4 Acceptance Mask Bit 4 CIDMR5.AM3 3 Acceptance Mask Bit 3 CIDMR5.AM2 2 Acceptance Mask Bit 2 CIDMR5.AM1 1 Acceptance Mask Bit 1 CIDMR5.AM0 0 Acceptance Mask Bit 0 CIDMR6 0x011E msCAN12 Identifier Mask Register 6 CIDMR6.AM7 7 Acceptance Mask Bit 7 CIDMR6.AM6 6 Acceptance Mask Bit 6 CIDMR6.AM5 5 Acceptance Mask Bit 5 CIDMR6.AM4 4 Acceptance Mask Bit 4 CIDMR6.AM3 3 Acceptance Mask Bit 3 CIDMR6.AM2 2 Acceptance Mask Bit 2 CIDMR6.AM1 1 Acceptance Mask Bit 1 CIDMR6.AM0 0 Acceptance Mask Bit 0 CIDMR7 0x011F msCAN12 Identifier Mask Register 7 CIDMR7.AM7 7 Acceptance Mask Bit 7 CIDMR7.AM6 6 Acceptance Mask Bit 6 CIDMR7.AM5 5 Acceptance Mask Bit 5 CIDMR7.AM4 4 Acceptance Mask Bit 4 CIDMR7.AM3 3 Acceptance Mask Bit 3 CIDMR7.AM2 2 Acceptance Mask Bit 2 CIDMR7.AM1 1 Acceptance Mask Bit 1 CIDMR7.AM0 0 Acceptance Mask Bit 0 RESERVED0120 0x0120 RESERVED RESERVED0121 0x0121 RESERVED RESERVED0122 0x0122 RESERVED RESERVED0123 0x0123 RESERVED RESERVED0124 0x0124 RESERVED RESERVED0125 0x0125 RESERVED RESERVED0126 0x0126 RESERVED RESERVED0127 0x0127 RESERVED RESERVED0128 0x0128 RESERVED RESERVED0129 0x0129 RESERVED RESERVED012A 0x012A RESERVED RESERVED012B 0x012B RESERVED RESERVED012C 0x012C RESERVED RESERVED012D 0x012D RESERVED RESERVED012E 0x012E RESERVED RESERVED012F 0x012F RESERVED RESERVED0130 0x0130 RESERVED RESERVED0131 0x0131 RESERVED RESERVED0132 0x0132 RESERVED RESERVED0133 0x0133 RESERVED RESERVED0134 0x0134 RESERVED RESERVED0135 0x0135 RESERVED RESERVED0136 0x0136 RESERVED RESERVED0137 0x0137 RESERVED RESERVED0138 0x0138 RESERVED RESERVED0139 0x0139 RESERVED RESERVED013A 0x013A RESERVED RESERVED013B 0x013B RESERVED RESERVED013C 0x013C RESERVED PCTLCAN 0x013D msCAN12 Port CAN Control Register PCTLCAN.PUECAN 1 Pullup Enable Port CAN Bit PCTLCAN.RDPCAN 0 Reduced Drive Port CAN PORTCAN 0x013E msCAN12 Port CAN Data Register PORTCAN.PCAN7 7 Port CAN Data Bit 7 PORTCAN.PCAN6 6 Port CAN Data Bit 6 PORTCAN.PCAN5 5 Port CAN Data Bit 5 PORTCAN.PCAN4 4 Port CAN Data Bit 4 PORTCAN.PCAN3 3 Port CAN Data Bit 3 PORTCAN.PCAN2 2 Port CAN Data Bit 2 PORTCAN.TxCAN 1 PORTCAN.RxCAN 0 DDRCAN 0x013F msCAN12 Port CAN Data Direction Register DDRCAN.DDRCAN7 7 Data Direction Port CAN Bit 7 DDRCAN.DDRCAN6 6 Data Direction Port CAN Bit 6 DDRCAN.DDRCAN5 5 Data Direction Port CAN Bit 5 DDRCAN.DDRCAN4 4 Data Direction Port CAN Bit 4 DDRCAN.DDRCAN3 3 Data Direction Port CAN Bit 3 DDRCAN.DDRCAN2 2 Data Direction Port CAN Bit 2 .68HC912BD32 ; http://e-www.motorola.com/brdata/PDFDB/docs/MC68HC912BD32.pdf ; MC68HC912BD32_D.pdf ; MEMORY MAP area DATA FSR 0x0000:0x0200 area BSS RESERVED 0x0200:0x0800 area DATA RAM 0x0800:0x0C00 area BSS RESERVED 0x0C00:0x0800 area DATA FLASH_EEPROM 0x8000:0xFFC0 area DATA USER_VEC 0xFFC0:0x10000 ; Interrupt and reset vector assignments interrupt __RESET 0xFFFE Reset interrupt _COPCTL 0xFFFC COP Clock Monitor Fail Reset interrupt COP_F_R 0xFFFA COP Failure Reset interrupt UIT 0xFFF8 Unimplemented Instruction Trap interrupt SWI 0xFFF6 SWI interrupt XIRQ 0xFFF4 XIRQ interrupt _INTCR_IRQEN 0xFFF2 IRQ interrupt RTICTL_RTIE 0xFFF0 Real Time Interrupt interrupt TMSK1_C0I 0xFFEE Timer Channel 0 interrupt TMSK1_C1I 0xFFEC Timer Channel 1 interrupt TMSK1_C2I 0xFFEA Timer Channel 2 interrupt TMSK1_C3I 0xFFE8 Timer Channel 3 interrupt TMSK1_C4I 0xFFE6 Timer Channel 4 interrupt TMSK1_C5I 0xFFE4 Timer Channel 5 interrupt TMSK1_C6I 0xFFE2 Timer Channel 6 interrupt TMSK1_C7I 0xFFE0 Timer Channel 7 interrupt TMSK2_TOI 0xFFDE Timer Overflow interrupt PACTL_PAOVI 0xFFDC Pulse Accumulator Overflow interrupt PACTL_PAI 0xFFDA Pulse Accumulator Input Edge interrupt SP0CR1_SPIE 0xFFD8 SPI Serial Transfer Complete interrupt _SC0CR2 0xFFD6 SCI 0 interrupt ATDCTL2 0xFFD2 ATD interrupt RIER_RCVFIE 0xFFD0 Receive Fifo interrupt RIER_RXIE 0xFFC8 SBI Receive interrupt RIER 0xFFC6 SBI Synchronization interrupt GIER 0xFFC4 SBI General Interrupt ; INPUT/ OUTPUT PORTS PORTA 0x0000 Port A Data Register PORTA.PA7 7 Port A Data Bit 7 PORTA.PA6 6 Port A Data Bit 6 PORTA.PA5 5 Port A Data Bit 5 PORTA.PA4 4 Port A Data Bit 4 PORTA.PA3 3 Port A Data Bit 3 PORTA.PA2 2 Port A Data Bit 2 PORTA.PA1 1 Port A Data Bit 1 PORTA.PA0 0 Port A Data Bit 0 PORTB 0x0001 Port B Data Register PORTB.PB7 7 Port B Data Bit 7 PORTB.PB6 6 Port B Data Bit 6 PORTB.PB5 5 Port B Data Bit 5 PORTB.PB4 4 Port B Data Bit 4 PORTB.PB3 3 Port B Data Bit 3 PORTB.PB2 2 Port B Data Bit 2 PORTB.PB1 1 Port B Data Bit 1 PORTB.PB0 0 Port B Data Bit 0 DDRA 0x0002 Data Direction Register A DDRA.DDA7 7 Data Direction Register A Bit 7 DDRA.DDA6 6 Data Direction Register A Bit 6 DDRA.DDA5 5 Data Direction Register A Bit 5 DDRA.DDA4 4 Data Direction Register A Bit 4 DDRA.DDA3 3 Data Direction Register A Bit 3 DDRA.DDA2 2 Data Direction Register A Bit 2 DDRA.DDA1 1 Data Direction Register A Bit 1 DDRA.DDA0 0 Data Direction Register A Bit 0 DDRB 0x0003 Data Direction Register B DDRB.DDB7 7 Data Direction Register B Bit 7 DDRB.DDB6 6 Data Direction Register B Bit 6 DDRB.DDB5 5 Data Direction Register B Bit 5 DDRB.DDB4 4 Data Direction Register B Bit 4 DDRB.DDB3 3 Data Direction Register B Bit 3 DDRB.DDB2 2 Data Direction Register B Bit 2 DDRB.DDB1 1 Data Direction Register B Bit 1 DDRB.DDB0 0 Data Direction Register B Bit 0 RESERVED00004 0x0004 RESERVED RESERVED00005 0x0005 RESERVED RESERVED00006 0x0006 RESERVED RESERVED00007 0x0007 RESERVED PORTE 0x0008 Port E Data Register PORTE.PE7 7 Port E Data Bit 7 PORTE.PE6 6 Port E Data Bit 6 PORTE.PE5 5 Port E Data Bit 5 PORTE.PE4 4 Port E Data Bit 4 PORTE.PE3 3 Port E Data Bit 3 PORTE.PE2 2 Port E Data Bit 2 PORTE.PE1 1 Port E Data Bit 1 PORTE.PE0 0 Port E Data Bit 0 DDRE 0x0009 Data Direction Register E DDRE.DDE7 7 Data Direction Register E Bit 7 DDRE.DDE6 6 Data Direction Register E Bit 6 DDRE.DDE5 5 Data Direction Register E Bit 5 DDRE.DDE4 4 Data Direction Register E Bit 4 DDRE.DDE3 3 Data Direction Register E Bit 3 DDRE.DDE2 2 Data Direction Register E Bit 2 DDRE.DDE1 1 Data Direction Register E Bit 1 DDRE.DDE0 0 Data Direction Register E Bit 0 PEAR 0x000A Port E Assignment Register PEAR.NDBE 7 No Data Bus Enable PEAR.PIPOE 5 Pipe Signal Output Enable PEAR.NECLK 4 No External E Clock PEAR.LSTRE 3 Low Strobe (LSTRB) Enable PEAR.RDWE 2 Read/Write Enable MODE 0x000B Mode Register MODE.SMODN 7 Mode Select Special MODE.MODB 6 Mode Select B MODE.MODA 5 Mode Select A MODE.ESTR 4 E Clock Stretch Enable MODE.IVIS 3 Internal Visibility MODE.EBSWAI 2 External Bus Module Stop in Wait Control MODE.EME 0 Emulate Port E PUCR 0x000C Pull Up Control Register PUCR.PUPE 4 Pull-Up Port E Enable PUCR.PUPB 1 Pull-Up Port B Enable PUCR.PUPA 0 Pull-Up Port A Enable RDRIV 0x000D Reduced Drive of I/O Lines RDRIV.RDPE 3 Reduced Drive of Port E RDRIV.RDPB 1 Reduced Drive of Port B RDRIV.RDPA 0 Reduced Drive of Port A RESERVED000E 0x000E RESERVED RESERVED000F 0x000F RESERVED INITRM 0x0010 Initialization of Internal RAM Position Register INITRM.RAM15 7 Internal RAM map position 15 INITRM.RAM14 6 Internal RAM map position 14 INITRM.RAM13 5 Internal RAM map position 13 INITRM.RAM12 4 Internal RAM map position 12 INITRM.RAM11 3 Internal RAM map position 11 INITRG 0x0011 Initialization of Internal Register Position Register INITRG.REG15 7 Internal register map position 15 INITRG.REG14 6 Internal register map position 14 INITRG.REG13 5 Internal register map position 13 INITRG.REG12 4 Internal register map position 12 INITRG.REG11 3 Internal register map position 11 INITRG.MMSWAI 0 Memory Mapping Interface Stop in Wait Control INITEE 0x0012 Initialization of Internal EEPROM Position Register INITEE.EE15 7 Internal EEPROM map position 15 INITEE.EE14 6 Internal EEPROM map position 14 INITEE.EE13 5 Internal EEPROM map position 13 INITEE.EE12 4 Internal EEPROM map position 12 INITEE.EEON 0 Internal EEPROM On (Enabled) MISC 0x0013 Miscellaneous Mapping Control Register MISC.NDRF 6 Narrow Data Bus for Register-Following Map MISC.RFSTR1 5 Register-Following Stretch Bit 1 MISC.RFSTR0 4 Register-Following Stretch Bit 0 MISC.EXSTR1 3 External Access Stretch Bit1 MISC.EXSTR0 2 External Access Stretch Bit0 MISC.MAPROM 1 Map Location of Flash EEPROM MISC.ROMON 0 Enable Flash EEPROM RTICTL 0x0014 Real-Time Interrupt Control Register RTICTL.RTIE 7 Real-Time Interrupt Enable RTICTL.RSWAI 6 RTI and COP Stop While in Wait RTICTL.RSBCK 5 RTI and COP Stop While in Background Debug Mode RTICTL.RTBYP 3 Real-Time Interrupt Divider Chain Bypass RTICTL.RTR2 2 Real-Time Interrupt Rate Select 2 RTICTL.RTR1 1 Real-Time Interrupt Rate Select 1 RTICTL.RTR0 0 Real-Time Interrupt Rate Select 0 RTIFLG 0x0015 Real-Time Interrupt Flag Register RTIFLG.RTIF 7 Real-Time Interrupt Flag COPCTL 0x0016 COP Control Register COPCTL.CME 7 Clock Monitor Enable COPCTL.FCME 6 Force Clock Monitor Enable COPCTL.FCM 5 Force Clock Monitor Reset COPCTL.FCOP 4 Force COP Watchdog Reset COPCTL.DISR 3 Disable Resets from COP Watchdog and Clock Monitor COPCTL.CR2 2 COP Watchdog Timer Rate Select Bit 2 COPCTL.CR1 1 COP Watchdog Timer Rate Select Bit 1 COPCTL.CR0 0 COP Watchdog Timer Rate Select Bit 0 COPRST 0x0017 Arm/Reset COP Timer Register ITST0 0x0018 ITST0.ITE6 7 ITST0.ITE8 6 ITST0.ITEA 5 ITST0.ITEC 4 ITST0.ITEE 3 ITST0.ITF0 2 ITST0.ITF2 1 ITST0.ITF4 0 ITST1 0x0019 ITST1.ITD6 7 ITST1.ITD8 6 ITST1.ITDA 5 ITST1.ITDC 4 ITST1.ITDE 3 ITST1.ITE0 2 ITST1.ITE2 1 ITST1.ITE4 0 ITST2 0x001A ITST2.ITC6 7 ITST2.ITC8 6 ITST2.ITCA 5 ITST2.ITCC 4 ITST2.ITCE 3 ITST2.ITD0 2 ITST2.ITD2 1 ITST2.ITD4 0 ITST3 0x001B ITST3.ITC0 2 ITST3.ITC2 1 ITST3.ITC4 0 RESERVED001C 0x001C RESERVED RESERVED001D 0x001D RESERVED INTCR 0x001E Interrupt Control Register INTCR.IRQE 7 IRQ Select Edge Sensitive Only INTCR.IRQEN 6 External IRQ Enable INTCR.DLY 5 Enable Oscillator Start-up Delay on Exit from STOP HPRIO 0x001F Highest Priority I Interrupt HPRIO.PSEL5 5 HPRIO.PSEL4 4 HPRIO.PSEL3 3 HPRIO.PSEL2 2 HPRIO.PSEL1 1 BRKCT0 0x0020 Breakpoint Control Register 0 BRKCT0.BKEN1 7 Breakpoint Mode Enable 1 BRKCT0.BKEN0 6 Breakpoint Mode Enable 0 BRKCT0.BKPM 5 Break on Program Addresses BRKCT0.BK1ALE 3 Breakpoint 1 Range Control BRKCT0.BK0ALE 2 Breakpoint 0 Range Control BRKCT1 0x0021 Breakpoint Control Register 1 BRKCT1.BKDBE 6 Enable Data Bus BRKCT1.BKMBH 5 Breakpoint Mask High BRKCT1.BKMBL 4 Breakpoint Mask Low BRKCT1.BK1RWE 3 R/W Compare Enable BRKCT1.BK1RW 2 R/W Compare Value BRKCT1.BK0RWE 1 R/W Compare Enable BRKCT1.BK0RW 0 R/W Compare Value BRKAH 0x0022 Breakpoint Address Register High BRKAL 0x0023 Breakpoint Address Register Low BRKDH 0x0024 Breakpoint Data Register High BRKDL 0x0025 Breakpoint Data Register Low RESERVED0026 0x0026 RESERVED RESERVED0027 0x0027 RESERVED RESERVED0028 0x0028 RESERVED RESERVED0029 0x0029 RESERVED RESERVED002A 0x002A RESERVED RESERVED002B 0x002B RESERVED RESERVED002C 0x002C RESERVED RESERVED002D 0x002D RESERVED RESERVED002E 0x002E RESERVED RESERVED002F 0x002F RESERVED RESERVED0030 0x0030 RESERVED RESERVED0031 0x0031 RESERVED RESERVED0032 0x0032 RESERVED RESERVED0033 0x0033 RESERVED RESERVED0034 0x0034 RESERVED RESERVED0035 0x0035 RESERVED RESERVED0036 0x0036 RESERVED RESERVED0037 0x0037 RESERVED RESERVED0038 0x0038 RESERVED RESERVED0039 0x0039 RESERVED RESERVED003A 0x003A RESERVED RESERVED003B 0x003B RESERVED RESERVED003C 0x003C RESERVED RESERVED003D 0x003D RESERVED RESERVED003E 0x003E RESERVED RESERVED003F 0x003F RESERVED PWCLK 0x0040 PWM Clock Select Register with Concatenate Bits PWCLK.CON23 7 Concatenate PWM Channels 2 and 3 PWCLK.CON01 6 Concatenate PWM Channels 0 and 1 PWCLK.PCKA2 5 Prescaler for Clock A 2 PWCLK.PCKA1 4 Prescaler for Clock A 1 PWCLK.PCKA0 3 Prescaler for Clock A 0 PWCLK.PCKB2 2 Prescaler for Clock B 2 PWCLK.PCKB1 1 Prescaler for Clock B 1 PWCLK.PCKB0 0 Prescaler for Clock B 0 PWPOL 0x0041 PWM Clock Select and Polarity PWPOL.PCLK3 7 PWM Channel 3 Clock Select PWPOL.PCLK2 6 PWM Channel 2 Clock Select PWPOL.PCLK1 5 PWM Channel 1 Clock Select PWPOL.PCLK0 4 PWM Channel 0 Clock Select PWPOL.PPOL3 3 PWM Channel 3 Polarity PWPOL.PPOL2 2 PWM Channel 2 Polarity PWPOL.PPOL1 1 PWM Channel 1 Polarity PWPOL.PPOL0 0 PWM Channel 0 Polarity PWEN 0x0042 PWM Enable PWEN.PWEN3 3 PWM Channel 3 Enable PWEN.PWEN2 2 PWM Channel 2 Enable PWEN.PWEN1 1 PWM Channel 1 Enable PWEN.PWEN0 0 PWM Channel 0 Enable PWPRES 0x0043 PWM Prescale Counter PWSCAL0 0x0044 PWM Scale Register 0 PWSCNT0 0x0045 PWM Scale Counter 0 Value PWSCAL1 0x0046 PWM Scale Register 1 PWSCNT1 0x0047 PWM Scale Counter 1 Value PWCNT0 0x0048 PWM Channel Counter 0 PWCNT1 0x0049 PWM Channel Counter 1 PWCNT2 0x004A PWM Channel Counter 2 PWCNT3 0x004B PWM Channel Counter 3 PWPER0 0x004C PWM Channel Period Register 0 PWPER1 0x004D PWM Channel Period Register 1 PWPER2 0x004E PWM Channel Period Register 2 PWPER3 0x004F PWM Channel Period Register 3 PWDTY0 0x0050 PWM Channel Duty Register 0 PWDTY1 0x0051 PWM Channel Duty Register 1 PWDTY2 0x0052 PWM Channel Duty Register 2 PWDTY3 0x0053 PWM Channel Duty Register 3 PWCTL 0x0054 PWM Control Register PWCTL.PSWAI 4 PWM Halts while in Wait Mode PWCTL.CENTR 3 Center-Aligned Output Mode PWCTL.RDP 2 Reduced Drive of Port P PWCTL.PUPP 1 Pull-Up Port P Enable PWCTL.PSBCK 0 PWM Stops while in Background Mode PWTST 0x0055 PWM Special Mode Register PWTST.DISCR 7 Disable Reset of Channel Counter on Write to Channel Counter PWTST.DISCP 6 Disable Compare Count Period PWTST.DISCAL 5 Disable load of Scale-counters on write to the associated scale-registers PORTPP 0x0056 Port P Data Register PORTPP.PP7 7 Port P Data Bit 7 PORTPP.PP6 6 Port P Data Bit 6 PORTPP.PP5 5 Port P Data Bit 5 PORTPP.PP4 4 Port P Data Bit 4 PORTPP.PP3 3 Port P Data Bit 3 PORTPP.PP2 2 Port P Data Bit 2 PORTPP.PP1 1 Port P Data Bit 1 PORTPP.PP0 0 Port P Data Bit 0 DDRP 0x0057 Data Direction Register P DDRP.DDP7 7 Data Direction Register P Bit 7 DDRP.DDP6 6 Data Direction Register P Bit 6 DDRP.DDP5 5 Data Direction Register P Bit 5 DDRP.DDP4 4 Data Direction Register P Bit 4 DDRP.DDP3 3 Data Direction Register P Bit 3 DDRP.DDP2 2 Data Direction Register P Bit 2 DDRP.DDP1 1 Data Direction Register P Bit 1 DDRP.DDP0 0 Data Direction Register P Bit 0 RESERVED0058 0x0058 RESERVED RESERVED0059 0x0059 RESERVED RESERVED005A 0x005A RESERVED RESERVED005B 0x005B RESERVED RESERVED005C 0x005C RESERVED RESERVED005D 0x005D RESERVED RESERVED005E 0x005E RESERVED RESERVED005F 0x005F RESERVED ATDCTL0 0x0060 Reserved ATDCTL1 0x0061 Reserved ATDCTL2 0x0062 ATD Control Register 2 ATDCTL2.ADPU 7 ATD Disable ATDCTL2.AFFC 6 ATD Fast Flag Clear All ATDCTL2.AWAI 5 ATD Stop in Wait Mode ATDCTL2.ASCIE 1 ATD Sequence Complete Interrupt Enable ATDCTL2.ASCIF 0 ATD Sequence Complete Interrupt ATDCTL3 0x0063 ATD Control Register 3 ATDCTL3.FRZ1 1 Background Debug (Freeze) Enable 1 ATDCTL3.FRZ0 0 Background Debug (Freeze) Enable 0 ATDCTL4 0x0064 ATD Control Register 4 ATDCTL4.S10BM 7 ATD 10-bit Mode Control ATDCTL4.SMP1 6 Select Sample Time 1 ATDCTL4.SMP0 5 Select Sample Time 0 ATDCTL4.PRS4 4 Select Divide-By Factor for ATD P-Clock Prescaler 4 ATDCTL4.PRS3 3 Select Divide-By Factor for ATD P-Clock Prescaler 3 ATDCTL4.PRS2 2 Select Divide-By Factor for ATD P-Clock Prescaler 2 ATDCTL4.PRS1 1 Select Divide-By Factor for ATD P-Clock Prescaler 1 ATDCTL4.PRS0 0 Select Divide-By Factor for ATD P-Clock Prescaler 0 ATDCTL5 0x0065 ATD Control Register 5 ATDCTL5.S8CM 6 Select 8 Channel Mode ATDCTL5.SCAN 5 Enable Continuous Channel Scan ATDCTL5.MULT 4 Enable Multichannel Conversion ATDCTL5.CD 3 Channel Select for Conversion D ATDCTL5.CC 2 Channel Select for Conversion C ATDCTL5.CB 1 Channel Select for Conversion B ATDCTL5.CA 0 Channel Select for Conversion A ATDSTAT_1 0x0066 ATD Status Register 1 ATDSTAT_1.SCF 7 Sequence Complete Flag ATDSTAT_1.CC2 2 Conversion Counter for Current Sequence of Four or Eight Conversions 2 ATDSTAT_1.CC1 1 Conversion Counter for Current Sequence of Four or Eight Conversions 1 ATDSTAT_1.CC0 0 Conversion Counter for Current Sequence of Four or Eight Conversions 0 ATDSTAT_2 0x0067 ATD Status Register 2 ATDSTAT_2.CCF7 7 Conversion Complete Flag 7 ATDSTAT_2.CCF6 6 Conversion Complete Flag 6 ATDSTAT_2.CCF5 5 Conversion Complete Flag 5 ATDSTAT_2.CCF4 4 Conversion Complete Flag 4 ATDSTAT_2.CCF3 3 Conversion Complete Flag 3 ATDSTAT_2.CCF2 2 Conversion Complete Flag 2 ATDSTAT_2.CCF1 1 Conversion Complete Flag 1 ATDSTAT_2.CCF0 0 Conversion Complete Flag 0 ATDTSTH 0x0068 ATD Test Register High ATDTSTH.SAR9 7 SAR Data 9 ATDTSTH.SAR8 6 SAR Data 8 ATDTSTH.SAR7 5 SAR Data 7 ATDTSTH.SAR6 4 SAR Data 6 ATDTSTH.SAR5 3 SAR Data 5 ATDTSTH.SAR4 2 SAR Data 4 ATDTSTH.SAR3 1 SAR Data 3 ATDTSTH.SAR2 0 SAR Data 2 ATDTSTL 0x0069 ATD Test Register Low ATDTSTL.SAR1 7 SAR Data 1 ATDTSTL.SAR0 6 SAR Data 0 ATDTSTL.RST 5 Module Reset Bit ATDTSTL.TSTOUT 4 Multiplex Output of TST[3:0] (Factory Use) ATDTSTL.TST3 3 Test Bit 3 ATDTSTL.TST2 2 Test Bit 2 ATDTSTL.TST1 1 Test Bit 1 ATDTSTL.TST0 0 Test Bit 0 RESERVED006A 0x006A RESERVED RESERVED006B 0x006B RESERVED RESERVED006C 0x006C RESERVED RESERVED006D 0x006D RESERVED RESERVED006E 0x006E RESERVED PORTAD 0x006F Port AD Data Input Register PORTAD.PAD7 7 Port AD Data Input Bit 7 PORTAD.PAD6 6 Port AD Data Input Bit 6 PORTAD.PAD5 5 Port AD Data Input Bit 5 PORTAD.PAD4 4 Port AD Data Input Bit 4 PORTAD.PAD3 3 Port AD Data Input Bit 3 PORTAD.PAD2 2 Port AD Data Input Bit 2 PORTAD.PAD1 1 Port AD Data Input Bit 1 PORTAD.PAD0 0 Port AD Data Input Bit 0 ADR0H 0x0070 A/D Converter Result Register 0 High ADR0L 0x0071 A/D Converter Result Register 0 Low ADR1H 0x0072 A/D Converter Result Register 1 High ADR1L 0x0073 A/D Converter Result Register 1 Low ADR2H 0x0074 A/D Converter Result Register 2 High ADR2L 0x0075 A/D Converter Result Register 2 Low ADR3H 0x0076 A/D Converter Result Register 3 High ADR3L 0x0077 A/D Converter Result Register 3 Low ADR4H 0x0078 A/D Converter Result Register 4 High ADR4L 0x0079 A/D Converter Result Register 4 Low ADR5H 0x007A A/D Converter Result Register 5 High ADR5L 0x007B A/D Converter Result Register 5 Low ADR6H 0x007C A/D Converter Result Register 6 High ADR6L 0x007D A/D Converter Result Register 6 Low ADR7H 0x007E A/D Converter Result Register 7 High ADR7L 0x007F A/D Converter Result Register 7 Low TIOS 0x0080 Timer Input Capture/Output Compare Select TIOS.IOS7 7 Input Capture or Output Compare Channel Configuration 7 TIOS.IOS6 6 Input Capture or Output Compare Channel Configuration 6 TIOS.IOS5 5 Input Capture or Output Compare Channel Configuration 5 TIOS.IOS4 4 Input Capture or Output Compare Channel Configuration 4 TIOS.IOS3 3 Input Capture or Output Compare Channel Configuration 3 TIOS.IOS2 2 Input Capture or Output Compare Channel Configuration 2 TIOS.IOS1 1 Input Capture or Output Compare Channel Configuration 1 TIOS.IOS0 0 Input Capture or Output Compare Channel Configuration 0 CFORC 0x0081 Timer Compare Force Register CFORC.FOC7 7 Force Output Compare Action for Channel 7 CFORC.FOC6 6 Force Output Compare Action for Channel 6 CFORC.FOC5 5 Force Output Compare Action for Channel 5 CFORC.FOC4 4 Force Output Compare Action for Channel 4 CFORC.FOC3 3 Force Output Compare Action for Channel 3 CFORC.FOC2 2 Force Output Compare Action for Channel 2 CFORC.FOC1 1 Force Output Compare Action for Channel 1 CFORC.FOC0 0 Force Output Compare Action for Channel 0 OC7M 0x0082 Output Compare 7 Mask Register OC7M.OC7M7 7 OC7M.OC7M6 6 OC7M.OC7M5 5 OC7M.OC7M4 4 OC7M.OC7M3 3 OC7M.OC7M2 2 OC7M.OC7M1 1 OC7M.OC7M0 0 OC7D 0x0083 Output Compare 7 Data Register OC7D.OC7D7 7 OC7D.OC7D6 6 OC7D.OC7D5 5 OC7D.OC7D4 4 OC7D.OC7D3 3 OC7D.OC7D2 2 OC7D.OC7D1 1 OC7D.OC7D0 0 TCNTH 0x0084 Timer Count Register High TCNTL 0x0085 Timer Count Register Low TSCR 0x0086 Timer System Control Register TSCR.TEN 7 Timer Enable TSCR.TSWAI 6 Timer Stops While in Wait TSCR.TSBCK 5 Timer Stops While in Background Mode TSCR.TFFCA 4 Timer Fast Flag Clear All TQCR 0x0087 Reserved TCTL1 0x0088 Timer Control Register 1 TCTL1.OM7 7 Output Mode 7 TCTL1.OL7 6 Output Level 7 TCTL1.OM6 5 Output Mode 6 TCTL1.OL6 4 Output Level 6 TCTL1.OM5 3 Output Mode 5 TCTL1.OL5 2 Output Level 5 TCTL1.OM4 1 Output Mode 4 TCTL1.OL4 0 Output Level 4 TCTL2 0x0089 Timer Control Register 2 TCTL2.OM3 7 Output Mode 3 TCTL2.OL3 6 Output Level 3 TCTL2.OM2 5 Output Mode 2 TCTL2.OL2 4 Output Level 2 TCTL2.OM1 3 Output Mode 1 TCTL2.OL1 2 Output Level 1 TCTL2.OM0 1 Output Mode 0 TCTL2.OL0 0 Output Level 0 TCTL3 0x008A Timer Control Register 3 TCTL3.EDG7B 7 Input Capture edge control 7B TCTL3.EDG7A 6 Input Capture edge control 7A TCTL3.EDG6B 5 Input Capture edge control 6B TCTL3.EDG6A 4 Input Capture edge control 6A TCTL3.EDG5B 3 Input Capture edge control 5B TCTL3.EDG5A 2 Input Capture edge control 5A TCTL3.EDG4B 1 Input Capture edge control 4B TCTL3.EDG4A 0 Input Capture edge control 4A TCTL4 0x008B Timer Control Register 4 TCTL4.EDG3B 7 Input Capture edge control 3B TCTL4.EDG3A 6 Input Capture edge control 3A TCTL4.EDG2B 5 Input Capture edge control 2B TCTL4.EDG2A 4 Input Capture edge control 2A TCTL4.EDG1B 3 Input Capture edge control 1B TCTL4.EDG1A 2 Input Capture edge control 1A TCTL4.EDG0B 1 Input Capture edge control 0B TCTL4.EDG0A 0 Input Capture edge control 0A TMSK1 0x008C Timer Interrupt Mask 1 TMSK1.C7I 7 Input Capture/Output Compare 7 Interrupt enable TMSK1.C6I 6 Input Capture/Output Compare 6 Interrupt enable TMSK1.C5I 5 Input Capture/Output Compare 5 Interrupt enable TMSK1.C4I 4 Input Capture/Output Compare 4 Interrupt enable TMSK1.C3I 3 Input Capture/Output Compare 3 Interrupt enable TMSK1.C2I 2 Input Capture/Output Compare 2 Interrupt enable TMSK1.C1I 1 Input Capture/Output Compare 1 Interrupt enable TMSK1.C0I 0 Input Capture/Output Compare 0 Interrupt enable TMSK2 0x008D Timer Interrupt Mask 2 TMSK2.TOI 7 Timer Overflow Interrupt Enable TMSK2.PUPT 5 Timer Pull-Up Resistor Enable TMSK2.RDPT 4 Timer Drive Reduction TMSK2.TCRE 3 Timer Counter Reset Enable TMSK2.PR2 2 Timer Prescaler Select 2 TMSK2.PR1 1 Timer Prescaler Select 1 TMSK2.PR0 0 Timer Prescaler Select 0 TFLG1 0x008E Timer Interrupt Flag 1 TFLG1.C7F 7 Input Capture/Output Compare Channel 7 Flag TFLG1.C6F 6 Input Capture/Output Compare Channel 6 Flag TFLG1.C5F 5 Input Capture/Output Compare Channel 5 Flag TFLG1.C4F 4 Input Capture/Output Compare Channel 4 Flag TFLG1.C3F 3 Input Capture/Output Compare Channel 3 Flag TFLG1.C2F 2 Input Capture/Output Compare Channel 2 Flag TFLG1.C1F 1 Input Capture/Output Compare Channel 1 Flag TFLG1.C0F 0 Input Capture/Output Compare Channel 0 Flag TFLG2 0x008F Timer Interrupt Flag 2 TFLG2.TOF 7 Timer Overflow Flag TC0H 0x0090 Timer Input Capture/Output Compare Register 0 High TC0L 0x0091 Timer Input Capture/Output Compare Register 0 Low TC1H 0x0092 Timer Input Capture/Output Compare Register 1 High TC1L 0x0093 Timer Input Capture/Output Compare Register 1 Low TC2H 0x0094 Timer Input Capture/Output Compare Register 2 High TC2L 0x0095 Timer Input Capture/Output Compare Register 2 Low TC3H 0x0096 Timer Input Capture/Output Compare Register 3 High TC3L 0x0097 Timer Input Capture/Output Compare Register 3 Low TC4H 0x0098 Timer Input Capture/Output Compare Register 4 High TC4L 0x0099 Timer Input Capture/Output Compare Register 4 Low TC5H 0x009A Timer Input Capture/Output Compare Register 5 High TC5L 0x009B Timer Input Capture/Output Compare Register 5 Low TC6H 0x009C Timer Input Capture/Output Compare Register 6 High TC6L 0x009D Timer Input Capture/Output Compare Register 6 Low TC7H 0x009E Timer Input Capture/Output Compare Register 7 High TC7L 0x009F Timer Input Capture/Output Compare Register 7 Low PACTL 0x00A0 Pulse Accumulator Control Register PACTL.PAEN 6 Pulse Accumulator System Enable PACTL.PAMOD 5 Pulse Accumulator Mode PACTL.PEDGE 4 Pulse Accumulator Edge Control PACTL.CLK1 3 Clock Select Register 1 PACTL.CLK0 2 Clock Select Register 0 PACTL.PAOVI 1 Pulse Accumulator Overflow Interrupt Enable PACTL.PAI 0 Pulse Accumulator Input Interrupt Enable PAFLG 0x00A1 Pulse Accumulator Flag Register PAFLG.PAOVF 1 Pulse Accumulator Overflow Flag PAFLG.PAIF 0 Pulse Accumulator Input Edge Flag PACNTH 0x00A2 16-bit Pulse Accumulator Count Register High PACNTL 0x00A3 16-bit Pulse Accumulator Count Register Low RESERVED00A4 0x00A4 RESERVED RESERVED00A5 0x00A5 RESERVED RESERVED00A6 0x00A6 RESERVED RESERVED00A7 0x00A7 RESERVED RESERVED00A8 0x00A8 RESERVED RESERVED00A9 0x00A9 RESERVED RESERVED00AA 0x00AA RESERVED RESERVED00AB 0x00AB RESERVED RESERVED00AC 0x00AC RESERVED TIMTST 0x00AD Timer Test Register TIMTST.TCBYP 1 Timer Divider Chain Bypass TIMTST.PCBYP 0 Pulse Accumulator Divider Chain Bypass PORTT 0x00AE Port T Data Register PORTT.PT7 7 Port T Data Bit 7 PORTT.PT6 6 Port T Data Bit 6 PORTT.PT5 5 Port T Data Bit 5 PORTT.PT4 4 Port T Data Bit 4 PORTT.PT3 3 Port T Data Bit 3 PORTT.PT2 2 Port T Data Bit 2 PORTT.PT1 1 Port T Data Bit 1 PORTT.PT0 0 Port T Data Bit 0 DDRT 0x00AF Data Direction Register T DDRT.DDT7 7 Data Direction Register T Bit 7 DDRT.DDT6 6 Data Direction Register T Bit 6 DDRT.DDT5 5 Data Direction Register T Bit 5 DDRT.DDT4 4 Data Direction Register T Bit 4 DDRT.DDT3 3 Data Direction Register T Bit 3 DDRT.DDT2 2 Data Direction Register T Bit 2 DDRT.DDT1 1 Data Direction Register T Bit 1 DDRT.DDT0 0 Data Direction Register T Bit 0 RESERVED00B0 0x00B0 RESERVED RESERVED00B1 0x00B1 RESERVED RESERVED00B2 0x00B2 RESERVED RESERVED00B3 0x00B3 RESERVED RESERVED00B4 0x00B4 RESERVED RESERVED00B5 0x00B5 RESERVED RESERVED00B6 0x00B6 RESERVED RESERVED00B7 0x00B7 RESERVED RESERVED00B8 0x00B8 RESERVED RESERVED00B9 0x00B9 RESERVED RESERVED00BA 0x00BA RESERVED RESERVED00BB 0x00BB RESERVED RESERVED00BC 0x00BC RESERVED RESERVED00BD 0x00BD RESERVED RESERVED00BE 0x00BE RESERVED RESERVED00BF 0x00BF RESERVED SC0BDH 0x00C0 SCI Baud Rate Control Register High SC0BDH.BTST 7 Baud Register Test SC0BDH.BSPL 6 Baud Rate Counter Split SC0BDH.BRLD 5 Baud Rate Reload SC0BDH.SBR12 4 SC0BDH.SBR11 3 SC0BDH.SBR10 2 SC0BDH.SBR9 1 SC0BDH.SBR8 0 SC0BDL 0x00C1 SCI Baud Rate Control Register Low SC0BDL.SBR7 7 SC0BDL.SBR6 6 SC0BDL.SBR5 5 SC0BDL.SBR4 4 SC0BDL.SBR3 3 SC0BDL.SBR2 2 SC0BDL.SBR1 1 SC0BDL.SBR0 0 SC0CR1 0x00C2 SCI Control Register 1 SC0CR1.LOOPS 7 SCI LOOP Mode/Single Wire Mode Enable SC0CR1.WOMS 6 Wired-Or Mode for Serial Pins SC0CR1.RSRC 5 Receiver Source SC0CR1.M 4 Mode (select character format) SC0CR1.WAKE 3 Wakeup by Address Mark/Idle SC0CR1.ILT 2 Idle Line Type SC0CR1.PE 1 Parity Enable SC0CR1.PT 0 Parity Enable SC0CR2 0x00C3 SCI Control Register 2 SC0CR2.TIE 7 Transmit Interrupt Enable SC0CR2.TCIE 6 Transmit Complete Interrupt Enable SC0CR2.RIE 5 Receiver Interrupt Enable SC0CR2.ILIE 4 Idle Line Interrupt Enable SC0CR2.TE 3 Transmitter Enable SC0CR2.RE 2 Receiver Enable SC0CR2.RWU 1 Receiver Wake-Up Control SC0CR2.SBK 0 Send Break SC0SR1 0x00C4 SCI Status Register 1 SC0SR1.TDRE 7 Transmit Data Register Empty Flag SC0SR1.TC 6 Transmit Complete Flag SC0SR1.RDRF 5 Receive Data Register Full Flag SC0SR1.IDLE 4 Idle Line Detected Flag SC0SR1.OR 3 Overrun Error Flag SC0SR1.NF 2 Noise Error Flag SC0SR1.FE 1 Framing Error Flag SC0SR1.PF 0 Parity Error Flag SC0SR2 0x00C5 SCI Status Register 2 SC0SR2.RAF 0 Receiver Active Flag SC0DRH 0x00C6 SCI Data Register High SC0DRH.R8 7 Receive Bit 8 SC0DRH.T8 6 Transmit Bit 8 SC0DRL 0x00C7 SCI Data Register Low SC0DRL.R7_T7 7 Receive/Transmit Data Bit 7 SC0DRL.R6_T6 6 Receive/Transmit Data Bit 6 SC0DRL.R5_T5 5 Receive/Transmit Data Bit 5 SC0DRL.R4_T4 4 Receive/Transmit Data Bit 4 SC0DRL.R3_T3 3 Receive/Transmit Data Bit 3 SC0DRL.R2_T2 2 Receive/Transmit Data Bit 2 SC0DRL.R1_T1 1 Receive/Transmit Data Bit 1 SC0DRL.R0_T0 0 Receive/Transmit Data Bit 0 RESERVED00C8 0x00C8 RESERVED RESERVED00C9 0x00C9 RESERVED RESERVED00CA 0x00CA RESERVED RESERVED00CB 0x00CB RESERVED RESERVED00CC 0x00CC RESERVED RESERVED00CD 0x00CD RESERVED RESERVED00CE 0x00CE RESERVED RESERVED00CF 0x00CF RESERVED SP0CR1 0x00D0 SPI Control Register 1 SP0CR1.SPIE 7 SPI Interrupt Enable SP0CR1.SPE 6 SPI System Enable SP0CR1.SWOM 5 Port S Wired-OR Mode SP0CR1.MSTR 4 SPI Master/Slave Mode Select SP0CR1.CPOL 3 SPI Clock Polarity SP0CR1.CPHA 2 Clock Phase SP0CR1.SSOE 1 Slave Select Output Enable SP0CR1.LSBF 0 SPI LSB First enable SP0CR2 0x00D1 SPI Control Register 2 SP0CR2.SSWAI 1 SSI Stop in Wait Mode SP0CR2.SPC0 0 Serial Pin Control 0 SP0BR 0x00D2 SPI Baud Rate Register SP0BR.SPR2 2 SPI Clock (SCK) Rate Select Bit 2 SP0BR.SPR1 1 SPI Clock (SCK) Rate Select Bit 1 SP0BR.SPR0 0 SPI Clock (SCK) Rate Select Bit 0 SP0SR 0x00D3 SPI Status Register SP0SR.SPIF 7 SPI Interrupt Request SP0SR.WCOL 6 Write Collision Status Flag SP0SR.MODF 4 SPI Mode Error Interrupt Status Flag RESERVED00D4 0x00D4 RESERVED SP0DR 0x00D5 SPI Data Register PORTS 0x00D6 Port S Data Register PORTS.PS7 7 Port S Data Bit 7 PORTS.PS6 6 Port S Data Bit 6 PORTS.PS5 5 Port S Data Bit 5 PORTS.PS4 4 Port S Data Bit 4 PORTS.PS3 3 Port S Data Bit 3 PORTS.PS2 2 Port S Data Bit 2 PORTS.PS1 1 Port S Data Bit 1 PORTS.PS0 0 Port S Data Bit 0 DDRS 0x00D7 Data Direction Register S DDRS.DDS7 7 Data Direction Register S Bit 7 DDRS.DDS6 6 Data Direction Register S Bit 6 DDRS.DDS5 5 Data Direction Register S Bit 5 DDRS.DDS4 4 Data Direction Register S Bit 4 DDRS.DDS3 3 Data Direction Register S Bit 3 DDRS.DDS2 2 Data Direction Register S Bit 2 DDRS.DDS1 1 Data Direction Register S Bit 1 DDRS.DDS0 0 Data Direction Register S Bit 0 RESERVED00D8 0x00D8 RESERVED RESERVED00D9 0x00D9 RESERVED RESERVED00DA 0x00DA RESERVED PURDS 0x00DB Pullup and Reduced Drive for Port S PURDS.RDPS2 6 Reduce Drive of PS[7:4] PURDS.RDPS1 5 Reduce Drive of PS[3:2] PURDS.RDPS0 4 Reduce Drive of PS[1:0] PURDS.PUPS2 2 Pull-Up Port S Enable PS[7:4] PURDS.PUPS1 1 Pull-Up Port S Enable PS[3:2] PURDS.PUPS0 0 Pull-Up Port S Enable PS[1:0] RESERVED00DC 0x00DC RESERVED RESERVED00DD 0x00DD RESERVED RESERVED00DE 0x00DE RESERVED RESERVED00DF 0x00DF RESERVED SLOW 0x00E0 Slow Mode Divider Register SLOW.SLDV2 2 Slow Mode Divisor Selector Bit 2 SLOW.SLDV1 1 Slow Mode Divisor Selector Bit 1 SLOW.SLDV0 0 Slow Mode Divisor Selector Bit 0 ;RESERVED00E0 0x00E0 RESERVED RESERVED00E1 0x00E1 RESERVED RESERVED00E2 0x00E2 RESERVED RESERVED00E3 0x00E3 RESERVED RESERVED00E4 0x00E4 RESERVED RESERVED00E5 0x00E5 RESERVED RESERVED00E6 0x00E6 RESERVED RESERVED00E7 0x00E7 RESERVED RESERVED00E8 0x00E8 RESERVED RESERVED00E9 0x00E9 RESERVED RESERVED00EA 0x00EA RESERVED RESERVED00EB 0x00EB RESERVED RESERVED00EC 0x00EC RESERVED RESERVED00ED 0x00ED RESERVED RESERVED00EE 0x00EE RESERVED RESERVED00EF 0x00EF RESERVED EEMCR 0x00F0 EEPROM Module Configuration EEMCR.NOBDML 7 Background Debug Mode Lockout Disable EEMCR.NOSHB 6 SHADOW Byte Disable EEMCR.EESWAI 2 EEPROM Stops in Wait Mode EEMCR.PROTLCK 1 Block Protect Write Lock EEMCR.EERC 0 EEPROM Charge Pump Clock EEPROT 0x00F1 EEPROM Block Protect EEPROT.SHPROT 7 SHADOW Byte Protection EEPROT.BPROT4 4 EEPROM Block Protection 4 EEPROT.BPROT3 3 EEPROM Block Protection 3 EEPROT.BPROT2 2 EEPROM Block Protection 2 EEPROT.BPROT1 1 EEPROM Block Protection 1 EEPROT.BPROT0 0 EEPROM Block Protection 0 EETST 0x00F2 EEPROM Test EETST.EEODD 7 Odd Row Programming EETST.EEVEN 6 Even Row Programming EETST.MARG 5 Program and Erase Voltage Margin Test Enable EETST.EECPD 4 Charge Pump Disable EETST.EECPRD 3 Charge Pump Ramp Disable EETST.EECPM 1 Charge Pump Monitor Enable EEPROG 0x00F3 EEPROM Control EEPROG.BULKP 7 Bulk Erase Protection EEPROG.BYTE 4 Byte and Aligned Word Erase EEPROG.ROW 3 Row or Bulk Erase (when BYTE = 0) EEPROG.ERASE 2 Erase Control EEPROG.EELAT 1 EEPROM Latch Control EEPROG.EEPGM 0 Program and Erase Enable FEELCK 0x00F4 Flash EEPROM Lock Control Register FEELCK.LOCK 0 Lock Register Bit FEEMCR 0x00F5 Flash EEPROM Module Configuration Register FEEMCR.BOOTP 0 Boot Protect FEETST 0x00F6 Flash EEPROM Module Test Register FEETST.FSTE 7 Stress Test Enable FEETST.GADR 6 Gate/Drain Stress Test Select FEETST.HVT 5 Stress Test High Voltage Status FEETST.FENLV 4 Enable Low Voltage FEETST.FDISVFP 3 Disable Status VFP Voltage Lock FEETST.VTCK 2 VT Check Test Enable FEETST.STRE 1 Spare Test Row Enable FEETST.MWPR 0 Multiple Word Programming FEECTL 0x00F7 Flash EEPROM Control Register FEECTL.FEESWAI 4 Flash EEPROM Stop in Wait Control FEECTL.SVFP 3 Status VFP Voltage FEECTL.ERAS 2 Erase Control FEECTL.LAT 1 Latch Control FEECTL.ENPE 0 Enable Programming/Erase RESERVED00F8 0x00F8 RESERVED RESERVED00F9 0x00F9 RESERVED RESERVED00FA 0x00FA RESERVED RESERVED00FB 0x00FB RESERVED RESERVED00FC 0x00FC RESERVED RESERVED00FD 0x00FD RESERVED RESERVED00FE 0x00FE RESERVED RESERVED00FF 0x00FF RESERVED MCR 0x0100 Module Configuration Register MCR.SFTRES 7 Soft Reset MCR.MASTER 6 Master Select MCR.ALARM 5 Master Alarm Pulses MCR.SLPRQ 4 Sleep request, enter Low Power Module Sleep Mode MCR.SLPACK 3 Sleep Acknowledge MCR.WPULSE 2 Wakeup Pulses MCR.SSWAI 1 Serial Bus Interface Stops in Wait Mode FSIZR 0x0101 FIFO Size Register FSIZR.FSIZ4 4 FIFO Size Bit 4 FSIZR.FSIZ3 3 FIFO Size Bit 3 FSIZR.FSIZ2 2 FIFO Size Bit 2 FSIZR.FSIZ1 1 FIFO Size Bit 1 FSIZR.FSIZ0 0 FIFO Size Bit 0 TCR1 0x0102 Time Configuration Register 1 TCR1.TWX0T7 7 TCR1.TWX0T6 6 TCR1.TWX0T5 5 TCR1.TWX0T4 4 TCR1.TWX0T3 3 TCR1.TWX0T2 2 TCR1.TWX0T1 1 TCR1.TWX0T0 0 TCR2 0x0103 Time Configuration Register 2 TCR2.TWX0R7 7 TCR2.TWX0R6 6 TCR2.TWX0R5 5 TCR2.TWX0R4 4 TCR2.TWX0R3 3 TCR2.TWX0R2 2 TCR2.TWX0R1 1 TCR2.TWX0R0 0 TCR3 0x0104 Time Configuration Register 3 TCR3.TWXD7 7 TCR3.TWXD6 6 TCR3.TWXD5 5 TCR3.TWXD4 4 TCR3.TWXD3 3 TCR3.TWXD2 2 TCR3.TWXD1 1 TCR3.TWXD0 0 RESERVED0105 0x0105 RESERVED RISR 0x0106 Receive Interrupt Status Register RISR.RCVFIF 7 Receive FIFO Not Empty Interrupt Flag RISR.RXIF 6 Receive Interrupt Flag RISR.SYNAIF 5 Synchronization Pulse ALARM Interrupt Flag RISR.SYNNIF 4 Synchronization Pulse NORMAL Interrupt Flag RISR.OPTDF 0 Optical Diagnosis Flag GISR 0x0107 General Interrupt Status Register GISR.TXIF 7 Transmit Interrupt Flag GISR.OVRNIF 6 Receive FIFO Overrun Interrupt Flag GISR.ERRIF 5 Message Format Error (CRC, Frame) Interrupt Flag GISR.SYNEIF 4 SYNC Pulse Too Early Error Interrupt Flag GISR.SYNLIF 3 SYNC Pulse Lost Error Interrupt Flag GISR.ILLPIF 2 Illegal Pulse Error Interrupt Flag GISR.LOCKIF 1 Locking Error Interrupt Flag GISR.WAKEIF 0 WAKEUP Interrupt Flag RIER 0x0108 Receive Interrupt Enable Register RIER.RCVFIE 7 Receive FIFO Not Empty Interrupt Enable RIER.RXIE 6 Receive Interrupt Enable RIER.SYNAIE 5 Synchronization Pulse ALARM Interrupt Enable RIER.SYNNIE 4 Synchronization Pulse NORMAL Interrupt Enable GIER 0x0109 General Interrupt Enable Register GIER.TXIE 7 Transmit Interrupt Enable GIER.OVRNIE 6 Receive FIFO Overrun Interrupt Enable GIER.ERRIE 5 Message Format Error (CRC or Frame) Interrupt Enable GIER.SYNEIE 4 SYNC Pulse Too Early Error Interrupt Enable GIER.SYNLIE 3 SYNC Pulse Lost Error Interrupt Enable GIER.ILLPIE 2 Illegal Pulse Error Interrupt Enable GIER.LOCKIE 1 Locking Error Interrupt Enable GIER.WAKEIE 0 WAKEUP Interrupt Enable RIVEC 0x010A Receive Interrupt Vector Register RIVEC.RIVEC3 3 RIVEC.RIVEC2 2 RIVEC.RIVEC1 1 RIVEC.RIVEC0 0 TIVEC 0x010B Transmit Interrupt Vector Register TIVEC.TIVEC3 3 TIVEC.TIVEC2 2 TIVEC.TIVEC1 1 TIVEC.TIVEC0 0 FIDAC 0x010C FIFO Identifier Acceptance Register FIDAC.FIDAC7 7 FIDAC.FIDAC6 6 FIDAC.FIDAC5 5 FIDAC.FIDAC4 4 FIDAC.FIDAC3 3 FIDAC.FIDAC2 2 FIDAC.FIDAC1 1 FIDAC.FIDAC0 0 FIDMR 0x010D FIFO Identifier Mask Register FIDMR.FIDMR7 7 FIDMR.FIDMR6 6 FIDMR.FIDMR5 5 FIDMR.FIDMR4 4 FIDMR.FIDMR3 3 FIDMR.FIDMR2 2 FIDMR.FIDMR1 1 FIDMR.FIDMR0 0 MVR 0x010E Module Version Register MVR.MVR7 7 MVR.MVR6 6 MVR.MVR5 5 MVR.MVR4 4 MVR.MVR3 3 MVR.MVR2 2 MVR.MVR1 1 MVR.MVR0 0 SITEST 0x010F SITEST SITEST.TACC 0 PCTLSBI 0x0110 Byteflight Port SBI Control Register PCTLSBI.PERREN 4 Error Pulse Enable PCTLSBI.PROKEN 3 Reception OK Pulse Enable PCTLSBI.PSYNEN 2 Sync Pulse Enable PCTLSBI.PUESBI 1 Pull Up Enable Port SBI PCTLSBI.RDRSBI 0 Reduced Drive Port SBI PORTSBI 0x0111 Byteflight Port SBI Data Register PORTSBI.PSBI7 7 Port SBI Data Bit 7 PORTSBI.PSBI6 6 Port SBI Data Bit 6 PORTSBI.PSBI5 5 Port SBI Data Bit 5 PORTSBI.PSBI4 4 Port SBI Data Bit 4 PORTSBI.PSBI3 3 Port SBI Data Bit 3 PORTSBI.PSBI2 2 Port SBI Data Bit 2 PORTSBI.TX 1 PORTSBI.RX 0 DDRSBI 0x0112 Byteflight Port SBI Data Direction Register DDRSBI.DDRSBI7 7 Data Direction Port SBI Bit 7 DDRSBI.DDRSBI6 6 Data Direction Port SBI Bit 6 DDRSBI.DDRSBI5 5 Data Direction Port SBI Bit 5 DDRSBI.DDRSBI4 4 Data Direction Port SBI Bit 4 DDRSBI.DDRSBI3 3 Data Direction Port SBI Bit 3 DDRSBI.DDRSBI2 2 Data Direction Port SBI Bit 2 RESERVED0113 0x0113 RESERVED RESERVED0114 0x0114 RESERVED RESERVED0115 0x0115 RESERVED RESERVED0116 0x0116 RESERVED RESERVED0117 0x0117 RESERVED RESERVED0118 0x0118 RESERVED RESERVED0119 0x0119 RESERVED RESERVED011A 0x011A RESERVED RESERVED011B 0x011B RESERVED RESERVED011C 0x011C RESERVED RESERVED011D 0x011D RESERVED RESERVED011E 0x011E RESERVED RESERVED011F 0x011F RESERVED IDENTIFIER_1 0x0120 IDENTIFIER_1 IDENTIFIER_1.ID7 7 IDENTIFIER_1.ID6 6 IDENTIFIER_1.ID5 5 IDENTIFIER_1.ID4 4 IDENTIFIER_1.ID3 3 IDENTIFIER_1.ID2 2 IDENTIFIER_1.ID1 1 IDENTIFIER_1.ID0 0 DATA_LENGTH_1 0x0121 DATA_LENGTH_1 DATA_LENGTH_1.LEN3 3 DATA_LENGTH_1.LEN2 2 DATA_LENGTH_1.LEN1 1 DATA_LENGTH_1.LEN0 0 DATA0_1 0x0122 DATA0_1 DATA0_1.D7 7 DATA0_1.D6 6 DATA0_1.D5 5 DATA0_1.D4 4 DATA0_1.D3 3 DATA0_1.D2 2 DATA0_1.D1 1 DATA0_1.D0 0 DATA1_1 0x0123 DATA1_1 DATA1_1.D7 7 DATA1_1.D6 6 DATA1_1.D5 5 DATA1_1.D4 4 DATA1_1.D3 3 DATA1_1.D2 2 DATA1_1.D1 1 DATA1_1.D0 0 DATA2_1 0x0124 DATA2_1 DATA2_1.D7 7 DATA2_1.D6 6 DATA2_1.D5 5 DATA2_1.D4 4 DATA2_1.D3 3 DATA2_1.D2 2 DATA2_1.D1 1 DATA2_1.D0 0 DATA3_1 0x0125 DATA3_1 DATA3_1.D7 7 DATA3_1.D6 6 DATA3_1.D5 5 DATA3_1.D4 4 DATA3_1.D3 3 DATA3_1.D2 2 DATA3_1.D1 1 DATA3_1.D0 0 DATA4_1 0x0126 DATA4_1 DATA4_1.D7 7 DATA4_1.D6 6 DATA4_1.D5 5 DATA4_1.D4 4 DATA4_1.D3 3 DATA4_1.D2 2 DATA4_1.D1 1 DATA4_1.D0 0 DATA5_1 0x0127 DATA5_1 DATA5_1.D7 7 DATA5_1.D6 6 DATA5_1.D5 5 DATA5_1.D4 4 DATA5_1.D3 3 DATA5_1.D2 2 DATA5_1.D1 1 DATA5_1.D0 0 DATA6_1 0x0128 DATA6_1 DATA6_1.D7 7 DATA6_1.D6 6 DATA6_1.D5 5 DATA6_1.D4 4 DATA6_1.D3 3 DATA6_1.D2 2 DATA6_1.D1 1 DATA6_1.D0 0 DATA7_1 0x0129 DATA7_1 DATA7_1.D7 7 DATA7_1.D6 6 DATA7_1.D5 5 DATA7_1.D4 4 DATA7_1.D3 3 DATA7_1.D2 2 DATA7_1.D1 1 DATA7_1.D0 0 DATA8_1 0x012A DATA8_1 DATA8_1.D7 7 DATA8_1.D6 6 DATA8_1.D5 5 DATA8_1.D4 4 DATA8_1.D3 3 DATA8_1.D2 2 DATA8_1.D1 1 DATA8_1.D0 0 DATA9_1 0x012B DATA9_1 DATA9_1.D7 7 DATA9_1.D6 6 DATA9_1.D5 5 DATA9_1.D4 4 DATA9_1.D3 3 DATA9_1.D2 2 DATA9_1.D1 1 DATA9_1.D0 0 DATA10_1 0x012C DATA10_1 DATA10_1.D7 7 DATA10_1.D6 6 DATA10_1.D5 5 DATA10_1.D4 4 DATA10_1.D3 3 DATA10_1.D2 2 DATA10_1.D1 1 DATA10_1.D0 0 DATA11_1 0x012D DATA11_1 DATA11_1.D7 7 DATA11_1.D6 6 DATA11_1.D5 5 DATA11_1.D4 4 DATA11_1.D3 3 DATA11_1.D2 2 DATA11_1.D1 1 DATA11_1.D0 0 RESERVED012E 0x012E RESERVED RESERVED012F 0x012F RESERVED IDENTIFIER_2 0x0130 IDENTIFIER_2 IDENTIFIER_2.ID7 7 IDENTIFIER_2.ID6 6 IDENTIFIER_2.ID5 5 IDENTIFIER_2.ID4 4 IDENTIFIER_2.ID3 3 IDENTIFIER_2.ID2 2 IDENTIFIER_2.ID1 1 IDENTIFIER_2.ID0 0 DATA_LENGTH_2 0x0131 DATA_LENGTH_2 DATA_LENGTH_2.LEN3 3 DATA_LENGTH_2.LEN2 2 DATA_LENGTH_2.LEN1 1 DATA_LENGTH_2.LEN0 0 DATA0_2 0x0132 DATA0_2 DATA0_2.D7 7 DATA0_2.D6 6 DATA0_2.D5 5 DATA0_2.D4 4 DATA0_2.D3 3 DATA0_2.D2 2 DATA0_2.D1 1 DATA0_2.D0 0 DATA1_2 0x0133 DATA1_2 DATA1_2.D7 7 DATA1_2.D6 6 DATA1_2.D5 5 DATA1_2.D4 4 DATA1_2.D3 3 DATA1_2.D2 2 DATA1_2.D1 1 DATA1_2.D0 0 DATA2_2 0x0134 DATA2_2 DATA2_2.D7 7 DATA2_2.D6 6 DATA2_2.D5 5 DATA2_2.D4 4 DATA2_2.D3 3 DATA2_2.D2 2 DATA2_2.D1 1 DATA2_2.D0 0 DATA3_2 0x0135 DATA3_2 DATA3_2.D7 7 DATA3_2.D6 6 DATA3_2.D5 5 DATA3_2.D4 4 DATA3_2.D3 3 DATA3_2.D2 2 DATA3_2.D1 1 DATA3_2.D0 0 DATA4_2 0x0136 DATA4_2 DATA4_2.D7 7 DATA4_2.D6 6 DATA4_2.D5 5 DATA4_2.D4 4 DATA4_2.D3 3 DATA4_2.D2 2 DATA4_2.D1 1 DATA4_2.D0 0 DATA5_2 0x0137 DATA5_2 DATA5_2.D7 7 DATA5_2.D6 6 DATA5_2.D5 5 DATA5_2.D4 4 DATA5_2.D3 3 DATA5_2.D2 2 DATA5_2.D1 1 DATA5_2.D0 0 DATA6_2 0x0138 DATA6_2 DATA6_2.D7 7 DATA6_2.D6 6 DATA6_2.D5 5 DATA6_2.D4 4 DATA6_2.D3 3 DATA6_2.D2 2 DATA6_2.D1 1 DATA6_2.D0 0 DATA7_2 0x0139 DATA7_2 DATA7_2.D7 7 DATA7_2.D6 6 DATA7_2.D5 5 DATA7_2.D4 4 DATA7_2.D3 3 DATA7_2.D2 2 DATA7_2.D1 1 DATA7_2.D0 0 DATA8_2 0x013A DATA8_2 DATA8_2.D7 7 DATA8_2.D6 6 DATA8_2.D5 5 DATA8_2.D4 4 DATA8_2.D3 3 DATA8_2.D2 2 DATA8_2.D1 1 DATA8_2.D0 0 DATA9_2 0x013B DATA9_2 DATA9_2.D7 7 DATA9_2.D6 6 DATA9_2.D5 5 DATA9_2.D4 4 DATA9_2.D3 3 DATA9_2.D2 2 DATA9_2.D1 1 DATA9_2.D0 0 DATA10_2 0x013C DATA10_2 DATA10_2.D7 7 DATA10_2.D6 6 DATA10_2.D5 5 DATA10_2.D4 4 DATA10_2.D3 3 DATA10_2.D2 2 DATA10_2.D1 1 DATA10_2.D0 0 DATA11_2 0x013D DATA11_2 DATA11_2.D7 7 DATA11_2.D6 6 DATA11_2.D5 5 DATA11_2.D4 4 DATA11_2.D3 3 DATA11_2.D2 2 DATA11_2.D1 1 DATA11_2.D0 0 RESERVED012E 0x013E RESERVED RESERVED012F 0x013F RESERVED IDENTIFIER_3 0x0140 IDENTIFIER_3 IDENTIFIER_3.ID7 7 IDENTIFIER_3.ID6 6 IDENTIFIER_3.ID5 5 IDENTIFIER_3.ID4 4 IDENTIFIER_3.ID3 3 IDENTIFIER_3.ID2 2 IDENTIFIER_3.ID1 1 IDENTIFIER_3.ID0 0 DATA_LENGTH_3 0x0141 DATA_LENGTH_3 DATA_LENGTH_3.LEN3 3 DATA_LENGTH_3.LEN2 2 DATA_LENGTH_3.LEN1 1 DATA_LENGTH_3.LEN0 0 DATA0_3 0x0142 DATA0_3 DATA0_3.D7 7 DATA0_3.D6 6 DATA0_3.D5 5 DATA0_3.D4 4 DATA0_3.D3 3 DATA0_3.D2 2 DATA0_3.D1 1 DATA0_3.D0 0 DATA1_3 0x0143 DATA1_3 DATA1_3.D7 7 DATA1_3.D6 6 DATA1_3.D5 5 DATA1_3.D4 4 DATA1_3.D3 3 DATA1_3.D2 2 DATA1_3.D1 1 DATA1_3.D0 0 DATA2_3 0x0144 DATA2_3 DATA2_3.D7 7 DATA2_3.D6 6 DATA2_3.D5 5 DATA2_3.D4 4 DATA2_3.D3 3 DATA2_3.D2 2 DATA2_3.D1 1 DATA2_3.D0 0 DATA3_3 0x0145 DATA3_3 DATA3_3.D7 7 DATA3_3.D6 6 DATA3_3.D5 5 DATA3_3.D4 4 DATA3_3.D3 3 DATA3_3.D2 2 DATA3_3.D1 1 DATA3_3.D0 0 DATA4_3 0x0146 DATA4_3 DATA4_3.D7 7 DATA4_3.D6 6 DATA4_3.D5 5 DATA4_3.D4 4 DATA4_3.D3 3 DATA4_3.D2 2 DATA4_3.D1 1 DATA4_3.D0 0 DATA5_3 0x0147 DATA5_3 DATA5_3.D7 7 DATA5_3.D6 6 DATA5_3.D5 5 DATA5_3.D4 4 DATA5_3.D3 3 DATA5_3.D2 2 DATA5_3.D1 1 DATA5_3.D0 0 DATA6_3 0x0148 DATA6_3 DATA6_3.D7 7 DATA6_3.D6 6 DATA6_3.D5 5 DATA6_3.D4 4 DATA6_3.D3 3 DATA6_3.D2 2 DATA6_3.D1 1 DATA6_3.D0 0 DATA7_3 0x0149 DATA7_3 DATA7_3.D7 7 DATA7_3.D6 6 DATA7_3.D5 5 DATA7_3.D4 4 DATA7_3.D3 3 DATA7_3.D2 2 DATA7_3.D1 1 DATA7_3.D0 0 DATA8_3 0x014A DATA8_3 DATA8_3.D7 7 DATA8_3.D6 6 DATA8_3.D5 5 DATA8_3.D4 4 DATA8_3.D3 3 DATA8_3.D2 2 DATA8_3.D1 1 DATA8_3.D0 0 DATA9_3 0x014B DATA9_3 DATA9_3.D7 7 DATA9_3.D6 6 DATA9_3.D5 5 DATA9_3.D4 4 DATA9_3.D3 3 DATA9_3.D2 2 DATA9_3.D1 1 DATA9_3.D0 0 DATA10_3 0x014C DATA10_3 DATA10_3.D7 7 DATA10_3.D6 6 DATA10_3.D5 5 DATA10_3.D4 4 DATA10_3.D3 3 DATA10_3.D2 2 DATA10_3.D1 1 DATA10_3.D0 0 DATA11_3 0x014D DATA11_3 DATA11_3.D7 7 DATA11_3.D6 6 DATA11_3.D5 5 DATA11_3.D4 4 DATA11_3.D3 3 DATA11_3.D2 2 DATA11_3.D1 1 DATA11_3.D0 0 RESERVED012E 0x014E RESERVED RESERVED012F 0x014F RESERVED BUFCTL0 0x0150 Message Buffer Control Register 0 BUFCTL0.IFLG 7 Interrupt Status Flag BUFCTL0.IENA 6 Interrupt Enable Bit BUFCTL0.LOCK 5 Message Buffer Lock BUFCTL0.CFG 0 Message Buffer Configuration Bit BUFCTL1 0x0151 Message Buffer Control Register 1 BUFCTL1.IFLG 7 Interrupt Status Flag BUFCTL1.IENA 6 Interrupt Enable Bit BUFCTL1.LOCK 5 Message Buffer Lock BUFCTL1.CFG 0 Message Buffer Configuration Bit BUFCTL2 0x0152 Message Buffer Control Register 2 BUFCTL2.IFLG 7 Interrupt Status Flag BUFCTL2.IENA 6 Interrupt Enable Bit BUFCTL2.LOCK 5 Message Buffer Lock BUFCTL2.CFG 0 Message Buffer Configuration Bit BUFCTL3 0x0153 Message Buffer Control Register 3 BUFCTL3.IFLG 7 Interrupt Status Flag BUFCTL3.IENA 6 Interrupt Enable Bit BUFCTL3.LOCK 5 Message Buffer Lock BUFCTL3.CFG 0 Message Buffer Configuration Bit BUFCTL4 0x0154 Message Buffer Control Register 4 BUFCTL4.IFLG 7 Interrupt Status Flag BUFCTL4.IENA 6 Interrupt Enable Bit BUFCTL4.LOCK 5 Message Buffer Lock BUFCTL4.CFG 0 Message Buffer Configuration Bit BUFCTL5 0x0155 Message Buffer Control Register 5 BUFCTL5.IFLG 7 Interrupt Status Flag BUFCTL5.IENA 6 Interrupt Enable Bit BUFCTL5.LOCK 5 Message Buffer Lock BUFCTL5.CFG 0 Message Buffer Configuration Bit BUFCTL6 0x0156 Message Buffer Control Register 6 BUFCTL6.IFLG 7 Interrupt Status Flag BUFCTL6.IENA 6 Interrupt Enable Bit BUFCTL6.LOCK 5 Message Buffer Lock BUFCTL6.CFG 0 Message Buffer Configuration Bit BUFCTL7 0x0157 Message Buffer Control Register 7 BUFCTL7.IFLG 7 Interrupt Status Flag BUFCTL7.IENA 6 Interrupt Enable Bit BUFCTL7.LOCK 5 Message Buffer Lock BUFCTL7.CFG 0 Message Buffer Configuration Bit BUFCTL8 0x0158 Message Buffer Control Register 8 BUFCTL8.IFLG 7 Interrupt Status Flag BUFCTL8.IENA 6 Interrupt Enable Bit BUFCTL8.LOCK 5 Message Buffer Lock BUFCTL8.CFG 0 Message Buffer Configuration Bit BUFCTL9 0x0159 Message Buffer Control Register 9 BUFCTL9.IFLG 7 Interrupt Status Flag BUFCTL9.IENA 6 Interrupt Enable Bit BUFCTL9.LOCK 5 Message Buffer Lock BUFCTL9.CFG 0 Message Buffer Configuration Bit BUFCTL10 0x015A Message Buffer Control Register 10 BUFCTL10.IFLG 7 Interrupt Status Flag BUFCTL10.IENA 6 Interrupt Enable Bit BUFCTL10.LOCK 5 Message Buffer Lock BUFCTL10.CFG 0 Message Buffer Configuration Bit BUFCTL11 0x015B Message Buffer Control Register 11 BUFCTL11.IFLG 7 Interrupt Status Flag BUFCTL11.IENA 6 Interrupt Enable Bit BUFCTL11.LOCK 5 Message Buffer Lock BUFCTL11.CFG 0 Message Buffer Configuration Bit BUFCTL12 0x015C Message Buffer Control Register 12 BUFCTL12.IFLG 7 Interrupt Status Flag BUFCTL12.IENA 6 Interrupt Enable Bit BUFCTL12.LOCK 5 Message Buffer Lock BUFCTL12.CFG 0 Message Buffer Configuration Bit BUFCTL13 0x015D Message Buffer Control Register 13 BUFCTL13.IFLG 7 Interrupt Status Flag BUFCTL13.IENA 6 Interrupt Enable Bit BUFCTL13.LOCK 5 Message Buffer Lock BUFCTL13.CFG 0 Message Buffer Configuration Bit BUFCTL14 0x015E Message Buffer Control Register 14 BUFCTL14.IFLG 7 Interrupt Status Flag BUFCTL14.IENA 6 Interrupt Enable Bit BUFCTL14.LOCK 5 Message Buffer Lock BUFCTL14.CFG 0 Message Buffer Configuration Bit BUFCTL15 0x015F Message Buffer Control Register 15 BUFCTL15.IFLG 7 Interrupt Status Flag BUFCTL15.IENA 6 Interrupt Enable Bit BUFCTL15.LOCK 5 Message Buffer Lock BUFCTL15.CFG 0 Message Buffer Configuration Bit .68HC12BC32 ; ; M68HC12B.pdf ; MEMORY MAP area DATA FSR 0x0000:0x0200 REGISTERS 512 BYTES area BSS RESERVED 0x0200:0x0800 area DATA RAM 0x0800:0x0C00 1-KBYTE RAM area BSS RESERVED 0x0C00:0x0D00 area DATA EEPROM 0x0D00:0x1000 768 BYTES EEPROM area BSS RESERVED 0x1000:0x8000 area DATA EEPROM_ROM 0x8000:0xFFC0 FLASH EEPROM/ROM area DATA USER_VEC 0xFFC0:0x10000 ; Interrupt and reset vector assignments interrupt __RESET 0xFFFE Processor reset interrupt CME_FCME 0xFFFC COP clock monitor fail reset interrupt COP_FR 0xFFFA COP failure reset interrupt UIT 0xFFF8 Unimplemented instruction trap interrupt SWI 0xFFF6 SWI interrupt XIRQ 0xFFF4 XIRQ interrupt IRQEN 0xFFF2 IRQ interrupt RTIE 0xFFF0 Real-time interrupt interrupt C0I 0xFFEE Timer channel 0 interrupt C1I 0xFFEC Timer channel 1 interrupt C2I 0xFFEA Timer channel 2 interrupt C3I 0xFFE8 Timer channel 3 interrupt C4I 0xFFE6 Timer channel 4 interrupt C5I 0xFFE4 Timer channel 5 interrupt C6I 0xFFE2 Timer channel 6 interrupt C7I 0xFFE0 Timer channel 7 interrupt TOI 0xFFDE Timer overflow interrupt PAOVI 0xFFDC Pulse accumulator overflow interrupt PAI 0xFFDA Pulse accumulator input edge interrupt SPIE 0xFFD8 SPI serial transfer complete interrupt TIE_TCIE_RIE_ILIE 0xFFD6 SCI 0 interrupt ASCIE 0xFFD2 ATD interrupt WUPIE 0xFFD0 MSCAN wakeup interrupt MSCAN_ER 0xFFC8 MSCAN errors interrupt RXFIE 0xFFC6 MSCAN receive interrupt TXEIE 0xFFC4 MSCAN transmit ; INPUT/ OUTPUT PORTS PORTA 0x0000 Port A Data Register PORTA.PA7 7 Port A Data Bit 7 PORTA.PA6 6 Port A Data Bit 6 PORTA.PA5 5 Port A Data Bit 5 PORTA.PA4 4 Port A Data Bit 4 PORTA.PA3 3 Port A Data Bit 3 PORTA.PA2 2 Port A Data Bit 2 PORTA.PA1 1 Port A Data Bit 1 PORTA.PA0 0 Port A Data Bit 0 PORTB 0x0001 Port B Data Register PORTB.PB7 7 Port B Data Bit 7 PORTB.PB6 6 Port B Data Bit 6 PORTB.PB5 5 Port B Data Bit 5 PORTB.PB4 4 Port B Data Bit 4 PORTB.PB3 3 Port B Data Bit 3 PORTB.PB2 2 Port B Data Bit 2 PORTB.PB1 1 Port B Data Bit 1 PORTB.PB0 0 Port B Data Bit 0 DDRA 0x0002 Data Direction Register A DDRA.DDA7 7 Data Direction Register A Bit 7 DDRA.DDA6 6 Data Direction Register A Bit 6 DDRA.DDA5 5 Data Direction Register A Bit 5 DDRA.DDA4 4 Data Direction Register A Bit 4 DDRA.DDA3 3 Data Direction Register A Bit 3 DDRA.DDA2 2 Data Direction Register A Bit 2 DDRA.DDA1 1 Data Direction Register A Bit 1 DDRA.DDA0 0 Data Direction Register A Bit 0 DDRB 0x0003 Data Direction Register B DDRB.DDB7 7 Data Direction Register B Bit 7 DDRB.DDB6 6 Data Direction Register B Bit 6 DDRB.DDB5 5 Data Direction Register B Bit 5 DDRB.DDB4 4 Data Direction Register B Bit 4 DDRB.DDB3 3 Data Direction Register B Bit 3 DDRB.DDB2 2 Data Direction Register B Bit 2 DDRB.DDB1 1 Data Direction Register B Bit 1 DDRB.DDB0 0 Data Direction Register B Bit 0 RESERVED00004 0x0004 RESERVED RESERVED00005 0x0005 RESERVED RESERVED00006 0x0006 RESERVED RESERVED00007 0x0007 RESERVED PORTE 0x0008 Port E Data Register PORTE.PE7 7 Port E Data Bit 7 PORTE.PE6 6 Port E Data Bit 6 PORTE.PE5 5 Port E Data Bit 5 PORTE.PE4 4 Port E Data Bit 4 PORTE.PE3 3 Port E Data Bit 3 PORTE.PE2 2 Port E Data Bit 2 PORTE.PE1 1 Port E Data Bit 1 PORTE.PE0 0 Port E Data Bit 0 DDRE 0x0009 Data Direction Register E DDRE.DDE7 7 Data Direction Register E Bit 7 DDRE.DDE6 6 Data Direction Register E Bit 6 DDRE.DDE5 5 Data Direction Register E Bit 5 DDRE.DDE4 4 Data Direction Register E Bit 4 DDRE.DDE3 3 Data Direction Register E Bit 3 DDRE.DDE2 2 Data Direction Register E Bit 2 DDRE.DDE1 1 Data Direction Register E Bit 1 DDRE.DDE0 0 Data Direction Register E Bit 0 PEAR 0x000A Port E Assignment Register PEAR.NDBE 7 No Data Bus Enable Bit PEAR.CGMTE 6 CGM Test Output Enable PEAR.PIPOE 5 Pipe Signal Output Enable Bit PEAR.NECLK 4 No External E Clock Bit PEAR.LSTRE 3 Low Strobe (LSTRB) Enable Bit PEAR.RDWE 2 Read/Write Enable Bit MODE 0x000B Mode Register MODE.SMODN 7 Mode Select Special MODE.MODB 6 Mode Select Special B Bit MODE.MODA 5 Mode Select Special A Bit MODE.ESTR 4 E Clock Stretch Enable Bit MODE.IVIS 3 Internal Visibility Bit MODE.EBSWAI 2 External Bus Module Stop in Wait Bit MODE.EME 0 Emulate Port E Bit PUCR 0x000C Pullup Control Register PUCR.PUPE 4 Pullup Port E Enable Bit PUCR.PUPB 1 Pullup Port B Enable Bit PUCR.PUPA 0 Pullup Port A Enable Bit RDRIV 0x000D Reduced Drive Register RDRIV.RDPE 3 Reduced Drive of Port E Bit RDRIV.RDPB 1 Reduced Drive of Port B Bit RDRIV.RDPA 0 Reduced Drive of Port A Bit RESERVED000E 0x000E RESERVED RESERVED000F 0x000F RESERVED INITRM 0x0010 RAM Initialization Register INITRM.RAM15 7 RAM Position Bit 15 INITRM.RAM14 6 RAM Position Bit 14 INITRM.RAM13 5 RAM Position Bit 13 INITRM.RAM12 4 RAM Position Bit 12 INITRM.RAM11 3 RAM Position Bit 11 INITRG 0x0011 Register Initialization Register INITRG.REG15 7 Register Position Bit 15 INITRG.REG14 6 Register Position Bit 14 INITRG.REG13 5 Register Position Bit 13 INITRG.REG12 4 Register Position Bit 12 INITRG.REG11 3 Register Position Bit 11 INITRG.MMSWAI 0 Memory Mapping Interface Stop in Wait Control Bit INITEE 0x0012 EEPROM Initialization Register INITEE.EE15 7 Internal EEPROM Position Bit 15 INITEE.EE14 6 Internal EEPROM Position Bit 14 INITEE.EE13 5 Internal EEPROM Position Bit 13 INITEE.EE12 4 Internal EEPROM Position Bit 12 INITEE.EEON 0 EEPROM On Bit MISC 0x0013 Miscellaneous Mapping Control Register MISC.NDRF 6 Narrow Data Bus for Register-Following Map Bit MISC.RFSTR1 5 Register-Following Stretch Bit 1 MISC.RFSTR0 4 Register-Following Stretch Bit 0 MISC.EXSTR1 3 External Access Stretch Bit 1 MISC.EXSTR0 2 External Access Stretch Bit 0 MISC.MAPROM 1 FLASH EEPROM/ROM Map Bit MISC.ROMON 0 FLASH EEPROM/ROM Enable Bit RTICTL 0x0014 Real-Time Interrupt Control Register RTICTL.RTIE 7 Real-Time Interrupt Enable Bit RTICTL.RSWAI 6 RTI and COP Stop While in Wait Bit RTICTL.RSBCK 5 RTI and COP Stop While in Background Debug Mode Bit RTICTL.RTBYP 3 Real-Time Interrupt Divider Chain Bypass Bit RTICTL.RTR2 2 Real-Time Interrupt Rate Select Bit 2 RTICTL.RTR1 1 Real-Time Interrupt Rate Select Bit 1 RTICTL.RTR0 0 Real-Time Interrupt Rate Select Bit 0 RTIFLG 0x0015 Real-Time Interrupt Flag Register RTIFLG.RTIF 7 Real-Time Interrupt Flag Bit COPCTL 0x0016 COP Control Register COPCTL.CME 7 Clock Monitor Enable Bit COPCTL.FCME 6 Force Clock Monitor Enable Bit COPCTL.FCM 5 Force Clock Monitor Reset Bit COPCTL.FCOP 4 Force COP Watchdog Reset Bit COPCTL.DISR 3 Disable Resets from COP Watchdog and Clock Monitor Bit COPCTL.CR2 2 COP Watchdog Timer Rate Select Bit 2 COPCTL.CR1 1 COP Watchdog Timer Rate Select Bit 1 COPCTL.CR0 0 COP Watchdog Timer Rate Select Bit 0 COPRST 0x0017 Arm/Reset COP Timer Register RESERVED0018 0x0018 RESERVED RESERVED0019 0x0019 RESERVED RESERVED001A 0x001A RESERVED RESERVED001B 0x001B RESERVED RESERVED001C 0x001C RESERVED RESERVED001D 0x001D RESERVED INTCR 0x001E Interrupt Control Register INTCR.IRQE 7 IRQ Edge-Sensitive Only Bit INTCR.IRQEN 6 External IRQ Enable Bit INTCR.DLY 5 Oscillator Startup Delay on Exit from Stop Mode Bit HPRIO 0x001F Highest Priority I Interrupt Register HPRIO.PSEL5 5 HPRIO.PSEL4 4 HPRIO.PSEL3 3 HPRIO.PSEL2 2 HPRIO.PSEL1 1 BRKCT0 0x0020 Breakpoint Control Register 0 BRKCT0.BKEN1 7 Breakpoint Mode Enable Bit 1 BRKCT0.BKEN0 6 Breakpoint Mode Enable Bit 0 BRKCT0.BKPM 5 Break on Program Addresses BRKCT0.BK1ALE 3 Breakpoint 1 Range Control Bit BRKCT0.BK0ALE 2 Breakpoint 0 Range Control Bit BRKCT1 0x0021 Breakpoint Control Register 1 BRKCT1.BKDBE 6 Enable Data Bus Bit BRKCT1.BKMBH 5 Breakpoint Mask High Bit BRKCT1.BKMBL 4 Breakpoint Mask Low Bit BRKCT1.BK1RWE 3 R/W Compare Enable Bit BRKCT1.BK1RW 2 R/W Compare Value Bit BRKCT1.BK0RWE 1 R/W Compare Enable Bit BRKCT1.BK0RW 0 R/W Compare Value Bit BRKAH 0x0022 Breakpoint Address Register High BRKAL 0x0023 Breakpoint Address Register Low BRKDH 0x0024 Breakpoint Data Register High BRKDL 0x0025 Breakpoint Data Register Low RESERVED0026 0x0026 RESERVED RESERVED0027 0x0027 RESERVED RESERVED0028 0x0028 RESERVED RESERVED0029 0x0029 RESERVED RESERVED002A 0x002A RESERVED RESERVED002B 0x002B RESERVED RESERVED002C 0x002C RESERVED RESERVED002D 0x002D RESERVED RESERVED002E 0x002E RESERVED RESERVED002F 0x002F RESERVED RESERVED0030 0x0030 RESERVED RESERVED0031 0x0031 RESERVED RESERVED0032 0x0032 RESERVED RESERVED0033 0x0033 RESERVED RESERVED0034 0x0034 RESERVED RESERVED0035 0x0035 RESERVED RESERVED0036 0x0036 RESERVED RESERVED0037 0x0037 RESERVED RESERVED0038 0x0038 RESERVED RESERVED0039 0x0039 RESERVED RESERVED003A 0x003A RESERVED RESERVED003B 0x003B RESERVED RESERVED003C 0x003C RESERVED RESERVED003D 0x003D RESERVED RESERVED003E 0x003E RESERVED RESERVED003F 0x003F RESERVED PWCLK 0x0040 PWM Clocks and Concatenate Register PWCLK.CON23 7 Concatenate PWM Channels 2 and 3 Bit PWCLK.CON01 6 Concatenate PWM Channels 0 and 1 Bit PWCLK.PCKA2 5 Prescaler for Clock A Bit 2 PWCLK.PCKA1 4 Prescaler for Clock A Bit 1 PWCLK.PCKA0 3 Prescaler for Clock A Bit 0 PWCLK.PCKB2 2 Prescaler for Clock B Bit 2 PWCLK.PCKB1 1 Prescaler for Clock B Bit 1 PWCLK.PCKB0 0 Prescaler for Clock B Bit 0 PWPOL 0x0041 PWM Clock Select and Polarity Register PWPOL.PCLK3 7 PWM Channel 3 Clock Select Bit PWPOL.PCLK2 6 PWM Channel 2 Clock Select Bit PWPOL.PCLK1 5 PWM Channel 1 Clock Select Bit PWPOL.PCLK0 4 PWM Channel 0 Clock Select Bit PWPOL.PPOL3 3 PWM Channel 3 Polarity Bit PWPOL.PPOL2 2 PWM Channel 2 Polarity Bit PWPOL.PPOL1 1 PWM Channel 1 Polarity Bit PWPOL.PPOL0 0 PWM Channel 0 Polarity Bit PWEN 0x0042 PWM Enable Register PWEN.PWEN3 3 PWM Channel 3 Enable Bit PWEN.PWEN2 2 PWM Channel 2 Enable Bit PWEN.PWEN1 1 PWM Channel 1 Enable Bit PWEN.PWEN0 0 PWM Channel 0 Enable Bit PWPRES 0x0043 PWM Prescaler Counter Register PWSCAL0 0x0044 PWM Scale Register 0 PWSCNT0 0x0045 PWM Scale Counter Register 0 PWSCAL1 0x0046 PWM Scale Register 1 PWSCNT1 0x0047 PWM Scale Counter Register 1 PWCNT0 0x0048 PWM Channel Counter Register 0 PWCNT1 0x0049 PWM Channel Counter Register 1 PWCNT2 0x004A PWM Channel Counter Register 2 PWCNT3 0x004B PWM Channel Counter Register 3 PWPER0 0x004C PWM Channel Period Register 0 PWPER1 0x004D PWM Channel Period Register 1 PWPER2 0x004E PWM Channel Period Register 2 PWPER3 0x004F PWM Channel Period Register 3 PWDTY0 0x0050 PWM Channel Duty Register 0 PWDTY1 0x0051 PWM Channel Duty Register 1 PWDTY2 0x0052 PWM Channel Duty Register 2 PWDTY3 0x0053 PWM Channel Duty Register 3 PWCTL 0x0054 PWM Control Register PWCTL.PSWAI 4 PWM Halts While in Wait Mode Bit PWCTL.CENTR 3 Center-Aligned Output Mode Bit PWCTL.RDPP 2 Reduced Drive of Port P Bit PWCTL.PUPP 1 Pullup Port P Enable Bit PWCTL.PSBCK 0 PWM Stops While in Background Mode Bit PWTST 0x0055 PWM Special Mode Register PWTST.DISCR 7 Disable Channel Counter Reset Bit PWTST.DISCP 6 Disable Compare Count Period Bit PWTST.DISCAL 5 Disable Scale Counter Loading Bit PORTP 0x0056 Port P Data Register PORTP.PP7 7 Port P Data Bit 7 PORTP.PP6 6 Port P Data Bit 6 PORTP.PP5 5 Port P Data Bit 5 PORTP.PP4 4 Port P Data Bit 4 PORTP.PP3 3 Port P Data Bit 3 PORTP.PP2 2 Port P Data Bit 2 PORTP.PP1 1 Port P Data Bit 1 PORTP.PP0 0 Port P Data Bit 0 DDRP 0x0057 Port P Data Direction Register DDRP.DDP7 7 Port P Data Direction Register Bit 7 DDRP.DDP6 6 Port P Data Direction Register Bit 6 DDRP.DDP5 5 Port P Data Direction Register Bit 5 DDRP.DDP4 4 Port P Data Direction Register Bit 4 DDRP.DDP3 3 Port P Data Direction Register Bit 3 DDRP.DDP2 2 Port P Data Direction Register Bit 2 DDRP.DDP1 1 Port P Data Direction Register Bit 1 DDRP.DDP0 0 Port P Data Direction Register Bit 0 RESERVED0058 0x0058 RESERVED RESERVED0059 0x0059 RESERVED RESERVED005A 0x005A RESERVED RESERVED005B 0x005B RESERVED RESERVED005C 0x005C RESERVED RESERVED005D 0x005D RESERVED RESERVED005E 0x005E RESERVED RESERVED005F 0x005F RESERVED ATDCTL0 0x0060 ATD Control Register 0 ATDCTL1 0x0061 ATD Control Register 1 ATDCTL2 0x0062 ATD Control Register 2 ATDCTL2.ADPU 7 ATD Disable Bit ATDCTL2.AFFC 6 ATD Fast Flag Clear Bit ATDCTL2.AWAI 5 ATD Stop in Wait Mode Bit ATDCTL2.ASCIE 1 ATD Sequence Complete Interrupt Enable Bit ATDCTL2.ASCIF 0 ATD Sequence Complete Interrupt Flag ATDCTL3 0x0063 ATD Control Register 3 ATDCTL3.FRZ1 1 Background Debug (Freeze) Enable Bit ATDCTL3.FRZ0 0 Background Debug (Freeze) Enable Bit ATDCTL4 0x0064 ATD Control Register 4 ATDCTL4.S10BM 7 ATD 10-Bit Mode Control Bit ATDCTL4.SMP1 6 Select Sample Time Bit 1 ATDCTL4.SMP0 5 Select Sample Time Bit 0 ATDCTL4.PRS4 4 Select Divide-By Factor for ATD P-Clock Prescaler Bit 4 ATDCTL4.PRS3 3 Select Divide-By Factor for ATD P-Clock Prescaler Bit 3 ATDCTL4.PRS2 2 Select Divide-By Factor for ATD P-Clock Prescaler Bit 2 ATDCTL4.PRS1 1 Select Divide-By Factor for ATD P-Clock Prescaler Bit 1 ATDCTL4.PRS0 0 Select Divide-By Factor for ATD P-Clock Prescaler Bit 0 ATDCTL5 0x0065 ATD Control Register 5 ATDCTL5.S8CM 6 Select 8 Channel Mode Bit ATDCTL5.SCAN 5 Enable Continuous Channel Scan Bit ATDCTL5.MULT 4 Enable Multichannel Conversion Bit ATDCTL5.CD 3 Channel Select for Conversion Bit ATDCTL5.CC 2 Channel Select for Conversion Bit ATDCTL5.CB 1 Channel Select for Conversion Bit ATDCTL5.CA 0 Channel Select for Conversion Bit ATDSTAT 0x0066 ATD Status Register ATDSTAT.SCF 7 Sequence Complete Flag ATDSTAT.CC2 2 Conversion Counter Bit 2 for Current 4 or 8 Conversions ATDSTAT.CC1 1 Conversion Counter Bit 1 for Current 4 or 8 Conversions ATDSTAT.CC0 0 Conversion Counter Bit 0 for Current 4 or 8 Conversions ATDSTTL 0x0067 ATD Status Register ATDSTTL.CCF7 7 Sequence Complete Flag 7 ATDSTTL.CCF6 6 Sequence Complete Flag 6 ATDSTTL.CCF5 5 Sequence Complete Flag 5 ATDSTTL.CCF4 4 Sequence Complete Flag 4 ATDSTTL.CCF3 3 Sequence Complete Flag 3 ATDSTTL.CCF2 2 Sequence Complete Flag 2 ATDSTTL.CCF1 1 Sequence Complete Flag 1 ATDSTTL.CCF0 0 Sequence Complete Flag 0 ATDTSTH 0x0068 ATD Test Register High ATDTSTH.SAR9 7 SAR Data Bit 9 ATDTSTH.SAR8 6 SAR Data Bit 8 ATDTSTH.SAR7 5 SAR Data Bit 7 ATDTSTH.SAR6 4 SAR Data Bit 6 ATDTSTH.SAR5 3 SAR Data Bit 5 ATDTSTH.SAR4 2 SAR Data Bit 4 ATDTSTH.SAR3 1 SAR Data Bit 3 ATDTSTH.SAR2 0 SAR Data Bit 2 ATDTSTL 0x0069 ATD Test Register Low ATDTSTL.SAR1 7 SAR Data Bit 1 ATDTSTL.SAR0 6 SAR Data Bit 0 ATDTSTL.RST 5 Module Reset Bit ATDTSTL.TSTOUT 4 Multiplex Output of TST3-TST0 (Factory Use) ATDTSTL.TST3 3 Test Bits 3 ATDTSTL.TST2 2 Test Bits 2 ATDTSTL.TST1 1 Test Bits 1 ATDTSTL.TST0 0 Test Bits 0 RESERVED006A 0x006A RESERVED RESERVED006B 0x006B RESERVED RESERVED006C 0x006C RESERVED RESERVED006D 0x006D RESERVED RESERVED006E 0x006E RESERVED PORTAD 0x006F Port AD Data Input Register PORTAD.PAD7 7 Port AD Data Input Bit 7 PORTAD.PAD6 6 Port AD Data Input Bit 6 PORTAD.PAD5 5 Port AD Data Input Bit 5 PORTAD.PAD4 4 Port AD Data Input Bit 4 PORTAD.PAD3 3 Port AD Data Input Bit 3 PORTAD.PAD2 2 Port AD Data Input Bit 2 PORTAD.PAD1 1 Port AD Data Input Bit 1 PORTAD.PAD0 0 Port AD Data Input Bit 0 ADRx0H 0x0070 ATD Result Register 0 High ADRx0H.ADRxH15 7 ATD Conversion Result Bit 15 ADRx0H.ADRxH14 6 ATD Conversion Result Bit 14 ADRx0H.ADRxH13 5 ATD Conversion Result Bit 13 ADRx0H.ADRxH12 4 ATD Conversion Result Bit 12 ADRx0H.ADRxH11 3 ATD Conversion Result Bit 11 ADRx0H.ADRxH10 2 ATD Conversion Result Bit 10 ADRx0H.ADRxH9 1 ATD Conversion Result Bit 9 ADRx0H.ADRxH8 0 ATD Conversion Result Bit 8 ADRx0L 0x0071 ATD Result Register 0 Low ADRx0L.ADRxHL7 7 ATD Conversion Result Bit 7 ADRx0L.ADRxHL6 6 ATD Conversion Result Bit 6 ADRx0L.ADRxHL5 5 ATD Conversion Result Bit 5 ADRx0L.ADRxHL4 4 ATD Conversion Result Bit 4 ADRx0L.ADRxHL3 3 ATD Conversion Result Bit 3 ADRx0L.ADRxHL2 2 ATD Conversion Result Bit 2 ADRx0L.ADRxHL1 1 ATD Conversion Result Bit 1 ADRx0L.ADRxHL0 0 ATD Conversion Result Bit 0 ADRx1H 0x0072 ATD Result Register 1 High ADRx1H.ADRxH15 7 ATD Conversion Result Bit 15 ADRx1H.ADRxH14 6 ATD Conversion Result Bit 14 ADRx1H.ADRxH13 5 ATD Conversion Result Bit 13 ADRx1H.ADRxH12 4 ATD Conversion Result Bit 12 ADRx1H.ADRxH11 3 ATD Conversion Result Bit 11 ADRx1H.ADRxH10 2 ATD Conversion Result Bit 10 ADRx1H.ADRxH9 1 ATD Conversion Result Bit 9 ADRx1H.ADRxH8 0 ATD Conversion Result Bit 8 ADRx1L 0x0073 ATD Result Register 1 Low ADRx1L.ADRxHL7 7 ATD Conversion Result Bit 7 ADRx1L.ADRxHL6 6 ATD Conversion Result Bit 6 ADRx1L.ADRxHL5 5 ATD Conversion Result Bit 5 ADRx1L.ADRxHL4 4 ATD Conversion Result Bit 4 ADRx1L.ADRxHL3 3 ATD Conversion Result Bit 3 ADRx1L.ADRxHL2 2 ATD Conversion Result Bit 2 ADRx1L.ADRxHL1 1 ATD Conversion Result Bit 1 ADRx1L.ADRxHL0 0 ATD Conversion Result Bit 0 ADRx2H 0x0074 ATD Result Register 2 High ADRx2H.ADRxH15 7 ATD Conversion Result Bit 15 ADRx2H.ADRxH14 6 ATD Conversion Result Bit 14 ADRx2H.ADRxH13 5 ATD Conversion Result Bit 13 ADRx2H.ADRxH12 4 ATD Conversion Result Bit 12 ADRx2H.ADRxH11 3 ATD Conversion Result Bit 11 ADRx2H.ADRxH10 2 ATD Conversion Result Bit 10 ADRx2H.ADRxH9 1 ATD Conversion Result Bit 9 ADRx2H.ADRxH8 0 ATD Conversion Result Bit 8 ADRx2L 0x0075 ATD Result Register 2 Low ADRx2L.ADRxHL7 7 ATD Conversion Result Bit 7 ADRx2L.ADRxHL6 6 ATD Conversion Result Bit 6 ADRx2L.ADRxHL5 5 ATD Conversion Result Bit 5 ADRx2L.ADRxHL4 4 ATD Conversion Result Bit 4 ADRx2L.ADRxHL3 3 ATD Conversion Result Bit 3 ADRx2L.ADRxHL2 2 ATD Conversion Result Bit 2 ADRx2L.ADRxHL1 1 ATD Conversion Result Bit 1 ADRx2L.ADRxHL0 0 ATD Conversion Result Bit 0 ADRx3H 0x0076 ATD Result Register 3 High ADRx3H.ADRxH15 7 ATD Conversion Result Bit 15 ADRx3H.ADRxH14 6 ATD Conversion Result Bit 14 ADRx3H.ADRxH13 5 ATD Conversion Result Bit 13 ADRx3H.ADRxH12 4 ATD Conversion Result Bit 12 ADRx3H.ADRxH11 3 ATD Conversion Result Bit 11 ADRx3H.ADRxH10 2 ATD Conversion Result Bit 10 ADRx3H.ADRxH9 1 ATD Conversion Result Bit 9 ADRx3H.ADRxH8 0 ATD Conversion Result Bit 8 ADRx3L 0x0077 ATD Result Register 3 Low ADRx3L.ADRxHL7 7 ATD Conversion Result Bit 7 ADRx3L.ADRxHL6 6 ATD Conversion Result Bit 6 ADRx3L.ADRxHL5 5 ATD Conversion Result Bit 5 ADRx3L.ADRxHL4 4 ATD Conversion Result Bit 4 ADRx3L.ADRxHL3 3 ATD Conversion Result Bit 3 ADRx3L.ADRxHL2 2 ATD Conversion Result Bit 2 ADRx3L.ADRxHL1 1 ATD Conversion Result Bit 1 ADRx3L.ADRxHL0 0 ATD Conversion Result Bit 0 ADRx4H 0x0078 ATD Result Register 4 High ADRx4H.ADRxH15 7 ATD Conversion Result Bit 15 ADRx4H.ADRxH14 6 ATD Conversion Result Bit 14 ADRx4H.ADRxH13 5 ATD Conversion Result Bit 13 ADRx4H.ADRxH12 4 ATD Conversion Result Bit 12 ADRx4H.ADRxH11 3 ATD Conversion Result Bit 11 ADRx4H.ADRxH10 2 ATD Conversion Result Bit 10 ADRx4H.ADRxH9 1 ATD Conversion Result Bit 9 ADRx4H.ADRxH8 0 ATD Conversion Result Bit 8 ADRx4L 0x0079 ATD Result Register 4 Low ADRx4L.ADRxHL7 7 ATD Conversion Result Bit 7 ADRx4L.ADRxHL6 6 ATD Conversion Result Bit 6 ADRx4L.ADRxHL5 5 ATD Conversion Result Bit 5 ADRx4L.ADRxHL4 4 ATD Conversion Result Bit 4 ADRx4L.ADRxHL3 3 ATD Conversion Result Bit 3 ADRx4L.ADRxHL2 2 ATD Conversion Result Bit 2 ADRx4L.ADRxHL1 1 ATD Conversion Result Bit 1 ADRx4L.ADRxHL0 0 ATD Conversion Result Bit 0 ADRx5H 0x007A ATD Result Register 5 High ADRx5H.ADRxH15 7 ATD Conversion Result Bit 15 ADRx5H.ADRxH14 6 ATD Conversion Result Bit 14 ADRx5H.ADRxH13 5 ATD Conversion Result Bit 13 ADRx5H.ADRxH12 4 ATD Conversion Result Bit 12 ADRx5H.ADRxH11 3 ATD Conversion Result Bit 11 ADRx5H.ADRxH10 2 ATD Conversion Result Bit 10 ADRx5H.ADRxH9 1 ATD Conversion Result Bit 9 ADRx5H.ADRxH8 0 ATD Conversion Result Bit 8 ADRx5L 0x007B ATD Result Register 5 Low ADRx5L.ADRxHL7 7 ATD Conversion Result Bit 7 ADRx5L.ADRxHL6 6 ATD Conversion Result Bit 6 ADRx5L.ADRxHL5 5 ATD Conversion Result Bit 5 ADRx5L.ADRxHL4 4 ATD Conversion Result Bit 4 ADRx5L.ADRxHL3 3 ATD Conversion Result Bit 3 ADRx5L.ADRxHL2 2 ATD Conversion Result Bit 2 ADRx5L.ADRxHL1 1 ATD Conversion Result Bit 1 ADRx5L.ADRxHL0 0 ATD Conversion Result Bit 0 ADRx6H 0x007C ATD Result Register 6 High ADRx6H.ADRxH15 7 ATD Conversion Result Bit 15 ADRx6H.ADRxH14 6 ATD Conversion Result Bit 14 ADRx6H.ADRxH13 5 ATD Conversion Result Bit 13 ADRx6H.ADRxH12 4 ATD Conversion Result Bit 12 ADRx6H.ADRxH11 3 ATD Conversion Result Bit 11 ADRx6H.ADRxH10 2 ATD Conversion Result Bit 10 ADRx6H.ADRxH9 1 ATD Conversion Result Bit 9 ADRx6H.ADRxH8 0 ATD Conversion Result Bit 8 ADRx6L 0x007D ATD Result Register 6 Low ADRx6L.ADRxHL7 7 ATD Conversion Result Bit 7 ADRx6L.ADRxHL6 6 ATD Conversion Result Bit 6 ADRx6L.ADRxHL5 5 ATD Conversion Result Bit 5 ADRx6L.ADRxHL4 4 ATD Conversion Result Bit 4 ADRx6L.ADRxHL3 3 ATD Conversion Result Bit 3 ADRx6L.ADRxHL2 2 ATD Conversion Result Bit 2 ADRx6L.ADRxHL1 1 ATD Conversion Result Bit 1 ADRx6L.ADRxHL0 0 ATD Conversion Result Bit 0 ADRx7H 0x007E ATD Result Register 7 High ADRx7H.ADRxH15 7 ATD Conversion Result Bit 15 ADRx7H.ADRxH14 6 ATD Conversion Result Bit 14 ADRx7H.ADRxH13 5 ATD Conversion Result Bit 13 ADRx7H.ADRxH12 4 ATD Conversion Result Bit 12 ADRx7H.ADRxH11 3 ATD Conversion Result Bit 11 ADRx7H.ADRxH10 2 ATD Conversion Result Bit 10 ADRx7H.ADRxH9 1 ATD Conversion Result Bit 9 ADRx7H.ADRxH8 0 ATD Conversion Result Bit 8 ADRx7L 0x007F ATD Result Register 7 Low ADRx7L.ADRxHL7 7 ATD Conversion Result Bit 7 ADRx7L.ADRxHL6 6 ATD Conversion Result Bit 6 ADRx7L.ADRxHL5 5 ATD Conversion Result Bit 5 ADRx7L.ADRxHL4 4 ATD Conversion Result Bit 4 ADRx7L.ADRxHL3 3 ATD Conversion Result Bit 3 ADRx7L.ADRxHL2 2 ATD Conversion Result Bit 2 ADRx7L.ADRxHL1 1 ATD Conversion Result Bit 1 ADRx7L.ADRxHL0 0 ATD Conversion Result Bit 0 TIOS 0x0080 Timer IC/OC Select Register TIOS.IOS7 7 Force Output Compare Action Bits for Channel 7 TIOS.IOS6 6 Force Output Compare Action Bits for Channel 6 TIOS.IOS5 5 Force Output Compare Action Bits for Channel 5 TIOS.IOS4 4 Force Output Compare Action Bits for Channel 4 TIOS.IOS3 3 Force Output Compare Action Bits for Channel 3 TIOS.IOS2 2 Force Output Compare Action Bits for Channel 2 TIOS.IOS1 1 Force Output Compare Action Bits for Channel 1 TIOS.IOS0 0 Force Output Compare Action Bits for Channel 0 CFORC 0x0081 Timer Compare Force Register CFORC.FOC7 7 Force Output Compare Action Bits for Channel 7 CFORC.FOC6 6 Force Output Compare Action Bits for Channel 6 CFORC.FOC5 5 Force Output Compare Action Bits for Channel 5 CFORC.FOC4 4 Force Output Compare Action Bits for Channel 4 CFORC.FOC3 3 Force Output Compare Action Bits for Channel 3 CFORC.FOC2 2 Force Output Compare Action Bits for Channel 2 CFORC.FOC1 1 Force Output Compare Action Bits for Channel 1 CFORC.FOC0 0 Force Output Compare Action Bits for Channel 0 OC7M 0x0082 Timer Output Compare 7 Mask Register OC7M.OC7M7 7 OC7M.OC7M6 6 OC7M.OC7M5 5 OC7M.OC7M4 4 OC7M.OC7M3 3 OC7M.OC7M2 2 OC7M.OC7M1 1 OC7M.OC7M0 0 OC7D 0x0083 Timer Output Compare 7 Data Register OC7D.OC7D7 7 OC7D.OC7D6 6 OC7D.OC7D5 5 OC7D.OC7D4 4 OC7D.OC7D3 3 OC7D.OC7D2 2 OC7D.OC7D1 1 OC7D.OC7D0 0 TCNTH 0x0084 Timer Count Register High TCNTL 0x0085 Timer Count Register Low TSCR 0x0086 Timer System Control Register TSCR.TEN 7 Timer Enable Bit TSCR.TSWAI 6 Timer Stops While in Wait Bit TSCR.TSBCK 5 Timer Stops While in Background Mode Bit TSCR.TFFCA 4 Timer Fast Flag Clear All Bit RESERVED0087 0x0087 RESERVED TCTL1 0x0088 Timer Control Register 1 TCTL1.OM7 7 Output mode 7 TCTL1.OL7 6 Output level 7 TCTL1.OM6 5 Output mode 6 TCTL1.OL6 4 Output level 6 TCTL1.OM5 3 Output mode 5 TCTL1.OL5 2 Output level 5 TCTL1.OM4 1 Output mode 4 TCTL1.OL4 0 Output level 4 TCTL2 0x0089 Timer Control Register 2 TCTL2.OM3 7 Output mode 3 TCTL2.OL3 6 Output level 3 TCTL2.OM2 5 Output mode 2 TCTL2.OL2 4 Output level 2 TCTL2.OM1 3 Output mode 1 TCTL2.OL1 2 Output level 1 TCTL2.OM0 1 Output mode 0 TCTL2.OL0 0 Output level 0 TCTL3 0x008A Timer Control Register 3 TCTL3.EDG7B 7 Input Capture Edge Control Bit 7B TCTL3.EDG7A 6 Input Capture Edge Control Bit 7A TCTL3.EDG6B 5 Input Capture Edge Control Bit 6B TCTL3.EDG6A 4 Input Capture Edge Control Bit 6A TCTL3.EDG5B 3 Input Capture Edge Control Bit 5B TCTL3.EDG5A 2 Input Capture Edge Control Bit 5A TCTL3.EDG4B 1 Input Capture Edge Control Bit 4B TCTL3.EDG4A 0 Input Capture Edge Control Bit 4A TCTL4 0x008B Timer Control Register 4 TCTL4.EDG3B 7 Input Capture Edge Control Bit 3B TCTL4.EDG3A 6 Input Capture Edge Control Bit 3A TCTL4.EDG2B 5 Input Capture Edge Control Bit 2B TCTL4.EDG2A 4 Input Capture Edge Control Bit 2A TCTL4.EDG1B 3 Input Capture Edge Control Bit 1B TCTL4.EDG1A 2 Input Capture Edge Control Bit 1A TCTL4.EDG0B 1 Input Capture Edge Control Bit 0B TCTL4.EDG0A 0 Input Capture Edge Control Bit 0A TMSK1 0x008C Timer Mask Register 1 TMSK1.C7I 7 Input Capture/Output Compare 1 Interrupt Enable Bit 7 TMSK1.C6I 6 Input Capture/Output Compare 1 Interrupt Enable Bit 6 TMSK1.C5I 5 Input Capture/Output Compare 1 Interrupt Enable Bit 5 TMSK1.C4I 4 Input Capture/Output Compare 1 Interrupt Enable Bit 4 TMSK1.C3I 3 Input Capture/Output Compare 1 Interrupt Enable Bit 3 TMSK1.C2I 2 Input Capture/Output Compare 1 Interrupt Enable Bit 2 TMSK1.C1I 1 Input Capture/Output Compare 1 Interrupt Enable Bit 1 TMSK1.C0I 0 Input Capture/Output Compare 1 Interrupt Enable Bit 0 TMSK2 0x008D Timer Mask Register 2 TMSK2.TOI 7 Timer Overflow Interrupt Enable Bit TMSK2.PUPT 5 Timer Pullup Resistor Enable Bit TMSK2.RDPT 4 Timer Drive Reduction Bit TMSK2.TCRE 3 Timer Counter Reset Enable Bit TMSK2.PR2 2 Timer Prescaler Select Bit 2 TMSK2.PR1 1 Timer Prescaler Select Bit 1 TMSK2.PR0 0 Timer Prescaler Select Bit 0 TFLG1 0x008E Timer Interrupt Flag Register 1 TFLG1.C7F 7 Input Capture/Output Compare Channel 7 Flag TFLG1.C6F 6 Input Capture/Output Compare Channel 6 Flag TFLG1.C5F 5 Input Capture/Output Compare Channel 5 Flag TFLG1.C4F 4 Input Capture/Output Compare Channel 4 Flag TFLG1.C3F 3 Input Capture/Output Compare Channel 3 Flag TFLG1.C2F 2 Input Capture/Output Compare Channel 2 Flag TFLG1.C1F 1 Input Capture/Output Compare Channel 1 Flag TFLG1.C0F 0 Input Capture/Output Compare Channel 0 Flag TFLG2 0x008F Timer Interrupt Flag Register 2 TFLG2.TOF 7 Timer Overflow Flag TC0H 0x0090 Timer Input Capture/Output Compare 0 Register High TC0L 0x0091 Timer Input Capture/Output Compare 0 Register Low TC1H 0x0092 Timer Input Capture/Output Compare 1 Register High TC1L 0x0093 Timer Input Capture/Output Compare 1 Register Low TC2H 0x0094 Timer Input Capture/Output Compare 2 Register High TC2L 0x0095 Timer Input Capture/Output Compare 2 Register Low TC3H 0x0096 Timer Input Capture/Output Compare 3 Register High TC3L 0x0097 Timer Input Capture/Output Compare 3 Register Low TC4H 0x0098 Timer Input Capture/Output Compare 4 Register High TC4L 0x0099 Timer Input Capture/Output Compare 4 Register Low TC5H 0x009A Timer Input Capture/Output Compare 5 Register High TC5L 0x009B Timer Input Capture/Output Compare 5 Register Low TC6H 0x009C Timer Input Capture/Output Compare 6 Register High TC6L 0x009D Timer Input Capture/Output Compare 6 Register Low TC7H 0x009E Timer Input Capture/Output Compare 7 Register High TC7L 0x009F Timer Input Capture/Output Compare 7 Register Low PACTL 0x00A0 Pulse Accumulator Control Register PACTL.PAEN 6 Pulse Accumulator System Enable Bit PACTL.PAMOD 5 Pulse Accumulator Mode Bit PACTL.PEDGE 4 Pulse Accumulator Edge Control Bit PACTL.CLK1 3 Clock Select Bit 1 PACTL.CLK0 2 Clock Select Bits 0 PACTL.PAOVI 1 Pulse Accumulator Overflow Interrupt Enable Bit PACTL.PAI 0 Pulse Accumulator Input Interrupt Enable Bit PAFLG 0x00A1 Pulse Accumulator Flag Register PAFLG.PAOVF 1 Pulse Accumulator Overflow Flag PAFLG.PAIF 0 Pulse Accumulator Input Edge Flag PACN3 0x00A2 Pulse Accumulator Count Register 3 PACN2 0x00A3 Pulse Accumulator Count Register 2 PACN1 0x00A4 Pulse Accumulator Count Register 1 PACN0 0x00A5 Pulse Accumulator Count Register 0 MCCTL 0x00A6 16-Bit Modulus Down-Counter Control Regster MCCTL.MCZI 7 Modulus Counter Underflow Interrupt Enable Bit MCCTL.MODMC 6 Modulus Mode Enable Bit MCCTL.RDMCL 5 Read Modulus Down-Counter Load Bit MCCTL.ICLAT 4 Input Capture Force Latch Action Bit MCCTL.FLMC 3 Force Load Register into the Modulus Counter Count Register Bit MCCTL.MCEN 2 Modulus Down-Counter Enable Bit MCCTL.MCPR1 1 Modulus Counter Prescaler Select Bit 1 MCCTL.MCPR0 0 Modulus Counter Prescaler Select Bit 0 MCFLG 0x00A7 16-Bit Modulus Down-Counter Flag Regster MCFLG.MCZF 7 Modulus Counter Underflow Interrupt Flag MCFLG.POLF3 3 First Input Capture Polarity Status Bit 3 MCFLG.POLF2 2 First Input Capture Polarity Status Bit 2 MCFLG.POLF1 1 First Input Capture Polarity Status Bit 1 MCFLG.POLF0 0 First Input Capture Polarity Status Bit 0 ICPACR 0x00A8 Input Control Pulse Accumulators Control Register ICPACR.PA3EN 3 8-Bit Pulse Accumulator 3 Enable Bit ICPACR.PA2EN 2 8-Bit Pulse Accumulator 2 Enable Bit ICPACR.PA1EN 1 8-Bit Pulse Accumulator 1 Enable Bit ICPACR.PA0EN 0 8-Bit Pulse Accumulator 0 Enable Bit DLYCT 0x00A9 Delay Counter Control Register DLYCT.DLY1 1 Delay Counter Select Bit 1 DLYCT.DLY0 0 Delay Counter Select Bit 0 ICOVW 0x00AA Input Control Overwrite Register ICOVW.NOVW7 7 No Input Capture Overwrite Bit 7 ICOVW.NOVW6 6 No Input Capture Overwrite Bit 6 ICOVW.NOVW5 5 No Input Capture Overwrite Bit 5 ICOVW.NOVW4 4 No Input Capture Overwrite Bit 4 ICOVW.NOVW3 3 No Input Capture Overwrite Bit 3 ICOVW.NOVW2 2 No Input Capture Overwrite Bit 2 ICOVW.NOVW1 1 No Input Capture Overwrite Bit 1 ICOVW.NOVW0 0 No Input Capture Overwrite Bit 0 ICSYS 0x00AB Input Control System Control Register ICSYS.SH37 7 Share Input Action of Input Capture Channels 3 and y Bit 7 ICSYS.SH26 6 Share Input Action of Input Capture Channels 2 and y Bit 6 ICSYS.SH15 5 Share Input Action of Input Capture Channels 1 and y Bit 5 ICSYS.SH04 4 Share Input Action of Input Capture Channels 0 and y Bit 4 ICSYS.TFMOD 3 Timer Flag-Setting Mode Bit ICSYS.PACMX 2 8-Bit Pulse Accumulators Maximum Count Bit ICSYS.BUFEN 1 IC Buffer Enable Bit ICSYS.LATQ 0 Input Control Latch or Queue Mode Enable Bit RESERVED00AC 0x00AC RESERVED TIMTST 0x00AD Timer Test Register TIMTST.TCBYP 1 Main Timer Divider Chain Bypass Bit PORTT 0x00AE Timer Port Data Register PORTT.PT7 7 Timer Port Data Register bit 7 PORTT.PT6 6 Timer Port Data Register bit 6 PORTT.PT5 5 Timer Port Data Register bit 5 PORTT.PT4 4 Timer Port Data Register bit 4 PORTT.PT3 3 Timer Port Data Register bit 3 PORTT.PT2 2 Timer Port Data Register bit 2 PORTT.PT1 1 Timer Port Data Register bit 1 PORTT.PT0 0 Timer Port Data Register bit 0 DDRT 0x00AF Data Direction Register for Timer Port DDRT.DDT7 7 Data Direction Register for Timer Port bit 7 DDRT.DDT6 6 Data Direction Register for Timer Port bit 6 DDRT.DDT5 5 Data Direction Register for Timer Port bit 5 DDRT.DDT4 4 Data Direction Register for Timer Port bit 4 DDRT.DDT3 3 Data Direction Register for Timer Port bit 3 DDRT.DDT2 2 Data Direction Register for Timer Port bit 2 DDRT.DDT1 1 Data Direction Register for Timer Port bit 1 DDRT.DDT0 0 Data Direction Register for Timer Port bit 0 PBCTL 0x00B0 16-Bit Pulse Accumulator B Control Register PBCTL.PBEN 6 Pulse Accumulator B System Enable Bit PBCTL.PBOVI 1 Pulse Accumulator B Overflow Interrupt Enable Bit PBFLG 0x00B1 Pulse Accumulator B Flag Register PBFLG.PBOVF 1 Pulse Accumulator B Overflow Flag PA3H 0x00B2 8-Bit Pulse Accumulator Holding Register 3 PA2H 0x00B3 8-Bit Pulse Accumulator Holding Register 2 PA1H 0x00B4 8-Bit Pulse Accumulator Holding Register 1 PA0H 0x00B5 8-Bit Pulse Accumulator Holding Register 0 MCCNTH 0x00B6 Modulus Down-Counter Count Register High MCCNTL 0x00B7 Modulus Down-Counter Count Register Low TC0HH 0x00B8 Timer Input Capture Holding Register 0 High TC0HL 0x00B9 Timer Input Capture Holding Register 0 Low TC1HH 0x00BA Timer Input Capture Holding Register 1 High TC1HL 0x00BB Timer Input Capture Holding Register 1 Low TC2HH 0x00BC Timer Input Capture Holding Register 2 High TC2HL 0x00BD Timer Input Capture Holding Register 2 Low TC3HH 0x00BE Timer Input Capture Holding Register 3 High TC3HL 0x00BF Timer Input Capture Holding Register 3 Low SC0BDH 0x00C0 SCI 0 Baud Rate Control Register High SC0BDH.BTST 7 SC0BDH.BSPL 6 SC0BDH.BRLD 5 SC0BDH.SBR12 4 SC0BDH.SBR11 3 SC0BDH.SBR10 2 SC0BDH.SBR9 1 SC0BDH.SBR8 0 SC0BDL 0x00C1 SCI 0 Baud Rate Control Register Low SC0BDL.SBR7 7 SC0BDL.SBR6 6 SC0BDL.SBR5 5 SC0BDL.SBR4 4 SC0BDL.SBR3 3 SC0BDL.SBR2 2 SC0BDL.SBR1 1 SC0BDL.SBR0 0 SC0CR1 0x00C2 SCI Control Register 1 SC0CR1.LOOPS 7 SCI LOOP Mode/Single-Wire Mode Enable Bit SC0CR1.WOMS 6 Wired-OR Mode for Serial Pins SC0CR1.RSRC 5 Receiver Source Bit SC0CR1.M 4 Mode Bit (select character format) SC0CR1.WAKE 3 Wakeup by Address Mark/Idle Bit SC0CR1.ILT 2 Idle Line Type Bit SC0CR1.PE 1 Parity Enable Bit SC0CR1.PT 0 Parity Type Bit SC0CR2 0x00C3 SCI Control Register 2 SC0CR2.TIE 7 Transmit Interrupt Enable Bit SC0CR2.TCIE 6 Transmit Complete Interrupt Enable Bit SC0CR2.RIE 5 Receiver Interrupt Enable Bit SC0CR2.ILIE 4 Idle Line Interrupt Enable Bit SC0CR2.TE 3 Transmitter Enable Bit SC0CR2.RE 2 Receiver Enable Bit SC0CR2.RWU 1 Receiver Wakeup Control Bit SC0CR2.SBK 0 Send Break Bit SC0SR1 0x00C4 SCI Status Register 1 SC0SR1.TDRE 7 Transmit Data Register Empty Flag SC0SR1.TC 6 Transmit Complete Flag SC0SR1.RDRF 5 Receive Data Register Full Flag SC0SR1.IDLE 4 Idle Line Detected Flag SC0SR1.OR 3 Overrun Error Flag SC0SR1.NF 2 Noise Error Flag SC0SR1.FE 1 Framing Error Flag SC0SR1.PF 0 Parity Error Flag SC0SR2 0x00C5 SCI Status Register 2 SC0SR2.RAF 0 Receiver Active Flag SC0DRH 0x00C6 SCI Data Register High SC0DRH.R8 7 Receive Bit 8 SC0DRH.T8 6 Transmit Bit 8 SC0DRL 0x00C7 SCI Data Register Low SC0DRL.R7T7 7 Receive/Transmit Data Bit 7 SC0DRL.R6T6 6 Receive/Transmit Data Bit 6 SC0DRL.R5T5 5 Receive/Transmit Data Bit 5 SC0DRL.R4T4 4 Receive/Transmit Data Bit 4 SC0DRL.R3T3 3 Receive/Transmit Data Bit 3 SC0DRL.R2T2 2 Receive/Transmit Data Bit 2 SC0DRL.R1T1 1 Receive/Transmit Data Bit 1 SC0DRL.R0T0 0 Receive/Transmit Data Bit 0 RESERVED00C8 0x00C8 RESERVED RESERVED00C9 0x00C9 RESERVED RESERVED00CA 0x00CA RESERVED RESERVED00CB 0x00CB RESERVED RESERVED00CC 0x00CC RESERVED RESERVED00CD 0x00CD RESERVED RESERVED00CE 0x00CE RESERVED RESERVED00CF 0x00CF RESERVED SP0CR1 0x00D0 SPI Control Register 1 SP0CR1.SPIE 7 SPI Interrupt Enable Bit SP0CR1.SPE 6 SPI System Enable Bit SP0CR1.SWOM 5 Port S Wired-OR Mode Bit SP0CR1.MSTR 4 SPI Master/Slave Mode Select Bit SP0CR1.CPOL 3 SPI Clock Polarity SP0CR1.CPHA 2 Clock Phase Bits SP0CR1.SSOE 1 Slave Select Output Enable Bit SP0CR1.LSBF 0 SPI LSB First Enable Bit SP0CR2 0x00D1 SPI Control Register 2 SP0CR2.PUPS 3 Pullup Port S Enable Bit SP0CR2.RDS 2 Reduce Drive of Port S Bit SP0CR2.SPC0 0 Serial Pin Control 0 Bit SP0BR 0x00D2 SPI Baud Rate Register SP0BR.SPR2 2 SPI Clock (SCK) Rate Select Bit 2 SP0BR.SPR1 1 SPI Clock (SCK) Rate Select Bit 1 SP0BR.SPR0 0 SPI Clock (SCK) Rate Select Bit 0 SP0SR 0x00D3 SPI Status Register SP0SR.SPIF 7 SPI Interrupt Request Bit SP0SR.WCOL 6 Write Collision Status Flag SP0SR.MODF 4 SPI Mode Error Interrupt Status Flag RESERVED00D4 0x00D4 RESERVED SP0DR 0x00D5 SPI Data Register PORTS 0x00D6 Port S Data Register PORTS.PS7 7 Port S Data Register Bit 7 PORTS.PS6 6 Port S Data Register Bit 6 PORTS.PS5 5 Port S Data Register Bit 5 PORTS.PS4 4 Port S Data Register Bit 4 PORTS.PS3 3 Port S Data Register Bit 3 PORTS.PS2 2 Port S Data Register Bit 2 PORTS.PS1 1 Port S Data Register Bit 1 PORTS.PS0 0 Port S Data Register Bit 0 DDRS 0x00D7 Port S Data Direction Register DDRS.DDS7 7 Port S Data Direction Register Bit 7 DDRS.DDS6 6 Port S Data Direction Register Bit 6 DDRS.DDS5 5 Port S Data Direction Register Bit 5 DDRS.DDS4 4 Port S Data Direction Register Bit 4 DDRS.DDS3 3 Port S Data Direction Register Bit 3 DDRS.DDS2 2 Port S Data Direction Register Bit 2 DDRS.DDS1 1 Port S Data Direction Register Bit 1 DDRS.DDS0 0 Port S Data Direction Register Bit 0 RESERVED00D8 0x00D8 RESERVED RESERVED00D9 0x00D9 RESERVED RESERVED00DA 0x00DA RESERVED PURDS 0x00DB Port S Pullup/Reduced Drive Register PURDS.RDPS2 6 Reduce Drive of PS7-PS4 PURDS.RDPS1 5 Reduce Drive of PS3 and PS2 PURDS.RDPS0 4 Reduce Drive of PS1 and PS0 PURDS.PUPS2 2 Pullup Port S Enable PS7-PS4 PURDS.PUPS1 1 Pullup Port S Enable PS3 and PS2 Bit PURDS.PUPS0 0 Pullup Port S Enable PS1 and PS0 Bit RESERVED00DC 0x00DC RESERVED RESERVED00DD 0x00DD RESERVED RESERVED00DE 0x00DE RESERVED RESERVED00DF 0x00DF RESERVED SLOW 0x00E0 Slow Mode Divider Register SLOW.SLDV2 2 Slow Mode Divisor Selector Bit 2 SLOW.SLDV1 1 Slow Mode Divisor Selector Bit 1 SLOW.SLDV0 0 Slow Mode Divisor Selector Bit 0 RESERVED00E1 0x00E1 RESERVED RESERVED00E2 0x00E2 RESERVED RESERVED00E3 0x00E3 RESERVED RESERVED00E4 0x00E4 RESERVED RESERVED00E5 0x00E5 RESERVED RESERVED00E6 0x00E6 RESERVED RESERVED00E7 0x00E7 RESERVED RESERVED00E8 0x00E8 RESERVED RESERVED00E9 0x00E9 RESERVED RESERVED00EA 0x00EA RESERVED RESERVED00EB 0x00EB RESERVED RESERVED00EC 0x00EC RESERVED RESERVED00ED 0x00ED RESERVED RESERVED00EE 0x00EE RESERVED RESERVED00EF 0x00EF RESERVED EEMCR 0x00F0 EEPROM Configuration Register EEMCR.EESWAI 2 EEPROM Stops in Wait Mode Bit EEMCR.PROTLCK 1 Block Protect Write Lock Bit EEMCR.EERC 0 EEPROM Charge Pump Clock Bit EEPROT 0x00F1 EEPROM Block Protect Register EEPROT.BRPROT4 4 EEPROM Block Protection Bit 4 EEPROT.BRPROT3 3 EEPROM Block Protection Bit 3 EEPROT.BRPROT2 2 EEPROM Block Protection Bit 2 EEPROT.BRPROT1 1 EEPROM Block Protection Bit 1 EEPROT.BRPROT0 0 EEPROM Block Protection Bit 0 EETST 0x00F2 EEPROM Test Register EETST.EEODD 7 Odd Row Programming Bit EETST.EEVEN 6 Even Row Programming Bit EETST.MARG 5 Program and Erase Voltage Margin Test Enable Bit EETST.EECPD 4 Charge Pump Disable Bit EETST.EECPRD 3 Charge Pump Ramp Disable Bit EETST.EECPM 1 Charge Pump Monitor Enable Bit EEPROG 0x00F3 EEPROM Control Register EEPROG.BULKP 7 Bulk Erase Protection Bit EEPROG.BYTE 4 Byte and Aligned Word Erase Bit EEPROG.ROW 3 Row or Bulk Erase Bit EEPROG.ERASE 2 Erase Control Bit EEPROG.EELAT 1 EEPROM Latch Control Bit EEPROG.EEPGM 0 Program and Erase Enable Bit RESERVED00F4 0x00F4 RESERVED RESERVED00F5 0x00F5 RESERVED RESERVED00F6 0x00F6 RESERVED RESERVED00F7 0x00F7 RESERVED RESERVED00F8 0x00F8 RESERVED RESERVED00F9 0x00F9 RESERVED RESERVED00FA 0x00FA RESERVED RESERVED00FB 0x00FB RESERVED RESERVED00FC 0x00FC RESERVED RESERVED00FD 0x00FD RESERVED RESERVED00FE 0x00FE RESERVED RESERVED00FF 0x00FF RESERVED ; CAN CMCR0 0x0100 msCAN12 Module Control Register 0 CMCR0.CSWAI 5 CAN Stops in Wait Mode Bit CMCR0.SYNCH 4 Synchronized Status Bit CMCR0.TLNKEN 3 Timer Enable Flag CMCR0.SLPAK 2 Sleep Mode Acknowledge Flag CMCR0.SLPRQ 1 Sleep Request, Go To Sleep Mode Flag CMCR0.SFTRES 0 Soft-Reset Bit CMCR1 0x0101 msCAN12 Module Control Register 1 CMCR1.LOOPB 2 Loop Back Self-Test Mode Bit CMCR1.WUPM 1 Wakeup Mode Flag CMCR1.CLKSRC 0 msCAN12 Clock Source Flag CBTR0 0x0102 msCAN12 Bus Timing Register 0 CBTR0.SJW1 7 Synchronization Jump Width Bit 1 CBTR0.SJW0 6 Synchronization Jump Width Bit 0 CBTR0.BRP5 5 Baud Rate Prescaler Bit 5 CBTR0.BRP4 4 Baud Rate Prescaler Bit 4 CBTR0.BRP3 3 Baud Rate Prescaler Bit 3 CBTR0.BRP2 2 Baud Rate Prescaler Bit 2 CBTR0.BRP1 1 Baud Rate Prescaler Bit 1 CBTR0.BRP0 0 Baud Rate Prescaler Bit 0 CBTR1 0x0103 msCAN12 Bus Timing Register 1 CBTR1.SAMP 7 Sampling Bit CBTR1.TSEG22 6 Time Segment Bit 22 CBTR1.TSEG21 5 Time Segment Bit 21 CBTR1.TSEG20 4 Time Segment Bit 20 CBTR1.TSEG13 3 Time Segment Bit 13 CBTR1.TSEG12 2 Time Segment Bit 12 CBTR1.TSEG11 1 Time Segment Bit 11 CBTR1.TSEG10 0 Time Segment Bit 10 CRFLG 0x0104 msCAN12 Receiver Flag Register CRFLG.WUPIF 7 Wakeup Interrupt Flag CRFLG.RWRNIF 6 Receiver Warning Interrupt Flag CRFLG.TWRNIF 5 Transmitter Warning Interrupt Flag CRFLG.RERRIF 4 Receiver Error Passive Interrupt Flag CRFLG.TERRIF 3 Transmitter Error Passive Interrupt Flag CRFLG.BOFFIF 2 Bus-Off Interrupt Flag CRFLG.OVRIF 1 Overrun Interrupt Flag CRFLG.RXF 0 Receive Buffer Full Flag CRIER 0x0105 msCAN12 Receiver Interrupt Enable Register CRIER.WUPIE 7 Wakeup Interrupt Enable Bit CRIER.RWRNIE 6 Receiver Warning Interrupt Enable Bit CRIER.TWRNIE 5 Transmitter Warning Interrupt Enable Bit CRIER.RERRIE 4 Receiver Error Passive Interrupt Enable Bit CRIER.TERRIE 3 Transmitter Error Passive Interrupt Enable Bit CRIER.BOFFIE 2 Bus-Off Interrupt Enable Bit CRIER.OVRIE 1 Overrun Interrupt Enable Bit CRIER.RXFIE 0 Receiver Full Interrupt Enable Bit CTFLG 0x0106 msCAN12 Transmitter Flag Register CTFLG.ABTAK2 6 Abort Acknowledge Flag 2 CTFLG.ABTAK1 5 Abort Acknowledge Flag 1 CTFLG.ABTAK0 4 Abort Acknowledge Flag 0 CTFLG.TXE2 2 Transmitter Buffer Empty Flag 2 CTFLG.TXE1 1 Transmitter Buffer Empty Flag 1 CTFLG.TXE0 0 Transmitter Buffer Empty Flag 0 CTCR 0x0107 msCAN12 Transmitter Control Register CTCR.ABTRQ2 6 Abort Request Bit 2 CTCR.ABTRQ1 5 Abort Request Bit 1 CTCR.ABTRQ0 4 Abort Request Bit 0 CTCR.TXEIE2 2 Transmitter Empty Interrupt Enable Bit 2 CTCR.TXEIE1 1 Transmitter Empty Interrupt Enable Bit 1 CTCR.TXEIE0 0 Transmitter Empty Interrupt Enable Bit 0 CIDAC 0x0108 msCAN12 Identifier Acceptance Control Register CIDAC.IDAM1 5 Identifier Acceptance Mode Flag 1 CIDAC.IDAM0 4 Identifier Acceptance Mode Flag 0 CIDAC.IDHIT2 2 Identifier Acceptance Hit Indicator Flag 2 CIDAC.IDHIT1 1 Identifier Acceptance Hit Indicator Flag 1 CIDAC.IDHIT0 0 Identifier Acceptance Hit Indicator Flag 0 RESERVED0109 0x0109 RESERVED RESERVED010A 0x010A RESERVED RESERVED010B 0x010B RESERVED RESERVED010C 0x010C RESERVED RESERVED010D 0x010D RESERVED CRXERR 0x010E msCAN12 Receive Error Counter CRXERR.RXERR7 7 CRXERR.RXERR6 6 CRXERR.RXERR5 5 CRXERR.RXERR4 4 CRXERR.RXERR3 3 CRXERR.RXERR2 2 CRXERR.RXERR1 1 CRXERR.RXERR0 0 CTXERR 0x010F msCAN12 Transmit Error Counter CTXERR.TXERR7 7 CTXERR.TXERR6 6 CTXERR.TXERR5 5 CTXERR.TXERR4 4 CTXERR.TXERR3 3 CTXERR.TXERR2 2 CTXERR.TXERR1 1 CTXERR.TXERR0 0 CIDAR0 0x0110 msCAN12 Identifier Acceptance Register 0 CIDAR0.AC7 7 Acceptance Code Bit 7 CIDAR0.AC6 6 Acceptance Code Bit 6 CIDAR0.AC5 5 Acceptance Code Bit 5 CIDAR0.AC4 4 Acceptance Code Bit 4 CIDAR0.AC3 3 Acceptance Code Bit 3 CIDAR0.AC2 2 Acceptance Code Bit 2 CIDAR0.AC1 1 Acceptance Code Bit 1 CIDAR0.AC0 0 Acceptance Code Bit 0 CIDAR1 0x0111 msCAN12 Identifier Acceptance Register 1 CIDAR1.AC7 7 Acceptance Code Bit 7 CIDAR1.AC6 6 Acceptance Code Bit 6 CIDAR1.AC5 5 Acceptance Code Bit 5 CIDAR1.AC4 4 Acceptance Code Bit 4 CIDAR1.AC3 3 Acceptance Code Bit 3 CIDAR1.AC2 2 Acceptance Code Bit 2 CIDAR1.AC1 1 Acceptance Code Bit 1 CIDAR1.AC0 0 Acceptance Code Bit 0 CIDAR2 0x0112 msCAN12 Identifier Acceptance Register 2 CIDAR2.AC7 7 Acceptance Code Bit 7 CIDAR2.AC6 6 Acceptance Code Bit 6 CIDAR2.AC5 5 Acceptance Code Bit 5 CIDAR2.AC4 4 Acceptance Code Bit 4 CIDAR2.AC3 3 Acceptance Code Bit 3 CIDAR2.AC2 2 Acceptance Code Bit 2 CIDAR2.AC1 1 Acceptance Code Bit 1 CIDAR2.AC0 0 Acceptance Code Bit 0 CIDAR3 0x0113 msCAN12 Identifier Acceptance Register 3 CIDAR3.AC7 7 Acceptance Code Bit 7 CIDAR3.AC6 6 Acceptance Code Bit 6 CIDAR3.AC5 5 Acceptance Code Bit 5 CIDAR3.AC4 4 Acceptance Code Bit 4 CIDAR3.AC3 3 Acceptance Code Bit 3 CIDAR3.AC2 2 Acceptance Code Bit 2 CIDAR3.AC1 1 Acceptance Code Bit 1 CIDAR3.AC0 0 Acceptance Code Bit 0 CIDMR0 0x0114 msCAN12 Identifier Mask Register 0 CIDMR0.AM7 7 Acceptance Mask Bit 7 CIDMR0.AM6 6 Acceptance Mask Bit 6 CIDMR0.AM5 5 Acceptance Mask Bit 5 CIDMR0.AM4 4 Acceptance Mask Bit 4 CIDMR0.AM3 3 Acceptance Mask Bit 3 CIDMR0.AM2 2 Acceptance Mask Bit 2 CIDMR0.AM1 1 Acceptance Mask Bit 1 CIDMR0.AM0 0 Acceptance Mask Bit 0 CIDMR1 0x0115 msCAN12 Identifier Mask Register 1 CIDMR1.AM7 7 Acceptance Mask Bit 7 CIDMR1.AM6 6 Acceptance Mask Bit 6 CIDMR1.AM5 5 Acceptance Mask Bit 5 CIDMR1.AM4 4 Acceptance Mask Bit 4 CIDMR1.AM3 3 Acceptance Mask Bit 3 CIDMR1.AM2 2 Acceptance Mask Bit 2 CIDMR1.AM1 1 Acceptance Mask Bit 1 CIDMR1.AM0 0 Acceptance Mask Bit 0 CIDMR2 0x0116 msCAN12 Identifier Mask Register 2 CIDMR2.AM7 7 Acceptance Mask Bit 7 CIDMR2.AM6 6 Acceptance Mask Bit 6 CIDMR2.AM5 5 Acceptance Mask Bit 5 CIDMR2.AM4 4 Acceptance Mask Bit 4 CIDMR2.AM3 3 Acceptance Mask Bit 3 CIDMR2.AM2 2 Acceptance Mask Bit 2 CIDMR2.AM1 1 Acceptance Mask Bit 1 CIDMR2.AM0 0 Acceptance Mask Bit 0 CIDMR3 0x0117 msCAN12 Identifier Mask Register 3 CIDMR3.AM7 7 Acceptance Mask Bit 7 CIDMR3.AM6 6 Acceptance Mask Bit 6 CIDMR3.AM5 5 Acceptance Mask Bit 5 CIDMR3.AM4 4 Acceptance Mask Bit 4 CIDMR3.AM3 3 Acceptance Mask Bit 3 CIDMR3.AM2 2 Acceptance Mask Bit 2 CIDMR3.AM1 1 Acceptance Mask Bit 1 CIDMR3.AM0 0 Acceptance Mask Bit 0 CIDAR4 0x0118 msCAN12 Identifier Acceptance Register 4 CIDAR4.AC7 7 Acceptance Code Bit 7 CIDAR4.AC6 6 Acceptance Code Bit 6 CIDAR4.AC5 5 Acceptance Code Bit 5 CIDAR4.AC4 4 Acceptance Code Bit 4 CIDAR4.AC3 3 Acceptance Code Bit 3 CIDAR4.AC2 2 Acceptance Code Bit 2 CIDAR4.AC1 1 Acceptance Code Bit 1 CIDAR4.AC0 0 Acceptance Code Bit 0 CIDAR5 0x0119 msCAN12 Identifier Acceptance Register 5 CIDAR5.AC7 7 Acceptance Code Bit 7 CIDAR5.AC6 6 Acceptance Code Bit 6 CIDAR5.AC5 5 Acceptance Code Bit 5 CIDAR5.AC4 4 Acceptance Code Bit 4 CIDAR5.AC3 3 Acceptance Code Bit 3 CIDAR5.AC2 2 Acceptance Code Bit 2 CIDAR5.AC1 1 Acceptance Code Bit 1 CIDAR5.AC0 0 Acceptance Code Bit 0 CIDAR6 0x011A msCAN12 Identifier Acceptance Register 6 CIDAR6.AC7 7 Acceptance Code Bit 7 CIDAR6.AC6 6 Acceptance Code Bit 6 CIDAR6.AC5 5 Acceptance Code Bit 5 CIDAR6.AC4 4 Acceptance Code Bit 4 CIDAR6.AC3 3 Acceptance Code Bit 3 CIDAR6.AC2 2 Acceptance Code Bit 2 CIDAR6.AC1 1 Acceptance Code Bit 1 CIDAR6.AC0 0 Acceptance Code Bit 0 CIDAR7 0x011B msCAN12 Identifier Acceptance Register 7 CIDAR7.AC7 7 Acceptance Code Bit 7 CIDAR7.AC6 6 Acceptance Code Bit 6 CIDAR7.AC5 5 Acceptance Code Bit 5 CIDAR7.AC4 4 Acceptance Code Bit 4 CIDAR7.AC3 3 Acceptance Code Bit 3 CIDAR7.AC2 2 Acceptance Code Bit 2 CIDAR7.AC1 1 Acceptance Code Bit 1 CIDAR7.AC0 0 Acceptance Code Bit 0 CIDMR4 0x011C msCAN12 Identifier Mask Register 4 CIDMR4.AM7 7 Acceptance Mask Bit 7 CIDMR4.AM6 6 Acceptance Mask Bit 6 CIDMR4.AM5 5 Acceptance Mask Bit 5 CIDMR4.AM4 4 Acceptance Mask Bit 4 CIDMR4.AM3 3 Acceptance Mask Bit 3 CIDMR4.AM2 2 Acceptance Mask Bit 2 CIDMR4.AM1 1 Acceptance Mask Bit 1 CIDMR4.AM0 0 Acceptance Mask Bit 0 CIDMR5 0x011D msCAN12 Identifier Mask Register 5 CIDMR5.AM7 7 Acceptance Mask Bit 7 CIDMR5.AM6 6 Acceptance Mask Bit 6 CIDMR5.AM5 5 Acceptance Mask Bit 5 CIDMR5.AM4 4 Acceptance Mask Bit 4 CIDMR5.AM3 3 Acceptance Mask Bit 3 CIDMR5.AM2 2 Acceptance Mask Bit 2 CIDMR5.AM1 1 Acceptance Mask Bit 1 CIDMR5.AM0 0 Acceptance Mask Bit 0 CIDMR6 0x011E msCAN12 Identifier Mask Register 6 CIDMR6.AM7 7 Acceptance Mask Bit 7 CIDMR6.AM6 6 Acceptance Mask Bit 6 CIDMR6.AM5 5 Acceptance Mask Bit 5 CIDMR6.AM4 4 Acceptance Mask Bit 4 CIDMR6.AM3 3 Acceptance Mask Bit 3 CIDMR6.AM2 2 Acceptance Mask Bit 2 CIDMR6.AM1 1 Acceptance Mask Bit 1 CIDMR6.AM0 0 Acceptance Mask Bit 0 CIDMR7 0x011F msCAN12 Identifier Mask Register 7 CIDMR7.AM7 7 Acceptance Mask Bit 7 CIDMR7.AM6 6 Acceptance Mask Bit 6 CIDMR7.AM5 5 Acceptance Mask Bit 5 CIDMR7.AM4 4 Acceptance Mask Bit 4 CIDMR7.AM3 3 Acceptance Mask Bit 3 CIDMR7.AM2 2 Acceptance Mask Bit 2 CIDMR7.AM1 1 Acceptance Mask Bit 1 CIDMR7.AM0 0 Acceptance Mask Bit 0 RESERVED0120 0x0120 RESERVED RESERVED0121 0x0121 RESERVED RESERVED0122 0x0122 RESERVED RESERVED0123 0x0123 RESERVED RESERVED0124 0x0124 RESERVED RESERVED0125 0x0125 RESERVED RESERVED0126 0x0126 RESERVED RESERVED0127 0x0127 RESERVED RESERVED0128 0x0128 RESERVED RESERVED0129 0x0129 RESERVED RESERVED012A 0x012A RESERVED RESERVED012B 0x012B RESERVED RESERVED012C 0x012C RESERVED RESERVED012D 0x012D RESERVED RESERVED012E 0x012E RESERVED RESERVED012F 0x012F RESERVED RESERVED0130 0x0130 RESERVED RESERVED0131 0x0131 RESERVED RESERVED0132 0x0132 RESERVED RESERVED0133 0x0133 RESERVED RESERVED0134 0x0134 RESERVED RESERVED0135 0x0135 RESERVED RESERVED0136 0x0136 RESERVED RESERVED0137 0x0137 RESERVED RESERVED0138 0x0138 RESERVED RESERVED0139 0x0139 RESERVED RESERVED013A 0x013A RESERVED RESERVED013B 0x013B RESERVED RESERVED013C 0x013C RESERVED PCTLCAN 0x013D msCAN12 Port CAN Control Register PCTLCAN.PUECAN 1 Pullup Enable Port CAN Bit PCTLCAN.RDPCAN 0 Reduced Drive Port CAN PORTCAN 0x013E msCAN12 Port CAN Data Register PORTCAN.PCAN7 7 Port CAN Data Bit 7 PORTCAN.PCAN6 6 Port CAN Data Bit 6 PORTCAN.PCAN5 5 Port CAN Data Bit 5 PORTCAN.PCAN4 4 Port CAN Data Bit 4 PORTCAN.PCAN3 3 Port CAN Data Bit 3 PORTCAN.PCAN2 2 Port CAN Data Bit 2 PORTCAN.TxCAN 1 PORTCAN.RxCAN 0 DDRCAN 0x013F msCAN12 Port CAN Data Direction Register DDRCAN.DDRCAN7 7 Data Direction Port CAN Bit 7 DDRCAN.DDRCAN6 6 Data Direction Port CAN Bit 6 DDRCAN.DDRCAN5 5 Data Direction Port CAN Bit 5 DDRCAN.DDRCAN4 4 Data Direction Port CAN Bit 4 DDRCAN.DDRCAN3 3 Data Direction Port CAN Bit 3 DDRCAN.DDRCAN2 2 Data Direction Port CAN Bit 2 .68HC12BE32 ; ; M68HC12B.pdf ; MEMORY MAP area DATA FSR 0x0000:0x0200 REGISTERS 512 BYTES area BSS RESERVED 0x0200:0x0800 area DATA RAM 0x0800:0x0C00 1-KBYTE RAM area BSS RESERVED 0x0C00:0x0D00 area DATA EEPROM 0x0D00:0x1000 768 BYTES EEPROM area BSS RESERVED 0x1000:0x8000 area DATA EEPROM_ROM 0x8000:0xFFC0 FLASH EEPROM/ROM area DATA USER_VEC 0xFFC0:0x10000 ; Interrupt and reset vector assignments interrupt __RESET 0xFFFE Processor reset interrupt CME_FCME 0xFFFC COP clock monitor fail reset interrupt COP_FR 0xFFFA COP failure reset interrupt UIT 0xFFF8 Unimplemented instruction trap interrupt SWI 0xFFF6 SWI interrupt XIRQ 0xFFF4 XIRQ interrupt IRQEN 0xFFF2 IRQ interrupt RTIE 0xFFF0 Real-time interrupt interrupt C0I 0xFFEE Timer channel 0 interrupt C1I 0xFFEC Timer channel 1 interrupt C2I 0xFFEA Timer channel 2 interrupt C3I 0xFFE8 Timer channel 3 interrupt C4I 0xFFE6 Timer channel 4 interrupt C5I 0xFFE4 Timer channel 5 interrupt C6I 0xFFE2 Timer channel 6 interrupt C7I 0xFFE0 Timer channel 7 interrupt TOI 0xFFDE Timer overflow interrupt PAOVI 0xFFDC Pulse accumulator overflow interrupt PAI 0xFFDA Pulse accumulator input edge interrupt SPIE 0xFFD8 SPI serial transfer complete interrupt TIE_TCIE_RIE_ILIE 0xFFD6 SCI 0 interrupt ASCIE 0xFFD2 ATD interrupt IE 0xFFD0 BDLC interrupt MCZI 0xFFCC Modulus down counter underflow interrupt PBOVI 0xFFCA Pulse accumulator B overflow ; INPUT/ OUTPUT PORTS PORTA 0x0000 Port A Data Register PORTA.PA7 7 Port A Data Bit 7 PORTA.PA6 6 Port A Data Bit 6 PORTA.PA5 5 Port A Data Bit 5 PORTA.PA4 4 Port A Data Bit 4 PORTA.PA3 3 Port A Data Bit 3 PORTA.PA2 2 Port A Data Bit 2 PORTA.PA1 1 Port A Data Bit 1 PORTA.PA0 0 Port A Data Bit 0 PORTB 0x0001 Port B Data Register PORTB.PB7 7 Port B Data Bit 7 PORTB.PB6 6 Port B Data Bit 6 PORTB.PB5 5 Port B Data Bit 5 PORTB.PB4 4 Port B Data Bit 4 PORTB.PB3 3 Port B Data Bit 3 PORTB.PB2 2 Port B Data Bit 2 PORTB.PB1 1 Port B Data Bit 1 PORTB.PB0 0 Port B Data Bit 0 DDRA 0x0002 Data Direction Register A DDRA.DDA7 7 Data Direction Register A Bit 7 DDRA.DDA6 6 Data Direction Register A Bit 6 DDRA.DDA5 5 Data Direction Register A Bit 5 DDRA.DDA4 4 Data Direction Register A Bit 4 DDRA.DDA3 3 Data Direction Register A Bit 3 DDRA.DDA2 2 Data Direction Register A Bit 2 DDRA.DDA1 1 Data Direction Register A Bit 1 DDRA.DDA0 0 Data Direction Register A Bit 0 DDRB 0x0003 Data Direction Register B DDRB.DDB7 7 Data Direction Register B Bit 7 DDRB.DDB6 6 Data Direction Register B Bit 6 DDRB.DDB5 5 Data Direction Register B Bit 5 DDRB.DDB4 4 Data Direction Register B Bit 4 DDRB.DDB3 3 Data Direction Register B Bit 3 DDRB.DDB2 2 Data Direction Register B Bit 2 DDRB.DDB1 1 Data Direction Register B Bit 1 DDRB.DDB0 0 Data Direction Register B Bit 0 RESERVED00004 0x0004 RESERVED RESERVED00005 0x0005 RESERVED RESERVED00006 0x0006 RESERVED RESERVED00007 0x0007 RESERVED PORTE 0x0008 Port E Data Register PORTE.PE7 7 Port E Data Bit 7 PORTE.PE6 6 Port E Data Bit 6 PORTE.PE5 5 Port E Data Bit 5 PORTE.PE4 4 Port E Data Bit 4 PORTE.PE3 3 Port E Data Bit 3 PORTE.PE2 2 Port E Data Bit 2 PORTE.PE1 1 Port E Data Bit 1 PORTE.PE0 0 Port E Data Bit 0 DDRE 0x0009 Data Direction Register E DDRE.DDE7 7 Data Direction Register E Bit 7 DDRE.DDE6 6 Data Direction Register E Bit 6 DDRE.DDE5 5 Data Direction Register E Bit 5 DDRE.DDE4 4 Data Direction Register E Bit 4 DDRE.DDE3 3 Data Direction Register E Bit 3 DDRE.DDE2 2 Data Direction Register E Bit 2 DDRE.DDE1 1 Data Direction Register E Bit 1 DDRE.DDE0 0 Data Direction Register E Bit 0 PEAR 0x000A Port E Assignment Register PEAR.NDBE 7 No Data Bus Enable Bit PEAR.CGMTE 6 CGM Test Output Enable PEAR.PIPOE 5 Pipe Signal Output Enable Bit PEAR.NECLK 4 No External E Clock Bit PEAR.LSTRE 3 Low Strobe (LSTRB) Enable Bit PEAR.RDWE 2 Read/Write Enable Bit MODE 0x000B Mode Register MODE.SMODN 7 Mode Select Special MODE.MODB 6 Mode Select Special B Bit MODE.MODA 5 Mode Select Special A Bit MODE.ESTR 4 E Clock Stretch Enable Bit MODE.IVIS 3 Internal Visibility Bit MODE.EBSWAI 2 External Bus Module Stop in Wait Bit MODE.EME 0 Emulate Port E Bit PUCR 0x000C Pullup Control Register PUCR.PUPE 4 Pullup Port E Enable Bit PUCR.PUPB 1 Pullup Port B Enable Bit PUCR.PUPA 0 Pullup Port A Enable Bit RDRIV 0x000D Reduced Drive Register RDRIV.RDPE 3 Reduced Drive of Port E Bit RDRIV.RDPB 1 Reduced Drive of Port B Bit RDRIV.RDPA 0 Reduced Drive of Port A Bit RESERVED000E 0x000E RESERVED RESERVED000F 0x000F RESERVED INITRM 0x0010 RAM Initialization Register INITRM.RAM15 7 RAM Position Bit 15 INITRM.RAM14 6 RAM Position Bit 14 INITRM.RAM13 5 RAM Position Bit 13 INITRM.RAM12 4 RAM Position Bit 12 INITRM.RAM11 3 RAM Position Bit 11 INITRG 0x0011 Register Initialization Register INITRG.REG15 7 Register Position Bit 15 INITRG.REG14 6 Register Position Bit 14 INITRG.REG13 5 Register Position Bit 13 INITRG.REG12 4 Register Position Bit 12 INITRG.REG11 3 Register Position Bit 11 INITRG.MMSWAI 0 Memory Mapping Interface Stop in Wait Control Bit INITEE 0x0012 EEPROM Initialization Register INITEE.EE15 7 Internal EEPROM Position Bit 15 INITEE.EE14 6 Internal EEPROM Position Bit 14 INITEE.EE13 5 Internal EEPROM Position Bit 13 INITEE.EE12 4 Internal EEPROM Position Bit 12 INITEE.EEON 0 EEPROM On Bit MISC 0x0013 Miscellaneous Mapping Control Register MISC.NDRF 6 Narrow Data Bus for Register-Following Map Bit MISC.RFSTR1 5 Register-Following Stretch Bit 1 MISC.RFSTR0 4 Register-Following Stretch Bit 0 MISC.EXSTR1 3 External Access Stretch Bit 1 MISC.EXSTR0 2 External Access Stretch Bit 0 MISC.MAPROM 1 FLASH EEPROM/ROM Map Bit MISC.ROMON 0 FLASH EEPROM/ROM Enable Bit RTICTL 0x0014 Real-Time Interrupt Control Register RTICTL.RTIE 7 Real-Time Interrupt Enable Bit RTICTL.RSWAI 6 RTI and COP Stop While in Wait Bit RTICTL.RSBCK 5 RTI and COP Stop While in Background Debug Mode Bit RTICTL.RTBYP 3 Real-Time Interrupt Divider Chain Bypass Bit RTICTL.RTR2 2 Real-Time Interrupt Rate Select Bit 2 RTICTL.RTR1 1 Real-Time Interrupt Rate Select Bit 1 RTICTL.RTR0 0 Real-Time Interrupt Rate Select Bit 0 RTIFLG 0x0015 Real-Time Interrupt Flag Register RTIFLG.RTIF 7 Real-Time Interrupt Flag Bit COPCTL 0x0016 COP Control Register COPCTL.CME 7 Clock Monitor Enable Bit COPCTL.FCME 6 Force Clock Monitor Enable Bit COPCTL.FCM 5 Force Clock Monitor Reset Bit COPCTL.FCOP 4 Force COP Watchdog Reset Bit COPCTL.DISR 3 Disable Resets from COP Watchdog and Clock Monitor Bit COPCTL.CR2 2 COP Watchdog Timer Rate Select Bit 2 COPCTL.CR1 1 COP Watchdog Timer Rate Select Bit 1 COPCTL.CR0 0 COP Watchdog Timer Rate Select Bit 0 COPRST 0x0017 Arm/Reset COP Timer Register RESERVED0018 0x0018 RESERVED RESERVED0019 0x0019 RESERVED RESERVED001A 0x001A RESERVED RESERVED001B 0x001B RESERVED RESERVED001C 0x001C RESERVED RESERVED001D 0x001D RESERVED INTCR 0x001E Interrupt Control Register INTCR.IRQE 7 IRQ Edge-Sensitive Only Bit INTCR.IRQEN 6 External IRQ Enable Bit INTCR.DLY 5 Oscillator Startup Delay on Exit from Stop Mode Bit HPRIO 0x001F Highest Priority I Interrupt Register HPRIO.PSEL5 5 HPRIO.PSEL4 4 HPRIO.PSEL3 3 HPRIO.PSEL2 2 HPRIO.PSEL1 1 BRKCT0 0x0020 Breakpoint Control Register 0 BRKCT0.BKEN1 7 Breakpoint Mode Enable Bit 1 BRKCT0.BKEN0 6 Breakpoint Mode Enable Bit 0 BRKCT0.BKPM 5 Break on Program Addresses BRKCT0.BK1ALE 3 Breakpoint 1 Range Control Bit BRKCT0.BK0ALE 2 Breakpoint 0 Range Control Bit BRKCT1 0x0021 Breakpoint Control Register 1 BRKCT1.BKDBE 6 Enable Data Bus Bit BRKCT1.BKMBH 5 Breakpoint Mask High Bit BRKCT1.BKMBL 4 Breakpoint Mask Low Bit BRKCT1.BK1RWE 3 R/W Compare Enable Bit BRKCT1.BK1RW 2 R/W Compare Value Bit BRKCT1.BK0RWE 1 R/W Compare Enable Bit BRKCT1.BK0RW 0 R/W Compare Value Bit BRKAH 0x0022 Breakpoint Address Register High BRKAL 0x0023 Breakpoint Address Register Low BRKDH 0x0024 Breakpoint Data Register High BRKDL 0x0025 Breakpoint Data Register Low RESERVED0026 0x0026 RESERVED RESERVED0027 0x0027 RESERVED RESERVED0028 0x0028 RESERVED RESERVED0029 0x0029 RESERVED RESERVED002A 0x002A RESERVED RESERVED002B 0x002B RESERVED RESERVED002C 0x002C RESERVED RESERVED002D 0x002D RESERVED RESERVED002E 0x002E RESERVED RESERVED002F 0x002F RESERVED RESERVED0030 0x0030 RESERVED RESERVED0031 0x0031 RESERVED RESERVED0032 0x0032 RESERVED RESERVED0033 0x0033 RESERVED RESERVED0034 0x0034 RESERVED RESERVED0035 0x0035 RESERVED RESERVED0036 0x0036 RESERVED RESERVED0037 0x0037 RESERVED RESERVED0038 0x0038 RESERVED RESERVED0039 0x0039 RESERVED RESERVED003A 0x003A RESERVED RESERVED003B 0x003B RESERVED RESERVED003C 0x003C RESERVED RESERVED003D 0x003D RESERVED RESERVED003E 0x003E RESERVED RESERVED003F 0x003F RESERVED PWCLK 0x0040 PWM Clocks and Concatenate Register PWCLK.CON23 7 Concatenate PWM Channels 2 and 3 Bit PWCLK.CON01 6 Concatenate PWM Channels 0 and 1 Bit PWCLK.PCKA2 5 Prescaler for Clock A Bit 2 PWCLK.PCKA1 4 Prescaler for Clock A Bit 1 PWCLK.PCKA0 3 Prescaler for Clock A Bit 0 PWCLK.PCKB2 2 Prescaler for Clock B Bit 2 PWCLK.PCKB1 1 Prescaler for Clock B Bit 1 PWCLK.PCKB0 0 Prescaler for Clock B Bit 0 PWPOL 0x0041 PWM Clock Select and Polarity Register PWPOL.PCLK3 7 PWM Channel 3 Clock Select Bit PWPOL.PCLK2 6 PWM Channel 2 Clock Select Bit PWPOL.PCLK1 5 PWM Channel 1 Clock Select Bit PWPOL.PCLK0 4 PWM Channel 0 Clock Select Bit PWPOL.PPOL3 3 PWM Channel 3 Polarity Bit PWPOL.PPOL2 2 PWM Channel 2 Polarity Bit PWPOL.PPOL1 1 PWM Channel 1 Polarity Bit PWPOL.PPOL0 0 PWM Channel 0 Polarity Bit PWEN 0x0042 PWM Enable Register PWEN.PWEN3 3 PWM Channel 3 Enable Bit PWEN.PWEN2 2 PWM Channel 2 Enable Bit PWEN.PWEN1 1 PWM Channel 1 Enable Bit PWEN.PWEN0 0 PWM Channel 0 Enable Bit PWPRES 0x0043 PWM Prescaler Counter Register PWSCAL0 0x0044 PWM Scale Register 0 PWSCNT0 0x0045 PWM Scale Counter Register 0 PWSCAL1 0x0046 PWM Scale Register 1 PWSCNT1 0x0047 PWM Scale Counter Register 1 PWCNT0 0x0048 PWM Channel Counter Register 0 PWCNT1 0x0049 PWM Channel Counter Register 1 PWCNT2 0x004A PWM Channel Counter Register 2 PWCNT3 0x004B PWM Channel Counter Register 3 PWPER0 0x004C PWM Channel Period Register 0 PWPER1 0x004D PWM Channel Period Register 1 PWPER2 0x004E PWM Channel Period Register 2 PWPER3 0x004F PWM Channel Period Register 3 PWDTY0 0x0050 PWM Channel Duty Register 0 PWDTY1 0x0051 PWM Channel Duty Register 1 PWDTY2 0x0052 PWM Channel Duty Register 2 PWDTY3 0x0053 PWM Channel Duty Register 3 PWCTL 0x0054 PWM Control Register PWCTL.PSWAI 4 PWM Halts While in Wait Mode Bit PWCTL.CENTR 3 Center-Aligned Output Mode Bit PWCTL.RDPP 2 Reduced Drive of Port P Bit PWCTL.PUPP 1 Pullup Port P Enable Bit PWCTL.PSBCK 0 PWM Stops While in Background Mode Bit PWTST 0x0055 PWM Special Mode Register PWTST.DISCR 7 Disable Channel Counter Reset Bit PWTST.DISCP 6 Disable Compare Count Period Bit PWTST.DISCAL 5 Disable Scale Counter Loading Bit PORTP 0x0056 Port P Data Register PORTP.PP7 7 Port P Data Bit 7 PORTP.PP6 6 Port P Data Bit 6 PORTP.PP5 5 Port P Data Bit 5 PORTP.PP4 4 Port P Data Bit 4 PORTP.PP3 3 Port P Data Bit 3 PORTP.PP2 2 Port P Data Bit 2 PORTP.PP1 1 Port P Data Bit 1 PORTP.PP0 0 Port P Data Bit 0 DDRP 0x0057 Port P Data Direction Register DDRP.DDP7 7 Port P Data Direction Register Bit 7 DDRP.DDP6 6 Port P Data Direction Register Bit 6 DDRP.DDP5 5 Port P Data Direction Register Bit 5 DDRP.DDP4 4 Port P Data Direction Register Bit 4 DDRP.DDP3 3 Port P Data Direction Register Bit 3 DDRP.DDP2 2 Port P Data Direction Register Bit 2 DDRP.DDP1 1 Port P Data Direction Register Bit 1 DDRP.DDP0 0 Port P Data Direction Register Bit 0 RESERVED0058 0x0058 RESERVED RESERVED0059 0x0059 RESERVED RESERVED005A 0x005A RESERVED RESERVED005B 0x005B RESERVED RESERVED005C 0x005C RESERVED RESERVED005D 0x005D RESERVED RESERVED005E 0x005E RESERVED RESERVED005F 0x005F RESERVED ATDCTL0 0x0060 ATD Control Register 0 ATDCTL1 0x0061 ATD Control Register 1 ATDCTL2 0x0062 ATD Control Register 2 ATDCTL2.ADPU 7 ATD Disable Bit ATDCTL2.AFFC 6 ATD Fast Flag Clear Bit ATDCTL2.AWAI 5 ATD Stop in Wait Mode Bit ATDCTL2.ASCIE 1 ATD Sequence Complete Interrupt Enable Bit ATDCTL2.ASCIF 0 ATD Sequence Complete Interrupt Flag ATDCTL3 0x0063 ATD Control Register 3 ATDCTL3.FRZ1 1 Background Debug (Freeze) Enable Bit ATDCTL3.FRZ0 0 Background Debug (Freeze) Enable Bit ATDCTL4 0x0064 ATD Control Register 4 ATDCTL4.S10BM 7 ATD 10-Bit Mode Control Bit ATDCTL4.SMP1 6 Select Sample Time Bit 1 ATDCTL4.SMP0 5 Select Sample Time Bit 0 ATDCTL4.PRS4 4 Select Divide-By Factor for ATD P-Clock Prescaler Bit 4 ATDCTL4.PRS3 3 Select Divide-By Factor for ATD P-Clock Prescaler Bit 3 ATDCTL4.PRS2 2 Select Divide-By Factor for ATD P-Clock Prescaler Bit 2 ATDCTL4.PRS1 1 Select Divide-By Factor for ATD P-Clock Prescaler Bit 1 ATDCTL4.PRS0 0 Select Divide-By Factor for ATD P-Clock Prescaler Bit 0 ATDCTL5 0x0065 ATD Control Register 5 ATDCTL5.S8CM 6 Select 8 Channel Mode Bit ATDCTL5.SCAN 5 Enable Continuous Channel Scan Bit ATDCTL5.MULT 4 Enable Multichannel Conversion Bit ATDCTL5.CD 3 Channel Select for Conversion Bit ATDCTL5.CC 2 Channel Select for Conversion Bit ATDCTL5.CB 1 Channel Select for Conversion Bit ATDCTL5.CA 0 Channel Select for Conversion Bit ATDSTAT 0x0066 ATD Status Register ATDSTAT.SCF 7 Sequence Complete Flag ATDSTAT.CC2 2 Conversion Counter Bit 2 for Current 4 or 8 Conversions ATDSTAT.CC1 1 Conversion Counter Bit 1 for Current 4 or 8 Conversions ATDSTAT.CC0 0 Conversion Counter Bit 0 for Current 4 or 8 Conversions ATDSTTL 0x0067 ATD Status Register ATDSTTL.CCF7 7 Sequence Complete Flag 7 ATDSTTL.CCF6 6 Sequence Complete Flag 6 ATDSTTL.CCF5 5 Sequence Complete Flag 5 ATDSTTL.CCF4 4 Sequence Complete Flag 4 ATDSTTL.CCF3 3 Sequence Complete Flag 3 ATDSTTL.CCF2 2 Sequence Complete Flag 2 ATDSTTL.CCF1 1 Sequence Complete Flag 1 ATDSTTL.CCF0 0 Sequence Complete Flag 0 ATDTSTH 0x0068 ATD Test Register High ATDTSTH.SAR9 7 SAR Data Bit 9 ATDTSTH.SAR8 6 SAR Data Bit 8 ATDTSTH.SAR7 5 SAR Data Bit 7 ATDTSTH.SAR6 4 SAR Data Bit 6 ATDTSTH.SAR5 3 SAR Data Bit 5 ATDTSTH.SAR4 2 SAR Data Bit 4 ATDTSTH.SAR3 1 SAR Data Bit 3 ATDTSTH.SAR2 0 SAR Data Bit 2 ATDTSTL 0x0069 ATD Test Register Low ATDTSTL.SAR1 7 SAR Data Bit 1 ATDTSTL.SAR0 6 SAR Data Bit 0 ATDTSTL.RST 5 Module Reset Bit ATDTSTL.TSTOUT 4 Multiplex Output of TST3-TST0 (Factory Use) ATDTSTL.TST3 3 Test Bits 3 ATDTSTL.TST2 2 Test Bits 2 ATDTSTL.TST1 1 Test Bits 1 ATDTSTL.TST0 0 Test Bits 0 RESERVED006A 0x006A RESERVED RESERVED006B 0x006B RESERVED RESERVED006C 0x006C RESERVED RESERVED006D 0x006D RESERVED RESERVED006E 0x006E RESERVED PORTAD 0x006F Port AD Data Input Register PORTAD.PAD7 7 Port AD Data Input Bit 7 PORTAD.PAD6 6 Port AD Data Input Bit 6 PORTAD.PAD5 5 Port AD Data Input Bit 5 PORTAD.PAD4 4 Port AD Data Input Bit 4 PORTAD.PAD3 3 Port AD Data Input Bit 3 PORTAD.PAD2 2 Port AD Data Input Bit 2 PORTAD.PAD1 1 Port AD Data Input Bit 1 PORTAD.PAD0 0 Port AD Data Input Bit 0 ADRx0H 0x0070 ATD Result Register 0 High ADRx0H.ADRxH15 7 ATD Conversion Result Bit 15 ADRx0H.ADRxH14 6 ATD Conversion Result Bit 14 ADRx0H.ADRxH13 5 ATD Conversion Result Bit 13 ADRx0H.ADRxH12 4 ATD Conversion Result Bit 12 ADRx0H.ADRxH11 3 ATD Conversion Result Bit 11 ADRx0H.ADRxH10 2 ATD Conversion Result Bit 10 ADRx0H.ADRxH9 1 ATD Conversion Result Bit 9 ADRx0H.ADRxH8 0 ATD Conversion Result Bit 8 ADRx0L 0x0071 ATD Result Register 0 Low ADRx0L.ADRxHL7 7 ATD Conversion Result Bit 7 ADRx0L.ADRxHL6 6 ATD Conversion Result Bit 6 ADRx0L.ADRxHL5 5 ATD Conversion Result Bit 5 ADRx0L.ADRxHL4 4 ATD Conversion Result Bit 4 ADRx0L.ADRxHL3 3 ATD Conversion Result Bit 3 ADRx0L.ADRxHL2 2 ATD Conversion Result Bit 2 ADRx0L.ADRxHL1 1 ATD Conversion Result Bit 1 ADRx0L.ADRxHL0 0 ATD Conversion Result Bit 0 ADRx1H 0x0072 ATD Result Register 1 High ADRx1H.ADRxH15 7 ATD Conversion Result Bit 15 ADRx1H.ADRxH14 6 ATD Conversion Result Bit 14 ADRx1H.ADRxH13 5 ATD Conversion Result Bit 13 ADRx1H.ADRxH12 4 ATD Conversion Result Bit 12 ADRx1H.ADRxH11 3 ATD Conversion Result Bit 11 ADRx1H.ADRxH10 2 ATD Conversion Result Bit 10 ADRx1H.ADRxH9 1 ATD Conversion Result Bit 9 ADRx1H.ADRxH8 0 ATD Conversion Result Bit 8 ADRx1L 0x0073 ATD Result Register 1 Low ADRx1L.ADRxHL7 7 ATD Conversion Result Bit 7 ADRx1L.ADRxHL6 6 ATD Conversion Result Bit 6 ADRx1L.ADRxHL5 5 ATD Conversion Result Bit 5 ADRx1L.ADRxHL4 4 ATD Conversion Result Bit 4 ADRx1L.ADRxHL3 3 ATD Conversion Result Bit 3 ADRx1L.ADRxHL2 2 ATD Conversion Result Bit 2 ADRx1L.ADRxHL1 1 ATD Conversion Result Bit 1 ADRx1L.ADRxHL0 0 ATD Conversion Result Bit 0 ADRx2H 0x0074 ATD Result Register 2 High ADRx2H.ADRxH15 7 ATD Conversion Result Bit 15 ADRx2H.ADRxH14 6 ATD Conversion Result Bit 14 ADRx2H.ADRxH13 5 ATD Conversion Result Bit 13 ADRx2H.ADRxH12 4 ATD Conversion Result Bit 12 ADRx2H.ADRxH11 3 ATD Conversion Result Bit 11 ADRx2H.ADRxH10 2 ATD Conversion Result Bit 10 ADRx2H.ADRxH9 1 ATD Conversion Result Bit 9 ADRx2H.ADRxH8 0 ATD Conversion Result Bit 8 ADRx2L 0x0075 ATD Result Register 2 Low ADRx2L.ADRxHL7 7 ATD Conversion Result Bit 7 ADRx2L.ADRxHL6 6 ATD Conversion Result Bit 6 ADRx2L.ADRxHL5 5 ATD Conversion Result Bit 5 ADRx2L.ADRxHL4 4 ATD Conversion Result Bit 4 ADRx2L.ADRxHL3 3 ATD Conversion Result Bit 3 ADRx2L.ADRxHL2 2 ATD Conversion Result Bit 2 ADRx2L.ADRxHL1 1 ATD Conversion Result Bit 1 ADRx2L.ADRxHL0 0 ATD Conversion Result Bit 0 ADRx3H 0x0076 ATD Result Register 3 High ADRx3H.ADRxH15 7 ATD Conversion Result Bit 15 ADRx3H.ADRxH14 6 ATD Conversion Result Bit 14 ADRx3H.ADRxH13 5 ATD Conversion Result Bit 13 ADRx3H.ADRxH12 4 ATD Conversion Result Bit 12 ADRx3H.ADRxH11 3 ATD Conversion Result Bit 11 ADRx3H.ADRxH10 2 ATD Conversion Result Bit 10 ADRx3H.ADRxH9 1 ATD Conversion Result Bit 9 ADRx3H.ADRxH8 0 ATD Conversion Result Bit 8 ADRx3L 0x0077 ATD Result Register 3 Low ADRx3L.ADRxHL7 7 ATD Conversion Result Bit 7 ADRx3L.ADRxHL6 6 ATD Conversion Result Bit 6 ADRx3L.ADRxHL5 5 ATD Conversion Result Bit 5 ADRx3L.ADRxHL4 4 ATD Conversion Result Bit 4 ADRx3L.ADRxHL3 3 ATD Conversion Result Bit 3 ADRx3L.ADRxHL2 2 ATD Conversion Result Bit 2 ADRx3L.ADRxHL1 1 ATD Conversion Result Bit 1 ADRx3L.ADRxHL0 0 ATD Conversion Result Bit 0 ADRx4H 0x0078 ATD Result Register 4 High ADRx4H.ADRxH15 7 ATD Conversion Result Bit 15 ADRx4H.ADRxH14 6 ATD Conversion Result Bit 14 ADRx4H.ADRxH13 5 ATD Conversion Result Bit 13 ADRx4H.ADRxH12 4 ATD Conversion Result Bit 12 ADRx4H.ADRxH11 3 ATD Conversion Result Bit 11 ADRx4H.ADRxH10 2 ATD Conversion Result Bit 10 ADRx4H.ADRxH9 1 ATD Conversion Result Bit 9 ADRx4H.ADRxH8 0 ATD Conversion Result Bit 8 ADRx4L 0x0079 ATD Result Register 4 Low ADRx4L.ADRxHL7 7 ATD Conversion Result Bit 7 ADRx4L.ADRxHL6 6 ATD Conversion Result Bit 6 ADRx4L.ADRxHL5 5 ATD Conversion Result Bit 5 ADRx4L.ADRxHL4 4 ATD Conversion Result Bit 4 ADRx4L.ADRxHL3 3 ATD Conversion Result Bit 3 ADRx4L.ADRxHL2 2 ATD Conversion Result Bit 2 ADRx4L.ADRxHL1 1 ATD Conversion Result Bit 1 ADRx4L.ADRxHL0 0 ATD Conversion Result Bit 0 ADRx5H 0x007A ATD Result Register 5 High ADRx5H.ADRxH15 7 ATD Conversion Result Bit 15 ADRx5H.ADRxH14 6 ATD Conversion Result Bit 14 ADRx5H.ADRxH13 5 ATD Conversion Result Bit 13 ADRx5H.ADRxH12 4 ATD Conversion Result Bit 12 ADRx5H.ADRxH11 3 ATD Conversion Result Bit 11 ADRx5H.ADRxH10 2 ATD Conversion Result Bit 10 ADRx5H.ADRxH9 1 ATD Conversion Result Bit 9 ADRx5H.ADRxH8 0 ATD Conversion Result Bit 8 ADRx5L 0x007B ATD Result Register 5 Low ADRx5L.ADRxHL7 7 ATD Conversion Result Bit 7 ADRx5L.ADRxHL6 6 ATD Conversion Result Bit 6 ADRx5L.ADRxHL5 5 ATD Conversion Result Bit 5 ADRx5L.ADRxHL4 4 ATD Conversion Result Bit 4 ADRx5L.ADRxHL3 3 ATD Conversion Result Bit 3 ADRx5L.ADRxHL2 2 ATD Conversion Result Bit 2 ADRx5L.ADRxHL1 1 ATD Conversion Result Bit 1 ADRx5L.ADRxHL0 0 ATD Conversion Result Bit 0 ADRx6H 0x007C ATD Result Register 6 High ADRx6H.ADRxH15 7 ATD Conversion Result Bit 15 ADRx6H.ADRxH14 6 ATD Conversion Result Bit 14 ADRx6H.ADRxH13 5 ATD Conversion Result Bit 13 ADRx6H.ADRxH12 4 ATD Conversion Result Bit 12 ADRx6H.ADRxH11 3 ATD Conversion Result Bit 11 ADRx6H.ADRxH10 2 ATD Conversion Result Bit 10 ADRx6H.ADRxH9 1 ATD Conversion Result Bit 9 ADRx6H.ADRxH8 0 ATD Conversion Result Bit 8 ADRx6L 0x007D ATD Result Register 6 Low ADRx6L.ADRxHL7 7 ATD Conversion Result Bit 7 ADRx6L.ADRxHL6 6 ATD Conversion Result Bit 6 ADRx6L.ADRxHL5 5 ATD Conversion Result Bit 5 ADRx6L.ADRxHL4 4 ATD Conversion Result Bit 4 ADRx6L.ADRxHL3 3 ATD Conversion Result Bit 3 ADRx6L.ADRxHL2 2 ATD Conversion Result Bit 2 ADRx6L.ADRxHL1 1 ATD Conversion Result Bit 1 ADRx6L.ADRxHL0 0 ATD Conversion Result Bit 0 ADRx7H 0x007E ATD Result Register 7 High ADRx7H.ADRxH15 7 ATD Conversion Result Bit 15 ADRx7H.ADRxH14 6 ATD Conversion Result Bit 14 ADRx7H.ADRxH13 5 ATD Conversion Result Bit 13 ADRx7H.ADRxH12 4 ATD Conversion Result Bit 12 ADRx7H.ADRxH11 3 ATD Conversion Result Bit 11 ADRx7H.ADRxH10 2 ATD Conversion Result Bit 10 ADRx7H.ADRxH9 1 ATD Conversion Result Bit 9 ADRx7H.ADRxH8 0 ATD Conversion Result Bit 8 ADRx7L 0x007F ATD Result Register 7 Low ADRx7L.ADRxHL7 7 ATD Conversion Result Bit 7 ADRx7L.ADRxHL6 6 ATD Conversion Result Bit 6 ADRx7L.ADRxHL5 5 ATD Conversion Result Bit 5 ADRx7L.ADRxHL4 4 ATD Conversion Result Bit 4 ADRx7L.ADRxHL3 3 ATD Conversion Result Bit 3 ADRx7L.ADRxHL2 2 ATD Conversion Result Bit 2 ADRx7L.ADRxHL1 1 ATD Conversion Result Bit 1 ADRx7L.ADRxHL0 0 ATD Conversion Result Bit 0 TIOS 0x0080 Timer IC/OC Select Register TIOS.IOS7 7 Force Output Compare Action Bits for Channel 7 TIOS.IOS6 6 Force Output Compare Action Bits for Channel 6 TIOS.IOS5 5 Force Output Compare Action Bits for Channel 5 TIOS.IOS4 4 Force Output Compare Action Bits for Channel 4 TIOS.IOS3 3 Force Output Compare Action Bits for Channel 3 TIOS.IOS2 2 Force Output Compare Action Bits for Channel 2 TIOS.IOS1 1 Force Output Compare Action Bits for Channel 1 TIOS.IOS0 0 Force Output Compare Action Bits for Channel 0 CFORC 0x0081 Timer Compare Force Register CFORC.FOC7 7 Force Output Compare Action Bits for Channel 7 CFORC.FOC6 6 Force Output Compare Action Bits for Channel 6 CFORC.FOC5 5 Force Output Compare Action Bits for Channel 5 CFORC.FOC4 4 Force Output Compare Action Bits for Channel 4 CFORC.FOC3 3 Force Output Compare Action Bits for Channel 3 CFORC.FOC2 2 Force Output Compare Action Bits for Channel 2 CFORC.FOC1 1 Force Output Compare Action Bits for Channel 1 CFORC.FOC0 0 Force Output Compare Action Bits for Channel 0 OC7M 0x0082 Timer Output Compare 7 Mask Register OC7M.OC7M7 7 OC7M.OC7M6 6 OC7M.OC7M5 5 OC7M.OC7M4 4 OC7M.OC7M3 3 OC7M.OC7M2 2 OC7M.OC7M1 1 OC7M.OC7M0 0 OC7D 0x0083 Timer Output Compare 7 Data Register OC7D.OC7D7 7 OC7D.OC7D6 6 OC7D.OC7D5 5 OC7D.OC7D4 4 OC7D.OC7D3 3 OC7D.OC7D2 2 OC7D.OC7D1 1 OC7D.OC7D0 0 TCNTH 0x0084 Timer Count Register High TCNTL 0x0085 Timer Count Register Low TSCR 0x0086 Timer System Control Register TSCR.TEN 7 Timer Enable Bit TSCR.TSWAI 6 Timer Stops While in Wait Bit TSCR.TSBCK 5 Timer Stops While in Background Mode Bit TSCR.TFFCA 4 Timer Fast Flag Clear All Bit RESERVED0087 0x0087 RESERVED TCTL1 0x0088 Timer Control Register 1 TCTL1.OM7 7 Output mode 7 TCTL1.OL7 6 Output level 7 TCTL1.OM6 5 Output mode 6 TCTL1.OL6 4 Output level 6 TCTL1.OM5 3 Output mode 5 TCTL1.OL5 2 Output level 5 TCTL1.OM4 1 Output mode 4 TCTL1.OL4 0 Output level 4 TCTL2 0x0089 Timer Control Register 2 TCTL2.OM3 7 Output mode 3 TCTL2.OL3 6 Output level 3 TCTL2.OM2 5 Output mode 2 TCTL2.OL2 4 Output level 2 TCTL2.OM1 3 Output mode 1 TCTL2.OL1 2 Output level 1 TCTL2.OM0 1 Output mode 0 TCTL2.OL0 0 Output level 0 TCTL3 0x008A Timer Control Register 3 TCTL3.EDG7B 7 Input Capture Edge Control Bit 7B TCTL3.EDG7A 6 Input Capture Edge Control Bit 7A TCTL3.EDG6B 5 Input Capture Edge Control Bit 6B TCTL3.EDG6A 4 Input Capture Edge Control Bit 6A TCTL3.EDG5B 3 Input Capture Edge Control Bit 5B TCTL3.EDG5A 2 Input Capture Edge Control Bit 5A TCTL3.EDG4B 1 Input Capture Edge Control Bit 4B TCTL3.EDG4A 0 Input Capture Edge Control Bit 4A TCTL4 0x008B Timer Control Register 4 TCTL4.EDG3B 7 Input Capture Edge Control Bit 3B TCTL4.EDG3A 6 Input Capture Edge Control Bit 3A TCTL4.EDG2B 5 Input Capture Edge Control Bit 2B TCTL4.EDG2A 4 Input Capture Edge Control Bit 2A TCTL4.EDG1B 3 Input Capture Edge Control Bit 1B TCTL4.EDG1A 2 Input Capture Edge Control Bit 1A TCTL4.EDG0B 1 Input Capture Edge Control Bit 0B TCTL4.EDG0A 0 Input Capture Edge Control Bit 0A TMSK1 0x008C Timer Mask Register 1 TMSK1.C7I 7 Input Capture/Output Compare 1 Interrupt Enable Bit 7 TMSK1.C6I 6 Input Capture/Output Compare 1 Interrupt Enable Bit 6 TMSK1.C5I 5 Input Capture/Output Compare 1 Interrupt Enable Bit 5 TMSK1.C4I 4 Input Capture/Output Compare 1 Interrupt Enable Bit 4 TMSK1.C3I 3 Input Capture/Output Compare 1 Interrupt Enable Bit 3 TMSK1.C2I 2 Input Capture/Output Compare 1 Interrupt Enable Bit 2 TMSK1.C1I 1 Input Capture/Output Compare 1 Interrupt Enable Bit 1 TMSK1.C0I 0 Input Capture/Output Compare 1 Interrupt Enable Bit 0 TMSK2 0x008D Timer Mask Register 2 TMSK2.TOI 7 Timer Overflow Interrupt Enable Bit TMSK2.PUPT 5 Timer Pullup Resistor Enable Bit TMSK2.RDPT 4 Timer Drive Reduction Bit TMSK2.TCRE 3 Timer Counter Reset Enable Bit TMSK2.PR2 2 Timer Prescaler Select Bit 2 TMSK2.PR1 1 Timer Prescaler Select Bit 1 TMSK2.PR0 0 Timer Prescaler Select Bit 0 TFLG1 0x008E Timer Interrupt Flag Register 1 TFLG1.C7F 7 Input Capture/Output Compare Channel 7 Flag TFLG1.C6F 6 Input Capture/Output Compare Channel 6 Flag TFLG1.C5F 5 Input Capture/Output Compare Channel 5 Flag TFLG1.C4F 4 Input Capture/Output Compare Channel 4 Flag TFLG1.C3F 3 Input Capture/Output Compare Channel 3 Flag TFLG1.C2F 2 Input Capture/Output Compare Channel 2 Flag TFLG1.C1F 1 Input Capture/Output Compare Channel 1 Flag TFLG1.C0F 0 Input Capture/Output Compare Channel 0 Flag TFLG2 0x008F Timer Interrupt Flag Register 2 TFLG2.TOF 7 Timer Overflow Flag TC0H 0x0090 Timer Input Capture/Output Compare 0 Register High TC0L 0x0091 Timer Input Capture/Output Compare 0 Register Low TC1H 0x0092 Timer Input Capture/Output Compare 1 Register High TC1L 0x0093 Timer Input Capture/Output Compare 1 Register Low TC2H 0x0094 Timer Input Capture/Output Compare 2 Register High TC2L 0x0095 Timer Input Capture/Output Compare 2 Register Low TC3H 0x0096 Timer Input Capture/Output Compare 3 Register High TC3L 0x0097 Timer Input Capture/Output Compare 3 Register Low TC4H 0x0098 Timer Input Capture/Output Compare 4 Register High TC4L 0x0099 Timer Input Capture/Output Compare 4 Register Low TC5H 0x009A Timer Input Capture/Output Compare 5 Register High TC5L 0x009B Timer Input Capture/Output Compare 5 Register Low TC6H 0x009C Timer Input Capture/Output Compare 6 Register High TC6L 0x009D Timer Input Capture/Output Compare 6 Register Low TC7H 0x009E Timer Input Capture/Output Compare 7 Register High TC7L 0x009F Timer Input Capture/Output Compare 7 Register Low PACTL 0x00A0 Pulse Accumulator Control Register PACTL.PAEN 6 Pulse Accumulator System Enable Bit PACTL.PAMOD 5 Pulse Accumulator Mode Bit PACTL.PEDGE 4 Pulse Accumulator Edge Control Bit PACTL.CLK1 3 Clock Select Bit 1 PACTL.CLK0 2 Clock Select Bits 0 PACTL.PAOVI 1 Pulse Accumulator Overflow Interrupt Enable Bit PACTL.PAI 0 Pulse Accumulator Input Interrupt Enable Bit PAFLG 0x00A1 Pulse Accumulator Flag Register PAFLG.PAOVF 1 Pulse Accumulator Overflow Flag PAFLG.PAIF 0 Pulse Accumulator Input Edge Flag PACN3 0x00A2 Pulse Accumulator Count Register 3 PACN2 0x00A3 Pulse Accumulator Count Register 2 PACN1 0x00A4 Pulse Accumulator Count Register 1 PACN0 0x00A5 Pulse Accumulator Count Register 0 MCCTL 0x00A6 16-Bit Modulus Down-Counter Control Regster MCCTL.MCZI 7 Modulus Counter Underflow Interrupt Enable Bit MCCTL.MODMC 6 Modulus Mode Enable Bit MCCTL.RDMCL 5 Read Modulus Down-Counter Load Bit MCCTL.ICLAT 4 Input Capture Force Latch Action Bit MCCTL.FLMC 3 Force Load Register into the Modulus Counter Count Register Bit MCCTL.MCEN 2 Modulus Down-Counter Enable Bit MCCTL.MCPR1 1 Modulus Counter Prescaler Select Bit 1 MCCTL.MCPR0 0 Modulus Counter Prescaler Select Bit 0 MCFLG 0x00A7 16-Bit Modulus Down-Counter Flag Regster MCFLG.MCZF 7 Modulus Counter Underflow Interrupt Flag MCFLG.POLF3 3 First Input Capture Polarity Status Bit 3 MCFLG.POLF2 2 First Input Capture Polarity Status Bit 2 MCFLG.POLF1 1 First Input Capture Polarity Status Bit 1 MCFLG.POLF0 0 First Input Capture Polarity Status Bit 0 ICPACR 0x00A8 Input Control Pulse Accumulators Control Register ICPACR.PA3EN 3 8-Bit Pulse Accumulator 3 Enable Bit ICPACR.PA2EN 2 8-Bit Pulse Accumulator 2 Enable Bit ICPACR.PA1EN 1 8-Bit Pulse Accumulator 1 Enable Bit ICPACR.PA0EN 0 8-Bit Pulse Accumulator 0 Enable Bit DLYCT 0x00A9 Delay Counter Control Register DLYCT.DLY1 1 Delay Counter Select Bit 1 DLYCT.DLY0 0 Delay Counter Select Bit 0 ICOVW 0x00AA Input Control Overwrite Register ICOVW.NOVW7 7 No Input Capture Overwrite Bit 7 ICOVW.NOVW6 6 No Input Capture Overwrite Bit 6 ICOVW.NOVW5 5 No Input Capture Overwrite Bit 5 ICOVW.NOVW4 4 No Input Capture Overwrite Bit 4 ICOVW.NOVW3 3 No Input Capture Overwrite Bit 3 ICOVW.NOVW2 2 No Input Capture Overwrite Bit 2 ICOVW.NOVW1 1 No Input Capture Overwrite Bit 1 ICOVW.NOVW0 0 No Input Capture Overwrite Bit 0 ICSYS 0x00AB Input Control System Control Register ICSYS.SH37 7 Share Input Action of Input Capture Channels 3 and y Bit 7 ICSYS.SH26 6 Share Input Action of Input Capture Channels 2 and y Bit 6 ICSYS.SH15 5 Share Input Action of Input Capture Channels 1 and y Bit 5 ICSYS.SH04 4 Share Input Action of Input Capture Channels 0 and y Bit 4 ICSYS.TFMOD 3 Timer Flag-Setting Mode Bit ICSYS.PACMX 2 8-Bit Pulse Accumulators Maximum Count Bit ICSYS.BUFEN 1 IC Buffer Enable Bit ICSYS.LATQ 0 Input Control Latch or Queue Mode Enable Bit RESERVED00AC 0x00AC RESERVED TIMTST 0x00AD Timer Test Register TIMTST.TCBYP 1 Main Timer Divider Chain Bypass Bit PORTT 0x00AE Timer Port Data Register PORTT.PT7 7 Timer Port Data Register bit 7 PORTT.PT6 6 Timer Port Data Register bit 6 PORTT.PT5 5 Timer Port Data Register bit 5 PORTT.PT4 4 Timer Port Data Register bit 4 PORTT.PT3 3 Timer Port Data Register bit 3 PORTT.PT2 2 Timer Port Data Register bit 2 PORTT.PT1 1 Timer Port Data Register bit 1 PORTT.PT0 0 Timer Port Data Register bit 0 DDRT 0x00AF Data Direction Register for Timer Port DDRT.DDT7 7 Data Direction Register for Timer Port bit 7 DDRT.DDT6 6 Data Direction Register for Timer Port bit 6 DDRT.DDT5 5 Data Direction Register for Timer Port bit 5 DDRT.DDT4 4 Data Direction Register for Timer Port bit 4 DDRT.DDT3 3 Data Direction Register for Timer Port bit 3 DDRT.DDT2 2 Data Direction Register for Timer Port bit 2 DDRT.DDT1 1 Data Direction Register for Timer Port bit 1 DDRT.DDT0 0 Data Direction Register for Timer Port bit 0 PBCTL 0x00B0 16-Bit Pulse Accumulator B Control Register PBCTL.PBEN 6 Pulse Accumulator B System Enable Bit PBCTL.PBOVI 1 Pulse Accumulator B Overflow Interrupt Enable Bit PBFLG 0x00B1 Pulse Accumulator B Flag Register PBFLG.PBOVF 1 Pulse Accumulator B Overflow Flag PA3H 0x00B2 8-Bit Pulse Accumulator Holding Register 3 PA2H 0x00B3 8-Bit Pulse Accumulator Holding Register 2 PA1H 0x00B4 8-Bit Pulse Accumulator Holding Register 1 PA0H 0x00B5 8-Bit Pulse Accumulator Holding Register 0 MCCNTH 0x00B6 Modulus Down-Counter Count Register High MCCNTL 0x00B7 Modulus Down-Counter Count Register Low TC0HH 0x00B8 Timer Input Capture Holding Register 0 High TC0HL 0x00B9 Timer Input Capture Holding Register 0 Low TC1HH 0x00BA Timer Input Capture Holding Register 1 High TC1HL 0x00BB Timer Input Capture Holding Register 1 Low TC2HH 0x00BC Timer Input Capture Holding Register 2 High TC2HL 0x00BD Timer Input Capture Holding Register 2 Low TC3HH 0x00BE Timer Input Capture Holding Register 3 High TC3HL 0x00BF Timer Input Capture Holding Register 3 Low SC0BDH 0x00C0 SCI 0 Baud Rate Control Register High SC0BDH.BTST 7 SC0BDH.BSPL 6 SC0BDH.BRLD 5 SC0BDH.SBR12 4 SC0BDH.SBR11 3 SC0BDH.SBR10 2 SC0BDH.SBR9 1 SC0BDH.SBR8 0 SC0BDL 0x00C1 SCI 0 Baud Rate Control Register Low SC0BDL.SBR7 7 SC0BDL.SBR6 6 SC0BDL.SBR5 5 SC0BDL.SBR4 4 SC0BDL.SBR3 3 SC0BDL.SBR2 2 SC0BDL.SBR1 1 SC0BDL.SBR0 0 SC0CR1 0x00C2 SCI Control Register 1 SC0CR1.LOOPS 7 SCI LOOP Mode/Single-Wire Mode Enable Bit SC0CR1.WOMS 6 Wired-OR Mode for Serial Pins SC0CR1.RSRC 5 Receiver Source Bit SC0CR1.M 4 Mode Bit (select character format) SC0CR1.WAKE 3 Wakeup by Address Mark/Idle Bit SC0CR1.ILT 2 Idle Line Type Bit SC0CR1.PE 1 Parity Enable Bit SC0CR1.PT 0 Parity Type Bit SC0CR2 0x00C3 SCI Control Register 2 SC0CR2.TIE 7 Transmit Interrupt Enable Bit SC0CR2.TCIE 6 Transmit Complete Interrupt Enable Bit SC0CR2.RIE 5 Receiver Interrupt Enable Bit SC0CR2.ILIE 4 Idle Line Interrupt Enable Bit SC0CR2.TE 3 Transmitter Enable Bit SC0CR2.RE 2 Receiver Enable Bit SC0CR2.RWU 1 Receiver Wakeup Control Bit SC0CR2.SBK 0 Send Break Bit SC0SR1 0x00C4 SCI Status Register 1 SC0SR1.TDRE 7 Transmit Data Register Empty Flag SC0SR1.TC 6 Transmit Complete Flag SC0SR1.RDRF 5 Receive Data Register Full Flag SC0SR1.IDLE 4 Idle Line Detected Flag SC0SR1.OR 3 Overrun Error Flag SC0SR1.NF 2 Noise Error Flag SC0SR1.FE 1 Framing Error Flag SC0SR1.PF 0 Parity Error Flag SC0SR2 0x00C5 SCI Status Register 2 SC0SR2.RAF 0 Receiver Active Flag SC0DRH 0x00C6 SCI Data Register High SC0DRH.R8 7 Receive Bit 8 SC0DRH.T8 6 Transmit Bit 8 SC0DRL 0x00C7 SCI Data Register Low SC0DRL.R7T7 7 Receive/Transmit Data Bit 7 SC0DRL.R6T6 6 Receive/Transmit Data Bit 6 SC0DRL.R5T5 5 Receive/Transmit Data Bit 5 SC0DRL.R4T4 4 Receive/Transmit Data Bit 4 SC0DRL.R3T3 3 Receive/Transmit Data Bit 3 SC0DRL.R2T2 2 Receive/Transmit Data Bit 2 SC0DRL.R1T1 1 Receive/Transmit Data Bit 1 SC0DRL.R0T0 0 Receive/Transmit Data Bit 0 RESERVED00C8 0x00C8 RESERVED RESERVED00C9 0x00C9 RESERVED RESERVED00CA 0x00CA RESERVED RESERVED00CB 0x00CB RESERVED RESERVED00CC 0x00CC RESERVED RESERVED00CD 0x00CD RESERVED RESERVED00CE 0x00CE RESERVED RESERVED00CF 0x00CF RESERVED SP0CR1 0x00D0 SPI Control Register 1 SP0CR1.SPIE 7 SPI Interrupt Enable Bit SP0CR1.SPE 6 SPI System Enable Bit SP0CR1.SWOM 5 Port S Wired-OR Mode Bit SP0CR1.MSTR 4 SPI Master/Slave Mode Select Bit SP0CR1.CPOL 3 SPI Clock Polarity SP0CR1.CPHA 2 Clock Phase Bits SP0CR1.SSOE 1 Slave Select Output Enable Bit SP0CR1.LSBF 0 SPI LSB First Enable Bit SP0CR2 0x00D1 SPI Control Register 2 SP0CR2.PUPS 3 Pullup Port S Enable Bit SP0CR2.RDS 2 Reduce Drive of Port S Bit SP0CR2.SPC0 0 Serial Pin Control 0 Bit SP0BR 0x00D2 SPI Baud Rate Register SP0BR.SPR2 2 SPI Clock (SCK) Rate Select Bit 2 SP0BR.SPR1 1 SPI Clock (SCK) Rate Select Bit 1 SP0BR.SPR0 0 SPI Clock (SCK) Rate Select Bit 0 SP0SR 0x00D3 SPI Status Register SP0SR.SPIF 7 SPI Interrupt Request Bit SP0SR.WCOL 6 Write Collision Status Flag SP0SR.MODF 4 SPI Mode Error Interrupt Status Flag RESERVED00D4 0x00D4 RESERVED SP0DR 0x00D5 SPI Data Register PORTS 0x00D6 Port S Data Register PORTS.PS7 7 Port S Data Register Bit 7 PORTS.PS6 6 Port S Data Register Bit 6 PORTS.PS5 5 Port S Data Register Bit 5 PORTS.PS4 4 Port S Data Register Bit 4 PORTS.PS3 3 Port S Data Register Bit 3 PORTS.PS2 2 Port S Data Register Bit 2 PORTS.PS1 1 Port S Data Register Bit 1 PORTS.PS0 0 Port S Data Register Bit 0 DDRS 0x00D7 Port S Data Direction Register DDRS.DDS7 7 Port S Data Direction Register Bit 7 DDRS.DDS6 6 Port S Data Direction Register Bit 6 DDRS.DDS5 5 Port S Data Direction Register Bit 5 DDRS.DDS4 4 Port S Data Direction Register Bit 4 DDRS.DDS3 3 Port S Data Direction Register Bit 3 DDRS.DDS2 2 Port S Data Direction Register Bit 2 DDRS.DDS1 1 Port S Data Direction Register Bit 1 DDRS.DDS0 0 Port S Data Direction Register Bit 0 RESERVED00D8 0x00D8 RESERVED RESERVED00D9 0x00D9 RESERVED RESERVED00DA 0x00DA RESERVED PURDS 0x00DB Port S Pullup/Reduced Drive Register PURDS.RDPS2 6 Reduce Drive of PS7-PS4 PURDS.RDPS1 5 Reduce Drive of PS3 and PS2 PURDS.RDPS0 4 Reduce Drive of PS1 and PS0 PURDS.PUPS2 2 Pullup Port S Enable PS7-PS4 PURDS.PUPS1 1 Pullup Port S Enable PS3 and PS2 Bit PURDS.PUPS0 0 Pullup Port S Enable PS1 and PS0 Bit RESERVED00DC 0x00DC RESERVED RESERVED00DD 0x00DD RESERVED RESERVED00DE 0x00DE RESERVED RESERVED00DF 0x00DF RESERVED SLOW 0x00E0 Slow Mode Divider Register SLOW.SLDV2 2 Slow Mode Divisor Selector Bit 2 SLOW.SLDV1 1 Slow Mode Divisor Selector Bit 1 SLOW.SLDV0 0 Slow Mode Divisor Selector Bit 0 RESERVED00E1 0x00E1 RESERVED RESERVED00E2 0x00E2 RESERVED RESERVED00E3 0x00E3 RESERVED RESERVED00E4 0x00E4 RESERVED RESERVED00E5 0x00E5 RESERVED RESERVED00E6 0x00E6 RESERVED RESERVED00E7 0x00E7 RESERVED RESERVED00E8 0x00E8 RESERVED RESERVED00E9 0x00E9 RESERVED RESERVED00EA 0x00EA RESERVED RESERVED00EB 0x00EB RESERVED RESERVED00EC 0x00EC RESERVED RESERVED00ED 0x00ED RESERVED RESERVED00EE 0x00EE RESERVED RESERVED00EF 0x00EF RESERVED EEMCR 0x00F0 EEPROM Configuration Register EEMCR.EESWAI 2 EEPROM Stops in Wait Mode Bit EEMCR.PROTLCK 1 Block Protect Write Lock Bit EEMCR.EERC 0 EEPROM Charge Pump Clock Bit EEPROT 0x00F1 EEPROM Block Protect Register EEPROT.BRPROT4 4 EEPROM Block Protection Bit 4 EEPROT.BRPROT3 3 EEPROM Block Protection Bit 3 EEPROT.BRPROT2 2 EEPROM Block Protection Bit 2 EEPROT.BRPROT1 1 EEPROM Block Protection Bit 1 EEPROT.BRPROT0 0 EEPROM Block Protection Bit 0 EETST 0x00F2 EEPROM Test Register EETST.EEODD 7 Odd Row Programming Bit EETST.EEVEN 6 Even Row Programming Bit EETST.MARG 5 Program and Erase Voltage Margin Test Enable Bit EETST.EECPD 4 Charge Pump Disable Bit EETST.EECPRD 3 Charge Pump Ramp Disable Bit EETST.EECPM 1 Charge Pump Monitor Enable Bit EEPROG 0x00F3 EEPROM Control Register EEPROG.BULKP 7 Bulk Erase Protection Bit EEPROG.BYTE 4 Byte and Aligned Word Erase Bit EEPROG.ROW 3 Row or Bulk Erase Bit EEPROG.ERASE 2 Erase Control Bit EEPROG.EELAT 1 EEPROM Latch Control Bit EEPROG.EEPGM 0 Program and Erase Enable Bit RESERVED00F4 0x00F4 RESERVED RESERVED00F5 0x00F5 RESERVED RESERVED00F6 0x00F6 RESERVED RESERVED00F7 0x00F7 RESERVED BCR1 0x00F8 BDLC Control Register 1 BCR1.IMSG 7 Ignore Message Bit BCR1.CLKS 6 Clock Select Bit BCR1.R1 5 Rate Select Bit 1 BCR1.R0 4 Rate Select Bit 0 BCR1.IE 1 Interrupt Enable Bit BCR1.WCM 0 Wait Clock Mode Bit BSVR 0x00F9 BDLC State Vector Register BSVR.I3 5 Interrupt Source Bit 3 BSVR.I2 4 Interrupt Source Bit 2 BSVR.I1 3 Interrupt Source Bit 1 BSVR.I0 2 Interrupt Source Bit 0 BCR2 0x00FA BDLC Control Register 2 BCR2.ALOOP 7 Analog Loopback Mode Bit BCR2.DLOOP 6 Digital Loopback Mode Bit BCR2.RX4XE 5 Receive 4X Enable Bit BCR2.NBFS 4 Normalization Bit Format Select Bit BCR2.TEOD 3 Transmit End of Data Bit BCR2.TSIFR 2 Transmit In-Frame Response Bit BCR2.TMIFR1 1 Transmit In-Frame Response Bit 1 BCR2.TMIFR0 0 Transmit In-Frame Response Bit 0 BDR 0x00FB BDLC Data Register BDR.BD7 7 BDR.BD6 6 BDR.BD5 5 BDR.BD4 4 BDR.BD3 3 BDR.BD2 2 BDR.BD1 1 BDR.BD0 0 BARD 0x00FC BDLC Analog Roundtrip Delay Register BARD.ATE 7 Analog Transceiver Enable Bit BARD.RXPOL 6 Receive Pin Polarity Bit BARD.BO3 3 BARD Offset Bit 3 BARD.BO2 2 BARD Offset Bit 2 BARD.BO1 1 BARD Offset Bit 1 BARD.BO0 0 BARD Offset Bit 0 DLCSCR 0x00FD Port DLC Control Register DLCSCR.BDLCEN 2 BDLC Enable Bit DLCSCR.PUPDLC 1 BDLC Pullup Enable Bit DLCSCR.RDPDLC 0 BDLC Reduced Drive Bit PORTDLC 0x00FE Port DLC Data Register PORTDLC.PDLC6 6 Port DLC Data Register Bit 6 PORTDLC.PDLC5 5 Port DLC Data Register Bit 5 PORTDLC.PDLC4 4 Port DLC Data Register Bit 4 PORTDLC.PDLC3 3 Port DLC Data Register Bit 3 PORTDLC.PDLC2 2 Port DLC Data Register Bit 2 PORTDLC.PDLC1 1 Port DLC Data Register Bit 1 PORTDLC.PDLC0 0 Port DLC Data Register Bit 0 DDRDLC 0x00FF Port DLC Data Direction Register DDRDLC.DDDLC6 6 Data Direction Port DLC Bit 6 DDRDLC.DDDLC5 5 Data Direction Port DLC Bit 5 DDRDLC.DDDLC4 4 Data Direction Port DLC Bit 4 DDRDLC.DDDLC3 3 Data Direction Port DLC Bit 3 DDRDLC.DDDLC2 2 Data Direction Port DLC Bit 2 DDRDLC.DDDLC1 1 Data Direction Port DLC Bit 1 DDRDLC.DDDLC0 0 Data Direction Port DLC Bit 0 ; CAN RESERVED0100 0x0100 RESERVED RESERVED0101 0x0101 RESERVED RESERVED0102 0x0102 RESERVED RESERVED0103 0x0103 RESERVED RESERVED0104 0x0104 RESERVED RESERVED0105 0x0105 RESERVED RESERVED0106 0x0106 RESERVED RESERVED0107 0x0107 RESERVED RESERVED0108 0x0108 RESERVED RESERVED0109 0x0109 RESERVED RESERVED010A 0x010A RESERVED RESERVED010B 0x010B RESERVED RESERVED010C 0x010C RESERVED RESERVED010D 0x010D RESERVED RESERVED010E 0x010E RESERVED RESERVED010F 0x010F RESERVED RESERVED0110 0x0110 RESERVED RESERVED0111 0x0111 RESERVED RESERVED0112 0x0112 RESERVED RESERVED0113 0x0113 RESERVED RESERVED0114 0x0114 RESERVED RESERVED0115 0x0115 RESERVED RESERVED0116 0x0116 RESERVED RESERVED0117 0x0117 RESERVED RESERVED0118 0x0118 RESERVED RESERVED0119 0x0119 RESERVED RESERVED011A 0x011A RESERVED RESERVED011B 0x011B RESERVED RESERVED011C 0x011C RESERVED RESERVED011D 0x011D RESERVED RESERVED011E 0x011E RESERVED RESERVED011F 0x011F RESERVED RESERVED0120 0x0120 RESERVED RESERVED0121 0x0121 RESERVED RESERVED0122 0x0122 RESERVED RESERVED0123 0x0123 RESERVED RESERVED0124 0x0124 RESERVED RESERVED0125 0x0125 RESERVED RESERVED0126 0x0126 RESERVED RESERVED0127 0x0127 RESERVED RESERVED0128 0x0128 RESERVED RESERVED0129 0x0129 RESERVED RESERVED012A 0x012A RESERVED RESERVED012B 0x012B RESERVED RESERVED012C 0x012C RESERVED RESERVED012D 0x012D RESERVED RESERVED012E 0x012E RESERVED RESERVED012F 0x012F RESERVED RESERVED0130 0x0130 RESERVED RESERVED0131 0x0131 RESERVED RESERVED0132 0x0132 RESERVED RESERVED0133 0x0133 RESERVED RESERVED0134 0x0134 RESERVED RESERVED0135 0x0135 RESERVED RESERVED0136 0x0136 RESERVED RESERVED0137 0x0137 RESERVED RESERVED0138 0x0138 RESERVED RESERVED0139 0x0139 RESERVED RESERVED013A 0x013A RESERVED RESERVED013B 0x013B RESERVED RESERVED013C 0x013C RESERVED RESERVED013D 0x013D RESERVED RESERVED013E 0x013E RESERVED RESERVED013F 0x013F RESERVED .68HC912D60A ; http://e-www.motorola.com/brdata/PDFDB/docs/MC68HC912D60A.pdf ; MC68HC912D60A_D.pdf ; MEMORY MAP area DATA FSR0 0x0000:0x0140 area DATA RECEIVE_BUF 0x0140:0x0150 area DATA TRANSMIT_BUF_0 0x0150:0x0160 area DATA TRANSMIT_BUF_1 0x0160:0x0170 area DATA TRANSMIT_BUF_1 0x0170:0x0180 area BSS RESERVED 0x0180:0x01E2 area DATA FSR1 0x01E2:0x0200 area DATA RAM 0x0200:0x0800 area BSS RESERVED 0x0800:0x0C00 area DATA EEPROM 0x0C00:0x1000 area BSS RESERVED 0x1000:0xFF00 area DATA USER_VEC 0xFF00:0x10000 ; Interrupt and reset vector assignments interrupt __RESET 0xFFFE Reset interrupt _COPCTL 0xFFFC Clock monitor fail reset interrupt COP_F_R 0xFFFA COP failure reset interrupt UIT 0xFFF8 Unimplemented instruction trap interrupt SWI 0xFFF6 SWI interrupt XIRQ 0xFFF4 XIRQ interrupt INTCR_IRQEN 0xFFF2 IRQ interrupt RTICTL_RTIE 0xFFF0 Real time interrupt interrupt TMSK1_C0I 0xFFEE Timer channel 0 interrupt TMSK1_C1I 0xFFEC Timer channel 1 interrupt TMSK1_C2I 0xFFEA Timer channel 2 interrupt TMSK1_C3I 0xFFE8 Timer channel 3 interrupt TMSK1_C4I 0xFFE6 Timer channel 4 interrupt TMSK1_C5I 0xFFE4 Timer channel 5 interrupt TMSK1_C6I 0xFFE2 Timer channel 6 interrupt TMSK1_C7I 0xFFE0 Timer channel 7 interrupt TMSK2_TOI 0xFFDE Timer overflow interrupt PACTL_PAOVI 0xFFDC Pulse accumulator overflow interrupt PACTL_PAI 0xFFDA Pulse accumulator input edge interrupt SP0CR1_SPIE 0xFFD8 SPI serial transfer complete interrupt _SC0CR2 0xFFD6 SCI 0 interrupt _SC1CR2 0xFFD4 SCI 1 interrupt ATDxCTL2_ASCIE 0xFFD2 ATD0 or ATD1 interrupt CRIER_WUPIE 0xFFD0 MSCAN wake-up interrupt KWIEG_KWIEH 0xFFCE Key wake-up G or H interrupt MCCTL_MCZI 0xFFCC Modulus down counter underflow interrupt PBCTL_PBOVI 0xFFCA Pulse Accumulator B Overflow interrupt CRIER_ERR 0xFFC8 MSCAN errors interrupt CRIER_RXFIE 0xFFC6 MSCAN receive interrupt CTCR_TXEIE 0xFFC4 MSCAN transmit interrupt PLLCR_LOCKIE_LHIE 0xFFC2 CGM lock and limp home ; INPUT/ OUTPUT PORTS PORTA 0x0000 Port A Data Register PORTA.PA7 7 Port A Data Bit 7 PORTA.PA6 6 Port A Data Bit 6 PORTA.PA5 5 Port A Data Bit 5 PORTA.PA4 4 Port A Data Bit 4 PORTA.PA3 3 Port A Data Bit 3 PORTA.PA2 2 Port A Data Bit 2 PORTA.PA1 1 Port A Data Bit 1 PORTA.PA0 0 Port A Data Bit 0 PORTB 0x0001 Port B Data Register PORTB.PB7 7 Port B Data Bit 7 PORTB.PB6 6 Port B Data Bit 6 PORTB.PB5 5 Port B Data Bit 5 PORTB.PB4 4 Port B Data Bit 4 PORTB.PB3 3 Port B Data Bit 3 PORTB.PB2 2 Port B Data Bit 2 PORTB.PB1 1 Port B Data Bit 1 PORTB.PB0 0 Port B Data Bit 0 DDRA 0x0002 Port A Data Direction Register DDRA.DDA7 7 Port A Data Direction Bit 7 DDRA.DDA6 6 Port A Data Direction Bit 6 DDRA.DDA5 5 Port A Data Direction Bit 5 DDRA.DDA4 4 Port A Data Direction Bit 4 DDRA.DDA3 3 Port A Data Direction Bit 3 DDRA.DDA2 2 Port A Data Direction Bit 2 DDRA.DDA1 1 Port A Data Direction Bit 1 DDRA.DDA0 0 Port A Data Direction Bit 0 DDRB 0x0003 Port B Data Direction Register DDRB.DDB7 7 Port B Data Direction Bit 7 DDRB.DDB6 6 Port B Data Direction Bit 6 DDRB.DDB5 5 Port B Data Direction Bit 5 DDRB.DDB4 4 Port B Data Direction Bit 4 DDRB.DDB3 3 Port B Data Direction Bit 3 DDRB.DDB2 2 Port B Data Direction Bit 2 DDRB.DDB1 1 Port B Data Direction Bit 1 DDRB.DDB0 0 Port B Data Direction Bit 0 RESERVED0004 0x0004 RESERVED RESERVED0005 0x0005 RESERVED RESERVED0006 0x0006 RESERVED RESERVED0007 0x0007 RESERVED PORTE 0x0008 Port E Data Register PORTE.PE7 7 Port E Data Bit 7 PORTE.PE6 6 Port E Data Bit 6 PORTE.PE5 5 Port E Data Bit 5 PORTE.PE4 4 Port E Data Bit 4 PORTE.PE3 3 Port E Data Bit 3 PORTE.PE2 2 Port E Data Bit 2 PORTE.PE1 1 Port E Data Bit 1 PORTE.PE0 0 Port E Data Bit 0 DDRE 0x0009 Port E Data Direction Register DDRE.DDE7 7 Port E Data Direction Bit 7 DDRE.DDE6 6 Port E Data Direction Bit 6 DDRE.DDE5 5 Port E Data Direction Bit 5 DDRE.DDE4 4 Port E Data Direction Bit 4 DDRE.DDE3 3 Port E Data Direction Bit 3 DDRE.DDE2 2 Port E Data Direction Bit 2 PEAR 0x000A Port E Assignment Register PEAR.NDBE 7 No Data Bus Enable PEAR.CGMTE 6 Clock Generator Module Testing Enable PEAR.PIPOE 5 Pipe Status Signal Output Enable PEAR.NECLK 4 No External E Clock PEAR.LSTRE 3 Low Strobe (LSTRB) Enable PEAR.RDWE 2 Read/Write Enable PEAR.CALE 1 Calibration Reference Enable PEAR.DBENE 0 DBE or Inverted E Clock on Port E MODE 0x000B Mode Register MODE.SMODN 7 Mode Select Special MODE.MODB 6 Mode Select B MODE.MODA 5 Mode Select A MODE.ESTR 4 E Clock Stretch Enable MODE.IVIS 3 Internal Visibility MODE.EBSWAI 2 External Bus Module Stop in Wait Control MODE.EME 0 Emulate Port E PUCR 0x000C Pull-Up Control Register PUCR.PUPH 7 Pull-Up or Pull-Down Port H Enable PUCR.PUPG 6 Pull-Up or Pull-Down Port G Enable PUCR.PUPE 4 Pull-Up Port E Enable PUCR.PUPB 1 Pull-Up Port B Enable PUCR.PUPA 0 Pull-Up Port A Enable RDRIV 0x000D Reduced Drive of I/O Lines RDRIV.RDPH 6 Reduced Drive of Port H RDRIV.RDPG 5 Reduced Drive of Port G RDRIV.RDPE 3 Reduced Drive of Port E RDRIV.RDPB 1 Reduced Drive of Port B RDRIV.RDPA 0 Reduced Drive of Port A RESERVED000E 0x000E RESERVED RESERVED000F 0x000F RESERVED INITRM 0x0010 Initialization of Internal RAM Position Register INITRM.RAM15 7 Internal RAM map position 15 INITRM.RAM14 6 Internal RAM map position 14 INITRM.RAM13 5 Internal RAM map position 13 INITRM.RAM12 4 Internal RAM map position 12 INITRM.RAM11 3 Internal RAM map position 11 INITRG 0x0011 Initialization of Internal Register Position Register INITRG.REG15 7 Internal register map position 15 INITRG.REG14 6 Internal register map position 14 INITRG.REG13 5 Internal register map position 13 INITRG.REG12 4 Internal register map position 12 INITRG.REG11 3 Internal register map position 11 INITRG.MMSWAI 0 Memory Mapping Interface Stop in Wait Control INITEE 0x0012 Initialization of Internal EEPROM Position Register INITEE.EE15 7 Internal EEPROM map position 15 INITEE.EE14 6 Internal EEPROM map position 14 INITEE.EE13 5 Internal EEPROM map position 13 INITEE.EE12 4 Internal EEPROM map position 12 INITEE.EEON 0 internal EEPROM On (Enabled) MISC 0x0013 Miscellaneous Mapping Control Register MISC.MAPROM 7 Map Location of ROM MISC.NDRF 6 Narrow Data Bus for Register-Following Map Space MISC.RFSTR1 5 Register Following Stretch 1 MISC.RFSTR0 4 Register Following Stretch 0 MISC.EXSTR1 3 External Access Stretch 1 MISC.EXSTR0 2 External Access Stretch 0 MISC.ROMON28 1 Enable bits for ROM 28 MISC.ROMON32 0 Enable bits for ROM 32 RTICTL 0x0014 Real-Time Interrupt Control Register RTICTL.RTIE 7 Real Time Interrupt Enable RTICTL.RSWAI 6 RTI and COP Stop While in Wait RTICTL.RSBCK 5 RTI and COP Stop While in Background Debug Mode RTICTL.RTBYP 3 Real Time Interrupt Divider Chain Bypass RTICTL.RTR2 2 Real-Time Interrupt Rate Select 2 RTICTL.RTR1 1 Real-Time Interrupt Rate Select 1 RTICTL.RTR0 0 Real-Time Interrupt Rate Select 0 RTIFLG 0x0015 Real Time Interrupt Flag Register RTIFLG.RTIF 7 Real Time Interrupt Flag COPCTL 0x0016 COP Control Register COPCTL.CME 7 Clock Monitor Enable COPCTL.FCME 6 Force Clock Monitor Enable COPCTL.FCMCOP 5 Force Clock Monitor Reset or COP Watchdog Reset COPCTL.WCOP 4 Window COP mode COPCTL.DISR 3 Disable Resets from COP Watchdog and Clock Monitor COPCTL.CR2 2 COP Watchdog Timer Rate select bit 2 COPCTL.CR1 1 COP Watchdog Timer Rate select bit 1 COPCTL.CR0 0 COP Watchdog Timer Rate select bit 0 COPRST 0x0017 Arm/Reset COP Timer Register RESERVED0018 0x0018 RESERVED RESERVED0019 0x0019 RESERVED RESERVED001A 0x001A RESERVED RESERVED001B 0x001B RESERVED RESERVED001C 0x001C RESERVED RESERVED001D 0x001D RESERVED INTCR 0x001E Interrupt Control Register INTCR.IRQE 7 IRQ Select Edge Sensitive Only INTCR.IRQEN 6 External IRQ Enable INTCR.DLY 5 Enable Oscillator Start-up Delay on Exit from STOP HPRIO 0x001F Highest Priority I Interrupt HPRIO.PSEL5 5 HPRIO.PSEL4 4 HPRIO.PSEL3 3 HPRIO.PSEL2 2 HPRIO.PSEL1 1 BRKCT0 0x0020 Breakpoint Control Register 0 BRKCT0.BKEN1 7 Breakpoint Mode Enable 1 BRKCT0.BKEN0 6 Breakpoint Mode Enable 0 BRKCT0.BKPM 5 Break on Program Addresses BRKCT0.BK1ALE 3 Breakpoint 1 Range Control BRKCT0.BK0ALE 2 Breakpoint 0 Range Control BRKCT1 0x0021 Breakpoint Control Register 1 BRKCT1.BKDBE 6 Enable Data Bus BRKCT1.BKMBH 5 Breakpoint Mask High BRKCT1.BKMBL 4 Breakpoint Mask Low BRKCT1.BK1RWE 3 R/W Compare Enable BRKCT1.BK1RW 2 R/W Compare Value BRKCT1.BK0RWE 1 R/W Compare Enable BRKCT1.BK0RW 0 R/W Compare Value BRKAH 0x0022 Breakpoint Address Register, High Byte BRKAL 0x0023 Breakpoint Address Register, Low Byte BRKDH 0x0024 Breakpoint Data Register, High Byte BRKDL 0x0025 Breakpoint Data Register, Low Byte RESERVED0026 0x0026 RESERVED RESERVED0027 0x0027 RESERVED PORTG 0x0028 Port G Data Register PORTG.PG7 7 Port G Data Bit 7 PORTG.PG6 6 Port G Data Bit 6 PORTG.PG5 5 Port G Data Bit 5 PORTG.PG4 4 Port G Data Bit 4 PORTG.PG3 3 Port G Data Bit 3 PORTG.PG2 2 Port G Data Bit 2 PORTG.PG1 1 Port G Data Bit 1 PORTG.PG0 0 Port G Data Bit 0 PORTH 0x0029 Port H Data Register PORTH.PH7 7 Port H Data Bit 7 PORTH.PH6 6 Port H Data Bit 6 PORTH.PH5 5 Port H Data Bit 5 PORTH.PH4 4 Port H Data Bit 4 PORTH.PH3 3 Port H Data Bit 3 PORTH.PH2 2 Port H Data Bit 2 PORTH.PH1 1 Port H Data Bit 1 PORTH.PH0 0 Port H Data Bit 0 DDRG 0x002A Port G Data Direction Register DDRG.DDG7 7 Port G Data Direction Bit 7 DDRG.DDG6 6 Port G Data Direction Bit 6 DDRG.DDG5 5 Port G Data Direction Bit 5 DDRG.DDG4 4 Port G Data Direction Bit 4 DDRG.DDG3 3 Port G Data Direction Bit 3 DDRG.DDG2 2 Port G Data Direction Bit 2 DDRG.DDG1 1 Port G Data Direction Bit 1 DDRG.DDG0 0 Port G Data Direction Bit 0 DDRH 0x002B Port H Data Direction Register DDRH.DDH7 7 Port H Data Direction Bit 7 DDRH.DDH6 6 Port H Data Direction Bit 6 DDRH.DDH5 5 Port H Data Direction Bit 5 DDRH.DDH4 4 Port H Data Direction Bit 4 DDRH.DDH3 3 Port H Data Direction Bit 3 DDRH.DDH2 2 Port H Data Direction Bit 2 DDRH.DDH1 1 Port H Data Direction Bit 1 DDRH.DDH0 0 Port H Data Direction Bit 0 KWIEG 0x002C Key Wake-up Port G Interrupt Enable Register KWIEG.WI2CE 7 Wake-up I2C Enable KWIEG.KWIEG6 6 Key Wake-up Port G Interrupt Enables 6 KWIEG.KWIEG5 5 Key Wake-up Port G Interrupt Enables 5 KWIEG.KWIEG4 4 Key Wake-up Port G Interrupt Enables 4 KWIEG.KWIEG3 3 Key Wake-up Port G Interrupt Enables 3 KWIEG.KWIEG2 2 Key Wake-up Port G Interrupt Enables 2 KWIEG.KWIEG1 1 Key Wake-up Port G Interrupt Enables 1 KWIEG.KWIEG0 0 Key Wake-up Port G Interrupt Enables 0 KWIEH 0x002D Key Wake-up Port H Interrupt Enable Register KWIEH.KWIEH7 7 Key Wake-up Port H Interrupt Enables 7 KWIEH.KWIEH6 6 Key Wake-up Port H Interrupt Enables 6 KWIEH.KWIEH5 5 Key Wake-up Port H Interrupt Enables 5 KWIEH.KWIEH4 4 Key Wake-up Port H Interrupt Enables 4 KWIEH.KWIEH3 3 Key Wake-up Port H Interrupt Enables 3 KWIEH.KWIEH2 2 Key Wake-up Port H Interrupt Enables 2 KWIEH.KWIEH1 1 Key Wake-up Port H Interrupt Enables 1 KWIEH.KWIEH0 0 Key Wake-up Port H Interrupt Enables 0 KWIFG 0x002E Key Wake-up Port G Flag Register KWIFG.KWIFG6 6 Key Wake-up Port G Flag 6 KWIFG.KWIFG5 5 Key Wake-up Port G Flag 5 KWIFG.KWIFG4 4 Key Wake-up Port G Flag 4 KWIFG.KWIFG3 3 Key Wake-up Port G Flag 3 KWIFG.KWIFG2 2 Key Wake-up Port G Flag 2 KWIFG.KWIFG1 1 Key Wake-up Port G Flag 1 KWIFG.KWIFG0 0 Key Wake-up Port G Flag 0 KWIFH 0x002F Key Wake-up Port H Flag Register KWIFH.KWIFH7 7 Key Wake-up Port H Flag 7 KWIFH.KWIFH6 6 Key Wake-up Port H Flag 6 KWIFH.KWIFH5 5 Key Wake-up Port H Flag 5 KWIFH.KWIFH4 4 Key Wake-up Port H Flag 4 KWIFH.KWIFH3 3 Key Wake-up Port H Flag 3 KWIFH.KWIFH2 2 Key Wake-up Port H Flag 2 KWIFH.KWIFH1 1 Key Wake-up Port H Flag 1 KWIFH.KWIFH0 0 Key Wake-up Port H Flag 0 RESERVED0030 0x0030 RESERVED RESERVED0031 0x0031 RESERVED RESERVED0032 0x0032 RESERVED RESERVED0033 0x0033 RESERVED RESERVED0034 0x0034 RESERVED RESERVED0035 0x0035 RESERVED RESERVED0036 0x0036 RESERVED RESERVED0037 0x0037 RESERVED SYNR 0x0038 Synthesizer Register SYNR.SYN5 5 SYNR.SYN4 4 SYNR.SYN3 3 SYNR.SYN2 2 SYNR.SYN1 1 SYNR.SYN0 0 REFDV 0x0039 Reference Divider Register REFDV.REFDV2 2 REFDV.REFDV1 1 REFDV.REFDV0 0 RESERVED003A 0x003A RESERVED PLLFLG 0x003B PLL Flags PLLFLG.LOCKIF 7 PLL Lock Interrupt Flag PLLFLG.LOCK 6 Locked Phase Lock Loop Circuit PLLFLG.LHIF 1 Limp-Home Interrupt Flag PLLFLG.LHOME 0 Limp-Home Mode Status PLLCR 0x003C PLL Control Register PLLCR.LOCKIE 7 PLL LOCK Interrupt Enable PLLCR.PLLON 6 Phase Lock Loop On PLLCR.AUTO 5 Automatic Bandwidth Control PLLCR.ACQ 4 Not in Acquisition PLLCR.PSTP 2 Pseudo-STOP Enable PLLCR.LHIE 1 Limp-Home Interrupt Enable PLLCR.NOLHM 0 No Limp-Home Mode CLKSEL 0x003D Clock Generator Clock select Register CLKSEL.BCSP 6 Bus Clock Select PLL CLKSEL.BCSS 5 Bus Clock Select Slow CLKSEL.MCS 2 Module Clock Select SLOW 0x003E Slow mode Divider Register SLOW.SLDV5 5 SLOW.SLDV4 4 SLOW.SLDV3 3 SLOW.SLDV2 2 SLOW.SLDV1 1 SLOW.SLDV0 0 RESERVED003F 0x003F RESERVED PWCLK 0x0040 PWM Clocks and Concatenate PWCLK.CON23 7 Concatenate PWM Channels 2 and 3 PWCLK.CON01 6 Concatenate PWM Channels 0 and 1 PWCLK.PCKA2 5 Prescaler for Clock A 2 PWCLK.PCKA1 4 Prescaler for Clock A 1 PWCLK.PCKA0 3 Prescaler for Clock A 0 PWCLK.PCKB2 2 Prescaler for Clock B 2 PWCLK.PCKB1 1 Prescaler for Clock B 1 PWCLK.PCKB0 0 Prescaler for Clock B 0 PWPOL 0x0041 PWM Clock Select and Polarity PWPOL.PCLK3 7 PWM Channel 3 Clock Select PWPOL.PCLK2 6 PWM Channel 2 Clock Select PWPOL.PCLK1 5 PWM Channel 1 Clock Select PWPOL.PCLK0 4 PWM Channel 0 Clock Select PWPOL.PPOL3 3 PWM Channel 3 Polarity PWPOL.PPOL2 2 PWM Channel 2 Polarity PWPOL.PPOL1 1 PWM Channel 1 Polarity PWPOL.PPOL0 0 PWM Channel 0 Polarity PWEN 0x0042 PWM Enable PWEN.PWEN3 3 PWM Channel 3 Enable PWEN.PWEN2 2 PWM Channel 2 Enable PWEN.PWEN1 1 PWM Channel 1 Enable PWEN.PWEN0 0 PWM Channel 0 Enable PWPRES 0x0043 PWM Prescale Counter PWSCAL0 0x0044 PWM Scale Register 0 PWSCNT0 0x0045 PWM Scale Counter 0 Value PWSCAL1 0x0046 PWM Scale Register 1 PWSCNT1 0x0047 PWM Scale Counter 1 Value PWCNT0 0x0048 PWM Channel Counter 0 PWCNT1 0x0049 PWM Channel Counter 1 PWCNT2 0x004A PWM Channel Counter 2 PWCNT3 0x004B PWM Channel Counter 3 PWPER0 0x004C PWM Channel Period Register 0 PWPER1 0x004D PWM Channel Period Register 1 PWPER2 0x004E PWM Channel Period Register 2 PWPER3 0x004F PWM Channel Period Register 3 PWDTY0 0x0050 PWM Channel Duty Register 0 PWDTY1 0x0051 PWM Channel Duty Register 1 PWDTY2 0x0052 PWM Channel Duty Register 2 PWDTY3 0x0053 PWM Channel Duty Register 3 PWCTL 0x0054 PWM Control Register PWCTL.PSWAI 4 PWM Halts while in Wait Mode PWCTL.CENTR 3 Center-Aligned Output Mode PWCTL.RDPP 2 Reduced Drive of Port P PWCTL.PUPP 1 Pull-Up Port P Enable PWCTL.PSBCK 0 PWM Stops while in Background Mode PWTST 0x0055 PWM Special Mode Register ("Test") PWTST.DISCR 7 Disable Reset of Channel Counter on Write to Channel Counter PWTST.DISCP 6 Disable Compare Count Period PWTST.DISCAL 5 Disable Load of Scale-Counters on Write to the Associated Scale-Registers PORTP 0x0056 Port P Data Register PORTP.PP7 7 Port P Data Bit 7 PORTP.PP6 6 Port P Data Bit 6 PORTP.PP5 5 Port P Data Bit 5 PORTP.PP4 4 Port P Data Bit 4 PORTP.PP3 3 Port P Data Bit 3 PORTP.PP2 2 Port P Data Bit 2 PORTP.PP1 1 Port P Data Bit 1 PORTP.PP0 0 Port P Data Bit 0 DDRP 0x0057 Port P Data Direction Register DDRP.DDP7 7 Port P Data Direction Bit 7 DDRP.DDP6 6 Port P Data Direction Bit 6 DDRP.DDP5 5 Port P Data Direction Bit 5 DDRP.DDP4 4 Port P Data Direction Bit 4 DDRP.DDP3 3 Port P Data Direction Bit 3 DDRP.DDP2 2 Port P Data Direction Bit 2 DDRP.DDP1 1 Port P Data Direction Bit 1 DDRP.DDP0 0 Port P Data Direction Bit 0 RESERVED0058 0x0058 RESERVED RESERVED0059 0x0059 RESERVED RESERVED005A 0x005A RESERVED RESERVED005B 0x005B RESERVED RESERVED005C 0x005C RESERVED RESERVED005D 0x005D RESERVED RESERVED005E 0x005E RESERVED RESERVED005F 0x005F RESERVED RESERVED0060 0x0060 RESERVED RESERVED0061 0x0061 RESERVED ATD0CTL2 0x0062 ATD0 Control Register 2 ATD0CTL2.ADPU 7 ATD Disable ATD0CTL2.AFFC 6 ATD Fast Flag Clear All ATD0CTL2.AWAI 5 ATD Wait Mode ATD0CTL2.DJM 4 Result Register Data Justification Mode ATD0CTL2.DSGN 3 Signed/Unsigned Result Data Mode ATD0CTL2.ASCIE 1 ATD Sequence Complete Interrupt Enable ATD0CTL2.ASCIF 0 ATD Sequence Complete Interrupt Flag ATD0CTL3 0x0063 ATD0 Control Register 3 ATD0CTL3.S1C 3 Conversion Sequence Length ATD0CTL3.FIFO 2 Result Register FIFO Mode ATD0CTL3.FRZ1 1 Background Debug Freeze Enable 1 ATD0CTL3.FRZ0 0 Background Debug Freeze Enable 0 ATD0CTL4 0x0064 ATD Control Register 4 ATD0CTL4.RES10 7 A/D Resolution Select ATD0CTL4.SMP1 6 Sample Time Select 1 ATD0CTL4.SMP0 5 Sample Time Select 0 ATD0CTL4.PRS4 4 ATD Clock Prescaler 4 ATD0CTL4.PRS3 3 ATD Clock Prescaler 3 ATD0CTL4.PRS2 2 ATD Clock Prescaler 2 ATD0CTL4.PRS1 1 ATD Clock Prescaler 1 ATD0CTL4.PRS0 0 ATD Clock Prescaler 0 ATD0CTL5 0x0065 ATD Control Register 5 ATD0CTL5.S8C 6 Conversion Sequence Length ATD0CTL5.SCAN 5 Continuous Conversion Sequence Mode ATD0CTL5.MULT 4 Multi-Channel Sample Mode ATD0CTL5.SC 3 Special Channel Conversion Mode ATD0CTL5.CC 2 Analog Input Channel Select Code C ATD0CTL5.CB 1 Analog Input Channel Select Code B ATD0CTL5.CA 0 Analog Input Channel Select Code A ATD0STAT0 0x0066 ATD Status Register 0 ATD0STAT0.SCF 7 Sequence Complete Flag ATD0STAT0.CC2 2 Conversion Counter 2 ATD0STAT0.CC1 1 Conversion Counter 1 ATD0STAT0.CC0 0 Conversion Counter 0 ATD0STAT1 0x0067 ATD Status Register 1 ATD0STAT1.CCF7 7 Conversion Complete Flag 7 ATD0STAT1.CCF6 6 Conversion Complete Flag 6 ATD0STAT1.CCF5 5 Conversion Complete Flag 5 ATD0STAT1.CCF4 4 Conversion Complete Flag 4 ATD0STAT1.CCF3 3 Conversion Complete Flag 3 ATD0STAT1.CCF2 2 Conversion Complete Flag 2 ATD0STAT1.CCF1 1 Conversion Complete Flag 1 ATD0STAT1.CCF0 0 Conversion Complete Flag 0 ATD0TESTH 0x0068 ATD Test Register High ATD0TESTH.SAR9 7 Successive Approximation Register 9 ATD0TESTH.SAR8 6 Successive Approximation Register 8 ATD0TESTH.SAR7 5 Successive Approximation Register 7 ATD0TESTH.SAR6 4 Successive Approximation Register 6 ATD0TESTH.SAR5 3 Successive Approximation Register 5 ATD0TESTH.SAR4 2 Successive Approximation Register 4 ATD0TESTH.SAR3 1 Successive Approximation Register 3 ATD0TESTH.SAR2 0 Successive Approximation Register 2 ATD0TESTL 0x0069 ATD Test Register Low ATD0TESTL.SAR1 7 Successive Approximation Register 1 ATD0TESTL.SAR0 6 Successive Approximation Register 0 ATD0TESTL.RST 5 Test Mode Reset Bit RESERVED006A 0x006A RESERVED RESERVED006B 0x006B RESERVED RESERVED006C 0x006C RESERVED RESERVED006D 0x006D RESERVED RESERVED006E 0x006E RESERVED PORTAD0 0x006F Port AD Data Input Register 0 PORTAD0.PAD07 7 Port AD Data Input Bit 7 PORTAD0.PAD06 6 Port AD Data Input Bit 6 PORTAD0.PAD05 5 Port AD Data Input Bit 5 PORTAD0.PAD04 4 Port AD Data Input Bit 4 PORTAD0.PAD03 3 Port AD Data Input Bit 3 PORTAD0.PAD02 2 Port AD Data Input Bit 2 PORTAD0.PAD01 1 Port AD Data Input Bit 1 PORTAD0.PAD00 0 Port AD Data Input Bit 0 ADR00H 0x0070 A/D Converter Result Register 00 High ADR00L 0x0071 A/D Converter Result Register 00 Low ADR01H 0x0072 A/D Converter Result Register 01 High ADR01L 0x0073 A/D Converter Result Register 01 Low ADR02H 0x0074 A/D Converter Result Register 02 High ADR02L 0x0075 A/D Converter Result Register 02 Low ADR03H 0x0076 A/D Converter Result Register 03 High ADR03L 0x0077 A/D Converter Result Register 03 Low ADR04H 0x0078 A/D Converter Result Register 04 High ADR04L 0x0079 A/D Converter Result Register 04 Low ADR05H 0x007A A/D Converter Result Register 05 High ADR05L 0x007B A/D Converter Result Register 05 Low ADR06H 0x007C A/D Converter Result Register 06 High ADR06L 0x007D A/D Converter Result Register 06 Low ADR07H 0x007E A/D Converter Result Register 07 High ADR07L 0x007F A/D Converter Result Register 07 Low TIOS 0x0080 Timer Input Capture/Output Compare Select TIOS.IOS7 7 Input Capture or Output Compare Channel Configuration 7 TIOS.IOS6 6 Input Capture or Output Compare Channel Configuration 6 TIOS.IOS5 5 Input Capture or Output Compare Channel Configuration 5 TIOS.IOS4 4 Input Capture or Output Compare Channel Configuration 4 TIOS.IOS3 3 Input Capture or Output Compare Channel Configuration 3 TIOS.IOS2 2 Input Capture or Output Compare Channel Configuration 2 TIOS.IOS1 1 Input Capture or Output Compare Channel Configuration 1 TIOS.IOS0 0 Input Capture or Output Compare Channel Configuration 0 CFORC 0x0081 Timer Compare Force Register CFORC.FOC7 7 Force Output Compare Action for Channel 7 CFORC.FOC6 6 Force Output Compare Action for Channel 6 CFORC.FOC5 5 Force Output Compare Action for Channel 5 CFORC.FOC4 4 Force Output Compare Action for Channel 4 CFORC.FOC3 3 Force Output Compare Action for Channel 3 CFORC.FOC2 2 Force Output Compare Action for Channel 2 CFORC.FOC1 1 Force Output Compare Action for Channel 1 CFORC.FOC0 0 Force Output Compare Action for Channel 0 OC7M 0x0082 Output Compare 7 Mask Register OC7M.OC7M7 7 OC7M.OC7M6 6 OC7M.OC7M5 5 OC7M.OC7M4 4 OC7M.OC7M3 3 OC7M.OC7M2 2 OC7M.OC7M1 1 OC7M.OC7M0 0 OC7D 0x0083 Output Compare 7 Data Register OC7D.OC7D7 7 OC7D.OC7D6 6 OC7D.OC7D5 5 OC7D.OC7D4 4 OC7D.OC7D3 3 OC7D.OC7D2 2 OC7D.OC7D1 1 OC7D.OC7D0 0 TCNTH 0x0084 Timer Count Register High TCNTL 0x0085 Timer Count Register Low TSCR 0x0086 Timer System Control Register TSCR.TEN 7 Timer Enable TSCR.TSWAI 6 Timer Module Stops While in Wait TSCR.TSBCK 5 Timer and Modulus Counter Stop While in Background Mode TSCR.TFFCA 4 Timer Fast Flag Clear All RESERVED 0x0087 RESERVED TCTL1 0x0088 Timer Control Register 1 TCTL1.OM7 7 Output Mode 7 TCTL1.OL7 6 Output Level 7 TCTL1.OM6 5 Output Mode 6 TCTL1.OL6 4 Output Level 6 TCTL1.OM5 3 Output Mode 5 TCTL1.OL5 2 Output Level 5 TCTL1.OM4 1 Output Mode 4 TCTL1.OL4 0 Output Level 4 TCTL2 0x0089 Timer Control Register 2 TCTL2.OM3 7 Output Mode 3 TCTL2.OL3 6 Output Level 3 TCTL2.OM2 5 Output Mode 2 TCTL2.OL2 4 Output Level 2 TCTL2.OM1 3 Output Mode 1 TCTL2.OL1 2 Output Level 1 TCTL2.OM0 1 Output Mode 0 TCTL2.OL0 0 Output Level 0 TCTL3 0x008A Timer Control Register 3 TCTL3.EDG7B 7 Input Capture Edge Control 7B TCTL3.EDG7A 6 Input Capture Edge Control 7A TCTL3.EDG6B 5 Input Capture Edge Control 6B TCTL3.EDG6A 4 Input Capture Edge Control 6A TCTL3.EDG5B 3 Input Capture Edge Control 5B TCTL3.EDG5A 2 Input Capture Edge Control 5A TCTL3.EDG4B 1 Input Capture Edge Control 4B TCTL3.EDG4A 0 Input Capture Edge Control 4A TCTL4 0x008B Timer Control Register 4 TCTL4.EDG3B 7 Input Capture Edge Control 3B TCTL4.EDG3A 6 Input Capture Edge Control 3A TCTL4.EDG2B 5 Input Capture Edge Control 2B TCTL4.EDG2A 4 Input Capture Edge Control 2A TCTL4.EDG1B 3 Input Capture Edge Control 1B TCTL4.EDG1A 2 Input Capture Edge Control 1A TCTL4.EDG0B 1 Input Capture Edge Control 0B TCTL4.EDG0A 0 Input Capture Edge Control 0A TMSK1 0x008C Timer Interrupt Mask 1 TMSK1.C7I 7 Input Capture/Output Compare 7 Interrupt Enable TMSK1.C6I 6 Input Capture/Output Compare 6 Interrupt Enable TMSK1.C5I 5 Input Capture/Output Compare 5 Interrupt Enable TMSK1.C4I 4 Input Capture/Output Compare 4 Interrupt Enable TMSK1.C3I 3 Input Capture/Output Compare 3 Interrupt Enable TMSK1.C2I 2 Input Capture/Output Compare 2 Interrupt Enable TMSK1.C1I 1 Input Capture/Output Compare 1 Interrupt Enable TMSK1.C0I 0 Input Capture/Output Compare 0 Interrupt Enable TMSK2 0x008D Timer Interrupt Mask 2 TMSK2.TOI 7 Timer Overflow Interrupt Enable TMSK2.PUPT 5 Timer Port Pull-Up Resistor Enable TMSK2.RDPT 4 Timer Port Drive Reduction TMSK2.TCRE 3 Timer Counter Reset Enable TMSK2.PR2 2 Timer Prescaler Select 2 TMSK2.PR1 1 Timer Prescaler Select 1 TMSK2.PR0 0 Timer Prescaler Select 0 TFLG1 0x008E Main Timer Interrupt Flag 1 TFLG1.C7F 7 Input Capture/Output Compare Channel 7 Flag TFLG1.C6F 6 Input Capture/Output Compare Channel 6 Flag TFLG1.C5F 5 Input Capture/Output Compare Channel 5 Flag TFLG1.C4F 4 Input Capture/Output Compare Channel 4 Flag TFLG1.C3F 3 Input Capture/Output Compare Channel 3 Flag TFLG1.C2F 2 Input Capture/Output Compare Channel 2 Flag TFLG1.C1F 1 Input Capture/Output Compare Channel 1 Flag TFLG1.C0F 0 Input Capture/Output Compare Channel 0 Flag TFLG2 0x008F Main Timer Interrupt Flag 2 TFLG2.TOF 7 Timer Overflow Flag TC0H 0x0090 Timer Input Capture/Output Compare Register 0 High TC0L 0x0091 Timer Input Capture/Output Compare Register 0 Low TC1H 0x0092 Timer Input Capture/Output Compare Register 1 High TC1L 0x0093 Timer Input Capture/Output Compare Register 1 Low TC2H 0x0094 Timer Input Capture/Output Compare Register 2 High TC2L 0x0095 Timer Input Capture/Output Compare Register 2 Low TC3H 0x0096 Timer Input Capture/Output Compare Register 3 High TC3L 0x0097 Timer Input Capture/Output Compare Register 3 Low TC4H 0x0098 Timer Input Capture/Output Compare Register 4 High TC4L 0x0099 Timer Input Capture/Output Compare Register 4 Low TC5H 0x009A Timer Input Capture/Output Compare Register 5 High TC5L 0x009B Timer Input Capture/Output Compare Register 5 Low TC6H 0x009C Timer Input Capture/Output Compare Register 6 High TC6L 0x009D Timer Input Capture/Output Compare Register 6 Low TC7H 0x009E Timer Input Capture/Output Compare Register 7 High TC7L 0x009F Timer Input Capture/Output Compare Register 7 Low PACTL 0x00A0 16-Bit Pulse Accumulator A Control Register PACTL.PAEN 6 Pulse Accumulator A System Enable PACTL.PAMOD 5 Pulse Accumulator Mode PACTL.PEDGE 4 Pulse Accumulator Edge Control PACTL.CLK1 3 Clock Select Bit 1 PACTL.CLK0 2 Clock Select Bit 0 PACTL.PAOVI 1 Pulse Accumulator A Overflow Interrupt enable PACTL.PAI 0 Pulse Accumulator Input Interrupt enable PAFLG 0x00A1 Pulse Accumulator A Flag Register PAFLG.PAOVF 1 Pulse Accumulator A Overflow Flag PAFLG.PAIF 0 Pulse Accumulator Input edge Flag PACN3 0x00A2 Pulse Accumulators Count Register 3 PACN2 0x00A3 Pulse Accumulators Count Register 2 PACN1 0x00A4 Pulse Accumulators Count Register 1 PACN0 0x00A5 Pulse Accumulators Count Register 0 MCCTL 0x00A6 16-Bit Modulus Down-Counter Control Register MCCTL.MCZI 7 Modulus Counter Underflow Interrupt Enable MCCTL.MODMC 6 Modulus Mode Enable MCCTL.RDMCL 5 Read Modulus Down-Counter Load MCCTL.ICLAT 4 Input Capture Force Latch Action MCCTL.FLMC 3 Force Load Register into the Modulus Counter Count Register MCCTL.MCEN 2 Modulus Down-Counter Enable MCCTL.MCPR1 1 Modulus Counter Prescaler select 1 MCCTL.MCPR0 0 Modulus Counter Prescaler select 0 MCFLG 0x00A7 16-Bit Modulus Down-Counter FLAG Register MCFLG.MCZF 7 Modulus Counter Underflow Interrupt Flag MCFLG.POLF3 3 First Input Capture Polarity Status 3 MCFLG.POLF2 2 First Input Capture Polarity Status 2 MCFLG.POLF1 1 First Input Capture Polarity Status 1 MCFLG.POLF0 0 First Input Capture Polarity Status 0 ICPACR 0x00A8 Input Control Pulse Accumulators Control Register ICPACR.PA3EN 3 8-Bit Pulse Accumulator 3 Enable ICPACR.PA2EN 2 8-Bit Pulse Accumulator 2 Enable ICPACR.PA1EN 1 8-Bit Pulse Accumulator 1 Enable ICPACR.PA0EN 0 8-Bit Pulse Accumulator 0 Enable DLYCT 0x00A9 Delay Counter Control Register DLYCT.DLY1 1 Delay Counter Select 1 DLYCT.DLY0 0 Delay Counter Select 0 ICOVW 0x00AA Input Control Overwrite Register ICOVW.NOVW7 7 No Input Capture Overwrite 7 ICOVW.NOVW6 6 No Input Capture Overwrite 6 ICOVW.NOVW5 5 No Input Capture Overwrite 5 ICOVW.NOVW4 4 No Input Capture Overwrite 4 ICOVW.NOVW3 3 No Input Capture Overwrite 3 ICOVW.NOVW2 2 No Input Capture Overwrite 2 ICOVW.NOVW1 1 No Input Capture Overwrite 1 ICOVW.NOVW0 0 No Input Capture Overwrite 0 ICSYS 0x00AB Input Control System Control Register ICSYS.SH37 7 Share Input action of Input Capture Channels 3 and 7 ICSYS.SH26 6 Share Input action of Input Capture Channels 2 and 6 ICSYS.SH15 5 Share Input action of Input Capture Channels 1 and 5 ICSYS.SH04 4 Share Input action of Input Capture Channels 0 and 4 ICSYS.TFMOD 3 Timer Flag-setting Mode ICSYS.PACMX 2 8-Bit Pulse Accumulators Maximum Count ICSYS.BUFEN 1 IC Buffer Enable ICSYS.LATQ 0 Input Control Latch or Queue Mode Enable RESERVED00AC 0x00AC RESERVED TIMTST 0x00AD Timer Test Register TIMTST.TCBYP 1 Main Timer Divider Chain Bypass PORTT 0x00AE Port T Data Register PORTT.PT7 7 Port T Data Bit 7 PORTT.PT6 6 Port T Data Bit 6 PORTT.PT5 5 Port T Data Bit 5 PORTT.PT4 4 Port T Data Bit 4 PORTT.PT3 3 Port T Data Bit 3 PORTT.PT2 2 Port T Data Bit 2 PORTT.PT1 1 Port T Data Bit 1 PORTT.PT0 0 Port T Data Bit 0 DDRT 0x00AF Port T Data Direction Register DDRT.DDT7 7 Port T Data Direction Bit 7 DDRT.DDT6 6 Port T Data Direction Bit 6 DDRT.DDT5 5 Port T Data Direction Bit 5 DDRT.DDT4 4 Port T Data Direction Bit 4 DDRT.DDT3 3 Port T Data Direction Bit 3 DDRT.DDT2 2 Port T Data Direction Bit 2 DDRT.DDT1 1 Port T Data Direction Bit 1 DDRT.DDT0 0 Port T Data Direction Bit 0 PBCTL 0x00B0 16-Bit Pulse Accumulator B Control Register PBCTL.PBEN 6 Pulse Accumulator B System Enable PBCTL.PBOVI 1 Pulse Accumulator B Overflow Interrupt enable PBFLG 0x00B1 Pulse Accumulator B Flag Register PBFLG.PBOVF 1 Pulse Accumulator B Overflow Flag PA3H 0x00B2 8-Bit Pulse Accumulators Holding Register 3 PA2H 0x00B3 8-Bit Pulse Accumulators Holding Register 2 PA1H 0x00B4 8-Bit Pulse Accumulators Holding Register 1 PA0H 0x00B5 8-Bit Pulse Accumulators Holding Register 0 MCCNTH 0x00B6 Modulus Down-Counter Count Register High MCCNTL 0x00B7 Modulus Down-Counter Count Register Low TC0HH 0x00B8 Timer Input Capture Holding Register 0 High TC0HL 0x00B9 Timer Input Capture Holding Register 0 Low TC1HH 0x00BA Timer Input Capture Holding Register 1 High TC1HL 0x00BB Timer Input Capture Holding Register 1 Low TC2HH 0x00BC Timer Input Capture Holding Register 2 High TC2HL 0x00BD Timer Input Capture Holding Register 2 Low TC3HH 0x00BE Timer Input Capture Holding Register 3 High TC3HL 0x00BF Timer Input Capture Holding Register 3 Low SC0BDH 0x00C0 SCI0 Baud Rate Control Register High SC0BDH.BTST 7 Reserved for test function SC0BDH.BSPL 6 Reserved for test function SC0BDH.BRLD 5 Reserved for test function SC0BDH.SBR12 4 SC0BDH.SBR11 3 SC0BDH.SBR10 2 SC0BDH.SBR9 1 SC0BDH.SBR8 0 SC0BDL 0x00C1 SCI0 Baud Rate Control Register Low SC0BDL.SBR7 7 SC0BDL.SBR6 6 SC0BDL.SBR5 5 SC0BDL.SBR4 4 SC0BDL.SBR3 3 SC0BDL.SBR2 2 SC0BDL.SBR1 1 SC0BDL.SBR0 0 SC0CR1 0x00C2 SCI0 Control Register 1 SC0CR1.LOOPS 7 SCI LOOP Mode/Single Wire Mode Enable SC0CR1.WOMS 6 Wired-Or Mode for Serial Pins SC0CR1.RSRC 5 Receiver Source SC0CR1.M 4 Mode (select character format) SC0CR1.WAKE 3 Wake-up by Address Mark/Idle SC0CR1.ILT 2 Idle Line Type SC0CR1.PE 1 Parity Enable SC0CR1.PT 0 Parity Type SC0CR2 0x00C3 SCI0 Control Register 2 SC0CR2.TIE 7 Transmit Interrupt Enable SC0CR2.TCIE 6 Transmit Complete Interrupt Enable SC0CR2.RIE 5 Receiver Interrupt Enable SC0CR2.ILIE 4 Idle Line Interrupt Enable SC0CR2.TE 3 Transmitter Enable SC0CR2.RE 2 Receiver Enable SC0CR2.RWU 1 Receiver Wake-Up Control SC0CR2.SBK 0 Send Break SC0SR1 0x00C4 SCI0 Status Register 1 SC0SR1.TDRE 7 Transmit Data Register Empty Flag SC0SR1.TC 6 Transmit Complete Flag SC0SR1.RDRF 5 Receive Data Register Full Flag SC0SR1.IDLE 4 Idle Line Detected Flag SC0SR1.OR 3 Overrun Error Flag SC0SR1.NF 2 Noise Error Flag SC0SR1.FE 1 Framing Error Flag SC0SR1.PF 0 Parity Error Flag SC0SR2 0x00C5 SCI0 Status Register 2 SC0SR2.SCSWAI 7 Serial Communications Interface Stop in WAIT Mode SC0SR2.MIE 6 SC0SR2.MDL1 5 SC0SR2.MDL0 4 SC0SR2.RAF 0 Receiver Active Flag SC0DRH 0x00C6 SCI0 Data Register High SC0DRH.R8 7 Receive Bit 8 SC0DRH.T8 6 Transmit Bit 8 SC0DRL 0x00C7 SCI0 Data Register Low SC0DRL.R7_T7 7 Receive/Transmit Data Bit 7 SC0DRL.R6_T6 6 Receive/Transmit Data Bit 6 SC0DRL.R5_T5 5 Receive/Transmit Data Bit 5 SC0DRL.R4_T4 4 Receive/Transmit Data Bit 4 SC0DRL.R3_T3 3 Receive/Transmit Data Bit 3 SC0DRL.R2_T2 2 Receive/Transmit Data Bit 2 SC0DRL.R1_T1 1 Receive/Transmit Data Bit 1 SC0DRL.R0_T0 0 Receive/Transmit Data Bit 0 SC1BDH 0x00C8 SCI1 Baud Rate Control Register High SC1BDH.BTST 7 Reserved for test function SC1BDH.BSPL 6 Reserved for test function SC1BDH.BRLD 5 Reserved for test function SC1BDH.SBR12 4 SC1BDH.SBR11 3 SC1BDH.SBR10 2 SC1BDH.SBR9 1 SC1BDH.SBR8 0 SC1BDL 0x00C9 SCI1Baud Rate Control Register Low SC1BDL.SBR7 7 SC1BDL.SBR6 6 SC1BDL.SBR5 5 SC1BDL.SBR4 4 SC1BDL.SBR3 3 SC1BDL.SBR2 2 SC1BDL.SBR1 1 SC1BDL.SBR0 0 SC1CR1 0x00CA SCI1 Control Register 1 SC1CR1.LOOPS 7 SCI LOOP Mode/Single Wire Mode Enable SC1CR1.WOMS 6 Wired-Or Mode for Serial Pins SC1CR1.RSRC 5 Receiver Source SC1CR1.M 4 Mode (select character format) SC1CR1.WAKE 3 Wake-up by Address Mark/Idle SC1CR1.ILT 2 Idle Line Type SC1CR1.PE 1 Parity Enable SC1CR1.PT 0 Parity Type SC1CR2 0x00CB SCI1 Control Register 2 SC1CR2.TIE 7 Transmit Interrupt Enable SC1CR2.TCIE 6 Transmit Complete Interrupt Enable SC1CR2.RIE 5 Receiver Interrupt Enable SC1CR2.ILIE 4 Idle Line Interrupt Enable SC1CR2.TE 3 Transmitter Enable SC1CR2.RE 2 Receiver Enable SC1CR2.RWU 1 Receiver Wake-Up Control SC1CR2.SBK 0 Send Break SC1SR1 0x00CC SCI1 Status Register 1 SC1SR1.TDRE 7 Transmit Data Register Empty Flag SC1SR1.TC 6 Transmit Complete Flag SC1SR1.RDRF 5 Receive Data Register Full Flag SC1SR1.IDLE 4 Idle Line Detected Flag SC1SR1.OR 3 Overrun Error Flag SC1SR1.NF 2 Noise Error Flag SC1SR1.FE 1 Framing Error Flag SC1SR1.PF 0 Parity Error Flag SC1SR2 0x00CD SCI1 Status Register 2 SC1SR2.SCSWAI 7 Serial Communications Interface Stop in WAIT Mode SC1SR2.RAF 0 Receiver Active Flag SC1DRH 0x00CE SCI1 Data Register High SC1DRH.R8 7 Receive Bit 8 SC1DRH.T8 6 Transmit Bit 8 SC1DRL 0x00CF SCI1 Data Register Low SC1DRL.R7_T7 7 Receive/Transmit Data Bit 7 SC1DRL.R6_T6 6 Receive/Transmit Data Bit 6 SC1DRL.R5_T5 5 Receive/Transmit Data Bit 5 SC1DRL.R4_T4 4 Receive/Transmit Data Bit 4 SC1DRL.R3_T3 3 Receive/Transmit Data Bit 3 SC1DRL.R2_T2 2 Receive/Transmit Data Bit 2 SC1DRL.R1_T1 1 Receive/Transmit Data Bit 1 SC1DRL.R0_T0 0 Receive/Transmit Data Bit 0 SP0CR1 0x00D0 SPI Control Register 1 SP0CR1.SPIE 7 SPI Interrupt Enable SP0CR1.SPE 6 SPI System Enable SP0CR1.SWOM 5 Port S Wired-OR Mode SP0CR1.MSTR 4 SPI Master/Slave Mode Select SP0CR1.CPOL 3 SPI Clock Polarity SP0CR1.CPHA 2 Clock Phase SP0CR1.SSOE 1 Slave Select Output Enable SP0CR1.LSBF 0 SPI LSB First enable SP0CR2 0x00D1 SPI Control Register 2 SP0CR2.SPSWAI 1 Serial Interface Stop in WAIT mode SP0CR2.SPC0 0 Serial Pin Control 0 SP0BR 0x00D2 SPI Baud Rate Register SP0BR.SPR2 2 SPI Clock (SCK) Rate Select Bit 2 SP0BR.SPR1 1 SPI Clock (SCK) Rate Select Bit 1 SP0BR.SPR0 0 SPI Clock (SCK) Rate Select Bit 0 SP0SR 0x00D3 SPI Status Register SP0SR.SPIF 7 SPI Interrupt Request SP0SR.WCOL 6 Write Collision Status Flag SP0SR.MODF 4 SPI Mode Error Interrupt Status Flag RESERVED00D4 0x00D4 RESERVED SP0DR 0x00D5 SPI Data Register PORTS 0x00D6 Port S Data Register PORTS.PS7 7 Port S Data Bit 7 PORTS.PS6 6 Port S Data Bit 6 PORTS.PS5 5 Port S Data Bit 5 PORTS.PS4 4 Port S Data Bit 4 PORTS.PS3 3 Port S Data Bit 3 PORTS.PS2 2 Port S Data Bit 2 PORTS.PS1 1 Port S Data Bit 1 PORTS.PS0 0 Port S Data Bit 0 DDRS 0x00D7 Port S Data Direction Register DDRS.DDS7 7 Port S Data Direction Bit 7 DDRS.DDS6 6 Port S Data Direction Bit 6 DDRS.DDS5 5 Port S Data Direction Bit 5 DDRS.DDS4 4 Port S Data Direction Bit 4 DDRS.DDS3 3 Port S Data Direction Bit 3 DDRS.DDS2 2 Port S Data Direction Bit 2 DDRS.DDS1 1 Port S Data Direction Bit 1 DDRS.DDS0 0 Port S Data Direction Bit 0 RESERVED00D8 0x00D8 RESERVED PURDS 0x00D9 Pull-Up Register for Port S PURDS.RDPS2 6 Reduce Drive of Port S[7:4] PURDS.RDPS1 5 Reduce Drive of Port S[3:2] PURDS.RDPS0 4 Reduce Drive of Port S[1:0] PURDS.PUPS2 2 Pull-up Port S[7:4] Enable PURDS.PUPS1 1 Pull-up Port S[3:2] Enable PURDS.PUPS0 0 Pull-up Port S[1:0] Enable RESERVED00DA 0x00DA RESERVED RESERVED00DB 0x00DB RESERVED RESERVED00DC 0x00DC RESERVED RESERVED00DD 0x00DD RESERVED RESERVED00DE 0x00DE RESERVED RESERVED00DF 0x00DF RESERVED RESERVED00E0 0x00E0 RESERVED RESERVED00E1 0x00E1 RESERVED RESERVED00E2 0x00E2 RESERVED RESERVED00E3 0x00E3 RESERVED RESERVED00E4 0x00E4 RESERVED RESERVED00E5 0x00E5 RESERVED RESERVED00E6 0x00E6 RESERVED RESERVED00E7 0x00E7 RESERVED RESERVED00E8 0x00E8 RESERVED RESERVED00E9 0x00E9 RESERVED RESERVED00EA 0x00EA RESERVED RESERVED00EB 0x00EB RESERVED RESERVED00EC 0x00EC RESERVED RESERVED00ED 0x00ED RESERVED EEDIVH 0x00EE EEPROM Modulus Divider High EEDIVH.EEDIV9 1 Prescaler divider 9 EEDIVH.EEDIV8 0 Prescaler divider 8 EEDIVL 0x00EF EEPROM Modulus Divider Low EEDIVL.EEDIV7 7 Prescaler divider 7 EEDIVL.EEDIV6 6 Prescaler divider 6 EEDIVL.EEDIV5 5 Prescaler divider 5 EEDIVL.EEDIV4 4 Prescaler divider 4 EEDIVL.EEDIV3 3 Prescaler divider 3 EEDIVL.EEDIV2 2 Prescaler divider 2 EEDIVL.EEDIV1 1 Prescaler divider 1 EEDIVL.EEDIV0 0 Prescaler divider 0 EEMCR 0x00F0 EEPROM Module Configuration EEMCR.NOBDML 7 Background Debug Mode Lockout Disable EEMCR.NOSHW 6 SHADOW Word Disable EEMCR.EESWAI 2 EEPROM Stops in Wait Mode EEMCR.PROTLCK 1 Block Protect Write Lock EEMCR.DMY 0 Dummy bit EEPROT 0x00F1 EEPROM Block Protect EEPROT.SHPROT 7 SHADOW Word Protection EEPROT.BPROT4 4 EEPROM Block Protection 4 EEPROT.BPROT3 3 EEPROM Block Protection 3 EEPROT.BPROT2 2 EEPROM Block Protection 2 EEPROT.BPROT1 1 EEPROM Block Protection 1 EEPROT.BPROT0 0 EEPROM Block Protection 0 RESERVED00D2 0x00F2 RESERVED EEPROG 0x00F3 EEPROM Control EEPROG.BULKP 7 Bulk Erase Protection EEPROG.AUTO 5 Automatic shutdown of program/erase operation EEPROG.BYTE 4 Byte and Aligned Word Erase EEPROG.ROW 3 Row or Bulk Erase (when BYTE = 0) EEPROG.ERASE 2 Erase Control EEPROG.EELAT 1 EEPROM Latch Control EEPROG.EEPGM 0 Program and Erase Enable FEE32LCK 0x00F4 Flash EEPROM Lock Control Register FEE32LCK.LOCK 0 Lock Register Bit FEE32MCR 0x00F5 Flash EEPROM Module Configuration Register FEE32MCR.BOOTP 0 Boot Protect RESERVED00D6 0x00F6 RESERVED FEE32CTL 0x00F7 Flash EEPROM Control Register FEE32CTL.FEESWAI 4 Flash EEPROM Stop in Wait Control FEE32CTL.HVEN 3 High-Voltage Enable FEE32CTL.ERAS 1 Erase Control FEE32CTL.PGM 0 Program Control FEE28LCK 0x00F8 Flash EEPROM Lock Control Register FEE28LCK.LOCK 0 Lock Register Bit FEE28MCR 0x00F9 Flash EEPROM Module Configuration Register FEE28MCR.BOOTP 0 Boot Protect RESERVED00DA 0x00FA RESERVED FEE28CTL 0x00FB Flash EEPROM Control Register FEE28CTL.FEESWAI 4 Flash EEPROM Stop in Wait Control FEE28CTL.HVEN 3 High-Voltage Enable FEE28CTL.ERAS 1 Erase Control FEE28CTL.PGM 0 Program Control RESERVED00DC 0x00FC RESERVED RESERVED00DD 0x00FD RESERVED RESERVED00DE 0x00FE RESERVED RESERVED00DF 0x00FF RESERVED CMCR0 0x0100 msCAN12 Module Control Register 0 CMCR0.CSWAI 5 CAN Stops in Wait Mode CMCR0.SYNCH 4 Synchronized Status CMCR0.TLNKEN 3 Timer Enable CMCR0.SLPAK 2 SLEEP Mode Acknowledge CMCR0.SLPRQ 1 SLEEP request CMCR0.SFTRES 0 SOFT_RESET CMCR1 0x0101 msCAN12 Module Control Register 1 CMCR1.LOOPB 2 Loop Back Self Test Mode CMCR1.WUPM 1 Wake-Up Mode CMCR1.CLKSRC 0 msCAN12 Clock Source CBTR0 0x0102 msCAN12 Bus Timing Register 0 CBTR0.SJW1 7 Synchronization Jump Width 1 CBTR0.SJW0 6 Synchronization Jump Width 0 CBTR0.BRP5 5 Baud Rate Prescaler 5 CBTR0.BRP4 4 Baud Rate Prescaler 4 CBTR0.BRP3 3 Baud Rate Prescaler 3 CBTR0.BRP2 2 Baud Rate Prescaler 2 CBTR0.BRP1 1 Baud Rate Prescaler 1 CBTR0.BRP0 0 Baud Rate Prescaler 0 CBTR1 0x0103 msCAN12 Bus Timing Register 1 CBTR1.SAMP 7 Sampling CBTR1.TSEG22 6 Time Segment 22 CBTR1.TSEG21 5 Time Segment 21 CBTR1.TSEG20 4 Time Segment 20 CBTR1.TSEG13 3 Time Segment 13 CBTR1.TSEG12 2 Time Segment 12 CBTR1.TSEG11 1 Time Segment 11 CBTR1.TSEG10 0 Time Segment 10 CRFLG 0x0104 msCAN12 Receiver Flag Register CRFLG.WUPIF 7 Wake-up Interrupt Flag CRFLG.RWRNIF 6 Receiver Warning Interrupt Flag CRFLG.TWRNIF 5 Transmitter Warning Interrupt Flag CRFLG.RERRIF 4 Receiver Error Passive Interrupt Flag CRFLG.TERRIF 3 Transmitter Error Passive Interrupt Flag CRFLG.BOFFIF 2 BUSOFF Interrupt Flag CRFLG.OVRIF 1 Overrun Interrupt Flag CRFLG.RXF 0 Receive Buffer Full CRIER 0x0105 msCAN12 Receiver Interrupt Enable Register CRIER.WUPIE 7 Wake-up Interrupt Enable CRIER.RWRNIE 6 Receiver Warning Interrupt Enable CRIER.TWRNIE 5 Transmitter Warning Interrupt Enable CRIER.RERRIE 4 Receiver Error Passive Interrupt Enable CRIER.TERRIE 3 Transmitter Error Passive Interrupt Enable CRIER.BOFFIE 2 BUSOFF Interrupt Enable CRIER.OVRIE 1 Overrun Interrupt Enable CRIER.RXFIE 0 Receiver Full Interrupt Enable CTFLG 0x0106 msCAN12 Transmitter Flag Register CTFLG.ABTAK2 6 Abort Acknowledge 2 CTFLG.ABTAK1 5 Abort Acknowledge 1 CTFLG.ABTAK0 4 Abort Acknowledge 0 CTFLG.TXE2 2 Transmitter Buffer Empty 2 CTFLG.TXE1 1 Transmitter Buffer Empty 1 CTFLG.TXE0 0 Transmitter Buffer Empty 0 CTCR 0x0107 msCAN12 Transmitter Control Register CTCR.ABTRQ2 6 Abort Request 2 CTCR.ABTRQ1 5 Abort Request 1 CTCR.ABTRQ0 4 Abort Request 0 CTCR.TXEIE2 2 Transmitter Empty Interrupt Enable 2 CTCR.TXEIE1 1 Transmitter Empty Interrupt Enable 1 CTCR.TXEIE0 0 Transmitter Empty Interrupt Enable 0 CIDAC 0x0108 msCAN12 Identifier Acceptance Control Register CIDAC.IDAM1 5 Identifier Acceptance Mode 1 CIDAC.IDAM0 4 Identifier Acceptance Mode 0 CIDAC.IDHIT2 2 Identifier Acceptance Hit Indicator 2 CIDAC.IDHIT1 1 Identifier Acceptance Hit Indicator 1 CIDAC.IDHIT0 0 Identifier Acceptance Hit Indicator 0 RESERVED0109 0x0109 RESERVED RESERVED010A 0x010A RESERVED RESERVED010B 0x010B RESERVED RESERVED010C 0x010C RESERVED RESERVED010D 0x010D RESERVED CRXERR 0x010E msCAN12 Receive Error Counter CRXERR.RXERR7 7 CRXERR.RXERR6 6 CRXERR.RXERR5 5 CRXERR.RXERR4 4 CRXERR.RXERR3 3 CRXERR.RXERR2 2 CRXERR.RXERR1 1 CRXERR.RXERR0 0 CTXERR 0x010F msCAN12 Transmit Error Counter CTXERR.TXERR7 7 CTXERR.TXERR6 6 CTXERR.TXERR5 5 CTXERR.TXERR4 4 CTXERR.TXERR3 3 CTXERR.TXERR2 2 CTXERR.TXERR1 1 CTXERR.TXERR0 0 CIDAR0 0x0110 msCAN12 Identifier Acceptance Register 0 CIDAR0.AC7 7 Acceptance Code Bit 7 CIDAR0.AC6 6 Acceptance Code Bit 6 CIDAR0.AC5 5 Acceptance Code Bit 5 CIDAR0.AC4 4 Acceptance Code Bit 4 CIDAR0.AC3 3 Acceptance Code Bit 3 CIDAR0.AC2 2 Acceptance Code Bit 2 CIDAR0.AC1 1 Acceptance Code Bit 1 CIDAR0.AC0 0 Acceptance Code Bit 0 CIDAR1 0x0111 msCAN12 Identifier Acceptance Register 1 CIDAR1.AC7 7 Acceptance Code Bit 7 CIDAR1.AC6 6 Acceptance Code Bit 6 CIDAR1.AC5 5 Acceptance Code Bit 5 CIDAR1.AC4 4 Acceptance Code Bit 4 CIDAR1.AC3 3 Acceptance Code Bit 3 CIDAR1.AC2 2 Acceptance Code Bit 2 CIDAR1.AC1 1 Acceptance Code Bit 1 CIDAR1.AC0 0 Acceptance Code Bit 0 CIDAR2 0x0112 msCAN12 Identifier Acceptance Register 2 CIDAR2.AC7 7 Acceptance Code Bit 7 CIDAR2.AC6 6 Acceptance Code Bit 6 CIDAR2.AC5 5 Acceptance Code Bit 5 CIDAR2.AC4 4 Acceptance Code Bit 4 CIDAR2.AC3 3 Acceptance Code Bit 3 CIDAR2.AC2 2 Acceptance Code Bit 2 CIDAR2.AC1 1 Acceptance Code Bit 1 CIDAR2.AC0 0 Acceptance Code Bit 0 CIDAR3 0x0113 msCAN12 Identifier Acceptance Register 3 CIDAR3.AC7 7 Acceptance Code Bit 7 CIDAR3.AC6 6 Acceptance Code Bit 6 CIDAR3.AC5 5 Acceptance Code Bit 5 CIDAR3.AC4 4 Acceptance Code Bit 4 CIDAR3.AC3 3 Acceptance Code Bit 3 CIDAR3.AC2 2 Acceptance Code Bit 2 CIDAR3.AC1 1 Acceptance Code Bit 1 CIDAR3.AC0 0 Acceptance Code Bit 0 CIDMR0 0x0114 msCAN12 Identifier Mask Register 0 CIDMR0.AM7 7 Acceptance Mask Bit 7 CIDMR0.AM6 6 Acceptance Mask Bit 6 CIDMR0.AM5 5 Acceptance Mask Bit 5 CIDMR0.AM4 4 Acceptance Mask Bit 4 CIDMR0.AM3 3 Acceptance Mask Bit 3 CIDMR0.AM2 2 Acceptance Mask Bit 2 CIDMR0.AM1 1 Acceptance Mask Bit 1 CIDMR0.AM0 0 Acceptance Mask Bit 0 CIDMR1 0x0115 msCAN12 Identifier Mask Register 1 CIDMR1.AM7 7 Acceptance Mask Bit 7 CIDMR1.AM6 6 Acceptance Mask Bit 6 CIDMR1.AM5 5 Acceptance Mask Bit 5 CIDMR1.AM4 4 Acceptance Mask Bit 4 CIDMR1.AM3 3 Acceptance Mask Bit 3 CIDMR1.AM2 2 Acceptance Mask Bit 2 CIDMR1.AM1 1 Acceptance Mask Bit 1 CIDMR1.AM0 0 Acceptance Mask Bit 0 CIDMR2 0x0116 msCAN12 Identifier Mask Register 2 CIDMR2.AM7 7 Acceptance Mask Bit 7 CIDMR2.AM6 6 Acceptance Mask Bit 6 CIDMR2.AM5 5 Acceptance Mask Bit 5 CIDMR2.AM4 4 Acceptance Mask Bit 4 CIDMR2.AM3 3 Acceptance Mask Bit 3 CIDMR2.AM2 2 Acceptance Mask Bit 2 CIDMR2.AM1 1 Acceptance Mask Bit 1 CIDMR2.AM0 0 Acceptance Mask Bit 0 CIDMR3 0x0117 msCAN12 Identifier Mask Register 3 CIDMR3.AM7 7 Acceptance Mask Bit 7 CIDMR3.AM6 6 Acceptance Mask Bit 6 CIDMR3.AM5 5 Acceptance Mask Bit 5 CIDMR3.AM4 4 Acceptance Mask Bit 4 CIDMR3.AM3 3 Acceptance Mask Bit 3 CIDMR3.AM2 2 Acceptance Mask Bit 2 CIDMR3.AM1 1 Acceptance Mask Bit 1 CIDMR3.AM0 0 Acceptance Mask Bit 0 CIDAR4 0x0118 msCAN12 Identifier Acceptance Register 4 CIDAR4.AC7 7 Acceptance Code Bit 7 CIDAR4.AC6 6 Acceptance Code Bit 6 CIDAR4.AC5 5 Acceptance Code Bit 5 CIDAR4.AC4 4 Acceptance Code Bit 4 CIDAR4.AC3 3 Acceptance Code Bit 3 CIDAR4.AC2 2 Acceptance Code Bit 2 CIDAR4.AC1 1 Acceptance Code Bit 1 CIDAR4.AC0 0 Acceptance Code Bit 0 CIDAR5 0x0119 msCAN12 Identifier Acceptance Register 5 CIDAR5.AC7 7 Acceptance Code Bit 7 CIDAR5.AC6 6 Acceptance Code Bit 6 CIDAR5.AC5 5 Acceptance Code Bit 5 CIDAR5.AC4 4 Acceptance Code Bit 4 CIDAR5.AC3 3 Acceptance Code Bit 3 CIDAR5.AC2 2 Acceptance Code Bit 2 CIDAR5.AC1 1 Acceptance Code Bit 1 CIDAR5.AC0 0 Acceptance Code Bit 0 CIDAR6 0x011A msCAN12 Identifier Acceptance Register 6 CIDAR6.AC7 7 Acceptance Code Bit 7 CIDAR6.AC6 6 Acceptance Code Bit 6 CIDAR6.AC5 5 Acceptance Code Bit 5 CIDAR6.AC4 4 Acceptance Code Bit 4 CIDAR6.AC3 3 Acceptance Code Bit 3 CIDAR6.AC2 2 Acceptance Code Bit 2 CIDAR6.AC1 1 Acceptance Code Bit 1 CIDAR6.AC0 0 Acceptance Code Bit 0 CIDAR7 0x011B msCAN12 Identifier Acceptance Register 7 CIDAR7.AC7 7 Acceptance Code Bit 7 CIDAR7.AC6 6 Acceptance Code Bit 6 CIDAR7.AC5 5 Acceptance Code Bit 5 CIDAR7.AC4 4 Acceptance Code Bit 4 CIDAR7.AC3 3 Acceptance Code Bit 3 CIDAR7.AC2 2 Acceptance Code Bit 2 CIDAR7.AC1 1 Acceptance Code Bit 1 CIDAR7.AC0 0 Acceptance Code Bit 0 CIDMR4 0x011C msCAN12 Identifier Mask Register 4 CIDMR4.AM7 7 Acceptance Mask Bit 7 CIDMR4.AM6 6 Acceptance Mask Bit 6 CIDMR4.AM5 5 Acceptance Mask Bit 5 CIDMR4.AM4 4 Acceptance Mask Bit 4 CIDMR4.AM3 3 Acceptance Mask Bit 3 CIDMR4.AM2 2 Acceptance Mask Bit 2 CIDMR4.AM1 1 Acceptance Mask Bit 1 CIDMR4.AM0 0 Acceptance Mask Bit 0 CIDMR5 0x011D msCAN12 Identifier Mask Register 5 CIDMR5.AM7 7 Acceptance Mask Bit 7 CIDMR5.AM6 6 Acceptance Mask Bit 6 CIDMR5.AM5 5 Acceptance Mask Bit 5 CIDMR5.AM4 4 Acceptance Mask Bit 4 CIDMR5.AM3 3 Acceptance Mask Bit 3 CIDMR5.AM2 2 Acceptance Mask Bit 2 CIDMR5.AM1 1 Acceptance Mask Bit 1 CIDMR5.AM0 0 Acceptance Mask Bit 0 CIDMR6 0x011E msCAN12 Identifier Mask Register 6 CIDMR6.AM7 7 Acceptance Mask Bit 7 CIDMR6.AM6 6 Acceptance Mask Bit 6 CIDMR6.AM5 5 Acceptance Mask Bit 5 CIDMR6.AM4 4 Acceptance Mask Bit 4 CIDMR6.AM3 3 Acceptance Mask Bit 3 CIDMR6.AM2 2 Acceptance Mask Bit 2 CIDMR6.AM1 1 Acceptance Mask Bit 1 CIDMR6.AM0 0 Acceptance Mask Bit 0 CIDMR7 0x011F msCAN12 Identifier Mask Register 7 CIDMR7.AM7 7 Acceptance Mask Bit 7 CIDMR7.AM6 6 Acceptance Mask Bit 6 CIDMR7.AM5 5 Acceptance Mask Bit 5 CIDMR7.AM4 4 Acceptance Mask Bit 4 CIDMR7.AM3 3 Acceptance Mask Bit 3 CIDMR7.AM2 2 Acceptance Mask Bit 2 CIDMR7.AM1 1 Acceptance Mask Bit 1 CIDMR7.AM0 0 Acceptance Mask Bit 0 RESERVED0120 0x0120 RESERVED RESERVED0121 0x0121 RESERVED RESERVED0122 0x0122 RESERVED RESERVED0123 0x0123 RESERVED RESERVED0124 0x0124 RESERVED RESERVED0125 0x0125 RESERVED RESERVED0126 0x0126 RESERVED RESERVED0127 0x0127 RESERVED RESERVED0128 0x0128 RESERVED RESERVED0129 0x0129 RESERVED RESERVED012A 0x012A RESERVED RESERVED012B 0x012B RESERVED RESERVED012C 0x012C RESERVED RESERVED012D 0x012D RESERVED RESERVED012E 0x012E RESERVED RESERVED012F 0x012F RESERVED RESERVED0130 0x0130 RESERVED RESERVED0131 0x0131 RESERVED RESERVED0132 0x0132 RESERVED RESERVED0133 0x0133 RESERVED RESERVED0134 0x0134 RESERVED RESERVED0135 0x0135 RESERVED RESERVED0136 0x0136 RESERVED RESERVED0137 0x0137 RESERVED RESERVED0138 0x0138 RESERVED RESERVED0139 0x0139 RESERVED RESERVED013A 0x013A RESERVED RESERVED013B 0x013B RESERVED RESERVED013C 0x013C RESERVED PCTLCAN 0x013D msCAN12 Port CAN Control Register PCTLCAN.PUPCAN 1 Pull-Up Enable Port CAN PCTLCAN.RDPCAN 0 Reduced Drive Port CAN PORTCAN 0x013E msCAN12 Port CAN Data Register PORTCAN.PCAN7 7 Port CAN Data Bit 7 PORTCAN.PCAN6 6 Port CAN Data Bit 6 PORTCAN.PCAN5 5 Port CAN Data Bit 5 PORTCAN.PCAN4 4 Port CAN Data Bit 4 PORTCAN.PCAN3 3 Port CAN Data Bit 3 PORTCAN.PCAN2 2 Port CAN Data Bit 2 PORTCAN.TxCAN 1 PORTCAN.RxCAN 0 DDRCAN 0x013F msCAN12 Port CAN Data Direction Register DDRCAN.DDCAN7 7 Data Direction Port CAN Bit 7 DDRCAN.DDCAN6 6 Data Direction Port CAN Bit 6 DDRCAN.DDCAN5 5 Data Direction Port CAN Bit 5 DDRCAN.DDCAN4 4 Data Direction Port CAN Bit 4 DDRCAN.DDCAN3 3 Data Direction Port CAN Bit 3 DDRCAN.DDCAN2 2 Data Direction Port CAN Bit 2 ATD1CTL2 0x01E2 ATD1 Control Register 2 ATD1CTL2.ADPU 7 ATD Disable ATD1CTL2.ADPU 6 ATD Fast Flag Clear All ATD1CTL2.ASWAI 5 ATD Wait Mode ATD1CTL2.DJM 4 Result Register Data Justification Mode ATD1CTL2.DSGN 3 Signed/Unsigned Result Data Mode ATD1CTL2.ASCIE 1 ATD Sequence Complete Interrupt Enable ATD1CTL2.ASCIF 0 ATD Sequence Complete Interrupt Flag ATD1CTL3 0x01E3 ATD1 Control Register 3 ATD1CTL3.S1C 3 Conversion Sequence Length ATD1CTL3.FIFO 2 Result Register FIFO Mode ATD1CTL3.FRZ1 1 Background Debug Freeze Enable 1 ATD1CTL3.FRZ0 0 Background Debug Freeze Enable 0 ATD1CTL4 0x01E4 ATD1 Control Register 4 ATD1CTL4.RES10 7 A/D Resolution Select ATD1CTL4.SMP1 6 Sample Time Select 1 ATD1CTL4.SMP0 5 Sample Time Select 0 ATD1CTL4.PRS4 4 ATD Clock Prescaler 4 ATD1CTL4.PRS3 3 ATD Clock Prescaler 3 ATD1CTL4.PRS2 2 ATD Clock Prescaler 2 ATD1CTL4.PRS1 1 ATD Clock Prescaler 1 ATD1CTL4.PRS0 0 ATD Clock Prescaler 0 ATD1CTL5 0x01E5 ATD1 Control Register 5 ATD1CTL5.S8C 6 Conversion Sequence Length ATD1CTL5.SCAN 5 Continuous Conversion Sequence Mode ATD1CTL5.MULT 4 Multi-Channel Sample Mode ATD1CTL5.SC 3 Special Channel Conversion Mode ATD1CTL5.CC 2 Analog Input Channel Select Code C ATD1CTL5.CB 1 Analog Input Channel Select Code B ATD1CTL5.CA 0 Analog Input Channel Select Code A ATD1STAT0 0x01E6 ATD1 Status Register ATD1STAT0.SCF 7 Sequence Complete Flag ATD1STAT0.CC2 2 Conversion Counter 2 ATD1STAT0.CC1 1 Conversion Counter 1 ATD1STAT0.CC0 0 Conversion Counter 0 ATD1STAT1 0x01E7 ATD1 Status Register ATD1STAT1.CCF7 7 Conversion Complete Flag 7 ATD1STAT1.CCF6 6 Conversion Complete Flag 6 ATD1STAT1.CCF5 5 Conversion Complete Flag 5 ATD1STAT1.CCF4 4 Conversion Complete Flag 4 ATD1STAT1.CCF3 3 Conversion Complete Flag 3 ATD1STAT1.CCF2 2 Conversion Complete Flag 2 ATD1STAT1.CCF1 1 Conversion Complete Flag 1 ATD1STAT1.CCF0 0 Conversion Complete Flag 0 ATD1TESTH 0x01E8 ATD1 Test Register ATD1TESTH.SAR9 7 Successive Approximation Register 9 ATD1TESTH.SAR8 6 Successive Approximation Register 8 ATD1TESTH.SAR7 5 Successive Approximation Register 7 ATD1TESTH.SAR6 4 Successive Approximation Register 6 ATD1TESTH.SAR5 3 Successive Approximation Register 5 ATD1TESTH.SAR4 2 Successive Approximation Register 4 ATD1TESTH.SAR3 1 Successive Approximation Register 3 ATD1TESTH.SAR2 0 Successive Approximation Register 2 ATD1TESTL 0x01E9 ATD1 Test Register ATD1TESTL.SAR1 7 Successive Approximation Register 1 ATD1TESTL.SAR0 6 Successive Approximation Register 0 ATD1TESTL.RST 5 Test Mode Reset Bit RESERVED01EA 0x01EA RESERVED RESERVED01EB 0x01EB RESERVED RESERVED01EC 0x01EC RESERVED RESERVED01ED 0x01ED RESERVED RESERVED01EE 0x01EE RESERVED PORTAD1 0x01EF Port AD Data Input Register 1 PORTAD1.PAD17 7 Port AD Data Input Bit 7 PORTAD1.PAD16 6 Port AD Data Input Bit 6 PORTAD1.PAD15 5 Port AD Data Input Bit 5 PORTAD1.PAD14 4 Port AD Data Input Bit 4 PORTAD1.PAD13 3 Port AD Data Input Bit 3 PORTAD1.PAD12 2 Port AD Data Input Bit 2 PORTAD1.PAD11 1 Port AD Data Input Bit 1 PORTAD1.PAD10 0 Port AD Data Input Bit 0 ADR10H 0x01F0 A/D Converter Result Register 10 High ADR10L 0x01F1 A/D Converter Result Register 10 Low ADR11H 0x01F2 A/D Converter Result Register 11 High ADR11H 0x01F3 A/D Converter Result Register 11 Low ADR12H 0x01F4 A/D Converter Result Register 12 High ADR12H 0x01F5 A/D Converter Result Register 12 Low ADR13H 0x01F6 A/D Converter Result Register 13 High ADR13H 0x01F7 A/D Converter Result Register 13 Low ADR14H 0x01F8 A/D Converter Result Register 14 High ADR14H 0x01F9 A/D Converter Result Register 14 Low ADR15H 0x01FA A/D Converter Result Register 15 High ADR15H 0x01FB A/D Converter Result Register 15 Low ADR16H 0x01FC A/D Converter Result Register 16 High ADR16H 0x01FD A/D Converter Result Register 16 Low ADR17H 0x01FE A/D Converter Result Register 17 High ADR17H 0x01FF A/D Converter Result Register 17 Low .68HC912D60C ; MEMORY MAP area DATA FSR0 0x0000:0x0140 area DATA RECEIVE_BUF 0x0140:0x0150 area DATA TRANSMIT_BUF_0 0x0150:0x0160 area DATA TRANSMIT_BUF_1 0x0160:0x0170 area DATA TRANSMIT_BUF_1 0x0170:0x0180 area BSS RESERVED 0x0180:0x01E2 area DATA FSR1 0x01E2:0x0200 area DATA RAM 0x0200:0x0800 area BSS RESERVED 0x0800:0x0C00 area DATA EEPROM 0x0C00:0x1000 area BSS RESERVED 0x1000:0xFF00 area DATA USER_VEC 0xFF00:0x10000 ; Interrupt and reset vector assignments interrupt __RESET 0xFFFE Reset interrupt _COPCTL 0xFFFC Clock monitor fail reset interrupt COP_F_R 0xFFFA COP failure reset interrupt UIT 0xFFF8 Unimplemented instruction trap interrupt SWI 0xFFF6 SWI interrupt XIRQ 0xFFF4 XIRQ interrupt INTCR_IRQEN 0xFFF2 IRQ interrupt RTICTL_RTIE 0xFFF0 Real time interrupt interrupt TMSK1_C0I 0xFFEE Timer channel 0 interrupt TMSK1_C1I 0xFFEC Timer channel 1 interrupt TMSK1_C2I 0xFFEA Timer channel 2 interrupt TMSK1_C3I 0xFFE8 Timer channel 3 interrupt TMSK1_C4I 0xFFE6 Timer channel 4 interrupt TMSK1_C5I 0xFFE4 Timer channel 5 interrupt TMSK1_C6I 0xFFE2 Timer channel 6 interrupt TMSK1_C7I 0xFFE0 Timer channel 7 interrupt TMSK2_TOI 0xFFDE Timer overflow interrupt PACTL_PAOVI 0xFFDC Pulse accumulator overflow interrupt PACTL_PAI 0xFFDA Pulse accumulator input edge interrupt SP0CR1_SPIE 0xFFD8 SPI serial transfer complete interrupt _SC0CR2 0xFFD6 SCI 0 interrupt _SC1CR2 0xFFD4 SCI 1 interrupt ATDxCTL2_ASCIE 0xFFD2 ATD0 or ATD1 interrupt CRIER_WUPIE 0xFFD0 MSCAN wake-up interrupt KWIEG_KWIEH 0xFFCE Key wake-up G or H interrupt MCCTL_MCZI 0xFFCC Modulus down counter underflow interrupt PBCTL_PBOVI 0xFFCA Pulse Accumulator B Overflow interrupt CRIER_ERR 0xFFC8 MSCAN errors interrupt CRIER_RXFIE 0xFFC6 MSCAN receive interrupt CTCR_TXEIE 0xFFC4 MSCAN transmit interrupt PLLCR_LOCKIE_LHIE 0xFFC2 CGM lock and limp home ; INPUT/ OUTPUT PORTS PORTA 0x0000 Port A Data Register PORTA.PA7 7 Port A Data Bit 7 PORTA.PA6 6 Port A Data Bit 6 PORTA.PA5 5 Port A Data Bit 5 PORTA.PA4 4 Port A Data Bit 4 PORTA.PA3 3 Port A Data Bit 3 PORTA.PA2 2 Port A Data Bit 2 PORTA.PA1 1 Port A Data Bit 1 PORTA.PA0 0 Port A Data Bit 0 PORTB 0x0001 Port B Data Register PORTB.PB7 7 Port B Data Bit 7 PORTB.PB6 6 Port B Data Bit 6 PORTB.PB5 5 Port B Data Bit 5 PORTB.PB4 4 Port B Data Bit 4 PORTB.PB3 3 Port B Data Bit 3 PORTB.PB2 2 Port B Data Bit 2 PORTB.PB1 1 Port B Data Bit 1 PORTB.PB0 0 Port B Data Bit 0 DDRA 0x0002 Port A Data Direction Register DDRA.DDA7 7 Port A Data Direction Bit 7 DDRA.DDA6 6 Port A Data Direction Bit 6 DDRA.DDA5 5 Port A Data Direction Bit 5 DDRA.DDA4 4 Port A Data Direction Bit 4 DDRA.DDA3 3 Port A Data Direction Bit 3 DDRA.DDA2 2 Port A Data Direction Bit 2 DDRA.DDA1 1 Port A Data Direction Bit 1 DDRA.DDA0 0 Port A Data Direction Bit 0 DDRB 0x0003 Port B Data Direction Register DDRB.DDB7 7 Port B Data Direction Bit 7 DDRB.DDB6 6 Port B Data Direction Bit 6 DDRB.DDB5 5 Port B Data Direction Bit 5 DDRB.DDB4 4 Port B Data Direction Bit 4 DDRB.DDB3 3 Port B Data Direction Bit 3 DDRB.DDB2 2 Port B Data Direction Bit 2 DDRB.DDB1 1 Port B Data Direction Bit 1 DDRB.DDB0 0 Port B Data Direction Bit 0 RESERVED0004 0x0004 RESERVED RESERVED0005 0x0005 RESERVED RESERVED0006 0x0006 RESERVED RESERVED0007 0x0007 RESERVED PORTE 0x0008 Port E Data Register PORTE.PE7 7 Port E Data Bit 7 PORTE.PE6 6 Port E Data Bit 6 PORTE.PE5 5 Port E Data Bit 5 PORTE.PE4 4 Port E Data Bit 4 PORTE.PE3 3 Port E Data Bit 3 PORTE.PE2 2 Port E Data Bit 2 PORTE.PE1 1 Port E Data Bit 1 PORTE.PE0 0 Port E Data Bit 0 DDRE 0x0009 Port E Data Direction Register DDRE.DDE7 7 Port E Data Direction Bit 7 DDRE.DDE6 6 Port E Data Direction Bit 6 DDRE.DDE5 5 Port E Data Direction Bit 5 DDRE.DDE4 4 Port E Data Direction Bit 4 DDRE.DDE3 3 Port E Data Direction Bit 3 DDRE.DDE2 2 Port E Data Direction Bit 2 PEAR 0x000A Port E Assignment Register PEAR.NDBE 7 No Data Bus Enable PEAR.CGMTE 6 Clock Generator Module Testing Enable PEAR.PIPOE 5 Pipe Status Signal Output Enable PEAR.NECLK 4 No External E Clock PEAR.LSTRE 3 Low Strobe (LSTRB) Enable PEAR.RDWE 2 Read/Write Enable PEAR.CALE 1 Calibration Reference Enable PEAR.DBENE 0 DBE or Inverted E Clock on Port E MODE 0x000B Mode Register MODE.SMODN 7 Mode Select Special MODE.MODB 6 Mode Select B MODE.MODA 5 Mode Select A MODE.ESTR 4 E Clock Stretch Enable MODE.IVIS 3 Internal Visibility MODE.EBSWAI 2 External Bus Module Stop in Wait Control MODE.EME 0 Emulate Port E PUCR 0x000C Pull-Up Control Register PUCR.PUPH 7 Pull-Up or Pull-Down Port H Enable PUCR.PUPG 6 Pull-Up or Pull-Down Port G Enable PUCR.PUPE 4 Pull-Up Port E Enable PUCR.PUPB 1 Pull-Up Port B Enable PUCR.PUPA 0 Pull-Up Port A Enable RDRIV 0x000D Reduced Drive of I/O Lines RDRIV.RDPH 6 Reduced Drive of Port H RDRIV.RDPG 5 Reduced Drive of Port G RDRIV.RDPE 3 Reduced Drive of Port E RDRIV.RDPB 1 Reduced Drive of Port B RDRIV.RDPA 0 Reduced Drive of Port A RESERVED000E 0x000E RESERVED RESERVED000F 0x000F RESERVED INITRM 0x0010 Initialization of Internal RAM Position Register INITRM.RAM15 7 Internal RAM map position 15 INITRM.RAM14 6 Internal RAM map position 14 INITRM.RAM13 5 Internal RAM map position 13 INITRM.RAM12 4 Internal RAM map position 12 INITRM.RAM11 3 Internal RAM map position 11 INITRG 0x0011 Initialization of Internal Register Position Register INITRG.REG15 7 Internal register map position 15 INITRG.REG14 6 Internal register map position 14 INITRG.REG13 5 Internal register map position 13 INITRG.REG12 4 Internal register map position 12 INITRG.REG11 3 Internal register map position 11 INITRG.MMSWAI 0 Memory Mapping Interface Stop in Wait Control INITEE 0x0012 Initialization of Internal EEPROM Position Register INITEE.EE15 7 Internal EEPROM map position 15 INITEE.EE14 6 Internal EEPROM map position 14 INITEE.EE13 5 Internal EEPROM map position 13 INITEE.EE12 4 Internal EEPROM map position 12 INITEE.EEON 0 internal EEPROM On (Enabled) MISC 0x0013 Miscellaneous Mapping Control Register MISC.MAPROM 7 Map Location of ROM MISC.NDRF 6 Narrow Data Bus for Register-Following Map Space MISC.RFSTR1 5 Register Following Stretch 1 MISC.RFSTR0 4 Register Following Stretch 0 MISC.EXSTR1 3 External Access Stretch 1 MISC.EXSTR0 2 External Access Stretch 0 MISC.ROMON28 1 Enable bits for ROM 28 MISC.ROMON32 0 Enable bits for ROM 32 RTICTL 0x0014 Real-Time Interrupt Control Register RTICTL.RTIE 7 Real Time Interrupt Enable RTICTL.RSWAI 6 RTI and COP Stop While in Wait RTICTL.RSBCK 5 RTI and COP Stop While in Background Debug Mode RTICTL.RTBYP 3 Real Time Interrupt Divider Chain Bypass RTICTL.RTR2 2 Real-Time Interrupt Rate Select 2 RTICTL.RTR1 1 Real-Time Interrupt Rate Select 1 RTICTL.RTR0 0 Real-Time Interrupt Rate Select 0 RTIFLG 0x0015 Real Time Interrupt Flag Register RTIFLG.RTIF 7 Real Time Interrupt Flag COPCTL 0x0016 COP Control Register COPCTL.CME 7 Clock Monitor Enable COPCTL.FCME 6 Force Clock Monitor Enable COPCTL.FCMCOP 5 Force Clock Monitor Reset or COP Watchdog Reset COPCTL.WCOP 4 Window COP mode COPCTL.DISR 3 Disable Resets from COP Watchdog and Clock Monitor COPCTL.CR2 2 COP Watchdog Timer Rate select bit 2 COPCTL.CR1 1 COP Watchdog Timer Rate select bit 1 COPCTL.CR0 0 COP Watchdog Timer Rate select bit 0 COPRST 0x0017 Arm/Reset COP Timer Register RESERVED0018 0x0018 RESERVED RESERVED0019 0x0019 RESERVED RESERVED001A 0x001A RESERVED RESERVED001B 0x001B RESERVED RESERVED001C 0x001C RESERVED RESERVED001D 0x001D RESERVED INTCR 0x001E Interrupt Control Register INTCR.IRQE 7 IRQ Select Edge Sensitive Only INTCR.IRQEN 6 External IRQ Enable INTCR.DLY 5 Enable Oscillator Start-up Delay on Exit from STOP HPRIO 0x001F Highest Priority I Interrupt HPRIO.PSEL5 5 HPRIO.PSEL4 4 HPRIO.PSEL3 3 HPRIO.PSEL2 2 HPRIO.PSEL1 1 BRKCT0 0x0020 Breakpoint Control Register 0 BRKCT0.BKEN1 7 Breakpoint Mode Enable 1 BRKCT0.BKEN0 6 Breakpoint Mode Enable 0 BRKCT0.BKPM 5 Break on Program Addresses BRKCT0.BK1ALE 3 Breakpoint 1 Range Control BRKCT0.BK0ALE 2 Breakpoint 0 Range Control BRKCT1 0x0021 Breakpoint Control Register 1 BRKCT1.BKDBE 6 Enable Data Bus BRKCT1.BKMBH 5 Breakpoint Mask High BRKCT1.BKMBL 4 Breakpoint Mask Low BRKCT1.BK1RWE 3 R/W Compare Enable BRKCT1.BK1RW 2 R/W Compare Value BRKCT1.BK0RWE 1 R/W Compare Enable BRKCT1.BK0RW 0 R/W Compare Value BRKAH 0x0022 Breakpoint Address Register, High Byte BRKAL 0x0023 Breakpoint Address Register, Low Byte BRKDH 0x0024 Breakpoint Data Register, High Byte BRKDL 0x0025 Breakpoint Data Register, Low Byte RESERVED0026 0x0026 RESERVED RESERVED0027 0x0027 RESERVED PORTG 0x0028 Port G Data Register PORTG.PG7 7 Port G Data Bit 7 PORTG.PG6 6 Port G Data Bit 6 PORTG.PG5 5 Port G Data Bit 5 PORTG.PG4 4 Port G Data Bit 4 PORTG.PG3 3 Port G Data Bit 3 PORTG.PG2 2 Port G Data Bit 2 PORTG.PG1 1 Port G Data Bit 1 PORTG.PG0 0 Port G Data Bit 0 PORTH 0x0029 Port H Data Register PORTH.PH7 7 Port H Data Bit 7 PORTH.PH6 6 Port H Data Bit 6 PORTH.PH5 5 Port H Data Bit 5 PORTH.PH4 4 Port H Data Bit 4 PORTH.PH3 3 Port H Data Bit 3 PORTH.PH2 2 Port H Data Bit 2 PORTH.PH1 1 Port H Data Bit 1 PORTH.PH0 0 Port H Data Bit 0 DDRG 0x002A Port G Data Direction Register DDRG.DDG7 7 Port G Data Direction Bit 7 DDRG.DDG6 6 Port G Data Direction Bit 6 DDRG.DDG5 5 Port G Data Direction Bit 5 DDRG.DDG4 4 Port G Data Direction Bit 4 DDRG.DDG3 3 Port G Data Direction Bit 3 DDRG.DDG2 2 Port G Data Direction Bit 2 DDRG.DDG1 1 Port G Data Direction Bit 1 DDRG.DDG0 0 Port G Data Direction Bit 0 DDRH 0x002B Port H Data Direction Register DDRH.DDH7 7 Port H Data Direction Bit 7 DDRH.DDH6 6 Port H Data Direction Bit 6 DDRH.DDH5 5 Port H Data Direction Bit 5 DDRH.DDH4 4 Port H Data Direction Bit 4 DDRH.DDH3 3 Port H Data Direction Bit 3 DDRH.DDH2 2 Port H Data Direction Bit 2 DDRH.DDH1 1 Port H Data Direction Bit 1 DDRH.DDH0 0 Port H Data Direction Bit 0 KWIEG 0x002C Key Wake-up Port G Interrupt Enable Register KWIEG.WI2CE 7 Wake-up I2C Enable KWIEG.KWIEG6 6 Key Wake-up Port G Interrupt Enables 6 KWIEG.KWIEG5 5 Key Wake-up Port G Interrupt Enables 5 KWIEG.KWIEG4 4 Key Wake-up Port G Interrupt Enables 4 KWIEG.KWIEG3 3 Key Wake-up Port G Interrupt Enables 3 KWIEG.KWIEG2 2 Key Wake-up Port G Interrupt Enables 2 KWIEG.KWIEG1 1 Key Wake-up Port G Interrupt Enables 1 KWIEG.KWIEG0 0 Key Wake-up Port G Interrupt Enables 0 KWIEH 0x002D Key Wake-up Port H Interrupt Enable Register KWIEH.KWIEH7 7 Key Wake-up Port H Interrupt Enables 7 KWIEH.KWIEH6 6 Key Wake-up Port H Interrupt Enables 6 KWIEH.KWIEH5 5 Key Wake-up Port H Interrupt Enables 5 KWIEH.KWIEH4 4 Key Wake-up Port H Interrupt Enables 4 KWIEH.KWIEH3 3 Key Wake-up Port H Interrupt Enables 3 KWIEH.KWIEH2 2 Key Wake-up Port H Interrupt Enables 2 KWIEH.KWIEH1 1 Key Wake-up Port H Interrupt Enables 1 KWIEH.KWIEH0 0 Key Wake-up Port H Interrupt Enables 0 KWIFG 0x002E Key Wake-up Port G Flag Register KWIFG.KWIFG6 6 Key Wake-up Port G Flag 6 KWIFG.KWIFG5 5 Key Wake-up Port G Flag 5 KWIFG.KWIFG4 4 Key Wake-up Port G Flag 4 KWIFG.KWIFG3 3 Key Wake-up Port G Flag 3 KWIFG.KWIFG2 2 Key Wake-up Port G Flag 2 KWIFG.KWIFG1 1 Key Wake-up Port G Flag 1 KWIFG.KWIFG0 0 Key Wake-up Port G Flag 0 KWIFH 0x002F Key Wake-up Port H Flag Register KWIFH.KWIFH7 7 Key Wake-up Port H Flag 7 KWIFH.KWIFH6 6 Key Wake-up Port H Flag 6 KWIFH.KWIFH5 5 Key Wake-up Port H Flag 5 KWIFH.KWIFH4 4 Key Wake-up Port H Flag 4 KWIFH.KWIFH3 3 Key Wake-up Port H Flag 3 KWIFH.KWIFH2 2 Key Wake-up Port H Flag 2 KWIFH.KWIFH1 1 Key Wake-up Port H Flag 1 KWIFH.KWIFH0 0 Key Wake-up Port H Flag 0 RESERVED0030 0x0030 RESERVED RESERVED0031 0x0031 RESERVED RESERVED0032 0x0032 RESERVED RESERVED0033 0x0033 RESERVED RESERVED0034 0x0034 RESERVED RESERVED0035 0x0035 RESERVED RESERVED0036 0x0036 RESERVED RESERVED0037 0x0037 RESERVED SYNR 0x0038 Synthesizer Register SYNR.SYN5 5 SYNR.SYN4 4 SYNR.SYN3 3 SYNR.SYN2 2 SYNR.SYN1 1 SYNR.SYN0 0 REFDV 0x0039 Reference Divider Register REFDV.REFDV2 2 REFDV.REFDV1 1 REFDV.REFDV0 0 RESERVED003A 0x003A RESERVED PLLFLG 0x003B PLL Flags PLLFLG.LOCKIF 7 PLL Lock Interrupt Flag PLLFLG.LOCK 6 Locked Phase Lock Loop Circuit PLLFLG.LHIF 1 Limp-Home Interrupt Flag PLLFLG.LHOME 0 Limp-Home Mode Status PLLCR 0x003C PLL Control Register PLLCR.LOCKIE 7 PLL LOCK Interrupt Enable PLLCR.PLLON 6 Phase Lock Loop On PLLCR.AUTO 5 Automatic Bandwidth Control PLLCR.ACQ 4 Not in Acquisition PLLCR.PSTP 2 Pseudo-STOP Enable PLLCR.LHIE 1 Limp-Home Interrupt Enable PLLCR.NOLHM 0 No Limp-Home Mode CLKSEL 0x003D Clock Generator Clock select Register CLKSEL.BCSP 6 Bus Clock Select PLL CLKSEL.BCSS 5 Bus Clock Select Slow CLKSEL.MCS 2 Module Clock Select SLOW 0x003E Slow mode Divider Register SLOW.SLDV5 5 SLOW.SLDV4 4 SLOW.SLDV3 3 SLOW.SLDV2 2 SLOW.SLDV1 1 SLOW.SLDV0 0 RESERVED003F 0x003F RESERVED PWCLK 0x0040 PWM Clocks and Concatenate PWCLK.CON23 7 Concatenate PWM Channels 2 and 3 PWCLK.CON01 6 Concatenate PWM Channels 0 and 1 PWCLK.PCKA2 5 Prescaler for Clock A 2 PWCLK.PCKA1 4 Prescaler for Clock A 1 PWCLK.PCKA0 3 Prescaler for Clock A 0 PWCLK.PCKB2 2 Prescaler for Clock B 2 PWCLK.PCKB1 1 Prescaler for Clock B 1 PWCLK.PCKB0 0 Prescaler for Clock B 0 PWPOL 0x0041 PWM Clock Select and Polarity PWPOL.PCLK3 7 PWM Channel 3 Clock Select PWPOL.PCLK2 6 PWM Channel 2 Clock Select PWPOL.PCLK1 5 PWM Channel 1 Clock Select PWPOL.PCLK0 4 PWM Channel 0 Clock Select PWPOL.PPOL3 3 PWM Channel 3 Polarity PWPOL.PPOL2 2 PWM Channel 2 Polarity PWPOL.PPOL1 1 PWM Channel 1 Polarity PWPOL.PPOL0 0 PWM Channel 0 Polarity PWEN 0x0042 PWM Enable PWEN.PWEN3 3 PWM Channel 3 Enable PWEN.PWEN2 2 PWM Channel 2 Enable PWEN.PWEN1 1 PWM Channel 1 Enable PWEN.PWEN0 0 PWM Channel 0 Enable PWPRES 0x0043 PWM Prescale Counter PWSCAL0 0x0044 PWM Scale Register 0 PWSCNT0 0x0045 PWM Scale Counter 0 Value PWSCAL1 0x0046 PWM Scale Register 1 PWSCNT1 0x0047 PWM Scale Counter 1 Value PWCNT0 0x0048 PWM Channel Counter 0 PWCNT1 0x0049 PWM Channel Counter 1 PWCNT2 0x004A PWM Channel Counter 2 PWCNT3 0x004B PWM Channel Counter 3 PWPER0 0x004C PWM Channel Period Register 0 PWPER1 0x004D PWM Channel Period Register 1 PWPER2 0x004E PWM Channel Period Register 2 PWPER3 0x004F PWM Channel Period Register 3 PWDTY0 0x0050 PWM Channel Duty Register 0 PWDTY1 0x0051 PWM Channel Duty Register 1 PWDTY2 0x0052 PWM Channel Duty Register 2 PWDTY3 0x0053 PWM Channel Duty Register 3 PWCTL 0x0054 PWM Control Register PWCTL.PSWAI 4 PWM Halts while in Wait Mode PWCTL.CENTR 3 Center-Aligned Output Mode PWCTL.RDPP 2 Reduced Drive of Port P PWCTL.PUPP 1 Pull-Up Port P Enable PWCTL.PSBCK 0 PWM Stops while in Background Mode PWTST 0x0055 PWM Special Mode Register ("Test") PWTST.DISCR 7 Disable Reset of Channel Counter on Write to Channel Counter PWTST.DISCP 6 Disable Compare Count Period PWTST.DISCAL 5 Disable Load of Scale-Counters on Write to the Associated Scale-Registers PORTP 0x0056 Port P Data Register PORTP.PP7 7 Port P Data Bit 7 PORTP.PP6 6 Port P Data Bit 6 PORTP.PP5 5 Port P Data Bit 5 PORTP.PP4 4 Port P Data Bit 4 PORTP.PP3 3 Port P Data Bit 3 PORTP.PP2 2 Port P Data Bit 2 PORTP.PP1 1 Port P Data Bit 1 PORTP.PP0 0 Port P Data Bit 0 DDRP 0x0057 Port P Data Direction Register DDRP.DDP7 7 Port P Data Direction Bit 7 DDRP.DDP6 6 Port P Data Direction Bit 6 DDRP.DDP5 5 Port P Data Direction Bit 5 DDRP.DDP4 4 Port P Data Direction Bit 4 DDRP.DDP3 3 Port P Data Direction Bit 3 DDRP.DDP2 2 Port P Data Direction Bit 2 DDRP.DDP1 1 Port P Data Direction Bit 1 DDRP.DDP0 0 Port P Data Direction Bit 0 RESERVED0058 0x0058 RESERVED RESERVED0059 0x0059 RESERVED RESERVED005A 0x005A RESERVED RESERVED005B 0x005B RESERVED RESERVED005C 0x005C RESERVED RESERVED005D 0x005D RESERVED RESERVED005E 0x005E RESERVED RESERVED005F 0x005F RESERVED RESERVED0060 0x0060 RESERVED RESERVED0061 0x0061 RESERVED ATD0CTL2 0x0062 ATD0 Control Register 2 ATD0CTL2.ADPU 7 ATD Disable ATD0CTL2.AFFC 6 ATD Fast Flag Clear All ATD0CTL2.AWAI 5 ATD Wait Mode ATD0CTL2.DJM 4 Result Register Data Justification Mode ATD0CTL2.DSGN 3 Signed/Unsigned Result Data Mode ATD0CTL2.ASCIE 1 ATD Sequence Complete Interrupt Enable ATD0CTL2.ASCIF 0 ATD Sequence Complete Interrupt Flag ATD0CTL3 0x0063 ATD0 Control Register 3 ATD0CTL3.S1C 3 Conversion Sequence Length ATD0CTL3.FIFO 2 Result Register FIFO Mode ATD0CTL3.FRZ1 1 Background Debug Freeze Enable 1 ATD0CTL3.FRZ0 0 Background Debug Freeze Enable 0 ATD0CTL4 0x0064 ATD Control Register 4 ATD0CTL4.RES10 7 A/D Resolution Select ATD0CTL4.SMP1 6 Sample Time Select 1 ATD0CTL4.SMP0 5 Sample Time Select 0 ATD0CTL4.PRS4 4 ATD Clock Prescaler 4 ATD0CTL4.PRS3 3 ATD Clock Prescaler 3 ATD0CTL4.PRS2 2 ATD Clock Prescaler 2 ATD0CTL4.PRS1 1 ATD Clock Prescaler 1 ATD0CTL4.PRS0 0 ATD Clock Prescaler 0 ATD0CTL5 0x0065 ATD Control Register 5 ATD0CTL5.S8C 6 Conversion Sequence Length ATD0CTL5.SCAN 5 Continuous Conversion Sequence Mode ATD0CTL5.MULT 4 Multi-Channel Sample Mode ATD0CTL5.SC 3 Special Channel Conversion Mode ATD0CTL5.CC 2 Analog Input Channel Select Code C ATD0CTL5.CB 1 Analog Input Channel Select Code B ATD0CTL5.CA 0 Analog Input Channel Select Code A ATD0STAT0 0x0066 ATD Status Register 0 ATD0STAT0.SCF 7 Sequence Complete Flag ATD0STAT0.CC2 2 Conversion Counter 2 ATD0STAT0.CC1 1 Conversion Counter 1 ATD0STAT0.CC0 0 Conversion Counter 0 ATD0STAT1 0x0067 ATD Status Register 1 ATD0STAT1.CCF7 7 Conversion Complete Flag 7 ATD0STAT1.CCF6 6 Conversion Complete Flag 6 ATD0STAT1.CCF5 5 Conversion Complete Flag 5 ATD0STAT1.CCF4 4 Conversion Complete Flag 4 ATD0STAT1.CCF3 3 Conversion Complete Flag 3 ATD0STAT1.CCF2 2 Conversion Complete Flag 2 ATD0STAT1.CCF1 1 Conversion Complete Flag 1 ATD0STAT1.CCF0 0 Conversion Complete Flag 0 ATD0TESTH 0x0068 ATD Test Register High ATD0TESTH.SAR9 7 Successive Approximation Register 9 ATD0TESTH.SAR8 6 Successive Approximation Register 8 ATD0TESTH.SAR7 5 Successive Approximation Register 7 ATD0TESTH.SAR6 4 Successive Approximation Register 6 ATD0TESTH.SAR5 3 Successive Approximation Register 5 ATD0TESTH.SAR4 2 Successive Approximation Register 4 ATD0TESTH.SAR3 1 Successive Approximation Register 3 ATD0TESTH.SAR2 0 Successive Approximation Register 2 ATD0TESTL 0x0069 ATD Test Register Low ATD0TESTL.SAR1 7 Successive Approximation Register 1 ATD0TESTL.SAR0 6 Successive Approximation Register 0 ATD0TESTL.RST 5 Test Mode Reset Bit RESERVED006A 0x006A RESERVED RESERVED006B 0x006B RESERVED RESERVED006C 0x006C RESERVED RESERVED006D 0x006D RESERVED RESERVED006E 0x006E RESERVED PORTAD0 0x006F Port AD Data Input Register 0 PORTAD0.PAD07 7 Port AD Data Input Bit 7 PORTAD0.PAD06 6 Port AD Data Input Bit 6 PORTAD0.PAD05 5 Port AD Data Input Bit 5 PORTAD0.PAD04 4 Port AD Data Input Bit 4 PORTAD0.PAD03 3 Port AD Data Input Bit 3 PORTAD0.PAD02 2 Port AD Data Input Bit 2 PORTAD0.PAD01 1 Port AD Data Input Bit 1 PORTAD0.PAD00 0 Port AD Data Input Bit 0 ADR00H 0x0070 A/D Converter Result Register 00 High ADR00L 0x0071 A/D Converter Result Register 00 Low ADR01H 0x0072 A/D Converter Result Register 01 High ADR01L 0x0073 A/D Converter Result Register 01 Low ADR02H 0x0074 A/D Converter Result Register 02 High ADR02L 0x0075 A/D Converter Result Register 02 Low ADR03H 0x0076 A/D Converter Result Register 03 High ADR03L 0x0077 A/D Converter Result Register 03 Low ADR04H 0x0078 A/D Converter Result Register 04 High ADR04L 0x0079 A/D Converter Result Register 04 Low ADR05H 0x007A A/D Converter Result Register 05 High ADR05L 0x007B A/D Converter Result Register 05 Low ADR06H 0x007C A/D Converter Result Register 06 High ADR06L 0x007D A/D Converter Result Register 06 Low ADR07H 0x007E A/D Converter Result Register 07 High ADR07L 0x007F A/D Converter Result Register 07 Low TIOS 0x0080 Timer Input Capture/Output Compare Select TIOS.IOS7 7 Input Capture or Output Compare Channel Configuration 7 TIOS.IOS6 6 Input Capture or Output Compare Channel Configuration 6 TIOS.IOS5 5 Input Capture or Output Compare Channel Configuration 5 TIOS.IOS4 4 Input Capture or Output Compare Channel Configuration 4 TIOS.IOS3 3 Input Capture or Output Compare Channel Configuration 3 TIOS.IOS2 2 Input Capture or Output Compare Channel Configuration 2 TIOS.IOS1 1 Input Capture or Output Compare Channel Configuration 1 TIOS.IOS0 0 Input Capture or Output Compare Channel Configuration 0 CFORC 0x0081 Timer Compare Force Register CFORC.FOC7 7 Force Output Compare Action for Channel 7 CFORC.FOC6 6 Force Output Compare Action for Channel 6 CFORC.FOC5 5 Force Output Compare Action for Channel 5 CFORC.FOC4 4 Force Output Compare Action for Channel 4 CFORC.FOC3 3 Force Output Compare Action for Channel 3 CFORC.FOC2 2 Force Output Compare Action for Channel 2 CFORC.FOC1 1 Force Output Compare Action for Channel 1 CFORC.FOC0 0 Force Output Compare Action for Channel 0 OC7M 0x0082 Output Compare 7 Mask Register OC7M.OC7M7 7 OC7M.OC7M6 6 OC7M.OC7M5 5 OC7M.OC7M4 4 OC7M.OC7M3 3 OC7M.OC7M2 2 OC7M.OC7M1 1 OC7M.OC7M0 0 OC7D 0x0083 Output Compare 7 Data Register OC7D.OC7D7 7 OC7D.OC7D6 6 OC7D.OC7D5 5 OC7D.OC7D4 4 OC7D.OC7D3 3 OC7D.OC7D2 2 OC7D.OC7D1 1 OC7D.OC7D0 0 TCNTH 0x0084 Timer Count Register High TCNTL 0x0085 Timer Count Register Low TSCR 0x0086 Timer System Control Register TSCR.TEN 7 Timer Enable TSCR.TSWAI 6 Timer Module Stops While in Wait TSCR.TSBCK 5 Timer and Modulus Counter Stop While in Background Mode TSCR.TFFCA 4 Timer Fast Flag Clear All RESERVED 0x0087 RESERVED TCTL1 0x0088 Timer Control Register 1 TCTL1.OM7 7 Output Mode 7 TCTL1.OL7 6 Output Level 7 TCTL1.OM6 5 Output Mode 6 TCTL1.OL6 4 Output Level 6 TCTL1.OM5 3 Output Mode 5 TCTL1.OL5 2 Output Level 5 TCTL1.OM4 1 Output Mode 4 TCTL1.OL4 0 Output Level 4 TCTL2 0x0089 Timer Control Register 2 TCTL2.OM3 7 Output Mode 3 TCTL2.OL3 6 Output Level 3 TCTL2.OM2 5 Output Mode 2 TCTL2.OL2 4 Output Level 2 TCTL2.OM1 3 Output Mode 1 TCTL2.OL1 2 Output Level 1 TCTL2.OM0 1 Output Mode 0 TCTL2.OL0 0 Output Level 0 TCTL3 0x008A Timer Control Register 3 TCTL3.EDG7B 7 Input Capture Edge Control 7B TCTL3.EDG7A 6 Input Capture Edge Control 7A TCTL3.EDG6B 5 Input Capture Edge Control 6B TCTL3.EDG6A 4 Input Capture Edge Control 6A TCTL3.EDG5B 3 Input Capture Edge Control 5B TCTL3.EDG5A 2 Input Capture Edge Control 5A TCTL3.EDG4B 1 Input Capture Edge Control 4B TCTL3.EDG4A 0 Input Capture Edge Control 4A TCTL4 0x008B Timer Control Register 4 TCTL4.EDG3B 7 Input Capture Edge Control 3B TCTL4.EDG3A 6 Input Capture Edge Control 3A TCTL4.EDG2B 5 Input Capture Edge Control 2B TCTL4.EDG2A 4 Input Capture Edge Control 2A TCTL4.EDG1B 3 Input Capture Edge Control 1B TCTL4.EDG1A 2 Input Capture Edge Control 1A TCTL4.EDG0B 1 Input Capture Edge Control 0B TCTL4.EDG0A 0 Input Capture Edge Control 0A TMSK1 0x008C Timer Interrupt Mask 1 TMSK1.C7I 7 Input Capture/Output Compare 7 Interrupt Enable TMSK1.C6I 6 Input Capture/Output Compare 6 Interrupt Enable TMSK1.C5I 5 Input Capture/Output Compare 5 Interrupt Enable TMSK1.C4I 4 Input Capture/Output Compare 4 Interrupt Enable TMSK1.C3I 3 Input Capture/Output Compare 3 Interrupt Enable TMSK1.C2I 2 Input Capture/Output Compare 2 Interrupt Enable TMSK1.C1I 1 Input Capture/Output Compare 1 Interrupt Enable TMSK1.C0I 0 Input Capture/Output Compare 0 Interrupt Enable TMSK2 0x008D Timer Interrupt Mask 2 TMSK2.TOI 7 Timer Overflow Interrupt Enable TMSK2.PUPT 5 Timer Port Pull-Up Resistor Enable TMSK2.RDPT 4 Timer Port Drive Reduction TMSK2.TCRE 3 Timer Counter Reset Enable TMSK2.PR2 2 Timer Prescaler Select 2 TMSK2.PR1 1 Timer Prescaler Select 1 TMSK2.PR0 0 Timer Prescaler Select 0 TFLG1 0x008E Main Timer Interrupt Flag 1 TFLG1.C7F 7 Input Capture/Output Compare Channel 7 Flag TFLG1.C6F 6 Input Capture/Output Compare Channel 6 Flag TFLG1.C5F 5 Input Capture/Output Compare Channel 5 Flag TFLG1.C4F 4 Input Capture/Output Compare Channel 4 Flag TFLG1.C3F 3 Input Capture/Output Compare Channel 3 Flag TFLG1.C2F 2 Input Capture/Output Compare Channel 2 Flag TFLG1.C1F 1 Input Capture/Output Compare Channel 1 Flag TFLG1.C0F 0 Input Capture/Output Compare Channel 0 Flag TFLG2 0x008F Main Timer Interrupt Flag 2 TFLG2.TOF 7 Timer Overflow Flag TC0H 0x0090 Timer Input Capture/Output Compare Register 0 High TC0L 0x0091 Timer Input Capture/Output Compare Register 0 Low TC1H 0x0092 Timer Input Capture/Output Compare Register 1 High TC1L 0x0093 Timer Input Capture/Output Compare Register 1 Low TC2H 0x0094 Timer Input Capture/Output Compare Register 2 High TC2L 0x0095 Timer Input Capture/Output Compare Register 2 Low TC3H 0x0096 Timer Input Capture/Output Compare Register 3 High TC3L 0x0097 Timer Input Capture/Output Compare Register 3 Low TC4H 0x0098 Timer Input Capture/Output Compare Register 4 High TC4L 0x0099 Timer Input Capture/Output Compare Register 4 Low TC5H 0x009A Timer Input Capture/Output Compare Register 5 High TC5L 0x009B Timer Input Capture/Output Compare Register 5 Low TC6H 0x009C Timer Input Capture/Output Compare Register 6 High TC6L 0x009D Timer Input Capture/Output Compare Register 6 Low TC7H 0x009E Timer Input Capture/Output Compare Register 7 High TC7L 0x009F Timer Input Capture/Output Compare Register 7 Low PACTL 0x00A0 16-Bit Pulse Accumulator A Control Register PACTL.PAEN 6 Pulse Accumulator A System Enable PACTL.PAMOD 5 Pulse Accumulator Mode PACTL.PEDGE 4 Pulse Accumulator Edge Control PACTL.CLK1 3 Clock Select Bit 1 PACTL.CLK0 2 Clock Select Bit 0 PACTL.PAOVI 1 Pulse Accumulator A Overflow Interrupt enable PACTL.PAI 0 Pulse Accumulator Input Interrupt enable PAFLG 0x00A1 Pulse Accumulator A Flag Register PAFLG.PAOVF 1 Pulse Accumulator A Overflow Flag PAFLG.PAIF 0 Pulse Accumulator Input edge Flag PACN3 0x00A2 Pulse Accumulators Count Register 3 PACN2 0x00A3 Pulse Accumulators Count Register 2 PACN1 0x00A4 Pulse Accumulators Count Register 1 PACN0 0x00A5 Pulse Accumulators Count Register 0 MCCTL 0x00A6 16-Bit Modulus Down-Counter Control Register MCCTL.MCZI 7 Modulus Counter Underflow Interrupt Enable MCCTL.MODMC 6 Modulus Mode Enable MCCTL.RDMCL 5 Read Modulus Down-Counter Load MCCTL.ICLAT 4 Input Capture Force Latch Action MCCTL.FLMC 3 Force Load Register into the Modulus Counter Count Register MCCTL.MCEN 2 Modulus Down-Counter Enable MCCTL.MCPR1 1 Modulus Counter Prescaler select 1 MCCTL.MCPR0 0 Modulus Counter Prescaler select 0 MCFLG 0x00A7 16-Bit Modulus Down-Counter FLAG Register MCFLG.MCZF 7 Modulus Counter Underflow Interrupt Flag MCFLG.POLF3 3 First Input Capture Polarity Status 3 MCFLG.POLF2 2 First Input Capture Polarity Status 2 MCFLG.POLF1 1 First Input Capture Polarity Status 1 MCFLG.POLF0 0 First Input Capture Polarity Status 0 ICPACR 0x00A8 Input Control Pulse Accumulators Control Register ICPACR.PA3EN 3 8-Bit Pulse Accumulator 3 Enable ICPACR.PA2EN 2 8-Bit Pulse Accumulator 2 Enable ICPACR.PA1EN 1 8-Bit Pulse Accumulator 1 Enable ICPACR.PA0EN 0 8-Bit Pulse Accumulator 0 Enable DLYCT 0x00A9 Delay Counter Control Register DLYCT.DLY1 1 Delay Counter Select 1 DLYCT.DLY0 0 Delay Counter Select 0 ICOVW 0x00AA Input Control Overwrite Register ICOVW.NOVW7 7 No Input Capture Overwrite 7 ICOVW.NOVW6 6 No Input Capture Overwrite 6 ICOVW.NOVW5 5 No Input Capture Overwrite 5 ICOVW.NOVW4 4 No Input Capture Overwrite 4 ICOVW.NOVW3 3 No Input Capture Overwrite 3 ICOVW.NOVW2 2 No Input Capture Overwrite 2 ICOVW.NOVW1 1 No Input Capture Overwrite 1 ICOVW.NOVW0 0 No Input Capture Overwrite 0 ICSYS 0x00AB Input Control System Control Register ICSYS.SH37 7 Share Input action of Input Capture Channels 3 and 7 ICSYS.SH26 6 Share Input action of Input Capture Channels 2 and 6 ICSYS.SH15 5 Share Input action of Input Capture Channels 1 and 5 ICSYS.SH04 4 Share Input action of Input Capture Channels 0 and 4 ICSYS.TFMOD 3 Timer Flag-setting Mode ICSYS.PACMX 2 8-Bit Pulse Accumulators Maximum Count ICSYS.BUFEN 1 IC Buffer Enable ICSYS.LATQ 0 Input Control Latch or Queue Mode Enable RESERVED00AC 0x00AC RESERVED TIMTST 0x00AD Timer Test Register TIMTST.TCBYP 1 Main Timer Divider Chain Bypass PORTT 0x00AE Port T Data Register PORTT.PT7 7 Port T Data Bit 7 PORTT.PT6 6 Port T Data Bit 6 PORTT.PT5 5 Port T Data Bit 5 PORTT.PT4 4 Port T Data Bit 4 PORTT.PT3 3 Port T Data Bit 3 PORTT.PT2 2 Port T Data Bit 2 PORTT.PT1 1 Port T Data Bit 1 PORTT.PT0 0 Port T Data Bit 0 DDRT 0x00AF Port T Data Direction Register DDRT.DDT7 7 Port T Data Direction Bit 7 DDRT.DDT6 6 Port T Data Direction Bit 6 DDRT.DDT5 5 Port T Data Direction Bit 5 DDRT.DDT4 4 Port T Data Direction Bit 4 DDRT.DDT3 3 Port T Data Direction Bit 3 DDRT.DDT2 2 Port T Data Direction Bit 2 DDRT.DDT1 1 Port T Data Direction Bit 1 DDRT.DDT0 0 Port T Data Direction Bit 0 PBCTL 0x00B0 16-Bit Pulse Accumulator B Control Register PBCTL.PBEN 6 Pulse Accumulator B System Enable PBCTL.PBOVI 1 Pulse Accumulator B Overflow Interrupt enable PBFLG 0x00B1 Pulse Accumulator B Flag Register PBFLG.PBOVF 1 Pulse Accumulator B Overflow Flag PA3H 0x00B2 8-Bit Pulse Accumulators Holding Register 3 PA2H 0x00B3 8-Bit Pulse Accumulators Holding Register 2 PA1H 0x00B4 8-Bit Pulse Accumulators Holding Register 1 PA0H 0x00B5 8-Bit Pulse Accumulators Holding Register 0 MCCNTH 0x00B6 Modulus Down-Counter Count Register High MCCNTL 0x00B7 Modulus Down-Counter Count Register Low TC0HH 0x00B8 Timer Input Capture Holding Register 0 High TC0HL 0x00B9 Timer Input Capture Holding Register 0 Low TC1HH 0x00BA Timer Input Capture Holding Register 1 High TC1HL 0x00BB Timer Input Capture Holding Register 1 Low TC2HH 0x00BC Timer Input Capture Holding Register 2 High TC2HL 0x00BD Timer Input Capture Holding Register 2 Low TC3HH 0x00BE Timer Input Capture Holding Register 3 High TC3HL 0x00BF Timer Input Capture Holding Register 3 Low SC0BDH 0x00C0 SCI0 Baud Rate Control Register High SC0BDH.BTST 7 Reserved for test function SC0BDH.BSPL 6 Reserved for test function SC0BDH.BRLD 5 Reserved for test function SC0BDH.SBR12 4 SC0BDH.SBR11 3 SC0BDH.SBR10 2 SC0BDH.SBR9 1 SC0BDH.SBR8 0 SC0BDL 0x00C1 SCI0 Baud Rate Control Register Low SC0BDL.SBR7 7 SC0BDL.SBR6 6 SC0BDL.SBR5 5 SC0BDL.SBR4 4 SC0BDL.SBR3 3 SC0BDL.SBR2 2 SC0BDL.SBR1 1 SC0BDL.SBR0 0 SC0CR1 0x00C2 SCI0 Control Register 1 SC0CR1.LOOPS 7 SCI LOOP Mode/Single Wire Mode Enable SC0CR1.WOMS 6 Wired-Or Mode for Serial Pins SC0CR1.RSRC 5 Receiver Source SC0CR1.M 4 Mode (select character format) SC0CR1.WAKE 3 Wake-up by Address Mark/Idle SC0CR1.ILT 2 Idle Line Type SC0CR1.PE 1 Parity Enable SC0CR1.PT 0 Parity Type SC0CR2 0x00C3 SCI0 Control Register 2 SC0CR2.TIE 7 Transmit Interrupt Enable SC0CR2.TCIE 6 Transmit Complete Interrupt Enable SC0CR2.RIE 5 Receiver Interrupt Enable SC0CR2.ILIE 4 Idle Line Interrupt Enable SC0CR2.TE 3 Transmitter Enable SC0CR2.RE 2 Receiver Enable SC0CR2.RWU 1 Receiver Wake-Up Control SC0CR2.SBK 0 Send Break SC0SR1 0x00C4 SCI0 Status Register 1 SC0SR1.TDRE 7 Transmit Data Register Empty Flag SC0SR1.TC 6 Transmit Complete Flag SC0SR1.RDRF 5 Receive Data Register Full Flag SC0SR1.IDLE 4 Idle Line Detected Flag SC0SR1.OR 3 Overrun Error Flag SC0SR1.NF 2 Noise Error Flag SC0SR1.FE 1 Framing Error Flag SC0SR1.PF 0 Parity Error Flag SC0SR2 0x00C5 SCI0 Status Register 2 SC0SR2.SCSWAI 7 Serial Communications Interface Stop in WAIT Mode SC0SR2.MIE 6 SC0SR2.MDL1 5 SC0SR2.MDL0 4 SC0SR2.RAF 0 Receiver Active Flag SC0DRH 0x00C6 SCI0 Data Register High SC0DRH.R8 7 Receive Bit 8 SC0DRH.T8 6 Transmit Bit 8 SC0DRL 0x00C7 SCI0 Data Register Low SC0DRL.R7_T7 7 Receive/Transmit Data Bit 7 SC0DRL.R6_T6 6 Receive/Transmit Data Bit 6 SC0DRL.R5_T5 5 Receive/Transmit Data Bit 5 SC0DRL.R4_T4 4 Receive/Transmit Data Bit 4 SC0DRL.R3_T3 3 Receive/Transmit Data Bit 3 SC0DRL.R2_T2 2 Receive/Transmit Data Bit 2 SC0DRL.R1_T1 1 Receive/Transmit Data Bit 1 SC0DRL.R0_T0 0 Receive/Transmit Data Bit 0 SC1BDH 0x00C8 SCI1 Baud Rate Control Register High SC1BDH.BTST 7 Reserved for test function SC1BDH.BSPL 6 Reserved for test function SC1BDH.BRLD 5 Reserved for test function SC1BDH.SBR12 4 SC1BDH.SBR11 3 SC1BDH.SBR10 2 SC1BDH.SBR9 1 SC1BDH.SBR8 0 SC1BDL 0x00C9 SCI1Baud Rate Control Register Low SC1BDL.SBR7 7 SC1BDL.SBR6 6 SC1BDL.SBR5 5 SC1BDL.SBR4 4 SC1BDL.SBR3 3 SC1BDL.SBR2 2 SC1BDL.SBR1 1 SC1BDL.SBR0 0 SC1CR1 0x00CA SCI1 Control Register 1 SC1CR1.LOOPS 7 SCI LOOP Mode/Single Wire Mode Enable SC1CR1.WOMS 6 Wired-Or Mode for Serial Pins SC1CR1.RSRC 5 Receiver Source SC1CR1.M 4 Mode (select character format) SC1CR1.WAKE 3 Wake-up by Address Mark/Idle SC1CR1.ILT 2 Idle Line Type SC1CR1.PE 1 Parity Enable SC1CR1.PT 0 Parity Type SC1CR2 0x00CB SCI1 Control Register 2 SC1CR2.TIE 7 Transmit Interrupt Enable SC1CR2.TCIE 6 Transmit Complete Interrupt Enable SC1CR2.RIE 5 Receiver Interrupt Enable SC1CR2.ILIE 4 Idle Line Interrupt Enable SC1CR2.TE 3 Transmitter Enable SC1CR2.RE 2 Receiver Enable SC1CR2.RWU 1 Receiver Wake-Up Control SC1CR2.SBK 0 Send Break SC1SR1 0x00CC SCI1 Status Register 1 SC1SR1.TDRE 7 Transmit Data Register Empty Flag SC1SR1.TC 6 Transmit Complete Flag SC1SR1.RDRF 5 Receive Data Register Full Flag SC1SR1.IDLE 4 Idle Line Detected Flag SC1SR1.OR 3 Overrun Error Flag SC1SR1.NF 2 Noise Error Flag SC1SR1.FE 1 Framing Error Flag SC1SR1.PF 0 Parity Error Flag SC1SR2 0x00CD SCI1 Status Register 2 SC1SR2.SCSWAI 7 Serial Communications Interface Stop in WAIT Mode SC1SR2.RAF 0 Receiver Active Flag SC1DRH 0x00CE SCI1 Data Register High SC1DRH.R8 7 Receive Bit 8 SC1DRH.T8 6 Transmit Bit 8 SC1DRL 0x00CF SCI1 Data Register Low SC1DRL.R7_T7 7 Receive/Transmit Data Bit 7 SC1DRL.R6_T6 6 Receive/Transmit Data Bit 6 SC1DRL.R5_T5 5 Receive/Transmit Data Bit 5 SC1DRL.R4_T4 4 Receive/Transmit Data Bit 4 SC1DRL.R3_T3 3 Receive/Transmit Data Bit 3 SC1DRL.R2_T2 2 Receive/Transmit Data Bit 2 SC1DRL.R1_T1 1 Receive/Transmit Data Bit 1 SC1DRL.R0_T0 0 Receive/Transmit Data Bit 0 SP0CR1 0x00D0 SPI Control Register 1 SP0CR1.SPIE 7 SPI Interrupt Enable SP0CR1.SPE 6 SPI System Enable SP0CR1.SWOM 5 Port S Wired-OR Mode SP0CR1.MSTR 4 SPI Master/Slave Mode Select SP0CR1.CPOL 3 SPI Clock Polarity SP0CR1.CPHA 2 Clock Phase SP0CR1.SSOE 1 Slave Select Output Enable SP0CR1.LSBF 0 SPI LSB First enable SP0CR2 0x00D1 SPI Control Register 2 SP0CR2.SPSWAI 1 Serial Interface Stop in WAIT mode SP0CR2.SPC0 0 Serial Pin Control 0 SP0BR 0x00D2 SPI Baud Rate Register SP0BR.SPR2 2 SPI Clock (SCK) Rate Select Bit 2 SP0BR.SPR1 1 SPI Clock (SCK) Rate Select Bit 1 SP0BR.SPR0 0 SPI Clock (SCK) Rate Select Bit 0 SP0SR 0x00D3 SPI Status Register SP0SR.SPIF 7 SPI Interrupt Request SP0SR.WCOL 6 Write Collision Status Flag SP0SR.MODF 4 SPI Mode Error Interrupt Status Flag RESERVED00D4 0x00D4 RESERVED SP0DR 0x00D5 SPI Data Register PORTS 0x00D6 Port S Data Register PORTS.PS7 7 Port S Data Bit 7 PORTS.PS6 6 Port S Data Bit 6 PORTS.PS5 5 Port S Data Bit 5 PORTS.PS4 4 Port S Data Bit 4 PORTS.PS3 3 Port S Data Bit 3 PORTS.PS2 2 Port S Data Bit 2 PORTS.PS1 1 Port S Data Bit 1 PORTS.PS0 0 Port S Data Bit 0 DDRS 0x00D7 Port S Data Direction Register DDRS.DDS7 7 Port S Data Direction Bit 7 DDRS.DDS6 6 Port S Data Direction Bit 6 DDRS.DDS5 5 Port S Data Direction Bit 5 DDRS.DDS4 4 Port S Data Direction Bit 4 DDRS.DDS3 3 Port S Data Direction Bit 3 DDRS.DDS2 2 Port S Data Direction Bit 2 DDRS.DDS1 1 Port S Data Direction Bit 1 DDRS.DDS0 0 Port S Data Direction Bit 0 RESERVED00D8 0x00D8 RESERVED PURDS 0x00D9 Pull-Up Register for Port S PURDS.RDPS2 6 Reduce Drive of Port S[7:4] PURDS.RDPS1 5 Reduce Drive of Port S[3:2] PURDS.RDPS0 4 Reduce Drive of Port S[1:0] PURDS.PUPS2 2 Pull-up Port S[7:4] Enable PURDS.PUPS1 1 Pull-up Port S[3:2] Enable PURDS.PUPS0 0 Pull-up Port S[1:0] Enable RESERVED00DA 0x00DA RESERVED RESERVED00DB 0x00DB RESERVED RESERVED00DC 0x00DC RESERVED RESERVED00DD 0x00DD RESERVED RESERVED00DE 0x00DE RESERVED RESERVED00DF 0x00DF RESERVED RESERVED00E0 0x00E0 RESERVED RESERVED00E1 0x00E1 RESERVED RESERVED00E2 0x00E2 RESERVED RESERVED00E3 0x00E3 RESERVED RESERVED00E4 0x00E4 RESERVED RESERVED00E5 0x00E5 RESERVED RESERVED00E6 0x00E6 RESERVED RESERVED00E7 0x00E7 RESERVED RESERVED00E8 0x00E8 RESERVED RESERVED00E9 0x00E9 RESERVED RESERVED00EA 0x00EA RESERVED RESERVED00EB 0x00EB RESERVED RESERVED00EC 0x00EC RESERVED RESERVED00ED 0x00ED RESERVED EEDIVH 0x00EE EEPROM Modulus Divider High EEDIVH.EEDIV9 1 Prescaler divider 9 EEDIVH.EEDIV8 0 Prescaler divider 8 EEDIVL 0x00EF EEPROM Modulus Divider Low EEDIVL.EEDIV7 7 Prescaler divider 7 EEDIVL.EEDIV6 6 Prescaler divider 6 EEDIVL.EEDIV5 5 Prescaler divider 5 EEDIVL.EEDIV4 4 Prescaler divider 4 EEDIVL.EEDIV3 3 Prescaler divider 3 EEDIVL.EEDIV2 2 Prescaler divider 2 EEDIVL.EEDIV1 1 Prescaler divider 1 EEDIVL.EEDIV0 0 Prescaler divider 0 EEMCR 0x00F0 EEPROM Module Configuration EEMCR.NOBDML 7 Background Debug Mode Lockout Disable EEMCR.NOSHW 6 SHADOW Word Disable EEMCR.EESWAI 2 EEPROM Stops in Wait Mode EEMCR.PROTLCK 1 Block Protect Write Lock EEMCR.DMY 0 Dummy bit EEPROT 0x00F1 EEPROM Block Protect EEPROT.SHPROT 7 SHADOW Word Protection EEPROT.BPROT4 4 EEPROM Block Protection 4 EEPROT.BPROT3 3 EEPROM Block Protection 3 EEPROT.BPROT2 2 EEPROM Block Protection 2 EEPROT.BPROT1 1 EEPROM Block Protection 1 EEPROT.BPROT0 0 EEPROM Block Protection 0 RESERVED00D2 0x00F2 RESERVED EEPROG 0x00F3 EEPROM Control EEPROG.BULKP 7 Bulk Erase Protection EEPROG.AUTO 5 Automatic shutdown of program/erase operation EEPROG.BYTE 4 Byte and Aligned Word Erase EEPROG.ROW 3 Row or Bulk Erase (when BYTE = 0) EEPROG.ERASE 2 Erase Control EEPROG.EELAT 1 EEPROM Latch Control EEPROG.EEPGM 0 Program and Erase Enable FEE32LCK 0x00F4 Flash EEPROM Lock Control Register FEE32LCK.LOCK 0 Lock Register Bit FEE32MCR 0x00F5 Flash EEPROM Module Configuration Register FEE32MCR.BOOTP 0 Boot Protect RESERVED00D6 0x00F6 RESERVED FEE32CTL 0x00F7 Flash EEPROM Control Register FEE32CTL.FEESWAI 4 Flash EEPROM Stop in Wait Control FEE32CTL.HVEN 3 High-Voltage Enable FEE32CTL.ERAS 1 Erase Control FEE32CTL.PGM 0 Program Control FEE28LCK 0x00F8 Flash EEPROM Lock Control Register FEE28LCK.LOCK 0 Lock Register Bit FEE28MCR 0x00F9 Flash EEPROM Module Configuration Register FEE28MCR.BOOTP 0 Boot Protect RESERVED00DA 0x00FA RESERVED FEE28CTL 0x00FB Flash EEPROM Control Register FEE28CTL.FEESWAI 4 Flash EEPROM Stop in Wait Control FEE28CTL.HVEN 3 High-Voltage Enable FEE28CTL.ERAS 1 Erase Control FEE28CTL.PGM 0 Program Control RESERVED00DC 0x00FC RESERVED RESERVED00DD 0x00FD RESERVED RESERVED00DE 0x00FE RESERVED RESERVED00DF 0x00FF RESERVED CMCR0 0x0100 msCAN12 Module Control Register 0 CMCR0.CSWAI 5 CAN Stops in Wait Mode CMCR0.SYNCH 4 Synchronized Status CMCR0.TLNKEN 3 Timer Enable CMCR0.SLPAK 2 SLEEP Mode Acknowledge CMCR0.SLPRQ 1 SLEEP request CMCR0.SFTRES 0 SOFT_RESET CMCR1 0x0101 msCAN12 Module Control Register 1 CMCR1.LOOPB 2 Loop Back Self Test Mode CMCR1.WUPM 1 Wake-Up Mode CMCR1.CLKSRC 0 msCAN12 Clock Source CBTR0 0x0102 msCAN12 Bus Timing Register 0 CBTR0.SJW1 7 Synchronization Jump Width 1 CBTR0.SJW0 6 Synchronization Jump Width 0 CBTR0.BRP5 5 Baud Rate Prescaler 5 CBTR0.BRP4 4 Baud Rate Prescaler 4 CBTR0.BRP3 3 Baud Rate Prescaler 3 CBTR0.BRP2 2 Baud Rate Prescaler 2 CBTR0.BRP1 1 Baud Rate Prescaler 1 CBTR0.BRP0 0 Baud Rate Prescaler 0 CBTR1 0x0103 msCAN12 Bus Timing Register 1 CBTR1.SAMP 7 Sampling CBTR1.TSEG22 6 Time Segment 22 CBTR1.TSEG21 5 Time Segment 21 CBTR1.TSEG20 4 Time Segment 20 CBTR1.TSEG13 3 Time Segment 13 CBTR1.TSEG12 2 Time Segment 12 CBTR1.TSEG11 1 Time Segment 11 CBTR1.TSEG10 0 Time Segment 10 CRFLG 0x0104 msCAN12 Receiver Flag Register CRFLG.WUPIF 7 Wake-up Interrupt Flag CRFLG.RWRNIF 6 Receiver Warning Interrupt Flag CRFLG.TWRNIF 5 Transmitter Warning Interrupt Flag CRFLG.RERRIF 4 Receiver Error Passive Interrupt Flag CRFLG.TERRIF 3 Transmitter Error Passive Interrupt Flag CRFLG.BOFFIF 2 BUSOFF Interrupt Flag CRFLG.OVRIF 1 Overrun Interrupt Flag CRFLG.RXF 0 Receive Buffer Full CRIER 0x0105 msCAN12 Receiver Interrupt Enable Register CRIER.WUPIE 7 Wake-up Interrupt Enable CRIER.RWRNIE 6 Receiver Warning Interrupt Enable CRIER.TWRNIE 5 Transmitter Warning Interrupt Enable CRIER.RERRIE 4 Receiver Error Passive Interrupt Enable CRIER.TERRIE 3 Transmitter Error Passive Interrupt Enable CRIER.BOFFIE 2 BUSOFF Interrupt Enable CRIER.OVRIE 1 Overrun Interrupt Enable CRIER.RXFIE 0 Receiver Full Interrupt Enable CTFLG 0x0106 msCAN12 Transmitter Flag Register CTFLG.ABTAK2 6 Abort Acknowledge 2 CTFLG.ABTAK1 5 Abort Acknowledge 1 CTFLG.ABTAK0 4 Abort Acknowledge 0 CTFLG.TXE2 2 Transmitter Buffer Empty 2 CTFLG.TXE1 1 Transmitter Buffer Empty 1 CTFLG.TXE0 0 Transmitter Buffer Empty 0 CTCR 0x0107 msCAN12 Transmitter Control Register CTCR.ABTRQ2 6 Abort Request 2 CTCR.ABTRQ1 5 Abort Request 1 CTCR.ABTRQ0 4 Abort Request 0 CTCR.TXEIE2 2 Transmitter Empty Interrupt Enable 2 CTCR.TXEIE1 1 Transmitter Empty Interrupt Enable 1 CTCR.TXEIE0 0 Transmitter Empty Interrupt Enable 0 CIDAC 0x0108 msCAN12 Identifier Acceptance Control Register CIDAC.IDAM1 5 Identifier Acceptance Mode 1 CIDAC.IDAM0 4 Identifier Acceptance Mode 0 CIDAC.IDHIT2 2 Identifier Acceptance Hit Indicator 2 CIDAC.IDHIT1 1 Identifier Acceptance Hit Indicator 1 CIDAC.IDHIT0 0 Identifier Acceptance Hit Indicator 0 RESERVED0109 0x0109 RESERVED RESERVED010A 0x010A RESERVED RESERVED010B 0x010B RESERVED RESERVED010C 0x010C RESERVED RESERVED010D 0x010D RESERVED CRXERR 0x010E msCAN12 Receive Error Counter CRXERR.RXERR7 7 CRXERR.RXERR6 6 CRXERR.RXERR5 5 CRXERR.RXERR4 4 CRXERR.RXERR3 3 CRXERR.RXERR2 2 CRXERR.RXERR1 1 CRXERR.RXERR0 0 CTXERR 0x010F msCAN12 Transmit Error Counter CTXERR.TXERR7 7 CTXERR.TXERR6 6 CTXERR.TXERR5 5 CTXERR.TXERR4 4 CTXERR.TXERR3 3 CTXERR.TXERR2 2 CTXERR.TXERR1 1 CTXERR.TXERR0 0 CIDAR0 0x0110 msCAN12 Identifier Acceptance Register 0 CIDAR0.AC7 7 Acceptance Code Bit 7 CIDAR0.AC6 6 Acceptance Code Bit 6 CIDAR0.AC5 5 Acceptance Code Bit 5 CIDAR0.AC4 4 Acceptance Code Bit 4 CIDAR0.AC3 3 Acceptance Code Bit 3 CIDAR0.AC2 2 Acceptance Code Bit 2 CIDAR0.AC1 1 Acceptance Code Bit 1 CIDAR0.AC0 0 Acceptance Code Bit 0 CIDAR1 0x0111 msCAN12 Identifier Acceptance Register 1 CIDAR1.AC7 7 Acceptance Code Bit 7 CIDAR1.AC6 6 Acceptance Code Bit 6 CIDAR1.AC5 5 Acceptance Code Bit 5 CIDAR1.AC4 4 Acceptance Code Bit 4 CIDAR1.AC3 3 Acceptance Code Bit 3 CIDAR1.AC2 2 Acceptance Code Bit 2 CIDAR1.AC1 1 Acceptance Code Bit 1 CIDAR1.AC0 0 Acceptance Code Bit 0 CIDAR2 0x0112 msCAN12 Identifier Acceptance Register 2 CIDAR2.AC7 7 Acceptance Code Bit 7 CIDAR2.AC6 6 Acceptance Code Bit 6 CIDAR2.AC5 5 Acceptance Code Bit 5 CIDAR2.AC4 4 Acceptance Code Bit 4 CIDAR2.AC3 3 Acceptance Code Bit 3 CIDAR2.AC2 2 Acceptance Code Bit 2 CIDAR2.AC1 1 Acceptance Code Bit 1 CIDAR2.AC0 0 Acceptance Code Bit 0 CIDAR3 0x0113 msCAN12 Identifier Acceptance Register 3 CIDAR3.AC7 7 Acceptance Code Bit 7 CIDAR3.AC6 6 Acceptance Code Bit 6 CIDAR3.AC5 5 Acceptance Code Bit 5 CIDAR3.AC4 4 Acceptance Code Bit 4 CIDAR3.AC3 3 Acceptance Code Bit 3 CIDAR3.AC2 2 Acceptance Code Bit 2 CIDAR3.AC1 1 Acceptance Code Bit 1 CIDAR3.AC0 0 Acceptance Code Bit 0 CIDMR0 0x0114 msCAN12 Identifier Mask Register 0 CIDMR0.AM7 7 Acceptance Mask Bit 7 CIDMR0.AM6 6 Acceptance Mask Bit 6 CIDMR0.AM5 5 Acceptance Mask Bit 5 CIDMR0.AM4 4 Acceptance Mask Bit 4 CIDMR0.AM3 3 Acceptance Mask Bit 3 CIDMR0.AM2 2 Acceptance Mask Bit 2 CIDMR0.AM1 1 Acceptance Mask Bit 1 CIDMR0.AM0 0 Acceptance Mask Bit 0 CIDMR1 0x0115 msCAN12 Identifier Mask Register 1 CIDMR1.AM7 7 Acceptance Mask Bit 7 CIDMR1.AM6 6 Acceptance Mask Bit 6 CIDMR1.AM5 5 Acceptance Mask Bit 5 CIDMR1.AM4 4 Acceptance Mask Bit 4 CIDMR1.AM3 3 Acceptance Mask Bit 3 CIDMR1.AM2 2 Acceptance Mask Bit 2 CIDMR1.AM1 1 Acceptance Mask Bit 1 CIDMR1.AM0 0 Acceptance Mask Bit 0 CIDMR2 0x0116 msCAN12 Identifier Mask Register 2 CIDMR2.AM7 7 Acceptance Mask Bit 7 CIDMR2.AM6 6 Acceptance Mask Bit 6 CIDMR2.AM5 5 Acceptance Mask Bit 5 CIDMR2.AM4 4 Acceptance Mask Bit 4 CIDMR2.AM3 3 Acceptance Mask Bit 3 CIDMR2.AM2 2 Acceptance Mask Bit 2 CIDMR2.AM1 1 Acceptance Mask Bit 1 CIDMR2.AM0 0 Acceptance Mask Bit 0 CIDMR3 0x0117 msCAN12 Identifier Mask Register 3 CIDMR3.AM7 7 Acceptance Mask Bit 7 CIDMR3.AM6 6 Acceptance Mask Bit 6 CIDMR3.AM5 5 Acceptance Mask Bit 5 CIDMR3.AM4 4 Acceptance Mask Bit 4 CIDMR3.AM3 3 Acceptance Mask Bit 3 CIDMR3.AM2 2 Acceptance Mask Bit 2 CIDMR3.AM1 1 Acceptance Mask Bit 1 CIDMR3.AM0 0 Acceptance Mask Bit 0 CIDAR4 0x0118 msCAN12 Identifier Acceptance Register 4 CIDAR4.AC7 7 Acceptance Code Bit 7 CIDAR4.AC6 6 Acceptance Code Bit 6 CIDAR4.AC5 5 Acceptance Code Bit 5 CIDAR4.AC4 4 Acceptance Code Bit 4 CIDAR4.AC3 3 Acceptance Code Bit 3 CIDAR4.AC2 2 Acceptance Code Bit 2 CIDAR4.AC1 1 Acceptance Code Bit 1 CIDAR4.AC0 0 Acceptance Code Bit 0 CIDAR5 0x0119 msCAN12 Identifier Acceptance Register 5 CIDAR5.AC7 7 Acceptance Code Bit 7 CIDAR5.AC6 6 Acceptance Code Bit 6 CIDAR5.AC5 5 Acceptance Code Bit 5 CIDAR5.AC4 4 Acceptance Code Bit 4 CIDAR5.AC3 3 Acceptance Code Bit 3 CIDAR5.AC2 2 Acceptance Code Bit 2 CIDAR5.AC1 1 Acceptance Code Bit 1 CIDAR5.AC0 0 Acceptance Code Bit 0 CIDAR6 0x011A msCAN12 Identifier Acceptance Register 6 CIDAR6.AC7 7 Acceptance Code Bit 7 CIDAR6.AC6 6 Acceptance Code Bit 6 CIDAR6.AC5 5 Acceptance Code Bit 5 CIDAR6.AC4 4 Acceptance Code Bit 4 CIDAR6.AC3 3 Acceptance Code Bit 3 CIDAR6.AC2 2 Acceptance Code Bit 2 CIDAR6.AC1 1 Acceptance Code Bit 1 CIDAR6.AC0 0 Acceptance Code Bit 0 CIDAR7 0x011B msCAN12 Identifier Acceptance Register 7 CIDAR7.AC7 7 Acceptance Code Bit 7 CIDAR7.AC6 6 Acceptance Code Bit 6 CIDAR7.AC5 5 Acceptance Code Bit 5 CIDAR7.AC4 4 Acceptance Code Bit 4 CIDAR7.AC3 3 Acceptance Code Bit 3 CIDAR7.AC2 2 Acceptance Code Bit 2 CIDAR7.AC1 1 Acceptance Code Bit 1 CIDAR7.AC0 0 Acceptance Code Bit 0 CIDMR4 0x011C msCAN12 Identifier Mask Register 4 CIDMR4.AM7 7 Acceptance Mask Bit 7 CIDMR4.AM6 6 Acceptance Mask Bit 6 CIDMR4.AM5 5 Acceptance Mask Bit 5 CIDMR4.AM4 4 Acceptance Mask Bit 4 CIDMR4.AM3 3 Acceptance Mask Bit 3 CIDMR4.AM2 2 Acceptance Mask Bit 2 CIDMR4.AM1 1 Acceptance Mask Bit 1 CIDMR4.AM0 0 Acceptance Mask Bit 0 CIDMR5 0x011D msCAN12 Identifier Mask Register 5 CIDMR5.AM7 7 Acceptance Mask Bit 7 CIDMR5.AM6 6 Acceptance Mask Bit 6 CIDMR5.AM5 5 Acceptance Mask Bit 5 CIDMR5.AM4 4 Acceptance Mask Bit 4 CIDMR5.AM3 3 Acceptance Mask Bit 3 CIDMR5.AM2 2 Acceptance Mask Bit 2 CIDMR5.AM1 1 Acceptance Mask Bit 1 CIDMR5.AM0 0 Acceptance Mask Bit 0 CIDMR6 0x011E msCAN12 Identifier Mask Register 6 CIDMR6.AM7 7 Acceptance Mask Bit 7 CIDMR6.AM6 6 Acceptance Mask Bit 6 CIDMR6.AM5 5 Acceptance Mask Bit 5 CIDMR6.AM4 4 Acceptance Mask Bit 4 CIDMR6.AM3 3 Acceptance Mask Bit 3 CIDMR6.AM2 2 Acceptance Mask Bit 2 CIDMR6.AM1 1 Acceptance Mask Bit 1 CIDMR6.AM0 0 Acceptance Mask Bit 0 CIDMR7 0x011F msCAN12 Identifier Mask Register 7 CIDMR7.AM7 7 Acceptance Mask Bit 7 CIDMR7.AM6 6 Acceptance Mask Bit 6 CIDMR7.AM5 5 Acceptance Mask Bit 5 CIDMR7.AM4 4 Acceptance Mask Bit 4 CIDMR7.AM3 3 Acceptance Mask Bit 3 CIDMR7.AM2 2 Acceptance Mask Bit 2 CIDMR7.AM1 1 Acceptance Mask Bit 1 CIDMR7.AM0 0 Acceptance Mask Bit 0 RESERVED0120 0x0120 RESERVED RESERVED0121 0x0121 RESERVED RESERVED0122 0x0122 RESERVED RESERVED0123 0x0123 RESERVED RESERVED0124 0x0124 RESERVED RESERVED0125 0x0125 RESERVED RESERVED0126 0x0126 RESERVED RESERVED0127 0x0127 RESERVED RESERVED0128 0x0128 RESERVED RESERVED0129 0x0129 RESERVED RESERVED012A 0x012A RESERVED RESERVED012B 0x012B RESERVED RESERVED012C 0x012C RESERVED RESERVED012D 0x012D RESERVED RESERVED012E 0x012E RESERVED RESERVED012F 0x012F RESERVED RESERVED0130 0x0130 RESERVED RESERVED0131 0x0131 RESERVED RESERVED0132 0x0132 RESERVED RESERVED0133 0x0133 RESERVED RESERVED0134 0x0134 RESERVED RESERVED0135 0x0135 RESERVED RESERVED0136 0x0136 RESERVED RESERVED0137 0x0137 RESERVED RESERVED0138 0x0138 RESERVED RESERVED0139 0x0139 RESERVED RESERVED013A 0x013A RESERVED RESERVED013B 0x013B RESERVED RESERVED013C 0x013C RESERVED PCTLCAN 0x013D msCAN12 Port CAN Control Register PCTLCAN.PUPCAN 1 Pull-Up Enable Port CAN PCTLCAN.RDPCAN 0 Reduced Drive Port CAN PORTCAN 0x013E msCAN12 Port CAN Data Register PORTCAN.PCAN7 7 Port CAN Data Bit 7 PORTCAN.PCAN6 6 Port CAN Data Bit 6 PORTCAN.PCAN5 5 Port CAN Data Bit 5 PORTCAN.PCAN4 4 Port CAN Data Bit 4 PORTCAN.PCAN3 3 Port CAN Data Bit 3 PORTCAN.PCAN2 2 Port CAN Data Bit 2 PORTCAN.TxCAN 1 PORTCAN.RxCAN 0 DDRCAN 0x013F msCAN12 Port CAN Data Direction Register DDRCAN.DDCAN7 7 Data Direction Port CAN Bit 7 DDRCAN.DDCAN6 6 Data Direction Port CAN Bit 6 DDRCAN.DDCAN5 5 Data Direction Port CAN Bit 5 DDRCAN.DDCAN4 4 Data Direction Port CAN Bit 4 DDRCAN.DDCAN3 3 Data Direction Port CAN Bit 3 DDRCAN.DDCAN2 2 Data Direction Port CAN Bit 2 ATD1CTL2 0x01E2 ATD1 Control Register 2 ATD1CTL2.ADPU 7 ATD Disable ATD1CTL2.ADPU 6 ATD Fast Flag Clear All ATD1CTL2.ASWAI 5 ATD Wait Mode ATD1CTL2.DJM 4 Result Register Data Justification Mode ATD1CTL2.DSGN 3 Signed/Unsigned Result Data Mode ATD1CTL2.ASCIE 1 ATD Sequence Complete Interrupt Enable ATD1CTL2.ASCIF 0 ATD Sequence Complete Interrupt Flag ATD1CTL3 0x01E3 ATD1 Control Register 3 ATD1CTL3.S1C 3 Conversion Sequence Length ATD1CTL3.FIFO 2 Result Register FIFO Mode ATD1CTL3.FRZ1 1 Background Debug Freeze Enable 1 ATD1CTL3.FRZ0 0 Background Debug Freeze Enable 0 ATD1CTL4 0x01E4 ATD1 Control Register 4 ATD1CTL4.RES10 7 A/D Resolution Select ATD1CTL4.SMP1 6 Sample Time Select 1 ATD1CTL4.SMP0 5 Sample Time Select 0 ATD1CTL4.PRS4 4 ATD Clock Prescaler 4 ATD1CTL4.PRS3 3 ATD Clock Prescaler 3 ATD1CTL4.PRS2 2 ATD Clock Prescaler 2 ATD1CTL4.PRS1 1 ATD Clock Prescaler 1 ATD1CTL4.PRS0 0 ATD Clock Prescaler 0 ATD1CTL5 0x01E5 ATD1 Control Register 5 ATD1CTL5.S8C 6 Conversion Sequence Length ATD1CTL5.SCAN 5 Continuous Conversion Sequence Mode ATD1CTL5.MULT 4 Multi-Channel Sample Mode ATD1CTL5.SC 3 Special Channel Conversion Mode ATD1CTL5.CC 2 Analog Input Channel Select Code C ATD1CTL5.CB 1 Analog Input Channel Select Code B ATD1CTL5.CA 0 Analog Input Channel Select Code A ATD1STAT0 0x01E6 ATD1 Status Register ATD1STAT0.SCF 7 Sequence Complete Flag ATD1STAT0.CC2 2 Conversion Counter 2 ATD1STAT0.CC1 1 Conversion Counter 1 ATD1STAT0.CC0 0 Conversion Counter 0 ATD1STAT1 0x01E7 ATD1 Status Register ATD1STAT1.CCF7 7 Conversion Complete Flag 7 ATD1STAT1.CCF6 6 Conversion Complete Flag 6 ATD1STAT1.CCF5 5 Conversion Complete Flag 5 ATD1STAT1.CCF4 4 Conversion Complete Flag 4 ATD1STAT1.CCF3 3 Conversion Complete Flag 3 ATD1STAT1.CCF2 2 Conversion Complete Flag 2 ATD1STAT1.CCF1 1 Conversion Complete Flag 1 ATD1STAT1.CCF0 0 Conversion Complete Flag 0 ATD1TESTH 0x01E8 ATD1 Test Register ATD1TESTH.SAR9 7 Successive Approximation Register 9 ATD1TESTH.SAR8 6 Successive Approximation Register 8 ATD1TESTH.SAR7 5 Successive Approximation Register 7 ATD1TESTH.SAR6 4 Successive Approximation Register 6 ATD1TESTH.SAR5 3 Successive Approximation Register 5 ATD1TESTH.SAR4 2 Successive Approximation Register 4 ATD1TESTH.SAR3 1 Successive Approximation Register 3 ATD1TESTH.SAR2 0 Successive Approximation Register 2 ATD1TESTL 0x01E9 ATD1 Test Register ATD1TESTL.SAR1 7 Successive Approximation Register 1 ATD1TESTL.SAR0 6 Successive Approximation Register 0 ATD1TESTL.RST 5 Test Mode Reset Bit RESERVED01EA 0x01EA RESERVED RESERVED01EB 0x01EB RESERVED RESERVED01EC 0x01EC RESERVED RESERVED01ED 0x01ED RESERVED RESERVED01EE 0x01EE RESERVED PORTAD1 0x01EF Port AD Data Input Register 1 PORTAD1.PAD17 7 Port AD Data Input Bit 7 PORTAD1.PAD16 6 Port AD Data Input Bit 6 PORTAD1.PAD15 5 Port AD Data Input Bit 5 PORTAD1.PAD14 4 Port AD Data Input Bit 4 PORTAD1.PAD13 3 Port AD Data Input Bit 3 PORTAD1.PAD12 2 Port AD Data Input Bit 2 PORTAD1.PAD11 1 Port AD Data Input Bit 1 PORTAD1.PAD10 0 Port AD Data Input Bit 0 ADR10H 0x01F0 A/D Converter Result Register 10 High ADR10L 0x01F1 A/D Converter Result Register 10 Low ADR11H 0x01F2 A/D Converter Result Register 11 High ADR11H 0x01F3 A/D Converter Result Register 11 Low ADR12H 0x01F4 A/D Converter Result Register 12 High ADR12H 0x01F5 A/D Converter Result Register 12 Low ADR13H 0x01F6 A/D Converter Result Register 13 High ADR13H 0x01F7 A/D Converter Result Register 13 Low ADR14H 0x01F8 A/D Converter Result Register 14 High ADR14H 0x01F9 A/D Converter Result Register 14 Low ADR15H 0x01FA A/D Converter Result Register 15 High ADR15H 0x01FB A/D Converter Result Register 15 Low ADR16H 0x01FC A/D Converter Result Register 16 High ADR16H 0x01FD A/D Converter Result Register 16 Low ADR17H 0x01FE A/D Converter Result Register 17 High ADR17H 0x01FF A/D Converter Result Register 17 Low .68HC912D60P ; MEMORY MAP area DATA FSR0 0x0000:0x0140 area DATA RECEIVE_BUF 0x0140:0x0150 area DATA TRANSMIT_BUF_0 0x0150:0x0160 area DATA TRANSMIT_BUF_1 0x0160:0x0170 area DATA TRANSMIT_BUF_1 0x0170:0x0180 area BSS RESERVED 0x0180:0x01E2 area DATA FSR1 0x01E2:0x0200 area DATA RAM 0x0200:0x0800 area BSS RESERVED 0x0800:0x0C00 area DATA EEPROM 0x0C00:0x1000 area BSS RESERVED 0x1000:0xFF00 area DATA USER_VEC 0xFF00:0x10000 ; Interrupt and reset vector assignments interrupt __RESET 0xFFFE Reset interrupt _COPCTL 0xFFFC Clock monitor fail reset interrupt COP_F_R 0xFFFA COP failure reset interrupt UIT 0xFFF8 Unimplemented instruction trap interrupt SWI 0xFFF6 SWI interrupt XIRQ 0xFFF4 XIRQ interrupt INTCR_IRQEN 0xFFF2 IRQ interrupt RTICTL_RTIE 0xFFF0 Real time interrupt interrupt TMSK1_C0I 0xFFEE Timer channel 0 interrupt TMSK1_C1I 0xFFEC Timer channel 1 interrupt TMSK1_C2I 0xFFEA Timer channel 2 interrupt TMSK1_C3I 0xFFE8 Timer channel 3 interrupt TMSK1_C4I 0xFFE6 Timer channel 4 interrupt TMSK1_C5I 0xFFE4 Timer channel 5 interrupt TMSK1_C6I 0xFFE2 Timer channel 6 interrupt TMSK1_C7I 0xFFE0 Timer channel 7 interrupt TMSK2_TOI 0xFFDE Timer overflow interrupt PACTL_PAOVI 0xFFDC Pulse accumulator overflow interrupt PACTL_PAI 0xFFDA Pulse accumulator input edge interrupt SP0CR1_SPIE 0xFFD8 SPI serial transfer complete interrupt _SC0CR2 0xFFD6 SCI 0 interrupt _SC1CR2 0xFFD4 SCI 1 interrupt ATDxCTL2_ASCIE 0xFFD2 ATD0 or ATD1 interrupt CRIER_WUPIE 0xFFD0 MSCAN wake-up interrupt KWIEG_KWIEH 0xFFCE Key wake-up G or H interrupt MCCTL_MCZI 0xFFCC Modulus down counter underflow interrupt PBCTL_PBOVI 0xFFCA Pulse Accumulator B Overflow interrupt CRIER_ERR 0xFFC8 MSCAN errors interrupt CRIER_RXFIE 0xFFC6 MSCAN receive interrupt CTCR_TXEIE 0xFFC4 MSCAN transmit interrupt PLLCR_LOCKIE_LHIE 0xFFC2 CGM lock and limp home ; INPUT/ OUTPUT PORTS PORTA 0x0000 Port A Data Register PORTA.PA7 7 Port A Data Bit 7 PORTA.PA6 6 Port A Data Bit 6 PORTA.PA5 5 Port A Data Bit 5 PORTA.PA4 4 Port A Data Bit 4 PORTA.PA3 3 Port A Data Bit 3 PORTA.PA2 2 Port A Data Bit 2 PORTA.PA1 1 Port A Data Bit 1 PORTA.PA0 0 Port A Data Bit 0 PORTB 0x0001 Port B Data Register PORTB.PB7 7 Port B Data Bit 7 PORTB.PB6 6 Port B Data Bit 6 PORTB.PB5 5 Port B Data Bit 5 PORTB.PB4 4 Port B Data Bit 4 PORTB.PB3 3 Port B Data Bit 3 PORTB.PB2 2 Port B Data Bit 2 PORTB.PB1 1 Port B Data Bit 1 PORTB.PB0 0 Port B Data Bit 0 DDRA 0x0002 Port A Data Direction Register DDRA.DDA7 7 Port A Data Direction Bit 7 DDRA.DDA6 6 Port A Data Direction Bit 6 DDRA.DDA5 5 Port A Data Direction Bit 5 DDRA.DDA4 4 Port A Data Direction Bit 4 DDRA.DDA3 3 Port A Data Direction Bit 3 DDRA.DDA2 2 Port A Data Direction Bit 2 DDRA.DDA1 1 Port A Data Direction Bit 1 DDRA.DDA0 0 Port A Data Direction Bit 0 DDRB 0x0003 Port B Data Direction Register DDRB.DDB7 7 Port B Data Direction Bit 7 DDRB.DDB6 6 Port B Data Direction Bit 6 DDRB.DDB5 5 Port B Data Direction Bit 5 DDRB.DDB4 4 Port B Data Direction Bit 4 DDRB.DDB3 3 Port B Data Direction Bit 3 DDRB.DDB2 2 Port B Data Direction Bit 2 DDRB.DDB1 1 Port B Data Direction Bit 1 DDRB.DDB0 0 Port B Data Direction Bit 0 RESERVED0004 0x0004 RESERVED RESERVED0005 0x0005 RESERVED RESERVED0006 0x0006 RESERVED RESERVED0007 0x0007 RESERVED PORTE 0x0008 Port E Data Register PORTE.PE7 7 Port E Data Bit 7 PORTE.PE6 6 Port E Data Bit 6 PORTE.PE5 5 Port E Data Bit 5 PORTE.PE4 4 Port E Data Bit 4 PORTE.PE3 3 Port E Data Bit 3 PORTE.PE2 2 Port E Data Bit 2 PORTE.PE1 1 Port E Data Bit 1 PORTE.PE0 0 Port E Data Bit 0 DDRE 0x0009 Port E Data Direction Register DDRE.DDE7 7 Port E Data Direction Bit 7 DDRE.DDE6 6 Port E Data Direction Bit 6 DDRE.DDE5 5 Port E Data Direction Bit 5 DDRE.DDE4 4 Port E Data Direction Bit 4 DDRE.DDE3 3 Port E Data Direction Bit 3 DDRE.DDE2 2 Port E Data Direction Bit 2 PEAR 0x000A Port E Assignment Register PEAR.NDBE 7 No Data Bus Enable PEAR.CGMTE 6 Clock Generator Module Testing Enable PEAR.PIPOE 5 Pipe Status Signal Output Enable PEAR.NECLK 4 No External E Clock PEAR.LSTRE 3 Low Strobe (LSTRB) Enable PEAR.RDWE 2 Read/Write Enable PEAR.CALE 1 Calibration Reference Enable PEAR.DBENE 0 DBE or Inverted E Clock on Port E MODE 0x000B Mode Register MODE.SMODN 7 Mode Select Special MODE.MODB 6 Mode Select B MODE.MODA 5 Mode Select A MODE.ESTR 4 E Clock Stretch Enable MODE.IVIS 3 Internal Visibility MODE.EBSWAI 2 External Bus Module Stop in Wait Control MODE.EME 0 Emulate Port E PUCR 0x000C Pull-Up Control Register PUCR.PUPH 7 Pull-Up or Pull-Down Port H Enable PUCR.PUPG 6 Pull-Up or Pull-Down Port G Enable PUCR.PUPE 4 Pull-Up Port E Enable PUCR.PUPB 1 Pull-Up Port B Enable PUCR.PUPA 0 Pull-Up Port A Enable RDRIV 0x000D Reduced Drive of I/O Lines RDRIV.RDPH 6 Reduced Drive of Port H RDRIV.RDPG 5 Reduced Drive of Port G RDRIV.RDPE 3 Reduced Drive of Port E RDRIV.RDPB 1 Reduced Drive of Port B RDRIV.RDPA 0 Reduced Drive of Port A RESERVED000E 0x000E RESERVED RESERVED000F 0x000F RESERVED INITRM 0x0010 Initialization of Internal RAM Position Register INITRM.RAM15 7 Internal RAM map position 15 INITRM.RAM14 6 Internal RAM map position 14 INITRM.RAM13 5 Internal RAM map position 13 INITRM.RAM12 4 Internal RAM map position 12 INITRM.RAM11 3 Internal RAM map position 11 INITRG 0x0011 Initialization of Internal Register Position Register INITRG.REG15 7 Internal register map position 15 INITRG.REG14 6 Internal register map position 14 INITRG.REG13 5 Internal register map position 13 INITRG.REG12 4 Internal register map position 12 INITRG.REG11 3 Internal register map position 11 INITRG.MMSWAI 0 Memory Mapping Interface Stop in Wait Control INITEE 0x0012 Initialization of Internal EEPROM Position Register INITEE.EE15 7 Internal EEPROM map position 15 INITEE.EE14 6 Internal EEPROM map position 14 INITEE.EE13 5 Internal EEPROM map position 13 INITEE.EE12 4 Internal EEPROM map position 12 INITEE.EEON 0 internal EEPROM On (Enabled) MISC 0x0013 Miscellaneous Mapping Control Register MISC.MAPROM 7 Map Location of ROM MISC.NDRF 6 Narrow Data Bus for Register-Following Map Space MISC.RFSTR1 5 Register Following Stretch 1 MISC.RFSTR0 4 Register Following Stretch 0 MISC.EXSTR1 3 External Access Stretch 1 MISC.EXSTR0 2 External Access Stretch 0 MISC.ROMON28 1 Enable bits for ROM 28 MISC.ROMON32 0 Enable bits for ROM 32 RTICTL 0x0014 Real-Time Interrupt Control Register RTICTL.RTIE 7 Real Time Interrupt Enable RTICTL.RSWAI 6 RTI and COP Stop While in Wait RTICTL.RSBCK 5 RTI and COP Stop While in Background Debug Mode RTICTL.RTBYP 3 Real Time Interrupt Divider Chain Bypass RTICTL.RTR2 2 Real-Time Interrupt Rate Select 2 RTICTL.RTR1 1 Real-Time Interrupt Rate Select 1 RTICTL.RTR0 0 Real-Time Interrupt Rate Select 0 RTIFLG 0x0015 Real Time Interrupt Flag Register RTIFLG.RTIF 7 Real Time Interrupt Flag COPCTL 0x0016 COP Control Register COPCTL.CME 7 Clock Monitor Enable COPCTL.FCME 6 Force Clock Monitor Enable COPCTL.FCMCOP 5 Force Clock Monitor Reset or COP Watchdog Reset COPCTL.WCOP 4 Window COP mode COPCTL.DISR 3 Disable Resets from COP Watchdog and Clock Monitor COPCTL.CR2 2 COP Watchdog Timer Rate select bit 2 COPCTL.CR1 1 COP Watchdog Timer Rate select bit 1 COPCTL.CR0 0 COP Watchdog Timer Rate select bit 0 COPRST 0x0017 Arm/Reset COP Timer Register RESERVED0018 0x0018 RESERVED RESERVED0019 0x0019 RESERVED RESERVED001A 0x001A RESERVED RESERVED001B 0x001B RESERVED RESERVED001C 0x001C RESERVED RESERVED001D 0x001D RESERVED INTCR 0x001E Interrupt Control Register INTCR.IRQE 7 IRQ Select Edge Sensitive Only INTCR.IRQEN 6 External IRQ Enable INTCR.DLY 5 Enable Oscillator Start-up Delay on Exit from STOP HPRIO 0x001F Highest Priority I Interrupt HPRIO.PSEL5 5 HPRIO.PSEL4 4 HPRIO.PSEL3 3 HPRIO.PSEL2 2 HPRIO.PSEL1 1 BRKCT0 0x0020 Breakpoint Control Register 0 BRKCT0.BKEN1 7 Breakpoint Mode Enable 1 BRKCT0.BKEN0 6 Breakpoint Mode Enable 0 BRKCT0.BKPM 5 Break on Program Addresses BRKCT0.BK1ALE 3 Breakpoint 1 Range Control BRKCT0.BK0ALE 2 Breakpoint 0 Range Control BRKCT1 0x0021 Breakpoint Control Register 1 BRKCT1.BKDBE 6 Enable Data Bus BRKCT1.BKMBH 5 Breakpoint Mask High BRKCT1.BKMBL 4 Breakpoint Mask Low BRKCT1.BK1RWE 3 R/W Compare Enable BRKCT1.BK1RW 2 R/W Compare Value BRKCT1.BK0RWE 1 R/W Compare Enable BRKCT1.BK0RW 0 R/W Compare Value BRKAH 0x0022 Breakpoint Address Register, High Byte BRKAL 0x0023 Breakpoint Address Register, Low Byte BRKDH 0x0024 Breakpoint Data Register, High Byte BRKDL 0x0025 Breakpoint Data Register, Low Byte RESERVED0026 0x0026 RESERVED RESERVED0027 0x0027 RESERVED PORTG 0x0028 Port G Data Register PORTG.PG7 7 Port G Data Bit 7 PORTG.PG6 6 Port G Data Bit 6 PORTG.PG5 5 Port G Data Bit 5 PORTG.PG4 4 Port G Data Bit 4 PORTG.PG3 3 Port G Data Bit 3 PORTG.PG2 2 Port G Data Bit 2 PORTG.PG1 1 Port G Data Bit 1 PORTG.PG0 0 Port G Data Bit 0 PORTH 0x0029 Port H Data Register PORTH.PH7 7 Port H Data Bit 7 PORTH.PH6 6 Port H Data Bit 6 PORTH.PH5 5 Port H Data Bit 5 PORTH.PH4 4 Port H Data Bit 4 PORTH.PH3 3 Port H Data Bit 3 PORTH.PH2 2 Port H Data Bit 2 PORTH.PH1 1 Port H Data Bit 1 PORTH.PH0 0 Port H Data Bit 0 DDRG 0x002A Port G Data Direction Register DDRG.DDG7 7 Port G Data Direction Bit 7 DDRG.DDG6 6 Port G Data Direction Bit 6 DDRG.DDG5 5 Port G Data Direction Bit 5 DDRG.DDG4 4 Port G Data Direction Bit 4 DDRG.DDG3 3 Port G Data Direction Bit 3 DDRG.DDG2 2 Port G Data Direction Bit 2 DDRG.DDG1 1 Port G Data Direction Bit 1 DDRG.DDG0 0 Port G Data Direction Bit 0 DDRH 0x002B Port H Data Direction Register DDRH.DDH7 7 Port H Data Direction Bit 7 DDRH.DDH6 6 Port H Data Direction Bit 6 DDRH.DDH5 5 Port H Data Direction Bit 5 DDRH.DDH4 4 Port H Data Direction Bit 4 DDRH.DDH3 3 Port H Data Direction Bit 3 DDRH.DDH2 2 Port H Data Direction Bit 2 DDRH.DDH1 1 Port H Data Direction Bit 1 DDRH.DDH0 0 Port H Data Direction Bit 0 KWIEG 0x002C Key Wake-up Port G Interrupt Enable Register KWIEG.WI2CE 7 Wake-up I2C Enable KWIEG.KWIEG6 6 Key Wake-up Port G Interrupt Enables 6 KWIEG.KWIEG5 5 Key Wake-up Port G Interrupt Enables 5 KWIEG.KWIEG4 4 Key Wake-up Port G Interrupt Enables 4 KWIEG.KWIEG3 3 Key Wake-up Port G Interrupt Enables 3 KWIEG.KWIEG2 2 Key Wake-up Port G Interrupt Enables 2 KWIEG.KWIEG1 1 Key Wake-up Port G Interrupt Enables 1 KWIEG.KWIEG0 0 Key Wake-up Port G Interrupt Enables 0 KWIEH 0x002D Key Wake-up Port H Interrupt Enable Register KWIEH.KWIEH7 7 Key Wake-up Port H Interrupt Enables 7 KWIEH.KWIEH6 6 Key Wake-up Port H Interrupt Enables 6 KWIEH.KWIEH5 5 Key Wake-up Port H Interrupt Enables 5 KWIEH.KWIEH4 4 Key Wake-up Port H Interrupt Enables 4 KWIEH.KWIEH3 3 Key Wake-up Port H Interrupt Enables 3 KWIEH.KWIEH2 2 Key Wake-up Port H Interrupt Enables 2 KWIEH.KWIEH1 1 Key Wake-up Port H Interrupt Enables 1 KWIEH.KWIEH0 0 Key Wake-up Port H Interrupt Enables 0 KWIFG 0x002E Key Wake-up Port G Flag Register KWIFG.KWIFG6 6 Key Wake-up Port G Flag 6 KWIFG.KWIFG5 5 Key Wake-up Port G Flag 5 KWIFG.KWIFG4 4 Key Wake-up Port G Flag 4 KWIFG.KWIFG3 3 Key Wake-up Port G Flag 3 KWIFG.KWIFG2 2 Key Wake-up Port G Flag 2 KWIFG.KWIFG1 1 Key Wake-up Port G Flag 1 KWIFG.KWIFG0 0 Key Wake-up Port G Flag 0 KWIFH 0x002F Key Wake-up Port H Flag Register KWIFH.KWIFH7 7 Key Wake-up Port H Flag 7 KWIFH.KWIFH6 6 Key Wake-up Port H Flag 6 KWIFH.KWIFH5 5 Key Wake-up Port H Flag 5 KWIFH.KWIFH4 4 Key Wake-up Port H Flag 4 KWIFH.KWIFH3 3 Key Wake-up Port H Flag 3 KWIFH.KWIFH2 2 Key Wake-up Port H Flag 2 KWIFH.KWIFH1 1 Key Wake-up Port H Flag 1 KWIFH.KWIFH0 0 Key Wake-up Port H Flag 0 RESERVED0030 0x0030 RESERVED RESERVED0031 0x0031 RESERVED RESERVED0032 0x0032 RESERVED RESERVED0033 0x0033 RESERVED RESERVED0034 0x0034 RESERVED RESERVED0035 0x0035 RESERVED RESERVED0036 0x0036 RESERVED RESERVED0037 0x0037 RESERVED SYNR 0x0038 Synthesizer Register SYNR.SYN5 5 SYNR.SYN4 4 SYNR.SYN3 3 SYNR.SYN2 2 SYNR.SYN1 1 SYNR.SYN0 0 REFDV 0x0039 Reference Divider Register REFDV.REFDV2 2 REFDV.REFDV1 1 REFDV.REFDV0 0 RESERVED003A 0x003A RESERVED PLLFLG 0x003B PLL Flags PLLFLG.LOCKIF 7 PLL Lock Interrupt Flag PLLFLG.LOCK 6 Locked Phase Lock Loop Circuit PLLFLG.LHIF 1 Limp-Home Interrupt Flag PLLFLG.LHOME 0 Limp-Home Mode Status PLLCR 0x003C PLL Control Register PLLCR.LOCKIE 7 PLL LOCK Interrupt Enable PLLCR.PLLON 6 Phase Lock Loop On PLLCR.AUTO 5 Automatic Bandwidth Control PLLCR.ACQ 4 Not in Acquisition PLLCR.PSTP 2 Pseudo-STOP Enable PLLCR.LHIE 1 Limp-Home Interrupt Enable PLLCR.NOLHM 0 No Limp-Home Mode CLKSEL 0x003D Clock Generator Clock select Register CLKSEL.BCSP 6 Bus Clock Select PLL CLKSEL.BCSS 5 Bus Clock Select Slow CLKSEL.MCS 2 Module Clock Select SLOW 0x003E Slow mode Divider Register SLOW.SLDV5 5 SLOW.SLDV4 4 SLOW.SLDV3 3 SLOW.SLDV2 2 SLOW.SLDV1 1 SLOW.SLDV0 0 RESERVED003F 0x003F RESERVED PWCLK 0x0040 PWM Clocks and Concatenate PWCLK.CON23 7 Concatenate PWM Channels 2 and 3 PWCLK.CON01 6 Concatenate PWM Channels 0 and 1 PWCLK.PCKA2 5 Prescaler for Clock A 2 PWCLK.PCKA1 4 Prescaler for Clock A 1 PWCLK.PCKA0 3 Prescaler for Clock A 0 PWCLK.PCKB2 2 Prescaler for Clock B 2 PWCLK.PCKB1 1 Prescaler for Clock B 1 PWCLK.PCKB0 0 Prescaler for Clock B 0 PWPOL 0x0041 PWM Clock Select and Polarity PWPOL.PCLK3 7 PWM Channel 3 Clock Select PWPOL.PCLK2 6 PWM Channel 2 Clock Select PWPOL.PCLK1 5 PWM Channel 1 Clock Select PWPOL.PCLK0 4 PWM Channel 0 Clock Select PWPOL.PPOL3 3 PWM Channel 3 Polarity PWPOL.PPOL2 2 PWM Channel 2 Polarity PWPOL.PPOL1 1 PWM Channel 1 Polarity PWPOL.PPOL0 0 PWM Channel 0 Polarity PWEN 0x0042 PWM Enable PWEN.PWEN3 3 PWM Channel 3 Enable PWEN.PWEN2 2 PWM Channel 2 Enable PWEN.PWEN1 1 PWM Channel 1 Enable PWEN.PWEN0 0 PWM Channel 0 Enable PWPRES 0x0043 PWM Prescale Counter PWSCAL0 0x0044 PWM Scale Register 0 PWSCNT0 0x0045 PWM Scale Counter 0 Value PWSCAL1 0x0046 PWM Scale Register 1 PWSCNT1 0x0047 PWM Scale Counter 1 Value PWCNT0 0x0048 PWM Channel Counter 0 PWCNT1 0x0049 PWM Channel Counter 1 PWCNT2 0x004A PWM Channel Counter 2 PWCNT3 0x004B PWM Channel Counter 3 PWPER0 0x004C PWM Channel Period Register 0 PWPER1 0x004D PWM Channel Period Register 1 PWPER2 0x004E PWM Channel Period Register 2 PWPER3 0x004F PWM Channel Period Register 3 PWDTY0 0x0050 PWM Channel Duty Register 0 PWDTY1 0x0051 PWM Channel Duty Register 1 PWDTY2 0x0052 PWM Channel Duty Register 2 PWDTY3 0x0053 PWM Channel Duty Register 3 PWCTL 0x0054 PWM Control Register PWCTL.PSWAI 4 PWM Halts while in Wait Mode PWCTL.CENTR 3 Center-Aligned Output Mode PWCTL.RDPP 2 Reduced Drive of Port P PWCTL.PUPP 1 Pull-Up Port P Enable PWCTL.PSBCK 0 PWM Stops while in Background Mode PWTST 0x0055 PWM Special Mode Register ("Test") PWTST.DISCR 7 Disable Reset of Channel Counter on Write to Channel Counter PWTST.DISCP 6 Disable Compare Count Period PWTST.DISCAL 5 Disable Load of Scale-Counters on Write to the Associated Scale-Registers PORTP 0x0056 Port P Data Register PORTP.PP7 7 Port P Data Bit 7 PORTP.PP6 6 Port P Data Bit 6 PORTP.PP5 5 Port P Data Bit 5 PORTP.PP4 4 Port P Data Bit 4 PORTP.PP3 3 Port P Data Bit 3 PORTP.PP2 2 Port P Data Bit 2 PORTP.PP1 1 Port P Data Bit 1 PORTP.PP0 0 Port P Data Bit 0 DDRP 0x0057 Port P Data Direction Register DDRP.DDP7 7 Port P Data Direction Bit 7 DDRP.DDP6 6 Port P Data Direction Bit 6 DDRP.DDP5 5 Port P Data Direction Bit 5 DDRP.DDP4 4 Port P Data Direction Bit 4 DDRP.DDP3 3 Port P Data Direction Bit 3 DDRP.DDP2 2 Port P Data Direction Bit 2 DDRP.DDP1 1 Port P Data Direction Bit 1 DDRP.DDP0 0 Port P Data Direction Bit 0 RESERVED0058 0x0058 RESERVED RESERVED0059 0x0059 RESERVED RESERVED005A 0x005A RESERVED RESERVED005B 0x005B RESERVED RESERVED005C 0x005C RESERVED RESERVED005D 0x005D RESERVED RESERVED005E 0x005E RESERVED RESERVED005F 0x005F RESERVED RESERVED0060 0x0060 RESERVED RESERVED0061 0x0061 RESERVED ATD0CTL2 0x0062 ATD0 Control Register 2 ATD0CTL2.ADPU 7 ATD Disable ATD0CTL2.AFFC 6 ATD Fast Flag Clear All ATD0CTL2.AWAI 5 ATD Wait Mode ATD0CTL2.DJM 4 Result Register Data Justification Mode ATD0CTL2.DSGN 3 Signed/Unsigned Result Data Mode ATD0CTL2.ASCIE 1 ATD Sequence Complete Interrupt Enable ATD0CTL2.ASCIF 0 ATD Sequence Complete Interrupt Flag ATD0CTL3 0x0063 ATD0 Control Register 3 ATD0CTL3.S1C 3 Conversion Sequence Length ATD0CTL3.FIFO 2 Result Register FIFO Mode ATD0CTL3.FRZ1 1 Background Debug Freeze Enable 1 ATD0CTL3.FRZ0 0 Background Debug Freeze Enable 0 ATD0CTL4 0x0064 ATD Control Register 4 ATD0CTL4.RES10 7 A/D Resolution Select ATD0CTL4.SMP1 6 Sample Time Select 1 ATD0CTL4.SMP0 5 Sample Time Select 0 ATD0CTL4.PRS4 4 ATD Clock Prescaler 4 ATD0CTL4.PRS3 3 ATD Clock Prescaler 3 ATD0CTL4.PRS2 2 ATD Clock Prescaler 2 ATD0CTL4.PRS1 1 ATD Clock Prescaler 1 ATD0CTL4.PRS0 0 ATD Clock Prescaler 0 ATD0CTL5 0x0065 ATD Control Register 5 ATD0CTL5.S8C 6 Conversion Sequence Length ATD0CTL5.SCAN 5 Continuous Conversion Sequence Mode ATD0CTL5.MULT 4 Multi-Channel Sample Mode ATD0CTL5.SC 3 Special Channel Conversion Mode ATD0CTL5.CC 2 Analog Input Channel Select Code C ATD0CTL5.CB 1 Analog Input Channel Select Code B ATD0CTL5.CA 0 Analog Input Channel Select Code A ATD0STAT0 0x0066 ATD Status Register 0 ATD0STAT0.SCF 7 Sequence Complete Flag ATD0STAT0.CC2 2 Conversion Counter 2 ATD0STAT0.CC1 1 Conversion Counter 1 ATD0STAT0.CC0 0 Conversion Counter 0 ATD0STAT1 0x0067 ATD Status Register 1 ATD0STAT1.CCF7 7 Conversion Complete Flag 7 ATD0STAT1.CCF6 6 Conversion Complete Flag 6 ATD0STAT1.CCF5 5 Conversion Complete Flag 5 ATD0STAT1.CCF4 4 Conversion Complete Flag 4 ATD0STAT1.CCF3 3 Conversion Complete Flag 3 ATD0STAT1.CCF2 2 Conversion Complete Flag 2 ATD0STAT1.CCF1 1 Conversion Complete Flag 1 ATD0STAT1.CCF0 0 Conversion Complete Flag 0 ATD0TESTH 0x0068 ATD Test Register High ATD0TESTH.SAR9 7 Successive Approximation Register 9 ATD0TESTH.SAR8 6 Successive Approximation Register 8 ATD0TESTH.SAR7 5 Successive Approximation Register 7 ATD0TESTH.SAR6 4 Successive Approximation Register 6 ATD0TESTH.SAR5 3 Successive Approximation Register 5 ATD0TESTH.SAR4 2 Successive Approximation Register 4 ATD0TESTH.SAR3 1 Successive Approximation Register 3 ATD0TESTH.SAR2 0 Successive Approximation Register 2 ATD0TESTL 0x0069 ATD Test Register Low ATD0TESTL.SAR1 7 Successive Approximation Register 1 ATD0TESTL.SAR0 6 Successive Approximation Register 0 ATD0TESTL.RST 5 Test Mode Reset Bit RESERVED006A 0x006A RESERVED RESERVED006B 0x006B RESERVED RESERVED006C 0x006C RESERVED RESERVED006D 0x006D RESERVED RESERVED006E 0x006E RESERVED PORTAD0 0x006F Port AD Data Input Register 0 PORTAD0.PAD07 7 Port AD Data Input Bit 7 PORTAD0.PAD06 6 Port AD Data Input Bit 6 PORTAD0.PAD05 5 Port AD Data Input Bit 5 PORTAD0.PAD04 4 Port AD Data Input Bit 4 PORTAD0.PAD03 3 Port AD Data Input Bit 3 PORTAD0.PAD02 2 Port AD Data Input Bit 2 PORTAD0.PAD01 1 Port AD Data Input Bit 1 PORTAD0.PAD00 0 Port AD Data Input Bit 0 ADR00H 0x0070 A/D Converter Result Register 00 High ADR00L 0x0071 A/D Converter Result Register 00 Low ADR01H 0x0072 A/D Converter Result Register 01 High ADR01L 0x0073 A/D Converter Result Register 01 Low ADR02H 0x0074 A/D Converter Result Register 02 High ADR02L 0x0075 A/D Converter Result Register 02 Low ADR03H 0x0076 A/D Converter Result Register 03 High ADR03L 0x0077 A/D Converter Result Register 03 Low ADR04H 0x0078 A/D Converter Result Register 04 High ADR04L 0x0079 A/D Converter Result Register 04 Low ADR05H 0x007A A/D Converter Result Register 05 High ADR05L 0x007B A/D Converter Result Register 05 Low ADR06H 0x007C A/D Converter Result Register 06 High ADR06L 0x007D A/D Converter Result Register 06 Low ADR07H 0x007E A/D Converter Result Register 07 High ADR07L 0x007F A/D Converter Result Register 07 Low TIOS 0x0080 Timer Input Capture/Output Compare Select TIOS.IOS7 7 Input Capture or Output Compare Channel Configuration 7 TIOS.IOS6 6 Input Capture or Output Compare Channel Configuration 6 TIOS.IOS5 5 Input Capture or Output Compare Channel Configuration 5 TIOS.IOS4 4 Input Capture or Output Compare Channel Configuration 4 TIOS.IOS3 3 Input Capture or Output Compare Channel Configuration 3 TIOS.IOS2 2 Input Capture or Output Compare Channel Configuration 2 TIOS.IOS1 1 Input Capture or Output Compare Channel Configuration 1 TIOS.IOS0 0 Input Capture or Output Compare Channel Configuration 0 CFORC 0x0081 Timer Compare Force Register CFORC.FOC7 7 Force Output Compare Action for Channel 7 CFORC.FOC6 6 Force Output Compare Action for Channel 6 CFORC.FOC5 5 Force Output Compare Action for Channel 5 CFORC.FOC4 4 Force Output Compare Action for Channel 4 CFORC.FOC3 3 Force Output Compare Action for Channel 3 CFORC.FOC2 2 Force Output Compare Action for Channel 2 CFORC.FOC1 1 Force Output Compare Action for Channel 1 CFORC.FOC0 0 Force Output Compare Action for Channel 0 OC7M 0x0082 Output Compare 7 Mask Register OC7M.OC7M7 7 OC7M.OC7M6 6 OC7M.OC7M5 5 OC7M.OC7M4 4 OC7M.OC7M3 3 OC7M.OC7M2 2 OC7M.OC7M1 1 OC7M.OC7M0 0 OC7D 0x0083 Output Compare 7 Data Register OC7D.OC7D7 7 OC7D.OC7D6 6 OC7D.OC7D5 5 OC7D.OC7D4 4 OC7D.OC7D3 3 OC7D.OC7D2 2 OC7D.OC7D1 1 OC7D.OC7D0 0 TCNTH 0x0084 Timer Count Register High TCNTL 0x0085 Timer Count Register Low TSCR 0x0086 Timer System Control Register TSCR.TEN 7 Timer Enable TSCR.TSWAI 6 Timer Module Stops While in Wait TSCR.TSBCK 5 Timer and Modulus Counter Stop While in Background Mode TSCR.TFFCA 4 Timer Fast Flag Clear All RESERVED 0x0087 RESERVED TCTL1 0x0088 Timer Control Register 1 TCTL1.OM7 7 Output Mode 7 TCTL1.OL7 6 Output Level 7 TCTL1.OM6 5 Output Mode 6 TCTL1.OL6 4 Output Level 6 TCTL1.OM5 3 Output Mode 5 TCTL1.OL5 2 Output Level 5 TCTL1.OM4 1 Output Mode 4 TCTL1.OL4 0 Output Level 4 TCTL2 0x0089 Timer Control Register 2 TCTL2.OM3 7 Output Mode 3 TCTL2.OL3 6 Output Level 3 TCTL2.OM2 5 Output Mode 2 TCTL2.OL2 4 Output Level 2 TCTL2.OM1 3 Output Mode 1 TCTL2.OL1 2 Output Level 1 TCTL2.OM0 1 Output Mode 0 TCTL2.OL0 0 Output Level 0 TCTL3 0x008A Timer Control Register 3 TCTL3.EDG7B 7 Input Capture Edge Control 7B TCTL3.EDG7A 6 Input Capture Edge Control 7A TCTL3.EDG6B 5 Input Capture Edge Control 6B TCTL3.EDG6A 4 Input Capture Edge Control 6A TCTL3.EDG5B 3 Input Capture Edge Control 5B TCTL3.EDG5A 2 Input Capture Edge Control 5A TCTL3.EDG4B 1 Input Capture Edge Control 4B TCTL3.EDG4A 0 Input Capture Edge Control 4A TCTL4 0x008B Timer Control Register 4 TCTL4.EDG3B 7 Input Capture Edge Control 3B TCTL4.EDG3A 6 Input Capture Edge Control 3A TCTL4.EDG2B 5 Input Capture Edge Control 2B TCTL4.EDG2A 4 Input Capture Edge Control 2A TCTL4.EDG1B 3 Input Capture Edge Control 1B TCTL4.EDG1A 2 Input Capture Edge Control 1A TCTL4.EDG0B 1 Input Capture Edge Control 0B TCTL4.EDG0A 0 Input Capture Edge Control 0A TMSK1 0x008C Timer Interrupt Mask 1 TMSK1.C7I 7 Input Capture/Output Compare 7 Interrupt Enable TMSK1.C6I 6 Input Capture/Output Compare 6 Interrupt Enable TMSK1.C5I 5 Input Capture/Output Compare 5 Interrupt Enable TMSK1.C4I 4 Input Capture/Output Compare 4 Interrupt Enable TMSK1.C3I 3 Input Capture/Output Compare 3 Interrupt Enable TMSK1.C2I 2 Input Capture/Output Compare 2 Interrupt Enable TMSK1.C1I 1 Input Capture/Output Compare 1 Interrupt Enable TMSK1.C0I 0 Input Capture/Output Compare 0 Interrupt Enable TMSK2 0x008D Timer Interrupt Mask 2 TMSK2.TOI 7 Timer Overflow Interrupt Enable TMSK2.PUPT 5 Timer Port Pull-Up Resistor Enable TMSK2.RDPT 4 Timer Port Drive Reduction TMSK2.TCRE 3 Timer Counter Reset Enable TMSK2.PR2 2 Timer Prescaler Select 2 TMSK2.PR1 1 Timer Prescaler Select 1 TMSK2.PR0 0 Timer Prescaler Select 0 TFLG1 0x008E Main Timer Interrupt Flag 1 TFLG1.C7F 7 Input Capture/Output Compare Channel 7 Flag TFLG1.C6F 6 Input Capture/Output Compare Channel 6 Flag TFLG1.C5F 5 Input Capture/Output Compare Channel 5 Flag TFLG1.C4F 4 Input Capture/Output Compare Channel 4 Flag TFLG1.C3F 3 Input Capture/Output Compare Channel 3 Flag TFLG1.C2F 2 Input Capture/Output Compare Channel 2 Flag TFLG1.C1F 1 Input Capture/Output Compare Channel 1 Flag TFLG1.C0F 0 Input Capture/Output Compare Channel 0 Flag TFLG2 0x008F Main Timer Interrupt Flag 2 TFLG2.TOF 7 Timer Overflow Flag TC0H 0x0090 Timer Input Capture/Output Compare Register 0 High TC0L 0x0091 Timer Input Capture/Output Compare Register 0 Low TC1H 0x0092 Timer Input Capture/Output Compare Register 1 High TC1L 0x0093 Timer Input Capture/Output Compare Register 1 Low TC2H 0x0094 Timer Input Capture/Output Compare Register 2 High TC2L 0x0095 Timer Input Capture/Output Compare Register 2 Low TC3H 0x0096 Timer Input Capture/Output Compare Register 3 High TC3L 0x0097 Timer Input Capture/Output Compare Register 3 Low TC4H 0x0098 Timer Input Capture/Output Compare Register 4 High TC4L 0x0099 Timer Input Capture/Output Compare Register 4 Low TC5H 0x009A Timer Input Capture/Output Compare Register 5 High TC5L 0x009B Timer Input Capture/Output Compare Register 5 Low TC6H 0x009C Timer Input Capture/Output Compare Register 6 High TC6L 0x009D Timer Input Capture/Output Compare Register 6 Low TC7H 0x009E Timer Input Capture/Output Compare Register 7 High TC7L 0x009F Timer Input Capture/Output Compare Register 7 Low PACTL 0x00A0 16-Bit Pulse Accumulator A Control Register PACTL.PAEN 6 Pulse Accumulator A System Enable PACTL.PAMOD 5 Pulse Accumulator Mode PACTL.PEDGE 4 Pulse Accumulator Edge Control PACTL.CLK1 3 Clock Select Bit 1 PACTL.CLK0 2 Clock Select Bit 0 PACTL.PAOVI 1 Pulse Accumulator A Overflow Interrupt enable PACTL.PAI 0 Pulse Accumulator Input Interrupt enable PAFLG 0x00A1 Pulse Accumulator A Flag Register PAFLG.PAOVF 1 Pulse Accumulator A Overflow Flag PAFLG.PAIF 0 Pulse Accumulator Input edge Flag PACN3 0x00A2 Pulse Accumulators Count Register 3 PACN2 0x00A3 Pulse Accumulators Count Register 2 PACN1 0x00A4 Pulse Accumulators Count Register 1 PACN0 0x00A5 Pulse Accumulators Count Register 0 MCCTL 0x00A6 16-Bit Modulus Down-Counter Control Register MCCTL.MCZI 7 Modulus Counter Underflow Interrupt Enable MCCTL.MODMC 6 Modulus Mode Enable MCCTL.RDMCL 5 Read Modulus Down-Counter Load MCCTL.ICLAT 4 Input Capture Force Latch Action MCCTL.FLMC 3 Force Load Register into the Modulus Counter Count Register MCCTL.MCEN 2 Modulus Down-Counter Enable MCCTL.MCPR1 1 Modulus Counter Prescaler select 1 MCCTL.MCPR0 0 Modulus Counter Prescaler select 0 MCFLG 0x00A7 16-Bit Modulus Down-Counter FLAG Register MCFLG.MCZF 7 Modulus Counter Underflow Interrupt Flag MCFLG.POLF3 3 First Input Capture Polarity Status 3 MCFLG.POLF2 2 First Input Capture Polarity Status 2 MCFLG.POLF1 1 First Input Capture Polarity Status 1 MCFLG.POLF0 0 First Input Capture Polarity Status 0 ICPACR 0x00A8 Input Control Pulse Accumulators Control Register ICPACR.PA3EN 3 8-Bit Pulse Accumulator 3 Enable ICPACR.PA2EN 2 8-Bit Pulse Accumulator 2 Enable ICPACR.PA1EN 1 8-Bit Pulse Accumulator 1 Enable ICPACR.PA0EN 0 8-Bit Pulse Accumulator 0 Enable DLYCT 0x00A9 Delay Counter Control Register DLYCT.DLY1 1 Delay Counter Select 1 DLYCT.DLY0 0 Delay Counter Select 0 ICOVW 0x00AA Input Control Overwrite Register ICOVW.NOVW7 7 No Input Capture Overwrite 7 ICOVW.NOVW6 6 No Input Capture Overwrite 6 ICOVW.NOVW5 5 No Input Capture Overwrite 5 ICOVW.NOVW4 4 No Input Capture Overwrite 4 ICOVW.NOVW3 3 No Input Capture Overwrite 3 ICOVW.NOVW2 2 No Input Capture Overwrite 2 ICOVW.NOVW1 1 No Input Capture Overwrite 1 ICOVW.NOVW0 0 No Input Capture Overwrite 0 ICSYS 0x00AB Input Control System Control Register ICSYS.SH37 7 Share Input action of Input Capture Channels 3 and 7 ICSYS.SH26 6 Share Input action of Input Capture Channels 2 and 6 ICSYS.SH15 5 Share Input action of Input Capture Channels 1 and 5 ICSYS.SH04 4 Share Input action of Input Capture Channels 0 and 4 ICSYS.TFMOD 3 Timer Flag-setting Mode ICSYS.PACMX 2 8-Bit Pulse Accumulators Maximum Count ICSYS.BUFEN 1 IC Buffer Enable ICSYS.LATQ 0 Input Control Latch or Queue Mode Enable RESERVED00AC 0x00AC RESERVED TIMTST 0x00AD Timer Test Register TIMTST.TCBYP 1 Main Timer Divider Chain Bypass PORTT 0x00AE Port T Data Register PORTT.PT7 7 Port T Data Bit 7 PORTT.PT6 6 Port T Data Bit 6 PORTT.PT5 5 Port T Data Bit 5 PORTT.PT4 4 Port T Data Bit 4 PORTT.PT3 3 Port T Data Bit 3 PORTT.PT2 2 Port T Data Bit 2 PORTT.PT1 1 Port T Data Bit 1 PORTT.PT0 0 Port T Data Bit 0 DDRT 0x00AF Port T Data Direction Register DDRT.DDT7 7 Port T Data Direction Bit 7 DDRT.DDT6 6 Port T Data Direction Bit 6 DDRT.DDT5 5 Port T Data Direction Bit 5 DDRT.DDT4 4 Port T Data Direction Bit 4 DDRT.DDT3 3 Port T Data Direction Bit 3 DDRT.DDT2 2 Port T Data Direction Bit 2 DDRT.DDT1 1 Port T Data Direction Bit 1 DDRT.DDT0 0 Port T Data Direction Bit 0 PBCTL 0x00B0 16-Bit Pulse Accumulator B Control Register PBCTL.PBEN 6 Pulse Accumulator B System Enable PBCTL.PBOVI 1 Pulse Accumulator B Overflow Interrupt enable PBFLG 0x00B1 Pulse Accumulator B Flag Register PBFLG.PBOVF 1 Pulse Accumulator B Overflow Flag PA3H 0x00B2 8-Bit Pulse Accumulators Holding Register 3 PA2H 0x00B3 8-Bit Pulse Accumulators Holding Register 2 PA1H 0x00B4 8-Bit Pulse Accumulators Holding Register 1 PA0H 0x00B5 8-Bit Pulse Accumulators Holding Register 0 MCCNTH 0x00B6 Modulus Down-Counter Count Register High MCCNTL 0x00B7 Modulus Down-Counter Count Register Low TC0HH 0x00B8 Timer Input Capture Holding Register 0 High TC0HL 0x00B9 Timer Input Capture Holding Register 0 Low TC1HH 0x00BA Timer Input Capture Holding Register 1 High TC1HL 0x00BB Timer Input Capture Holding Register 1 Low TC2HH 0x00BC Timer Input Capture Holding Register 2 High TC2HL 0x00BD Timer Input Capture Holding Register 2 Low TC3HH 0x00BE Timer Input Capture Holding Register 3 High TC3HL 0x00BF Timer Input Capture Holding Register 3 Low SC0BDH 0x00C0 SCI0 Baud Rate Control Register High SC0BDH.BTST 7 Reserved for test function SC0BDH.BSPL 6 Reserved for test function SC0BDH.BRLD 5 Reserved for test function SC0BDH.SBR12 4 SC0BDH.SBR11 3 SC0BDH.SBR10 2 SC0BDH.SBR9 1 SC0BDH.SBR8 0 SC0BDL 0x00C1 SCI0 Baud Rate Control Register Low SC0BDL.SBR7 7 SC0BDL.SBR6 6 SC0BDL.SBR5 5 SC0BDL.SBR4 4 SC0BDL.SBR3 3 SC0BDL.SBR2 2 SC0BDL.SBR1 1 SC0BDL.SBR0 0 SC0CR1 0x00C2 SCI0 Control Register 1 SC0CR1.LOOPS 7 SCI LOOP Mode/Single Wire Mode Enable SC0CR1.WOMS 6 Wired-Or Mode for Serial Pins SC0CR1.RSRC 5 Receiver Source SC0CR1.M 4 Mode (select character format) SC0CR1.WAKE 3 Wake-up by Address Mark/Idle SC0CR1.ILT 2 Idle Line Type SC0CR1.PE 1 Parity Enable SC0CR1.PT 0 Parity Type SC0CR2 0x00C3 SCI0 Control Register 2 SC0CR2.TIE 7 Transmit Interrupt Enable SC0CR2.TCIE 6 Transmit Complete Interrupt Enable SC0CR2.RIE 5 Receiver Interrupt Enable SC0CR2.ILIE 4 Idle Line Interrupt Enable SC0CR2.TE 3 Transmitter Enable SC0CR2.RE 2 Receiver Enable SC0CR2.RWU 1 Receiver Wake-Up Control SC0CR2.SBK 0 Send Break SC0SR1 0x00C4 SCI0 Status Register 1 SC0SR1.TDRE 7 Transmit Data Register Empty Flag SC0SR1.TC 6 Transmit Complete Flag SC0SR1.RDRF 5 Receive Data Register Full Flag SC0SR1.IDLE 4 Idle Line Detected Flag SC0SR1.OR 3 Overrun Error Flag SC0SR1.NF 2 Noise Error Flag SC0SR1.FE 1 Framing Error Flag SC0SR1.PF 0 Parity Error Flag SC0SR2 0x00C5 SCI0 Status Register 2 SC0SR2.SCSWAI 7 Serial Communications Interface Stop in WAIT Mode SC0SR2.MIE 6 SC0SR2.MDL1 5 SC0SR2.MDL0 4 SC0SR2.RAF 0 Receiver Active Flag SC0DRH 0x00C6 SCI0 Data Register High SC0DRH.R8 7 Receive Bit 8 SC0DRH.T8 6 Transmit Bit 8 SC0DRL 0x00C7 SCI0 Data Register Low SC0DRL.R7_T7 7 Receive/Transmit Data Bit 7 SC0DRL.R6_T6 6 Receive/Transmit Data Bit 6 SC0DRL.R5_T5 5 Receive/Transmit Data Bit 5 SC0DRL.R4_T4 4 Receive/Transmit Data Bit 4 SC0DRL.R3_T3 3 Receive/Transmit Data Bit 3 SC0DRL.R2_T2 2 Receive/Transmit Data Bit 2 SC0DRL.R1_T1 1 Receive/Transmit Data Bit 1 SC0DRL.R0_T0 0 Receive/Transmit Data Bit 0 SC1BDH 0x00C8 SCI1 Baud Rate Control Register High SC1BDH.BTST 7 Reserved for test function SC1BDH.BSPL 6 Reserved for test function SC1BDH.BRLD 5 Reserved for test function SC1BDH.SBR12 4 SC1BDH.SBR11 3 SC1BDH.SBR10 2 SC1BDH.SBR9 1 SC1BDH.SBR8 0 SC1BDL 0x00C9 SCI1Baud Rate Control Register Low SC1BDL.SBR7 7 SC1BDL.SBR6 6 SC1BDL.SBR5 5 SC1BDL.SBR4 4 SC1BDL.SBR3 3 SC1BDL.SBR2 2 SC1BDL.SBR1 1 SC1BDL.SBR0 0 SC1CR1 0x00CA SCI1 Control Register 1 SC1CR1.LOOPS 7 SCI LOOP Mode/Single Wire Mode Enable SC1CR1.WOMS 6 Wired-Or Mode for Serial Pins SC1CR1.RSRC 5 Receiver Source SC1CR1.M 4 Mode (select character format) SC1CR1.WAKE 3 Wake-up by Address Mark/Idle SC1CR1.ILT 2 Idle Line Type SC1CR1.PE 1 Parity Enable SC1CR1.PT 0 Parity Type SC1CR2 0x00CB SCI1 Control Register 2 SC1CR2.TIE 7 Transmit Interrupt Enable SC1CR2.TCIE 6 Transmit Complete Interrupt Enable SC1CR2.RIE 5 Receiver Interrupt Enable SC1CR2.ILIE 4 Idle Line Interrupt Enable SC1CR2.TE 3 Transmitter Enable SC1CR2.RE 2 Receiver Enable SC1CR2.RWU 1 Receiver Wake-Up Control SC1CR2.SBK 0 Send Break SC1SR1 0x00CC SCI1 Status Register 1 SC1SR1.TDRE 7 Transmit Data Register Empty Flag SC1SR1.TC 6 Transmit Complete Flag SC1SR1.RDRF 5 Receive Data Register Full Flag SC1SR1.IDLE 4 Idle Line Detected Flag SC1SR1.OR 3 Overrun Error Flag SC1SR1.NF 2 Noise Error Flag SC1SR1.FE 1 Framing Error Flag SC1SR1.PF 0 Parity Error Flag SC1SR2 0x00CD SCI1 Status Register 2 SC1SR2.SCSWAI 7 Serial Communications Interface Stop in WAIT Mode SC1SR2.RAF 0 Receiver Active Flag SC1DRH 0x00CE SCI1 Data Register High SC1DRH.R8 7 Receive Bit 8 SC1DRH.T8 6 Transmit Bit 8 SC1DRL 0x00CF SCI1 Data Register Low SC1DRL.R7_T7 7 Receive/Transmit Data Bit 7 SC1DRL.R6_T6 6 Receive/Transmit Data Bit 6 SC1DRL.R5_T5 5 Receive/Transmit Data Bit 5 SC1DRL.R4_T4 4 Receive/Transmit Data Bit 4 SC1DRL.R3_T3 3 Receive/Transmit Data Bit 3 SC1DRL.R2_T2 2 Receive/Transmit Data Bit 2 SC1DRL.R1_T1 1 Receive/Transmit Data Bit 1 SC1DRL.R0_T0 0 Receive/Transmit Data Bit 0 SP0CR1 0x00D0 SPI Control Register 1 SP0CR1.SPIE 7 SPI Interrupt Enable SP0CR1.SPE 6 SPI System Enable SP0CR1.SWOM 5 Port S Wired-OR Mode SP0CR1.MSTR 4 SPI Master/Slave Mode Select SP0CR1.CPOL 3 SPI Clock Polarity SP0CR1.CPHA 2 Clock Phase SP0CR1.SSOE 1 Slave Select Output Enable SP0CR1.LSBF 0 SPI LSB First enable SP0CR2 0x00D1 SPI Control Register 2 SP0CR2.SPSWAI 1 Serial Interface Stop in WAIT mode SP0CR2.SPC0 0 Serial Pin Control 0 SP0BR 0x00D2 SPI Baud Rate Register SP0BR.SPR2 2 SPI Clock (SCK) Rate Select Bit 2 SP0BR.SPR1 1 SPI Clock (SCK) Rate Select Bit 1 SP0BR.SPR0 0 SPI Clock (SCK) Rate Select Bit 0 SP0SR 0x00D3 SPI Status Register SP0SR.SPIF 7 SPI Interrupt Request SP0SR.WCOL 6 Write Collision Status Flag SP0SR.MODF 4 SPI Mode Error Interrupt Status Flag RESERVED00D4 0x00D4 RESERVED SP0DR 0x00D5 SPI Data Register PORTS 0x00D6 Port S Data Register PORTS.PS7 7 Port S Data Bit 7 PORTS.PS6 6 Port S Data Bit 6 PORTS.PS5 5 Port S Data Bit 5 PORTS.PS4 4 Port S Data Bit 4 PORTS.PS3 3 Port S Data Bit 3 PORTS.PS2 2 Port S Data Bit 2 PORTS.PS1 1 Port S Data Bit 1 PORTS.PS0 0 Port S Data Bit 0 DDRS 0x00D7 Port S Data Direction Register DDRS.DDS7 7 Port S Data Direction Bit 7 DDRS.DDS6 6 Port S Data Direction Bit 6 DDRS.DDS5 5 Port S Data Direction Bit 5 DDRS.DDS4 4 Port S Data Direction Bit 4 DDRS.DDS3 3 Port S Data Direction Bit 3 DDRS.DDS2 2 Port S Data Direction Bit 2 DDRS.DDS1 1 Port S Data Direction Bit 1 DDRS.DDS0 0 Port S Data Direction Bit 0 RESERVED00D8 0x00D8 RESERVED PURDS 0x00D9 Pull-Up Register for Port S PURDS.RDPS2 6 Reduce Drive of Port S[7:4] PURDS.RDPS1 5 Reduce Drive of Port S[3:2] PURDS.RDPS0 4 Reduce Drive of Port S[1:0] PURDS.PUPS2 2 Pull-up Port S[7:4] Enable PURDS.PUPS1 1 Pull-up Port S[3:2] Enable PURDS.PUPS0 0 Pull-up Port S[1:0] Enable RESERVED00DA 0x00DA RESERVED RESERVED00DB 0x00DB RESERVED RESERVED00DC 0x00DC RESERVED RESERVED00DD 0x00DD RESERVED RESERVED00DE 0x00DE RESERVED RESERVED00DF 0x00DF RESERVED RESERVED00E0 0x00E0 RESERVED RESERVED00E1 0x00E1 RESERVED RESERVED00E2 0x00E2 RESERVED RESERVED00E3 0x00E3 RESERVED RESERVED00E4 0x00E4 RESERVED RESERVED00E5 0x00E5 RESERVED RESERVED00E6 0x00E6 RESERVED RESERVED00E7 0x00E7 RESERVED RESERVED00E8 0x00E8 RESERVED RESERVED00E9 0x00E9 RESERVED RESERVED00EA 0x00EA RESERVED RESERVED00EB 0x00EB RESERVED RESERVED00EC 0x00EC RESERVED RESERVED00ED 0x00ED RESERVED EEDIVH 0x00EE EEPROM Modulus Divider High EEDIVH.EEDIV9 1 Prescaler divider 9 EEDIVH.EEDIV8 0 Prescaler divider 8 EEDIVL 0x00EF EEPROM Modulus Divider Low EEDIVL.EEDIV7 7 Prescaler divider 7 EEDIVL.EEDIV6 6 Prescaler divider 6 EEDIVL.EEDIV5 5 Prescaler divider 5 EEDIVL.EEDIV4 4 Prescaler divider 4 EEDIVL.EEDIV3 3 Prescaler divider 3 EEDIVL.EEDIV2 2 Prescaler divider 2 EEDIVL.EEDIV1 1 Prescaler divider 1 EEDIVL.EEDIV0 0 Prescaler divider 0 EEMCR 0x00F0 EEPROM Module Configuration EEMCR.NOBDML 7 Background Debug Mode Lockout Disable EEMCR.NOSHW 6 SHADOW Word Disable EEMCR.EESWAI 2 EEPROM Stops in Wait Mode EEMCR.PROTLCK 1 Block Protect Write Lock EEMCR.DMY 0 Dummy bit EEPROT 0x00F1 EEPROM Block Protect EEPROT.SHPROT 7 SHADOW Word Protection EEPROT.BPROT4 4 EEPROM Block Protection 4 EEPROT.BPROT3 3 EEPROM Block Protection 3 EEPROT.BPROT2 2 EEPROM Block Protection 2 EEPROT.BPROT1 1 EEPROM Block Protection 1 EEPROT.BPROT0 0 EEPROM Block Protection 0 RESERVED00D2 0x00F2 RESERVED EEPROG 0x00F3 EEPROM Control EEPROG.BULKP 7 Bulk Erase Protection EEPROG.AUTO 5 Automatic shutdown of program/erase operation EEPROG.BYTE 4 Byte and Aligned Word Erase EEPROG.ROW 3 Row or Bulk Erase (when BYTE = 0) EEPROG.ERASE 2 Erase Control EEPROG.EELAT 1 EEPROM Latch Control EEPROG.EEPGM 0 Program and Erase Enable FEE32LCK 0x00F4 Flash EEPROM Lock Control Register FEE32LCK.LOCK 0 Lock Register Bit FEE32MCR 0x00F5 Flash EEPROM Module Configuration Register FEE32MCR.BOOTP 0 Boot Protect RESERVED00D6 0x00F6 RESERVED FEE32CTL 0x00F7 Flash EEPROM Control Register FEE32CTL.FEESWAI 4 Flash EEPROM Stop in Wait Control FEE32CTL.HVEN 3 High-Voltage Enable FEE32CTL.ERAS 1 Erase Control FEE32CTL.PGM 0 Program Control FEE28LCK 0x00F8 Flash EEPROM Lock Control Register FEE28LCK.LOCK 0 Lock Register Bit FEE28MCR 0x00F9 Flash EEPROM Module Configuration Register FEE28MCR.BOOTP 0 Boot Protect RESERVED00DA 0x00FA RESERVED FEE28CTL 0x00FB Flash EEPROM Control Register FEE28CTL.FEESWAI 4 Flash EEPROM Stop in Wait Control FEE28CTL.HVEN 3 High-Voltage Enable FEE28CTL.ERAS 1 Erase Control FEE28CTL.PGM 0 Program Control RESERVED00DC 0x00FC RESERVED RESERVED00DD 0x00FD RESERVED RESERVED00DE 0x00FE RESERVED RESERVED00DF 0x00FF RESERVED CMCR0 0x0100 msCAN12 Module Control Register 0 CMCR0.CSWAI 5 CAN Stops in Wait Mode CMCR0.SYNCH 4 Synchronized Status CMCR0.TLNKEN 3 Timer Enable CMCR0.SLPAK 2 SLEEP Mode Acknowledge CMCR0.SLPRQ 1 SLEEP request CMCR0.SFTRES 0 SOFT_RESET CMCR1 0x0101 msCAN12 Module Control Register 1 CMCR1.LOOPB 2 Loop Back Self Test Mode CMCR1.WUPM 1 Wake-Up Mode CMCR1.CLKSRC 0 msCAN12 Clock Source CBTR0 0x0102 msCAN12 Bus Timing Register 0 CBTR0.SJW1 7 Synchronization Jump Width 1 CBTR0.SJW0 6 Synchronization Jump Width 0 CBTR0.BRP5 5 Baud Rate Prescaler 5 CBTR0.BRP4 4 Baud Rate Prescaler 4 CBTR0.BRP3 3 Baud Rate Prescaler 3 CBTR0.BRP2 2 Baud Rate Prescaler 2 CBTR0.BRP1 1 Baud Rate Prescaler 1 CBTR0.BRP0 0 Baud Rate Prescaler 0 CBTR1 0x0103 msCAN12 Bus Timing Register 1 CBTR1.SAMP 7 Sampling CBTR1.TSEG22 6 Time Segment 22 CBTR1.TSEG21 5 Time Segment 21 CBTR1.TSEG20 4 Time Segment 20 CBTR1.TSEG13 3 Time Segment 13 CBTR1.TSEG12 2 Time Segment 12 CBTR1.TSEG11 1 Time Segment 11 CBTR1.TSEG10 0 Time Segment 10 CRFLG 0x0104 msCAN12 Receiver Flag Register CRFLG.WUPIF 7 Wake-up Interrupt Flag CRFLG.RWRNIF 6 Receiver Warning Interrupt Flag CRFLG.TWRNIF 5 Transmitter Warning Interrupt Flag CRFLG.RERRIF 4 Receiver Error Passive Interrupt Flag CRFLG.TERRIF 3 Transmitter Error Passive Interrupt Flag CRFLG.BOFFIF 2 BUSOFF Interrupt Flag CRFLG.OVRIF 1 Overrun Interrupt Flag CRFLG.RXF 0 Receive Buffer Full CRIER 0x0105 msCAN12 Receiver Interrupt Enable Register CRIER.WUPIE 7 Wake-up Interrupt Enable CRIER.RWRNIE 6 Receiver Warning Interrupt Enable CRIER.TWRNIE 5 Transmitter Warning Interrupt Enable CRIER.RERRIE 4 Receiver Error Passive Interrupt Enable CRIER.TERRIE 3 Transmitter Error Passive Interrupt Enable CRIER.BOFFIE 2 BUSOFF Interrupt Enable CRIER.OVRIE 1 Overrun Interrupt Enable CRIER.RXFIE 0 Receiver Full Interrupt Enable CTFLG 0x0106 msCAN12 Transmitter Flag Register CTFLG.ABTAK2 6 Abort Acknowledge 2 CTFLG.ABTAK1 5 Abort Acknowledge 1 CTFLG.ABTAK0 4 Abort Acknowledge 0 CTFLG.TXE2 2 Transmitter Buffer Empty 2 CTFLG.TXE1 1 Transmitter Buffer Empty 1 CTFLG.TXE0 0 Transmitter Buffer Empty 0 CTCR 0x0107 msCAN12 Transmitter Control Register CTCR.ABTRQ2 6 Abort Request 2 CTCR.ABTRQ1 5 Abort Request 1 CTCR.ABTRQ0 4 Abort Request 0 CTCR.TXEIE2 2 Transmitter Empty Interrupt Enable 2 CTCR.TXEIE1 1 Transmitter Empty Interrupt Enable 1 CTCR.TXEIE0 0 Transmitter Empty Interrupt Enable 0 CIDAC 0x0108 msCAN12 Identifier Acceptance Control Register CIDAC.IDAM1 5 Identifier Acceptance Mode 1 CIDAC.IDAM0 4 Identifier Acceptance Mode 0 CIDAC.IDHIT2 2 Identifier Acceptance Hit Indicator 2 CIDAC.IDHIT1 1 Identifier Acceptance Hit Indicator 1 CIDAC.IDHIT0 0 Identifier Acceptance Hit Indicator 0 RESERVED0109 0x0109 RESERVED RESERVED010A 0x010A RESERVED RESERVED010B 0x010B RESERVED RESERVED010C 0x010C RESERVED RESERVED010D 0x010D RESERVED CRXERR 0x010E msCAN12 Receive Error Counter CRXERR.RXERR7 7 CRXERR.RXERR6 6 CRXERR.RXERR5 5 CRXERR.RXERR4 4 CRXERR.RXERR3 3 CRXERR.RXERR2 2 CRXERR.RXERR1 1 CRXERR.RXERR0 0 CTXERR 0x010F msCAN12 Transmit Error Counter CTXERR.TXERR7 7 CTXERR.TXERR6 6 CTXERR.TXERR5 5 CTXERR.TXERR4 4 CTXERR.TXERR3 3 CTXERR.TXERR2 2 CTXERR.TXERR1 1 CTXERR.TXERR0 0 CIDAR0 0x0110 msCAN12 Identifier Acceptance Register 0 CIDAR0.AC7 7 Acceptance Code Bit 7 CIDAR0.AC6 6 Acceptance Code Bit 6 CIDAR0.AC5 5 Acceptance Code Bit 5 CIDAR0.AC4 4 Acceptance Code Bit 4 CIDAR0.AC3 3 Acceptance Code Bit 3 CIDAR0.AC2 2 Acceptance Code Bit 2 CIDAR0.AC1 1 Acceptance Code Bit 1 CIDAR0.AC0 0 Acceptance Code Bit 0 CIDAR1 0x0111 msCAN12 Identifier Acceptance Register 1 CIDAR1.AC7 7 Acceptance Code Bit 7 CIDAR1.AC6 6 Acceptance Code Bit 6 CIDAR1.AC5 5 Acceptance Code Bit 5 CIDAR1.AC4 4 Acceptance Code Bit 4 CIDAR1.AC3 3 Acceptance Code Bit 3 CIDAR1.AC2 2 Acceptance Code Bit 2 CIDAR1.AC1 1 Acceptance Code Bit 1 CIDAR1.AC0 0 Acceptance Code Bit 0 CIDAR2 0x0112 msCAN12 Identifier Acceptance Register 2 CIDAR2.AC7 7 Acceptance Code Bit 7 CIDAR2.AC6 6 Acceptance Code Bit 6 CIDAR2.AC5 5 Acceptance Code Bit 5 CIDAR2.AC4 4 Acceptance Code Bit 4 CIDAR2.AC3 3 Acceptance Code Bit 3 CIDAR2.AC2 2 Acceptance Code Bit 2 CIDAR2.AC1 1 Acceptance Code Bit 1 CIDAR2.AC0 0 Acceptance Code Bit 0 CIDAR3 0x0113 msCAN12 Identifier Acceptance Register 3 CIDAR3.AC7 7 Acceptance Code Bit 7 CIDAR3.AC6 6 Acceptance Code Bit 6 CIDAR3.AC5 5 Acceptance Code Bit 5 CIDAR3.AC4 4 Acceptance Code Bit 4 CIDAR3.AC3 3 Acceptance Code Bit 3 CIDAR3.AC2 2 Acceptance Code Bit 2 CIDAR3.AC1 1 Acceptance Code Bit 1 CIDAR3.AC0 0 Acceptance Code Bit 0 CIDMR0 0x0114 msCAN12 Identifier Mask Register 0 CIDMR0.AM7 7 Acceptance Mask Bit 7 CIDMR0.AM6 6 Acceptance Mask Bit 6 CIDMR0.AM5 5 Acceptance Mask Bit 5 CIDMR0.AM4 4 Acceptance Mask Bit 4 CIDMR0.AM3 3 Acceptance Mask Bit 3 CIDMR0.AM2 2 Acceptance Mask Bit 2 CIDMR0.AM1 1 Acceptance Mask Bit 1 CIDMR0.AM0 0 Acceptance Mask Bit 0 CIDMR1 0x0115 msCAN12 Identifier Mask Register 1 CIDMR1.AM7 7 Acceptance Mask Bit 7 CIDMR1.AM6 6 Acceptance Mask Bit 6 CIDMR1.AM5 5 Acceptance Mask Bit 5 CIDMR1.AM4 4 Acceptance Mask Bit 4 CIDMR1.AM3 3 Acceptance Mask Bit 3 CIDMR1.AM2 2 Acceptance Mask Bit 2 CIDMR1.AM1 1 Acceptance Mask Bit 1 CIDMR1.AM0 0 Acceptance Mask Bit 0 CIDMR2 0x0116 msCAN12 Identifier Mask Register 2 CIDMR2.AM7 7 Acceptance Mask Bit 7 CIDMR2.AM6 6 Acceptance Mask Bit 6 CIDMR2.AM5 5 Acceptance Mask Bit 5 CIDMR2.AM4 4 Acceptance Mask Bit 4 CIDMR2.AM3 3 Acceptance Mask Bit 3 CIDMR2.AM2 2 Acceptance Mask Bit 2 CIDMR2.AM1 1 Acceptance Mask Bit 1 CIDMR2.AM0 0 Acceptance Mask Bit 0 CIDMR3 0x0117 msCAN12 Identifier Mask Register 3 CIDMR3.AM7 7 Acceptance Mask Bit 7 CIDMR3.AM6 6 Acceptance Mask Bit 6 CIDMR3.AM5 5 Acceptance Mask Bit 5 CIDMR3.AM4 4 Acceptance Mask Bit 4 CIDMR3.AM3 3 Acceptance Mask Bit 3 CIDMR3.AM2 2 Acceptance Mask Bit 2 CIDMR3.AM1 1 Acceptance Mask Bit 1 CIDMR3.AM0 0 Acceptance Mask Bit 0 CIDAR4 0x0118 msCAN12 Identifier Acceptance Register 4 CIDAR4.AC7 7 Acceptance Code Bit 7 CIDAR4.AC6 6 Acceptance Code Bit 6 CIDAR4.AC5 5 Acceptance Code Bit 5 CIDAR4.AC4 4 Acceptance Code Bit 4 CIDAR4.AC3 3 Acceptance Code Bit 3 CIDAR4.AC2 2 Acceptance Code Bit 2 CIDAR4.AC1 1 Acceptance Code Bit 1 CIDAR4.AC0 0 Acceptance Code Bit 0 CIDAR5 0x0119 msCAN12 Identifier Acceptance Register 5 CIDAR5.AC7 7 Acceptance Code Bit 7 CIDAR5.AC6 6 Acceptance Code Bit 6 CIDAR5.AC5 5 Acceptance Code Bit 5 CIDAR5.AC4 4 Acceptance Code Bit 4 CIDAR5.AC3 3 Acceptance Code Bit 3 CIDAR5.AC2 2 Acceptance Code Bit 2 CIDAR5.AC1 1 Acceptance Code Bit 1 CIDAR5.AC0 0 Acceptance Code Bit 0 CIDAR6 0x011A msCAN12 Identifier Acceptance Register 6 CIDAR6.AC7 7 Acceptance Code Bit 7 CIDAR6.AC6 6 Acceptance Code Bit 6 CIDAR6.AC5 5 Acceptance Code Bit 5 CIDAR6.AC4 4 Acceptance Code Bit 4 CIDAR6.AC3 3 Acceptance Code Bit 3 CIDAR6.AC2 2 Acceptance Code Bit 2 CIDAR6.AC1 1 Acceptance Code Bit 1 CIDAR6.AC0 0 Acceptance Code Bit 0 CIDAR7 0x011B msCAN12 Identifier Acceptance Register 7 CIDAR7.AC7 7 Acceptance Code Bit 7 CIDAR7.AC6 6 Acceptance Code Bit 6 CIDAR7.AC5 5 Acceptance Code Bit 5 CIDAR7.AC4 4 Acceptance Code Bit 4 CIDAR7.AC3 3 Acceptance Code Bit 3 CIDAR7.AC2 2 Acceptance Code Bit 2 CIDAR7.AC1 1 Acceptance Code Bit 1 CIDAR7.AC0 0 Acceptance Code Bit 0 CIDMR4 0x011C msCAN12 Identifier Mask Register 4 CIDMR4.AM7 7 Acceptance Mask Bit 7 CIDMR4.AM6 6 Acceptance Mask Bit 6 CIDMR4.AM5 5 Acceptance Mask Bit 5 CIDMR4.AM4 4 Acceptance Mask Bit 4 CIDMR4.AM3 3 Acceptance Mask Bit 3 CIDMR4.AM2 2 Acceptance Mask Bit 2 CIDMR4.AM1 1 Acceptance Mask Bit 1 CIDMR4.AM0 0 Acceptance Mask Bit 0 CIDMR5 0x011D msCAN12 Identifier Mask Register 5 CIDMR5.AM7 7 Acceptance Mask Bit 7 CIDMR5.AM6 6 Acceptance Mask Bit 6 CIDMR5.AM5 5 Acceptance Mask Bit 5 CIDMR5.AM4 4 Acceptance Mask Bit 4 CIDMR5.AM3 3 Acceptance Mask Bit 3 CIDMR5.AM2 2 Acceptance Mask Bit 2 CIDMR5.AM1 1 Acceptance Mask Bit 1 CIDMR5.AM0 0 Acceptance Mask Bit 0 CIDMR6 0x011E msCAN12 Identifier Mask Register 6 CIDMR6.AM7 7 Acceptance Mask Bit 7 CIDMR6.AM6 6 Acceptance Mask Bit 6 CIDMR6.AM5 5 Acceptance Mask Bit 5 CIDMR6.AM4 4 Acceptance Mask Bit 4 CIDMR6.AM3 3 Acceptance Mask Bit 3 CIDMR6.AM2 2 Acceptance Mask Bit 2 CIDMR6.AM1 1 Acceptance Mask Bit 1 CIDMR6.AM0 0 Acceptance Mask Bit 0 CIDMR7 0x011F msCAN12 Identifier Mask Register 7 CIDMR7.AM7 7 Acceptance Mask Bit 7 CIDMR7.AM6 6 Acceptance Mask Bit 6 CIDMR7.AM5 5 Acceptance Mask Bit 5 CIDMR7.AM4 4 Acceptance Mask Bit 4 CIDMR7.AM3 3 Acceptance Mask Bit 3 CIDMR7.AM2 2 Acceptance Mask Bit 2 CIDMR7.AM1 1 Acceptance Mask Bit 1 CIDMR7.AM0 0 Acceptance Mask Bit 0 RESERVED0120 0x0120 RESERVED RESERVED0121 0x0121 RESERVED RESERVED0122 0x0122 RESERVED RESERVED0123 0x0123 RESERVED RESERVED0124 0x0124 RESERVED RESERVED0125 0x0125 RESERVED RESERVED0126 0x0126 RESERVED RESERVED0127 0x0127 RESERVED RESERVED0128 0x0128 RESERVED RESERVED0129 0x0129 RESERVED RESERVED012A 0x012A RESERVED RESERVED012B 0x012B RESERVED RESERVED012C 0x012C RESERVED RESERVED012D 0x012D RESERVED RESERVED012E 0x012E RESERVED RESERVED012F 0x012F RESERVED RESERVED0130 0x0130 RESERVED RESERVED0131 0x0131 RESERVED RESERVED0132 0x0132 RESERVED RESERVED0133 0x0133 RESERVED RESERVED0134 0x0134 RESERVED RESERVED0135 0x0135 RESERVED RESERVED0136 0x0136 RESERVED RESERVED0137 0x0137 RESERVED RESERVED0138 0x0138 RESERVED RESERVED0139 0x0139 RESERVED RESERVED013A 0x013A RESERVED RESERVED013B 0x013B RESERVED RESERVED013C 0x013C RESERVED PCTLCAN 0x013D msCAN12 Port CAN Control Register PCTLCAN.PUPCAN 1 Pull-Up Enable Port CAN PCTLCAN.RDPCAN 0 Reduced Drive Port CAN PORTCAN 0x013E msCAN12 Port CAN Data Register PORTCAN.PCAN7 7 Port CAN Data Bit 7 PORTCAN.PCAN6 6 Port CAN Data Bit 6 PORTCAN.PCAN5 5 Port CAN Data Bit 5 PORTCAN.PCAN4 4 Port CAN Data Bit 4 PORTCAN.PCAN3 3 Port CAN Data Bit 3 PORTCAN.PCAN2 2 Port CAN Data Bit 2 PORTCAN.TxCAN 1 PORTCAN.RxCAN 0 DDRCAN 0x013F msCAN12 Port CAN Data Direction Register DDRCAN.DDCAN7 7 Data Direction Port CAN Bit 7 DDRCAN.DDCAN6 6 Data Direction Port CAN Bit 6 DDRCAN.DDCAN5 5 Data Direction Port CAN Bit 5 DDRCAN.DDCAN4 4 Data Direction Port CAN Bit 4 DDRCAN.DDCAN3 3 Data Direction Port CAN Bit 3 DDRCAN.DDCAN2 2 Data Direction Port CAN Bit 2 ATD1CTL2 0x01E2 ATD1 Control Register 2 ATD1CTL2.ADPU 7 ATD Disable ATD1CTL2.ADPU 6 ATD Fast Flag Clear All ATD1CTL2.ASWAI 5 ATD Wait Mode ATD1CTL2.DJM 4 Result Register Data Justification Mode ATD1CTL2.DSGN 3 Signed/Unsigned Result Data Mode ATD1CTL2.ASCIE 1 ATD Sequence Complete Interrupt Enable ATD1CTL2.ASCIF 0 ATD Sequence Complete Interrupt Flag ATD1CTL3 0x01E3 ATD1 Control Register 3 ATD1CTL3.S1C 3 Conversion Sequence Length ATD1CTL3.FIFO 2 Result Register FIFO Mode ATD1CTL3.FRZ1 1 Background Debug Freeze Enable 1 ATD1CTL3.FRZ0 0 Background Debug Freeze Enable 0 ATD1CTL4 0x01E4 ATD1 Control Register 4 ATD1CTL4.RES10 7 A/D Resolution Select ATD1CTL4.SMP1 6 Sample Time Select 1 ATD1CTL4.SMP0 5 Sample Time Select 0 ATD1CTL4.PRS4 4 ATD Clock Prescaler 4 ATD1CTL4.PRS3 3 ATD Clock Prescaler 3 ATD1CTL4.PRS2 2 ATD Clock Prescaler 2 ATD1CTL4.PRS1 1 ATD Clock Prescaler 1 ATD1CTL4.PRS0 0 ATD Clock Prescaler 0 ATD1CTL5 0x01E5 ATD1 Control Register 5 ATD1CTL5.S8C 6 Conversion Sequence Length ATD1CTL5.SCAN 5 Continuous Conversion Sequence Mode ATD1CTL5.MULT 4 Multi-Channel Sample Mode ATD1CTL5.SC 3 Special Channel Conversion Mode ATD1CTL5.CC 2 Analog Input Channel Select Code C ATD1CTL5.CB 1 Analog Input Channel Select Code B ATD1CTL5.CA 0 Analog Input Channel Select Code A ATD1STAT0 0x01E6 ATD1 Status Register ATD1STAT0.SCF 7 Sequence Complete Flag ATD1STAT0.CC2 2 Conversion Counter 2 ATD1STAT0.CC1 1 Conversion Counter 1 ATD1STAT0.CC0 0 Conversion Counter 0 ATD1STAT1 0x01E7 ATD1 Status Register ATD1STAT1.CCF7 7 Conversion Complete Flag 7 ATD1STAT1.CCF6 6 Conversion Complete Flag 6 ATD1STAT1.CCF5 5 Conversion Complete Flag 5 ATD1STAT1.CCF4 4 Conversion Complete Flag 4 ATD1STAT1.CCF3 3 Conversion Complete Flag 3 ATD1STAT1.CCF2 2 Conversion Complete Flag 2 ATD1STAT1.CCF1 1 Conversion Complete Flag 1 ATD1STAT1.CCF0 0 Conversion Complete Flag 0 ATD1TESTH 0x01E8 ATD1 Test Register ATD1TESTH.SAR9 7 Successive Approximation Register 9 ATD1TESTH.SAR8 6 Successive Approximation Register 8 ATD1TESTH.SAR7 5 Successive Approximation Register 7 ATD1TESTH.SAR6 4 Successive Approximation Register 6 ATD1TESTH.SAR5 3 Successive Approximation Register 5 ATD1TESTH.SAR4 2 Successive Approximation Register 4 ATD1TESTH.SAR3 1 Successive Approximation Register 3 ATD1TESTH.SAR2 0 Successive Approximation Register 2 ATD1TESTL 0x01E9 ATD1 Test Register ATD1TESTL.SAR1 7 Successive Approximation Register 1 ATD1TESTL.SAR0 6 Successive Approximation Register 0 ATD1TESTL.RST 5 Test Mode Reset Bit RESERVED01EA 0x01EA RESERVED RESERVED01EB 0x01EB RESERVED RESERVED01EC 0x01EC RESERVED RESERVED01ED 0x01ED RESERVED RESERVED01EE 0x01EE RESERVED PORTAD1 0x01EF Port AD Data Input Register 1 PORTAD1.PAD17 7 Port AD Data Input Bit 7 PORTAD1.PAD16 6 Port AD Data Input Bit 6 PORTAD1.PAD15 5 Port AD Data Input Bit 5 PORTAD1.PAD14 4 Port AD Data Input Bit 4 PORTAD1.PAD13 3 Port AD Data Input Bit 3 PORTAD1.PAD12 2 Port AD Data Input Bit 2 PORTAD1.PAD11 1 Port AD Data Input Bit 1 PORTAD1.PAD10 0 Port AD Data Input Bit 0 ADR10H 0x01F0 A/D Converter Result Register 10 High ADR10L 0x01F1 A/D Converter Result Register 10 Low ADR11H 0x01F2 A/D Converter Result Register 11 High ADR11H 0x01F3 A/D Converter Result Register 11 Low ADR12H 0x01F4 A/D Converter Result Register 12 High ADR12H 0x01F5 A/D Converter Result Register 12 Low ADR13H 0x01F6 A/D Converter Result Register 13 High ADR13H 0x01F7 A/D Converter Result Register 13 Low ADR14H 0x01F8 A/D Converter Result Register 14 High ADR14H 0x01F9 A/D Converter Result Register 14 Low ADR15H 0x01FA A/D Converter Result Register 15 High ADR15H 0x01FB A/D Converter Result Register 15 Low ADR16H 0x01FC A/D Converter Result Register 16 High ADR16H 0x01FD A/D Converter Result Register 16 Low ADR17H 0x01FE A/D Converter Result Register 17 High ADR17H 0x01FF A/D Converter Result Register 17 Low .68HC12D60 ; ; MC68HC912D60.pdf ; MEMORY MAP area DATA FSR0 0x0000:0x0140 area DATA R_BUFFER 0x0140:0x0150 RECEIVE BUFFER area DATA T_BUFFER0 0x0150:0x0160 TRANSMIT BUFFER 0 area DATA T_BUFFER1 0x0160:0x0170 TRANSMIT BUFFER 1 area DATA T_BUFFER2 0x0170:0x0180 TRANSMIT BUFFER 2 area BSS RESERVED 0x0180:0x01E1 area DATA FSR1 0x01E1:0x0200 area DATA RAM 0x0200:0x0800 area BSS RESERVED 0x0800:0x0C00 area DATA EEPROM_1 0x0C00:0x1000 area DATA ROM_1 0x1000:0x8000 area DATA ROM_2 0x8000:0xFF00 area DATA USER_VEC 0xFF00:0x10000 ; Interrupt and reset vector assignments interrupt __RESET 0xFFFE Reset interrupt _COPCTL 0xFFFC Clock monitor fail reset interrupt COP_FR 0xFFFA COP failure reset interrupt UIT 0xFFF8 Unimplemented instruction trap interrupt SWI 0xFFF6 SWI interrupt XIRQ 0xFFF4 XIRQ interrupt _INTCR_IRQEN 0xFFF2 IRQ interrupt RTICTL_RTIE 0xFFF0 Real time interrupt interrupt TMSK1_C0I 0xFFEE Timer channel 0 interrupt TMSK1_C1I 0xFFEC Timer channel 1 interrupt TMSK1_C2I 0xFFEA Timer channel 2 interrupt TMSK1_C3I 0xFFE8 Timer channel 3 interrupt TMSK1_C4I 0xFFE6 Timer channel 4 interrupt TMSK1_C5I 0xFFE4 Timer channel 5 interrupt TMSK1_C6I 0xFFE2 Timer channel 6 interrupt TMSK1_C7I 0xFFE0 Timer channel 7 interrupt TMSK2_TOI 0xFFDE Timer overflow interrupt PACTL_PAOVI 0xFFDC Pulse accumulator overflow interrupt PACTL_PAI 0xFFDA Pulse accumulator input edge interrupt SP0CR1_SPIE 0xFFD8 SPI serial transfer complete interrupt _SC0CR2 0xFFD6 SCI 0 interrupt _SC1CR2 0xFFD4 SCI 1 interrupt ATDxCTL2_ASCIE 0xFFD2 ATD0 or ATD1 interrupt CRIER_WUPIE 0xFFD0 MSCAN wake-up interrupt KWIEG_KWIEH 0xFFCE Key wake-up G or H interrupt MCCTL_MCZI 0xFFCC Modulus down counter underflow interrupt PBCTL_PBOVI 0xFFCA Pulse Accumulator B Overflow interrupt CRIER_ERR 0xFFC8 MSCAN errors interrupt CRIER_RXFIE 0xFFC6 MSCAN receive interrupt CTCR_TXEIE 0xFFC4 MSCAN transmit interrupt _PLLCR_LOCKIE_LHIE 0xFFC2 CGM lock and limp home ; INPUT/ OUTPUT PORTS PORTA 0x0000 Port A Data Register PORTA.PA7 7 Port A Data Bit 7 PORTA.PA6 6 Port A Data Bit 6 PORTA.PA5 5 Port A Data Bit 5 PORTA.PA4 4 Port A Data Bit 4 PORTA.PA3 3 Port A Data Bit 3 PORTA.PA2 2 Port A Data Bit 2 PORTA.PA1 1 Port A Data Bit 1 PORTA.PA0 0 Port A Data Bit 0 PORTB 0x0001 Port B Data Register PORTB.PB7 7 Port B Data Bit 7 PORTB.PB6 6 Port B Data Bit 6 PORTB.PB5 5 Port B Data Bit 5 PORTB.PB4 4 Port B Data Bit 4 PORTB.PB3 3 Port B Data Bit 3 PORTB.PB2 2 Port B Data Bit 2 PORTB.PB1 1 Port B Data Bit 1 PORTB.PB0 0 Port B Data Bit 0 DDRA 0x0002 Port A Data Direction Register DDRA.DDA7 7 Port A Data Direction Bit 7 DDRA.DDA6 6 Port A Data Direction Bit 6 DDRA.DDA5 5 Port A Data Direction Bit 5 DDRA.DDA4 4 Port A Data Direction Bit 4 DDRA.DDA3 3 Port A Data Direction Bit 3 DDRA.DDA2 2 Port A Data Direction Bit 2 DDRA.DDA1 1 Port A Data Direction Bit 1 DDRA.DDA0 0 Port A Data Direction Bit 0 DDRB 0x0003 Port B Data Direction Register DDRB.DDB7 7 Port B Data Direction Bit 7 DDRB.DDB6 6 Port B Data Direction Bit 6 DDRB.DDB5 5 Port B Data Direction Bit 5 DDRB.DDB4 4 Port B Data Direction Bit 4 DDRB.DDB3 3 Port B Data Direction Bit 3 DDRB.DDB2 2 Port B Data Direction Bit 2 DDRB.DDB1 1 Port B Data Direction Bit 1 DDRB.DDB0 0 Port B Data Direction Bit 0 RESERVED0004 0x0004 RESERVED RESERVED0005 0x0005 RESERVED RESERVED0006 0x0006 RESERVED RESERVED0007 0x0007 RESERVED PORTE 0x0008 Port E Data Register PORTE.PE7 7 Port E Data Bit 7 PORTE.PE6 6 Port E Data Bit 6 PORTE.PE5 5 Port E Data Bit 5 PORTE.PE4 4 Port E Data Bit 4 PORTE.PE3 3 Port E Data Bit 3 PORTE.PE2 2 Port E Data Bit 2 PORTE.PE1 1 Port E Data Bit 1 PORTE.PE0 0 Port E Data Bit 0 DDRE 0x0009 Port E Data Direction Register DDRE.DDE7 7 Port E Data Direction Bit 7 DDRE.DDE6 6 Port E Data Direction Bit 6 DDRE.DDE5 5 Port E Data Direction Bit 5 DDRE.DDE4 4 Port E Data Direction Bit 4 DDRE.DDE3 3 Port E Data Direction Bit 3 DDRE.DDE2 2 Port E Data Direction Bit 2 PEAR 0x000A Port E Assignment Register PEAR.NDBE 7 No Data Bus Enable PEAR.CGMTE 6 Clock Generator Module Testing Enable PEAR.PIPOE 5 Pipe Status Signal Output Enable PEAR.NECLK 4 No External E Clock PEAR.LSTRE 3 Low Strobe (LSTRB) Enable PEAR.RDWE 2 Read/Write Enable PEAR.CALE 1 Calibration Reference Enable PEAR.DBENE 0 DBE or Inverted E Clock on Port E MODE 0x000B Mode Register MODE.SMODN 7 Mode Select Special MODE.MODB 6 Mode Select B MODE.MODA 5 Mode Select A MODE.ESTR 4 E Clock Stretch Enable MODE.IVIS 3 Internal Visibility MODE.EBSWAI 2 External Bus Module Stop in Wait Control MODE.EME 0 Emulate Port E PUCR 0x000C Pull-Up Control Register PUCR.PUPH 7 Pull-Up or Pull-Down Port H Enable PUCR.PUPG 6 Pull-Up or Pull-Down Port G Enable PUCR.PUPE 4 Pull-Up Port E Enable PUCR.PUPB 1 Pull-Up Port B Enable PUCR.PUPA 0 Pull-Up Port A Enable RDRIV 0x000D Reduced Drive of I/O Lines RDRIV.RDPH 6 Reduced Drive of Port H RDRIV.RDPG 5 Reduced Drive of Port G RDRIV.RDPE 3 Reduced Drive of Port E RDRIV.RDPB 1 Reduced Drive of Port B RDRIV.RDPA 0 Reduced Drive of Port A RESERVED000E 0x000E RESERVED RESERVED000F 0x000F RESERVED INITRM 0x0010 Initialization of Internal RAM Position Register INITRM.RAM15 7 Internal RAM map position 15 INITRM.RAM14 6 Internal RAM map position 14 INITRM.RAM13 5 Internal RAM map position 13 INITRM.RAM12 4 Internal RAM map position 12 INITRM.RAM11 3 Internal RAM map position 11 INITRG 0x0011 Initialization of Internal Register Position Register INITRG.REG15 7 Internal register map position 15 INITRG.REG14 6 Internal register map position 14 INITRG.REG13 5 Internal register map position 13 INITRG.REG12 4 Internal register map position 12 INITRG.REG11 3 Internal register map position 11 INITRG.MMSWAI 0 Memory Mapping Interface Stop in Wait Control INITEE 0x0012 Initialization of Internal EEPROM Position Register INITEE.EE15 7 Internal EEPROM map position 15 INITEE.EE14 6 Internal EEPROM map position 14 INITEE.EE13 5 Internal EEPROM map position 13 INITEE.EE12 4 Internal EEPROM map position 12 INITEE.EEON 0 internal EEPROM On (Enabled) MISC 0x0013 Miscellaneous Mapping Control Register MISC.MAPROM 7 Map Location of ROM MISC.NDRF 6 Narrow Data Bus for Register-Following Map Space MISC.RFSTR1 5 Register Following Stretch 1 MISC.RFSTR0 4 Register Following Stretch 0 MISC.EXSTR1 3 External Access Stretch 1 MISC.EXSTR0 2 External Access Stretch 0 MISC.ROMON28 1 Enable bits for ROM 28 MISC.ROMON32 0 Enable bits for ROM 32 RTICTL 0x0014 Real-Time Interrupt Control Register RTICTL.RTIE 7 Real Time Interrupt Enable RTICTL.RSWAI 6 RTI and COP Stop While in Wait RTICTL.RSBCK 5 RTI and COP Stop While in Background Debug Mode RTICTL.RTBYP 3 Real Time Interrupt Divider Chain Bypass RTICTL.RTR2 2 Real-Time Interrupt Rate Select 2 RTICTL.RTR1 1 Real-Time Interrupt Rate Select 1 RTICTL.RTR0 0 Real-Time Interrupt Rate Select 0 RTIFLG 0x0015 Real Time Interrupt Flag Register RTIFLG.RTIF 7 Real Time Interrupt Flag COPCTL 0x0016 COP Control Register COPCTL.CME 7 Clock Monitor Enable COPCTL.FCME 6 Force Clock Monitor Enable COPCTL.FCMCOP 5 Force Clock Monitor Reset or COP Watchdog Reset COPCTL.WCOP 4 Window COP mode COPCTL.DISR 3 Disable Resets from COP Watchdog and Clock Monitor COPCTL.CR2 2 COP Watchdog Timer Rate select bit 2 COPCTL.CR1 1 COP Watchdog Timer Rate select bit 1 COPCTL.CR0 0 COP Watchdog Timer Rate select bit 0 COPRST 0x0017 Arm/Reset COP Timer Register RESERVED0018 0x0018 RESERVED RESERVED0019 0x0019 RESERVED RESERVED001A 0x001A RESERVED RESERVED001B 0x001B RESERVED RESERVED001C 0x001C RESERVED RESERVED001D 0x001D RESERVED INTCR 0x001E Interrupt Control Register INTCR.IRQE 7 IRQ Select Edge Sensitive Only INTCR.IRQEN 6 External IRQ Enable INTCR.DLY 5 Enable Oscillator Start-up Delay on Exit from STOP HPRIO 0x001F Highest Priority I Interrupt HPRIO.PSEL5 5 HPRIO.PSEL4 4 HPRIO.PSEL3 3 HPRIO.PSEL2 2 HPRIO.PSEL1 1 BRKCT0 0x0020 Breakpoint Control Register 0 BRKCT0.BKEN1 7 Breakpoint Mode Enable 1 BRKCT0.BKEN0 6 Breakpoint Mode Enable 0 BRKCT0.BKPM 5 Break on Program Addresses BRKCT0.BK1ALE 3 Breakpoint 1 Range Control BRKCT0.BK0ALE 2 Breakpoint 0 Range Control BRKCT1 0x0021 Breakpoint Control Register 1 BRKCT1.BKDBE 6 Enable Data Bus BRKCT1.BKMBH 5 Breakpoint Mask High BRKCT1.BKMBL 4 Breakpoint Mask Low BRKCT1.BK1RWE 3 R/W Compare Enable BRKCT1.BK1RW 2 R/W Compare Value BRKCT1.BK0RWE 1 R/W Compare Enable BRKCT1.BK0RW 0 R/W Compare Value BRKAH 0x0022 Breakpoint Address Register, High Byte BRKAL 0x0023 Breakpoint Address Register, Low Byte BRKDH 0x0024 Breakpoint Data Register, High Byte BRKDL 0x0025 Breakpoint Data Register, Low Byte RESERVED0026 0x0026 RESERVED RESERVED0027 0x0027 RESERVED PORTG 0x0028 Port G Data Register PORTG.PG7 7 Port G Data Bit 7 PORTG.PG6 6 Port G Data Bit 6 PORTG.PG5 5 Port G Data Bit 5 PORTG.PG4 4 Port G Data Bit 4 PORTG.PG3 3 Port G Data Bit 3 PORTG.PG2 2 Port G Data Bit 2 PORTG.PG1 1 Port G Data Bit 1 PORTG.PG0 0 Port G Data Bit 0 PORTH 0x0029 Port H Data Register PORTH.PH7 7 Port H Data Bit 7 PORTH.PH6 6 Port H Data Bit 6 PORTH.PH5 5 Port H Data Bit 5 PORTH.PH4 4 Port H Data Bit 4 PORTH.PH3 3 Port H Data Bit 3 PORTH.PH2 2 Port H Data Bit 2 PORTH.PH1 1 Port H Data Bit 1 PORTH.PH0 0 Port H Data Bit 0 DDRG 0x002A Port G Data Direction Register DDRG.DDG7 7 Port G Data Direction Bit 7 DDRG.DDG6 6 Port G Data Direction Bit 6 DDRG.DDG5 5 Port G Data Direction Bit 5 DDRG.DDG4 4 Port G Data Direction Bit 4 DDRG.DDG3 3 Port G Data Direction Bit 3 DDRG.DDG2 2 Port G Data Direction Bit 2 DDRG.DDG1 1 Port G Data Direction Bit 1 DDRG.DDG0 0 Port G Data Direction Bit 0 DDRH 0x002B Port H Data Direction Register DDRH.DDH7 7 Port H Data Direction Bit 7 DDRH.DDH6 6 Port H Data Direction Bit 6 DDRH.DDH5 5 Port H Data Direction Bit 5 DDRH.DDH4 4 Port H Data Direction Bit 4 DDRH.DDH3 3 Port H Data Direction Bit 3 DDRH.DDH2 2 Port H Data Direction Bit 2 DDRH.DDH1 1 Port H Data Direction Bit 1 DDRH.DDH0 0 Port H Data Direction Bit 0 KWIEG 0x002C Key Wake-up Port G Interrupt Enable Register KWIEG.WI2CE 7 Wake-up I2C Enable KWIEG.KWIEG6 6 Key Wake-up Port G Interrupt Enables 6 KWIEG.KWIEG5 5 Key Wake-up Port G Interrupt Enables 5 KWIEG.KWIEG4 4 Key Wake-up Port G Interrupt Enables 4 KWIEG.KWIEG3 3 Key Wake-up Port G Interrupt Enables 3 KWIEG.KWIEG2 2 Key Wake-up Port G Interrupt Enables 2 KWIEG.KWIEG1 1 Key Wake-up Port G Interrupt Enables 1 KWIEG.KWIEG0 0 Key Wake-up Port G Interrupt Enables 0 KWIEH 0x002D Key Wake-up Port H Interrupt Enable Register KWIEH.KWIEH7 7 Key Wake-up Port H Interrupt Enables 7 KWIEH.KWIEH6 6 Key Wake-up Port H Interrupt Enables 6 KWIEH.KWIEH5 5 Key Wake-up Port H Interrupt Enables 5 KWIEH.KWIEH4 4 Key Wake-up Port H Interrupt Enables 4 KWIEH.KWIEH3 3 Key Wake-up Port H Interrupt Enables 3 KWIEH.KWIEH2 2 Key Wake-up Port H Interrupt Enables 2 KWIEH.KWIEH1 1 Key Wake-up Port H Interrupt Enables 1 KWIEH.KWIEH0 0 Key Wake-up Port H Interrupt Enables 0 KWIFG 0x002E Key Wake-up Port G Flag Register KWIFG.KWIFG6 6 Key Wake-up Port G Flag 6 KWIFG.KWIFG5 5 Key Wake-up Port G Flag 5 KWIFG.KWIFG4 4 Key Wake-up Port G Flag 4 KWIFG.KWIFG3 3 Key Wake-up Port G Flag 3 KWIFG.KWIFG2 2 Key Wake-up Port G Flag 2 KWIFG.KWIFG1 1 Key Wake-up Port G Flag 1 KWIFG.KWIFG0 0 Key Wake-up Port G Flag 0 KWIFH 0x002F Key Wake-up Port H Flag Register KWIFH.KWIFH7 7 Key Wake-up Port H Flag 7 KWIFH.KWIFH6 6 Key Wake-up Port H Flag 6 KWIFH.KWIFH5 5 Key Wake-up Port H Flag 5 KWIFH.KWIFH4 4 Key Wake-up Port H Flag 4 KWIFH.KWIFH3 3 Key Wake-up Port H Flag 3 KWIFH.KWIFH2 2 Key Wake-up Port H Flag 2 KWIFH.KWIFH1 1 Key Wake-up Port H Flag 1 KWIFH.KWIFH0 0 Key Wake-up Port H Flag 0 RESERVED0030 0x0030 RESERVED RESERVED0031 0x0031 RESERVED RESERVED0032 0x0032 RESERVED RESERVED0033 0x0033 RESERVED RESERVED0034 0x0034 RESERVED RESERVED0035 0x0035 RESERVED RESERVED0036 0x0036 RESERVED RESERVED0037 0x0037 RESERVED SYNR 0x0038 Synthesizer Register SYNR.SYN5 5 SYNR.SYN4 4 SYNR.SYN3 3 SYNR.SYN2 2 SYNR.SYN1 1 SYNR.SYN0 0 REFDV 0x0039 Reference Divider Register REFDV.REFDV2 2 REFDV.REFDV1 1 REFDV.REFDV0 0 RESERVED003A 0x003A PLLFLG 0x003B PLL Flags PLLFLG.LOCKIF 7 PLL Flags PLLFLG.LOCK 6 Locked Phase Lock Loop Circuit PLLFLG.LHIF 1 Limp-Home Interrupt Flag PLLFLG.LHOME 0 Limp-Home Mode Status PLLCR 0x003C PLL Control Register PLLCR.LOCKIE 7 PLL LOCK Interrupt Enable PLLCR.PLLON 6 Phase Lock Loop On PLLCR.AUTO 5 Automatic Bandwidth Control PLLCR.ACQ 4 Not in Acquisition PLLCR.PSTP 2 Pseudo-STOP Enable PLLCR.LHIE 1 Limp-Home Interrupt Enable PLLCR.NOLHM 0 No Limp-Home Mode CLKSEL 0x003D Clock Generator Clock select Register CLKSEL.BCSP 6 Bus Clock Select PLL CLKSEL.BCSS 5 Bus Clock Select Slow CLKSEL.MCS 2 Module Clock Select SLOW 0x003E Slow mode Divider Register SLOW.SLDV5 5 SLOW.SLDV4 4 SLOW.SLDV3 3 SLOW.SLDV2 2 SLOW.SLDV1 1 SLOW.SLDV0 0 RESERVED003F 0x003F RESERVED PWCLK 0x0040 PWM Clocks and Concatenate PWCLK.CON23 7 Concatenate PWM Channels 2 and 3 PWCLK.CON01 6 Concatenate PWM Channels 0 and 1 PWCLK.PCKA2 5 Prescaler for Clock A 2 PWCLK.PCKA1 4 Prescaler for Clock A 1 PWCLK.PCKA0 3 Prescaler for Clock A 0 PWCLK.PCKB2 2 Prescaler for Clock B 2 PWCLK.PCKB1 1 Prescaler for Clock B 1 PWCLK.PCKB0 0 Prescaler for Clock B 0 PWPOL 0x0041 PWM Clock Select and Polarity PWPOL.PCLK3 7 PWM Channel 3 Clock Select PWPOL.PCLK2 6 PWM Channel 2 Clock Select PWPOL.PCLK1 5 PWM Channel 1 Clock Select PWPOL.PCLK0 4 PWM Channel 0 Clock Select PWPOL.PPOL3 3 PWM Channel 3 Polarity PWPOL.PPOL2 2 PWM Channel 2 Polarity PWPOL.PPOL1 1 PWM Channel 1 Polarity PWPOL.PPOL0 0 PWM Channel 0 Polarity PWEN 0x0042 PWM Enable PWEN.PWEN3 3 PWM Channel 3 Enable PWEN.PWEN2 2 PWM Channel 2 Enable PWEN.PWEN1 1 PWM Channel 1 Enable PWEN.PWEN0 0 PWM Channel 0 Enable PWPRES 0x0043 PWM Prescale Counter PWSCAL0 0x0044 PWM Scale Register 0 PWSCNT0 0x0045 PWM Scale Counter 0 Value PWSCAL1 0x0046 PWM Scale Register 1 PWSCNT1 0x0047 PWM Scale Counter 1 Value PWCNT0 0x0048 PWM Channel Counter 0 PWCNT1 0x0049 PWM Channel Counter 1 PWCNT2 0x004A PWM Channel Counter 2 PWCNT3 0x004B PWM Channel Counter 3 PWPER0 0x004C PWM Channel Period Register 0 PWPER1 0x004D PWM Channel Period Register 1 PWPER2 0x004E PWM Channel Period Register 2 PWPER3 0x004F PWM Channel Period Register 3 PWDTY0 0x0050 PWM Channel Duty Register 0 PWDTY1 0x0051 PWM Channel Duty Register 1 PWDTY2 0x0052 PWM Channel Duty Register 2 PWDTY3 0x0053 PWM Channel Duty Register 3 PWCTL 0x0054 PWM Control Register PWCTL.PSWAI 4 PWM Halts while in Wait Mode PWCTL.CENTR 3 Center-Aligned Output Mode PWCTL.RDPP 2 Reduced Drive of Port P PWCTL.PUPP 1 Pull-Up Port P Enable PWCTL.PSBCK 0 PWM Stops while in Background Mode PWTST 0x0055 PWM Special Mode Register ("Test") PWTST.DISCR 7 Disable Reset of Channel Counter on Write to Channel Counter PWTST.DISCP 6 Disable Compare Count Period PWTST.DISCAL 5 Disable Load of Scale-Counters on Write to the Associated Scale-Registers PORTP 0x0056 Port P Data Register PORTP.PP7 7 Port P Data Bit 7 PORTP.PP6 6 Port P Data Bit 6 PORTP.PP5 5 Port P Data Bit 5 PORTP.PP4 4 Port P Data Bit 4 PORTP.PP3 3 Port P Data Bit 3 PORTP.PP2 2 Port P Data Bit 2 PORTP.PP1 1 Port P Data Bit 1 PORTP.PP0 0 Port P Data Bit 0 DDRP 0x0057 Port P Data Direction Register DDRP.DDP7 7 Port P Data Direction Bit 7 DDRP.DDP6 6 Port P Data Direction Bit 6 DDRP.DDP5 5 Port P Data Direction Bit 5 DDRP.DDP4 4 Port P Data Direction Bit 4 DDRP.DDP3 3 Port P Data Direction Bit 3 DDRP.DDP2 2 Port P Data Direction Bit 2 DDRP.DDP1 1 Port P Data Direction Bit 1 DDRP.DDP0 0 Port P Data Direction Bit 0 RESERVED0058 0x0058 RESERVED RESERVED0059 0x0059 RESERVED RESERVED005A 0x005A RESERVED RESERVED005B 0x005B RESERVED RESERVED005C 0x005C RESERVED RESERVED005D 0x005D RESERVED RESERVED005E 0x005E RESERVED RESERVED005F 0x005F RESERVED RESERVED0060 0x0060 RESERVED RESERVED0061 0x0061 RESERVED ATD0CTL2 0x0062 ATD0 Control Register 2 ATD0CTL2.ADPU 7 ATD Disable ATD0CTL2.AFFC 6 ATD Fast Flag Clear All ATD0CTL2.AWAI 5 ATD Wait Mode ATD0CTL2.ASCIE 1 ATD Sequence Complete Interrupt Enable ATD0CTL2.ASCIF 0 ATD Sequence Complete Interrupt Flag ATD0CTL3 0x0063 ATD0 Control Register 3 ATD0CTL3.FRZ1 1 Background Debug (Freeze) Enable 1 ATD0CTL3.FRZ0 0 Background Debug (Freeze) Enable 0 ATD0CTL4 0x0064 ATD0 Control Register 4 ATD0CTL4.S10BM 7 10 bit Mode ATD0CTL4.SMP1 6 Select Sample Time 1 ATD0CTL4.SMP0 5 Select Sample Time 0 ATD0CTL4.PRS4 4 Select Divide-By Factor for ATD P-Clock Prescaler 4 ATD0CTL4.PRS3 3 Select Divide-By Factor for ATD P-Clock Prescaler 3 ATD0CTL4.PRS2 2 Select Divide-By Factor for ATD P-Clock Prescaler 2 ATD0CTL4.PRS1 1 Select Divide-By Factor for ATD P-Clock Prescaler 1 ATD0CTL4.PRS0 0 Select Divide-By Factor for ATD P-Clock Prescaler 0 ATD0CTL5 0x0065 ATD0 Control Register 5 ATD0CTL5.S8CM 6 Select 8 Channel Mode ATD0CTL5.SCAN 5 Enable Continuous Channel Scan ATD0CTL5.MULT 4 Enable Multichannel Conversion ATD0CTL5.CD 3 Channel D Select for Conversion ATD0CTL5.CC 2 Channel C Select for Conversion ATD0CTL5.CB 1 Channel B Select for Conversion ATD0CTL5.CA 0 Channel A Select for Conversion ATD0STAT0 0x0066 ATD0 Status Register 0 ATD0STAT0.SCF 7 Sequence Complete Flag ATD0STAT0.CC2 2 Conversion Counter 2 for Current Sequence of Four or Eight Conversions ATD0STAT0.CC1 1 Conversion Counter 1 for Current Sequence of Four or Eight Conversions ATD0STAT0.CC0 0 Conversion Counter 0 for Current Sequence of Four or Eight Conversions ATD0STAT1 0x0067 ATD Status Register 1 ATD0STAT1.CCF7 7 Conversion Complete Flag 7 ATD0STAT1.CCF6 6 Conversion Complete Flag 6 ATD0STAT1.CCF5 5 Conversion Complete Flag 5 ATD0STAT1.CCF4 4 Conversion Complete Flag 4 ATD0STAT1.CCF3 3 Conversion Complete Flag 3 ATD0STAT1.CCF2 2 Conversion Complete Flag 2 ATD0STAT1.CCF1 1 Conversion Complete Flag 1 ATD0STAT1.CCF0 0 Conversion Complete Flag 0 ATD0TESTH 0x0068 ATD0 Test Register H ATD0TESTH.SAR9 7 SAR Data 9 ATD0TESTH.SAR8 6 SAR Data 8 ATD0TESTH.SAR7 5 SAR Data 7 ATD0TESTH.SAR6 4 SAR Data 6 ATD0TESTH.SAR5 3 SAR Data 5 ATD0TESTH.SAR4 2 SAR Data 4 ATD0TESTH.SAR3 1 SAR Data 3 ATD0TESTH.SAR2 0 SAR Data 2 ATD0TESTL 0x0069 ATD0 Test Register L ATD0TESTL.SAR1 7 SAR Data 1 ATD0TESTL.SAR0 6 SAR Data 0 ATD0TESTL.RST 5 Module Reset Bit ATD0TESTL.TSTOUT 4 Multiplex Output of TST ATD0TESTL.TST3 3 Test Bit 3 ATD0TESTL.TST2 2 Test Bit 2 ATD0TESTL.TST1 1 Test Bit 1 ATD0TESTL.TST0 0 Test Bit 0 RESERVED006A 0x006A RESERVED RESERVED006B 0x006B RESERVED RESERVED006C 0x006C RESERVED RESERVED006D 0x006D RESERVED RESERVED006E 0x006E RESERVED PORTAD0 0x006F Port AD0 Data Input Register PORTAD0.PAD07 7 Port AD0 Data Input Bit 7 PORTAD0.PAD06 6 Port AD0 Data Input Bit 6 PORTAD0.PAD05 5 Port AD0 Data Input Bit 5 PORTAD0.PAD04 4 Port AD0 Data Input Bit 4 PORTAD0.PAD03 3 Port AD0 Data Input Bit 3 PORTAD0.PAD02 2 Port AD0 Data Input Bit 2 PORTAD0.PAD01 1 Port AD0 Data Input Bit 1 PORTAD0.PAD00 0 Port AD0 Data Input Bit 0 ADR00H 0x0070 A/D Conversion Result Register High 0 ADR00L 0x0071 A/D Conversion Result Register Low 0 ADR01H 0x0072 A/D Conversion Result Register High 1 ADR01L 0x0073 A/D Conversion Result Register Low 1 ADR02H 0x0074 A/D Conversion Result Register High 2 ADR02L 0x0075 A/D Conversion Result Register Low 2 ADR03H 0x0076 A/D Conversion Result Register High 3 ADR03L 0x0077 A/D Conversion Result Register Low 3 ADR04H 0x0078 A/D Conversion Result Register High 4 ADR04L 0x0079 A/D Conversion Result Register Low 4 ADR05H 0x007A A/D Conversion Result Register High 5 ADR05L 0x007B A/D Conversion Result Register Low 5 ADR06H 0x007C A/D Conversion Result Register High 6 ADR06L 0x007D A/D Conversion Result Register Low 6 ADR07H 0x007E A/D Conversion Result Register High 7 ADR07L 0x007F A/D Conversion Result Register Low 7 TIOS 0x0080 Timer Input Capture/Output Compare Select TIOS.IOS7 7 Input Capture or Output Compare Channel 7 Configuration 7 TIOS.IOS6 6 Input Capture or Output Compare Channel 6 Configuration 6 TIOS.IOS5 5 Input Capture or Output Compare Channel 5 Configuration 5 TIOS.IOS4 4 Input Capture or Output Compare Channel 4 Configuration 4 TIOS.IOS3 3 Input Capture or Output Compare Channel 3 Configuration 3 TIOS.IOS2 2 Input Capture or Output Compare Channel 2 Configuration 2 TIOS.IOS1 1 Input Capture or Output Compare Channel 1 Configuration 1 TIOS.IOS0 0 Input Capture or Output Compare Channel 0 Configuration 0 CFORC 0x0081 Timer Compare Force Register CFORC.FOC7 7 Force Output Compare Action for Channel 7 CFORC.FOC6 6 Force Output Compare Action for Channel 6 CFORC.FOC5 5 Force Output Compare Action for Channel 5 CFORC.FOC4 4 Force Output Compare Action for Channel 4 CFORC.FOC3 3 Force Output Compare Action for Channel 3 CFORC.FOC2 2 Force Output Compare Action for Channel 2 CFORC.FOC1 1 Force Output Compare Action for Channel 1 CFORC.FOC0 0 Force Output Compare Action for Channel 0 OC7M 0x0082 Output Compare 7 Mask Register OC7M.OC7M7 7 OC7M.OC7M6 6 OC7M.OC7M5 5 OC7M.OC7M4 4 OC7M.OC7M3 3 OC7M.OC7M2 2 OC7M.OC7M1 1 OC7M.OC7M0 0 OC7D 0x0083 Output Compare 7 Data Register OC7D.OC7D7 7 OC7D.OC7D6 6 OC7D.OC7D5 5 OC7D.OC7D4 4 OC7D.OC7D3 3 OC7D.OC7D2 2 OC7D.OC7D1 1 OC7D.OC7D0 0 TCNTH 0x0084 Timer Count Register High TCNTL 0x0085 Timer Count Register Low TSCR 0x0086 Timer System Control Register TSCR.TEN 7 Timer Enable TSCR.TSWAI 6 Timer Module Stops While in Wait TSCR.TSBCK 5 Timer and Modulus Counter Stop While in Background Mode TSCR.TFFCA 4 Timer Fast Flag Clear All RESERVED0087 0x0087 RESERVED TCTL1 0x0088 Timer Control Register 1 TCTL1.OM7 7 Output Mode 7 TCTL1.OL7 6 Output Level 7 TCTL1.OM6 5 Output Mode 6 TCTL1.OL6 4 Output Level 6 TCTL1.OM5 3 Output Mode 5 TCTL1.OL5 2 Output Level 5 TCTL1.OM4 1 Output Mode 4 TCTL1.OL4 0 Output Level 4 TCTL2 0x0089 Timer Control Register 2 TCTL2.OM3 7 Output Mode 3 TCTL2.OL3 6 Output Level 3 TCTL2.OM2 5 Output Mode 2 TCTL2.OL2 4 Output Level 2 TCTL2.OM1 3 Output Mode 1 TCTL2.OL1 2 Output Level 1 TCTL2.OM0 1 Output Mode 0 TCTL2.OL0 0 Output Level 0 TCTL3 0x008A Timer Control Register 3 TCTL3.EDG7B 7 Input Capture Edge Control 7B TCTL3.EDG7A 6 Input Capture Edge Control 7A TCTL3.EDG6B 5 Input Capture Edge Control 6B TCTL3.EDG6A 4 Input Capture Edge Control 6A TCTL3.EDG5B 3 Input Capture Edge Control 5B TCTL3.EDG5A 2 Input Capture Edge Control 5A TCTL3.EDG4B 1 Input Capture Edge Control 4B TCTL3.EDG4A 0 Input Capture Edge Control 4A TCTL4 0x008B Timer Control Register 4 TCTL4.EDG3B 7 Input Capture Edge Control 3B TCTL4.EDG3A 6 Input Capture Edge Control 3A TCTL4.EDG2B 5 Input Capture Edge Control 2B TCTL4.EDG2A 4 Input Capture Edge Control 2A TCTL4.EDG1B 3 Input Capture Edge Control 1B TCTL4.EDG1A 2 Input Capture Edge Control 1A TCTL4.EDG0B 1 Input Capture Edge Control 0B TCTL4.EDG0A 0 Input Capture Edge Control 0A TMSK1 0x008C Timer Interrupt Mask 1 TMSK1.C7I 7 Input Capture/Output Compare 7 Interrupt Enable TMSK1.C6I 6 Input Capture/Output Compare 6 Interrupt Enable TMSK1.C5I 5 Input Capture/Output Compare 5 Interrupt Enable TMSK1.C4I 4 Input Capture/Output Compare 4 Interrupt Enable TMSK1.C3I 3 Input Capture/Output Compare 3 Interrupt Enable TMSK1.C2I 2 Input Capture/Output Compare 2 Interrupt Enable TMSK1.C1I 1 Input Capture/Output Compare 1 Interrupt Enable TMSK1.C0I 0 Input Capture/Output Compare 0 Interrupt Enable TMSK2 0x008D Timer Interrupt Mask 2 TMSK2.TOI 7 Timer Overflow Interrupt Enable TMSK2.PUPT 5 Timer Port Pull-Up Resistor Enable TMSK2.RDPT 4 Timer Port Drive Reduction TMSK2.TCRE 3 Timer Counter Reset Enable TMSK2.PR2 2 Timer Prescaler Select 2 TMSK2.PR1 1 Timer Prescaler Select 1 TMSK2.PR0 0 Timer Prescaler Select 0 TFLG1 0x008E Main Timer Interrupt Flag 1 TFLG1.C7F 7 Input Capture/Output Compare Channel 7 Flag TFLG1.C6F 6 Input Capture/Output Compare Channel 6 Flag TFLG1.C5F 5 Input Capture/Output Compare Channel 5 Flag TFLG1.C4F 4 Input Capture/Output Compare Channel 4 Flag TFLG1.C3F 3 Input Capture/Output Compare Channel 3 Flag TFLG1.C2F 2 Input Capture/Output Compare Channel 2 Flag TFLG1.C1F 1 Input Capture/Output Compare Channel 1 Flag TFLG1.C0F 0 Input Capture/Output Compare Channel 0 Flag TFLG2 0x008F Main Timer Interrupt Flag 2 TFLG2.TOF 7 Timer Overflow Flag TC0H 0x0090 Timer Input Capture/Output Compare Register 0 H TC0L 0x0091 Timer Input Capture/Output Compare Register 0 L TC1H 0x0092 Timer Input Capture/Output Compare Register 1 H TC1L 0x0093 Timer Input Capture/Output Compare Register 1 L TC2H 0x0094 Timer Input Capture/Output Compare Register 2 H TC2L 0x0095 Timer Input Capture/Output Compare Register 2 L TC3H 0x0096 Timer Input Capture/Output Compare Register 3 H TC3L 0x0097 Timer Input Capture/Output Compare Register 3 L TC4H 0x0098 Timer Input Capture/Output Compare Register 4 H TC4L 0x0099 Timer Input Capture/Output Compare Register 4 L TC5H 0x009A Timer Input Capture/Output Compare Register 5 H TC5L 0x009B Timer Input Capture/Output Compare Register 5 L TC6H 0x009C Timer Input Capture/Output Compare Register 6 H TC6L 0x009D Timer Input Capture/Output Compare Register 6 L TC7H 0x009E Timer Input Capture/Output Compare Register 7 H TC7L 0x009F Timer Input Capture/Output Compare Register 7 L PACTL 0x00A0 16-Bit Pulse Accumulator A Control Register PACTL.PAEN 6 Pulse Accumulator A System Enable PACTL.PAMOD 5 Pulse Accumulator Mode PACTL.PEDGE 4 Pulse Accumulator Edge Control PACTL.CLK1 3 Clock Select Bit 1 PACTL.CLK0 2 Clock Select Bit 0 PACTL.PAOVI 1 Pulse Accumulator A Overflow Interrupt enable PACTL.PAI 0 Pulse Accumulator Input Interrupt enable PAFLG 0x00A1 Pulse Accumulator A Flag Register PAFLG.PAOVF 1 Pulse Accumulator A Overflow Flag PAFLG.PAIF 0 Pulse Accumulator Input edge Flag PACN3 0x00A2 Pulse Accumulators Count Register 3 PACN2 0x00A3 Pulse Accumulators Count Register 2 PACN1 0x00A4 Pulse Accumulators Count Register 1 PACN0 0x00A5 Pulse Accumulators Count Register 0 MCCTL 0x00A6 16-Bit Modulus Down-Counter Control Register MCCTL.MCZI 7 Modulus Counter Underflow Interrupt Enable MCCTL.MODMC 6 Modulus Mode Enable MCCTL.RDMCL 5 Read Modulus Down-Counter Load MCCTL.ICLAT 4 Input Capture Force Latch Action MCCTL.FLMC 3 Force Load Register into the Modulus Counter Count Register MCCTL.MCEN 2 Modulus Down-Counter Enable MCCTL.MCPR1 1 Modulus Counter Prescaler select 1 MCCTL.MCPR0 0 Modulus Counter Prescaler select 0 MCFLG 0x00A7 16-Bit Modulus Down-Counter FLAG Register MCFLG.MCZF 7 Modulus Counter Underflow Interrupt Flag MCFLG.POLF3 3 First Input Capture Polarity Status 3 MCFLG.POLF2 2 First Input Capture Polarity Status 2 MCFLG.POLF1 1 First Input Capture Polarity Status 1 MCFLG.POLF0 0 First Input Capture Polarity Status 0 ICPACR 0x00A8 Input Control Pulse Accumulators Control Register ICPACR.0PA3EN 3 8-Bit Pulse Accumulator 3 Enable ICPACR.0PA2EN 2 8-Bit Pulse Accumulator 2 Enable ICPACR.0PA1EN 1 8-Bit Pulse Accumulator 1 Enable ICPACR.0PA0EN 0 8-Bit Pulse Accumulator 0 Enable DLYCT 0x00A9 Delay Counter Control Register DLYCT.DLY1 1 Delay Counter Select 1 DLYCT.DLY0 0 Delay Counter Select 0 ICOVW 0x00AA Input Control Overwrite Register ICOVW.NOVW7 7 No Input Capture Overwrite 7 ICOVW.NOVW6 6 No Input Capture Overwrite 6 ICOVW.NOVW5 5 No Input Capture Overwrite 5 ICOVW.NOVW4 4 No Input Capture Overwrite 4 ICOVW.NOVW3 3 No Input Capture Overwrite 3 ICOVW.NOVW2 2 No Input Capture Overwrite 2 ICOVW.NOVW1 1 No Input Capture Overwrite 1 ICOVW.NOVW0 0 No Input Capture Overwrite 0 ICSYS 0x00AB Input Control System Control Register ICSYS.SH37 7 Share Input action of Input Capture Channels 3 and 7 ICSYS.SH26 6 Share Input action of Input Capture Channels 2 and 6 ICSYS.SH15 5 Share Input action of Input Capture Channels 1 and 5 ICSYS.SH04 4 Share Input action of Input Capture Channels 0 and 4 ICSYS.TFMOD 3 Timer Flag-setting Mode ICSYS.PACMX 2 8-Bit Pulse Accumulators Maximum Count ICSYS.BUFEN 1 IC Buffer Enable ICSYS.LATQ 0 Input Control Latch or Queue Mode Enable RESERVED00AC 0x00AC RESERVED TIMTST 0x00AD Timer Test Register TIMTST.TCBYP 1 Main Timer Divider Chain Bypass PORTT 0x00AE Port T Data Register PORTT.PT7 7 Port T Data Bit 7 PORTT.PT6 6 Port T Data Bit 6 PORTT.PT5 5 Port T Data Bit 5 PORTT.PT4 4 Port T Data Bit 4 PORTT.PT3 3 Port T Data Bit 3 PORTT.PT2 2 Port T Data Bit 2 PORTT.PT1 1 Port T Data Bit 1 PORTT.PT0 0 Port T Data Bit 0 DDRT 0x00AF Port T Data Direction Register DDRT.DDT7 7 Port T Data Direction Bit 7 DDRT.DDT6 6 Port T Data Direction Bit 6 DDRT.DDT5 5 Port T Data Direction Bit 5 DDRT.DDT4 4 Port T Data Direction Bit 4 DDRT.DDT3 3 Port T Data Direction Bit 3 DDRT.DDT2 2 Port T Data Direction Bit 2 DDRT.DDT1 1 Port T Data Direction Bit 1 DDRT.DDT0 0 Port T Data Direction Bit 0 PBCTL 0x00B0 16-Bit Pulse Accumulator B Control Register PBCTL.PBEN 6 Pulse Accumulator B System Enable PBCTL.PBOVI 1 Pulse Accumulator B Overflow Interrupt enable PBFLG 0x00B1 Pulse Accumulator B Flag Register PBFLG.PBOVF 1 Pulse Accumulator B Overflow Flag PA3H 0x00B2 8-Bit Pulse Accumulators Holding Register 3 H PA2H 0x00B3 8-Bit Pulse Accumulators Holding Register 2 H PA1H 0x00B4 8-Bit Pulse Accumulators Holding Register 1 H PA0H 0x00B5 8-Bit Pulse Accumulators Holding Register 0 H MCCNTH 0x00B6 Modulus Down-Counter Count Register H MCCNTL 0x00B7 Modulus Down-Counter Count Register L TC0HH 0x00B8 Timer Input Capture Holding Register 0 H TC0HL 0x00B9 Timer Input Capture Holding Register 0 L TC1HH 0x00BA Timer Input Capture Holding Register 1 H TC1HL 0x00BB Timer Input Capture Holding Register 1 L TC2HH 0x00BC Timer Input Capture Holding Register 2 H TC2HL 0x00BD Timer Input Capture Holding Register 2 L TC3HH 0x00BE Timer Input Capture Holding Register 3 H TC3HL 0x00BF Timer Input Capture Holding Register 3 L SC0BDH 0x00C0 SCI Baud Rate Control Register SC0BDH.BTST 7 Reserved for test function SC0BDH.BSPL 6 Reserved for test function SC0BDH.BRLD 5 Reserved for test function SC0BDH.SBR12 4 SC0BDH.SBR11 3 SC0BDH.SBR10 2 SC0BDH.SBR9 1 SC0BDH.SBR8 0 SC0BDL 0x00C1 SCI Baud Rate Control Register SC0BDL.SBR7 7 SC0BDL.SBR6 6 SC0BDL.SBR5 5 SC0BDL.SBR4 4 SC0BDL.SBR3 3 SC0BDL.SBR2 2 SC0BDL.SBR1 1 SC0BDL.SBR0 0 SC0CR1 0x00C2 SCI Control Register 1 SC0CR1.LOOPS 7 SCI LOOP Mode/Single Wire Mode Enable SC0CR1.WOMS 6 Wired-Or Mode for Serial Pins SC0CR1.RSRC 5 Receiver Source SC0CR1.M 4 Mode (select character format) SC0CR1.WAKE 3 Wake-up by Address Mark/Idle SC0CR1.ILT 2 Idle Line Type SC0CR1.PE 1 Parity Enable SC0CR1.PT 0 Parity Type SC0CR2 0x00C3 SCI Control Register 2 SC0CR2.TIE 7 Transmit Interrupt Enable SC0CR2.TCIE 6 Transmit Complete Interrupt Enable SC0CR2.RIE 5 Receiver Interrupt Enable SC0CR2.ILIE 4 Idle Line Interrupt Enable SC0CR2.TE 3 Transmitter Enable SC0CR2.RE 2 Receiver Enable SC0CR2.RWU 1 Receiver Wake-Up Control SC0CR2.SBK 0 Send Break SC0SR1 0x00C4 SCI Status Register 1 SC0SR1.TDRE 7 Transmit Data Register Empty Flag SC0SR1.TC 6 Transmit Complete Flag SC0SR1.RDRF 5 Receive Data Register Full Flag SC0SR1.IDLE 4 Idle Line Detected Flag SC0SR1.OR 3 Overrun Error Flag SC0SR1.NF 2 Noise Error Flag SC0SR1.FE 1 Framing Error Flag SC0SR1.PF 0 Parity Error Flag SC0SR2 0x00C5 SCI Status Register 2 SC0SR2.SCSWAI 7 Serial Communications Interface Stop in WAIT Mode SC0SR2.MIE 6 SC0SR2.MDL1 5 SC0SR2.MDL0 4 SC0SR2.RAF 0 Receiver Active Flag SC0DRH 0x00C6 SCI Data Register High SC0DRH.R8 7 Receive Bit 8 SC0DRH.T8 6 Transmit Bit 8 SC0DRL 0x00C7 SCI Data Register Low SC0DRL.R7_T7 7 Receive/Transmit Data Bit 7 SC0DRL.R6_T6 6 Receive/Transmit Data Bit 6 SC0DRL.R5_T5 5 Receive/Transmit Data Bit 5 SC0DRL.R4_T4 4 Receive/Transmit Data Bit 4 SC0DRL.R3_T3 3 Receive/Transmit Data Bit 3 SC0DRL.R2_T2 2 Receive/Transmit Data Bit 2 SC0DRL.R1_T1 1 Receive/Transmit Data Bit 1 SC0DRL.R0_T0 0 Receive/Transmit Data Bit 0 SC1BDH 0x00C8 SCI Baud Rate Control Register SC1BDH.BTST 7 Reserved for test function SC1BDH.BSPL 6 Reserved for test function SC1BDH.BRLD 5 Reserved for test function SC1BDH.SBR12 4 SC1BDH.SBR11 3 SC1BDH.SBR10 2 SC1BDH.SBR9 1 SC1BDH.SBR8 0 SC1BDL 0x00C9 SCI Baud Rate Control Register SC1BDL.SBR7 7 SC1BDL.SBR6 6 SC1BDL.SBR5 5 SC1BDL.SBR4 4 SC1BDL.SBR3 3 SC1BDL.SBR2 2 SC1BDL.SBR1 1 SC1BDL.SBR0 0 SC1CR1 0x00CA SCI Control Register 1 SC1CR1.LOOPS 7 SCI LOOP Mode/Single Wire Mode Enable SC1CR1.WOMS 6 Wired-Or Mode for Serial Pins SC1CR1.RSRC 5 Receiver Source SC1CR1.M 4 Mode (select character format) SC1CR1.WAKE 3 Wake-up by Address Mark/Idle SC1CR1.ILT 2 Idle Line Type SC1CR1.PE 1 Parity Enable SC1CR1.PT 0 Parity Type SC1CR2 0x00CB SCI Control Register 2 SC1CR2.TIE 7 Transmit Interrupt Enable SC1CR2.TCIE 6 Transmit Complete Interrupt Enable SC1CR2.RIE 5 Receiver Interrupt Enable SC1CR2.ILIE 4 Idle Line Interrupt Enable SC1CR2.TE 3 Transmitter Enable SC1CR2.RE 2 Receiver Enable SC1CR2.RWU 1 Receiver Wake-Up Control SC1CR2.SBK 0 Send Break SC1SR1 0x00CC SCI Status Register 1 SC1SR1.TDRE 7 Transmit Data Register Empty Flag SC1SR1.TC 6 Transmit Complete Flag SC1SR1.RDRF 5 Receive Data Register Full Flag SC1SR1.IDLE 4 Idle Line Detected Flag SC1SR1.OR 3 Overrun Error Flag SC1SR1.NF 2 Noise Error Flag SC1SR1.FE 1 Framing Error Flag SC1SR1.PF 0 Parity Error Flag SC1SR2 0x00CD SCI Status Register 2 SC1SR2.SCSWAI 7 Serial Communications Interface Stop in WAIT Mode SC1SR2.RAF 0 Receiver Active Flag SC1DRH 0x00CE SCI Data Register High SC1DRH.R8 7 Receive Bit 8 SC1DRH.T8 6 Transmit Bit 8 SC1DRL 0x00CF SCI Data Register Low SC1DRL.R7_T7 7 Receive/Transmit Data Bit 7 SC1DRL.R6_T6 6 Receive/Transmit Data Bit 6 SC1DRL.R5_T5 5 Receive/Transmit Data Bit 5 SC1DRL.R4_T4 4 Receive/Transmit Data Bit 4 SC1DRL.R3_T3 3 Receive/Transmit Data Bit 3 SC1DRL.R2_T2 2 Receive/Transmit Data Bit 2 SC1DRL.R1_T1 1 Receive/Transmit Data Bit 1 SC1DRL.R0_T0 0 Receive/Transmit Data Bit 0 SP0CR1 0x00D0 SPI Control Register 1 SP0CR1.SPIE 7 SPI Interrupt Enable SP0CR1.SPE 6 SPI System Enable SP0CR1.SWOM 5 Port S Wired-OR Mode SP0CR1.MSTR 4 SPI Master/Slave Mode Select SP0CR1.CPOL 3 SPI Clock Polarity SP0CR1.CPHA 2 Clock Phase SP0CR1.SSOE 1 Slave Select Output Enable SP0CR1.LSBF 0 SPI LSB First enable SP0CR2 0x00D1 SPI Control Register 2 SP0CR2.SPSWAI 1 Serial Interface Stop in WAIT mode SP0CR2.SPC0 0 Serial Pin Control 0 SP0BR 0x00D2 SPI Baud Rate Register SP0BR.SPR2 2 SPI Clock (SCK) Rate Select Bit 2 SP0BR.SPR1 1 SPI Clock (SCK) Rate Select Bit 1 SP0BR.SPR0 0 SPI Clock (SCK) Rate Select Bit 0 SP0SR 0x00D3 SPI Status Register SP0SR.SPIF 7 SPI Interrupt Request SP0SR.WCOL 6 Write Collision Status Flag SP0SR.MODF 4 SPI Mode Error Interrupt Status Flag RESERVED00D4 0x00D4 RESERVED SP0DR 0x00D5 SPI Data Register PORTS 0x00D6 Port S Data Register PORTS.PS7 7 Port S Data Bit 7 PORTS.PS6 6 Port S Data Bit 6 PORTS.PS5 5 Port S Data Bit 5 PORTS.PS4 4 Port S Data Bit 4 PORTS.PS3 3 Port S Data Bit 3 PORTS.PS2 2 Port S Data Bit 2 PORTS.PS1 1 Port S Data Bit 1 PORTS.PS0 0 Port S Data Bit 0 DDRS 0x00D7 Port S Data Direction Register DDRS.DDS7 7 Port S Data Direction Bit 7 DDRS.DDS6 6 Port S Data Direction Bit 6 DDRS.DDS5 5 Port S Data Direction Bit 5 DDRS.DDS4 4 Port S Data Direction Bit 4 DDRS.DDS3 3 Port S Data Direction Bit 3 DDRS.DDS2 2 Port S Data Direction Bit 2 DDRS.DDS1 1 Port S Data Direction Bit 1 DDRS.DDS0 0 Port S Data Direction Bit 0 RESERVED00D8 0x00D8 RESERVED PURDS 0x00D9 Pull-Up Register for Port S PURDS.RDPS2 6 Reduce Drive of Port S[7:4] PURDS.RDPS1 5 Reduce Drive of Port S[3:2] PURDS.RDPS0 4 Reduce Drive of Port S[1:0] PURDS.PUPS2 2 Pull-up Port S[7:4] Enable PURDS.PUPS1 1 Pull-up Port S[3:2] Enable PURDS.PUPS0 0 Pull-up Port S[1:0] Enable RESERVED00DA 0x00DA RESERVED RESERVED00DB 0x00DB RESERVED RESERVED00DC 0x00DC RESERVED RESERVED00DD 0x00DD RESERVED RESERVED00DE 0x00DE RESERVED RESERVED00DF 0x00DF RESERVED RESERVED00E0 0x00E0 RESERVED RESERVED00E1 0x00E1 RESERVED RESERVED00E2 0x00E2 RESERVED RESERVED00E3 0x00E3 RESERVED RESERVED00E4 0x00E4 RESERVED RESERVED00E5 0x00E5 RESERVED RESERVED00E6 0x00E6 RESERVED RESERVED00E7 0x00E7 RESERVED RESERVED00E8 0x00E8 RESERVED RESERVED00E9 0x00E9 RESERVED RESERVED00EA 0x00EA RESERVED RESERVED00EB 0x00EB RESERVED RESERVED00EC 0x00EC RESERVED RESERVED00ED 0x00ED RESERVED RESERVED00EE 0x00EE RESERVED RESERVED00EF 0x00EF RESERVED EEMCR 0x00F0 EEPROM Module Configuration EEMCR.NOBDML 7 Background Debug Mode Lockout Disable EEMCR.NOSHB 6 SHADOW Byte Disable EEMCR.EESWAI 2 EEPROM Stops in Wait Mode EEMCR.PROTLCK 1 Block Protect Write Lock EEMCR.EERC 0 EEPROM Charge Pump Clock EEPROT 0x00F1 EEPROM Block Protect EEPROT.SHPROT 7 SHADOW Byte Protection EEPROT.BPROT4 4 EEPROM Block Protection 4 EEPROT.BPROT3 3 EEPROM Block Protection 3 EEPROT.BPROT2 2 EEPROM Block Protection 2 EEPROT.BPROT1 1 EEPROM Block Protection 1 EEPROT.BPROT0 0 EEPROM Block Protection 0 RESERVED00F2 0x00F2 RESERVED EEPROG 0x00F3 EEPROM Control EEPROG.BULKP 7 Bulk Erase Protection EEPROG.BYTE 4 Byte and Aligned Word Erase EEPROG.ROW 3 Row or Bulk Erase (when BYTE = 0) EEPROG.ERASE 2 Erase Control EEPROG.EELAT 1 EEPROM Latch Control EEPROG.EEPGM 0 Program and Erase Enable RESERVED00F4 0x00F4 RESERVED RESERVED00F5 0x00F5 RESERVED RESERVED00F6 0x00F6 RESERVED RESERVED00F7 0x00F7 RESERVED RESERVED00F8 0x00F8 RESERVED RESERVED00F9 0x00F9 RESERVED RESERVED00FA 0x00FA RESERVED RESERVED00FB 0x00FB RESERVED RESERVED00FC 0x00FC RESERVED RESERVED00FD 0x00FD RESERVED RESERVED00FE 0x00FE RESERVED RESERVED00FF 0x00FF RESERVED CMCR0 0x0100 msCAN12 Module Control Register 0 CMCR0.CSWAI 5 CAN Stops in Wait Mode CMCR0.SYNCH 4 Synchronized Status CMCR0.TLNKEN 3 Timer Enable CMCR0.SLPAK 2 SLEEP Mode Acknowledge CMCR0.SLPRQ 1 SLEEP request CMCR0.SFTRES 0 SOFT_RESET CMCR1 0x0101 msCAN12 Module Control Register 1 CMCR1.LOOPB 2 Loop Back Self Test Mode CMCR1.WUPM 1 Wake-Up Mode CMCR1.CLKSRC 0 msCAN12 Clock Source CBTR0 0x0102 msCAN12 Bus Timing Register 0 CBTR0.SJW1 7 Synchronization Jump Width 1 CBTR0.SJW0 6 Synchronization Jump Width 0 CBTR0.BRP5 5 Baud Rate Prescaler 5 CBTR0.BRP4 4 Baud Rate Prescaler 4 CBTR0.BRP3 3 Baud Rate Prescaler 3 CBTR0.BRP2 2 Baud Rate Prescaler 2 CBTR0.BRP1 1 Baud Rate Prescaler 1 CBTR0.BRP0 0 Baud Rate Prescaler 0 CBTR1 0x0103 msCAN12 Bus Timing Register 1 CBTR1.SAMP 7 Sampling CBTR1.TSEG22 6 Time Segment 22 CBTR1.TSEG21 5 Time Segment 21 CBTR1.TSEG20 4 Time Segment 20 CBTR1.TSEG13 3 Time Segment 13 CBTR1.TSEG12 2 Time Segment 12 CBTR1.TSEG11 1 Time Segment 11 CBTR1.TSEG10 0 Time Segment 10 CRFLG 0x0104 msCAN12 Receiver Flag Register CRFLG.WUPIF 7 Wake-up Interrupt Flag CRFLG.RWRNIF 6 Receiver Warning Interrupt Flag CRFLG.TWRNIF 5 Transmitter Warning Interrupt Flag CRFLG.RERRIF 4 Receiver Error Passive Interrupt Flag CRFLG.TERRIF 3 Transmitter Error Passive Interrupt Flag CRFLG.BOFFIF 2 BUSOFF Interrupt Flag CRFLG.OVRIF 1 Overrun Interrupt Flag CRFLG.RXF 0 Receive Buffer Full CRIER 0x0105 msCAN12 Receiver Interrupt Enable Register CRIER.WUPIE 7 Wake-up Interrupt Enable CRIER.RWRNIE 6 Receiver Warning Interrupt Enable CRIER.TWRNIE 5 Transmitter Warning Interrupt Enable CRIER.RERRIE 4 Receiver Error Passive Interrupt Enable CRIER.TERRIE 3 Transmitter Error Passive Interrupt Enable CRIER.BOFFIE 2 BUSOFF Interrupt Enable CRIER.OVRIE 1 Overrun Interrupt Enable CRIER.RXFIE 0 Receiver Full Interrupt Enable CTFLG 0x0106 msCAN12 Transmitter Flag Register CTFLG.ABTAK2 6 Abort Acknowledge 2 CTFLG.ABTAK1 5 Abort Acknowledge 1 CTFLG.ABTAK0 4 Abort Acknowledge 0 CTFLG.TXE2 2 Transmitter Buffer Empty 2 CTFLG.TXE1 1 Transmitter Buffer Empty 1 CTFLG.TXE0 0 Transmitter Buffer Empty 0 CTCR 0x0107 msCAN12 Transmitter Control Register CTCR.ABTRQ2 6 Abort Request 2 CTCR.ABTRQ1 5 Abort Request 1 CTCR.ABTRQ0 4 Abort Request 0 CTCR.TXEIE2 2 Transmitter Empty Interrupt Enable 2 CTCR.TXEIE1 1 Transmitter Empty Interrupt Enable 1 CTCR.TXEIE0 0 Transmitter Empty Interrupt Enable 0 CIDAC 0x0108 msCAN12 Identifier Acceptance Control Register CIDAC.IDAM1 5 Identifier Acceptance Mode 1 CIDAC.IDAM0 4 Identifier Acceptance Mode 0 CIDAC.IDHIT2 2 Identifier Acceptance Hit Indicator 2 CIDAC.IDHIT1 1 Identifier Acceptance Hit Indicator 1 CIDAC.IDHIT0 0 Identifier Acceptance Hit Indicator 0 RESERVED0109 0x0109 RESERVED RESERVED010A 0x010A RESERVED RESERVED010B 0x010B RESERVED RESERVED010C 0x010C RESERVED RESERVED010D 0x010D RESERVED CRXERR 0x010E msCAN12 Receive Error Counter CRXERR.RXERR7 7 CRXERR.RXERR6 6 CRXERR.RXERR5 5 CRXERR.RXERR4 4 CRXERR.RXERR3 3 CRXERR.RXERR2 2 CRXERR.RXERR1 1 CRXERR.RXERR0 0 CTXERR 0x010F msCAN12 Transmit Error Counter CTXERR.TXERR7 7 CTXERR.TXERR6 6 CTXERR.TXERR5 5 CTXERR.TXERR4 4 CTXERR.TXERR3 3 CTXERR.TXERR2 2 CTXERR.TXERR1 1 CTXERR.TXERR0 0 CIDAR0 0x0110 msCAN12 Identifier Acceptance Register 0 CIDAR0.AC7 7 Acceptance Code Bit 7 CIDAR0.AC6 6 Acceptance Code Bit 6 CIDAR0.AC5 5 Acceptance Code Bit 5 CIDAR0.AC4 4 Acceptance Code Bit 4 CIDAR0.AC3 3 Acceptance Code Bit 3 CIDAR0.AC2 2 Acceptance Code Bit 2 CIDAR0.AC1 1 Acceptance Code Bit 1 CIDAR0.AC0 0 Acceptance Code Bit 0 CIDAR1 0x0111 msCAN12 Identifier Acceptance Register 1 CIDAR1.AC7 7 Acceptance Code Bit 7 CIDAR1.AC6 6 Acceptance Code Bit 6 CIDAR1.AC5 5 Acceptance Code Bit 5 CIDAR1.AC4 4 Acceptance Code Bit 4 CIDAR1.AC3 3 Acceptance Code Bit 3 CIDAR1.AC2 2 Acceptance Code Bit 2 CIDAR1.AC1 1 Acceptance Code Bit 1 CIDAR1.AC0 0 Acceptance Code Bit 0 CIDAR2 0x0112 msCAN12 Identifier Acceptance Register 2 CIDAR2.AC7 7 Acceptance Code Bit 7 CIDAR2.AC6 6 Acceptance Code Bit 6 CIDAR2.AC5 5 Acceptance Code Bit 5 CIDAR2.AC4 4 Acceptance Code Bit 4 CIDAR2.AC3 3 Acceptance Code Bit 3 CIDAR2.AC2 2 Acceptance Code Bit 2 CIDAR2.AC1 1 Acceptance Code Bit 1 CIDAR2.AC0 0 Acceptance Code Bit 0 CIDAR3 0x0113 msCAN12 Identifier Acceptance Register 3 CIDAR3.AC7 7 Acceptance Code Bit 7 CIDAR3.AC6 6 Acceptance Code Bit 6 CIDAR3.AC5 5 Acceptance Code Bit 5 CIDAR3.AC4 4 Acceptance Code Bit 4 CIDAR3.AC3 3 Acceptance Code Bit 3 CIDAR3.AC2 2 Acceptance Code Bit 2 CIDAR3.AC1 1 Acceptance Code Bit 1 CIDAR3.AC0 0 Acceptance Code Bit 0 CIDMR0 0x0114 msCAN12 Identifier Mask Register 0 CIDMR0.AM7 7 Acceptance Mask Bit 7 CIDMR0.AM6 6 Acceptance Mask Bit 6 CIDMR0.AM5 5 Acceptance Mask Bit 5 CIDMR0.AM4 4 Acceptance Mask Bit 4 CIDMR0.AM3 3 Acceptance Mask Bit 3 CIDMR0.AM2 2 Acceptance Mask Bit 2 CIDMR0.AM1 1 Acceptance Mask Bit 1 CIDMR0.AM0 0 Acceptance Mask Bit 0 CIDMR1 0x0115 msCAN12 Identifier Mask Register 1 CIDMR1.AM7 7 Acceptance Mask Bit 7 CIDMR1.AM6 6 Acceptance Mask Bit 6 CIDMR1.AM5 5 Acceptance Mask Bit 5 CIDMR1.AM4 4 Acceptance Mask Bit 4 CIDMR1.AM3 3 Acceptance Mask Bit 3 CIDMR1.AM2 2 Acceptance Mask Bit 2 CIDMR1.AM1 1 Acceptance Mask Bit 1 CIDMR1.AM0 0 Acceptance Mask Bit 0 CIDMR2 0x0116 msCAN12 Identifier Mask Register 2 CIDMR2.AM7 7 Acceptance Mask Bit 7 CIDMR2.AM6 6 Acceptance Mask Bit 6 CIDMR2.AM5 5 Acceptance Mask Bit 5 CIDMR2.AM4 4 Acceptance Mask Bit 4 CIDMR2.AM3 3 Acceptance Mask Bit 3 CIDMR2.AM2 2 Acceptance Mask Bit 2 CIDMR2.AM1 1 Acceptance Mask Bit 1 CIDMR2.AM0 0 Acceptance Mask Bit 0 CIDMR3 0x0117 msCAN12 Identifier Mask Register 3 CIDMR3.AM7 7 Acceptance Mask Bit 7 CIDMR3.AM6 6 Acceptance Mask Bit 6 CIDMR3.AM5 5 Acceptance Mask Bit 5 CIDMR3.AM4 4 Acceptance Mask Bit 4 CIDMR3.AM3 3 Acceptance Mask Bit 3 CIDMR3.AM2 2 Acceptance Mask Bit 2 CIDMR3.AM1 1 Acceptance Mask Bit 1 CIDMR3.AM0 0 Acceptance Mask Bit 0 CIDAR4 0x0118 msCAN12 Identifier Acceptance Register 4 CIDAR4.AC7 7 Acceptance Code Bit 7 CIDAR4.AC6 6 Acceptance Code Bit 6 CIDAR4.AC5 5 Acceptance Code Bit 5 CIDAR4.AC4 4 Acceptance Code Bit 4 CIDAR4.AC3 3 Acceptance Code Bit 3 CIDAR4.AC2 2 Acceptance Code Bit 2 CIDAR4.AC1 1 Acceptance Code Bit 1 CIDAR4.AC0 0 Acceptance Code Bit 0 CIDAR5 0x0119 msCAN12 Identifier Acceptance Register 5 CIDAR5.AC7 7 Acceptance Code Bit 7 CIDAR5.AC6 6 Acceptance Code Bit 6 CIDAR5.AC5 5 Acceptance Code Bit 5 CIDAR5.AC4 4 Acceptance Code Bit 4 CIDAR5.AC3 3 Acceptance Code Bit 3 CIDAR5.AC2 2 Acceptance Code Bit 2 CIDAR5.AC1 1 Acceptance Code Bit 1 CIDAR5.AC0 0 Acceptance Code Bit 0 CIDAR6 0x011A msCAN12 Identifier Acceptance Register 6 CIDAR6.AC7 7 Acceptance Code Bit 7 CIDAR6.AC6 6 Acceptance Code Bit 6 CIDAR6.AC5 5 Acceptance Code Bit 5 CIDAR6.AC4 4 Acceptance Code Bit 4 CIDAR6.AC3 3 Acceptance Code Bit 3 CIDAR6.AC2 2 Acceptance Code Bit 2 CIDAR6.AC1 1 Acceptance Code Bit 1 CIDAR6.AC0 0 Acceptance Code Bit 0 CIDAR7 0x011B msCAN12 Identifier Acceptance Register 7 CIDAR7.AC7 7 Acceptance Code Bit 7 CIDAR7.AC6 6 Acceptance Code Bit 6 CIDAR7.AC5 5 Acceptance Code Bit 5 CIDAR7.AC4 4 Acceptance Code Bit 4 CIDAR7.AC3 3 Acceptance Code Bit 3 CIDAR7.AC2 2 Acceptance Code Bit 2 CIDAR7.AC1 1 Acceptance Code Bit 1 CIDAR7.AC0 0 Acceptance Code Bit 0 CIDMR4 0x011C msCAN12 Identifier Mask Register 4 CIDMR4.AM7 7 Acceptance Mask Bit 7 CIDMR4.AM6 6 Acceptance Mask Bit 6 CIDMR4.AM5 5 Acceptance Mask Bit 5 CIDMR4.AM4 4 Acceptance Mask Bit 4 CIDMR4.AM3 3 Acceptance Mask Bit 3 CIDMR4.AM2 2 Acceptance Mask Bit 2 CIDMR4.AM1 1 Acceptance Mask Bit 1 CIDMR4.AM0 0 Acceptance Mask Bit 0 CIDMR5 0x011D msCAN12 Identifier Mask Register 5 CIDMR5.AM7 7 Acceptance Mask Bit 7 CIDMR5.AM6 6 Acceptance Mask Bit 6 CIDMR5.AM5 5 Acceptance Mask Bit 5 CIDMR5.AM4 4 Acceptance Mask Bit 4 CIDMR5.AM3 3 Acceptance Mask Bit 3 CIDMR5.AM2 2 Acceptance Mask Bit 2 CIDMR5.AM1 1 Acceptance Mask Bit 1 CIDMR5.AM0 0 Acceptance Mask Bit 0 CIDMR6 0x011E msCAN12 Identifier Mask Register 6 CIDMR6.AM7 7 Acceptance Mask Bit 7 CIDMR6.AM6 6 Acceptance Mask Bit 6 CIDMR6.AM5 5 Acceptance Mask Bit 5 CIDMR6.AM4 4 Acceptance Mask Bit 4 CIDMR6.AM3 3 Acceptance Mask Bit 3 CIDMR6.AM2 2 Acceptance Mask Bit 2 CIDMR6.AM1 1 Acceptance Mask Bit 1 CIDMR6.AM0 0 Acceptance Mask Bit 0 CIDMR7 0x011F msCAN12 Identifier Mask Register 7 CIDMR7.AM7 7 Acceptance Mask Bit 7 CIDMR7.AM6 6 Acceptance Mask Bit 6 CIDMR7.AM5 5 Acceptance Mask Bit 5 CIDMR7.AM4 4 Acceptance Mask Bit 4 CIDMR7.AM3 3 Acceptance Mask Bit 3 CIDMR7.AM2 2 Acceptance Mask Bit 2 CIDMR7.AM1 1 Acceptance Mask Bit 1 CIDMR7.AM0 0 Acceptance Mask Bit 0 RESERVED0120 0x0120 RESERVED RESERVED0121 0x0121 RESERVED RESERVED0122 0x0122 RESERVED RESERVED0123 0x0123 RESERVED RESERVED0124 0x0124 RESERVED RESERVED0125 0x0125 RESERVED RESERVED0126 0x0126 RESERVED RESERVED0127 0x0127 RESERVED RESERVED0128 0x0128 RESERVED RESERVED0129 0x0129 RESERVED RESERVED012A 0x012A RESERVED RESERVED012B 0x012B RESERVED RESERVED012C 0x012C RESERVED RESERVED012D 0x012D RESERVED RESERVED012E 0x012E RESERVED RESERVED012F 0x012F RESERVED RESERVED0130 0x0130 RESERVED RESERVED0131 0x0131 RESERVED RESERVED0132 0x0132 RESERVED RESERVED0133 0x0133 RESERVED RESERVED0134 0x0134 RESERVED RESERVED0135 0x0135 RESERVED RESERVED0136 0x0136 RESERVED RESERVED0137 0x0137 RESERVED RESERVED0138 0x0138 RESERVED RESERVED0139 0x0139 RESERVED RESERVED013A 0x013A RESERVED RESERVED013B 0x013B RESERVED RESERVED013C 0x013C RESERVED PCTLCAN 0x013D msCAN12 Port CAN Control Register PCTLCAN.PUPCAN 1 Pull-Up Enable Port CAN PCTLCAN.RDPCAN 0 Reduced Drive Port CAN PORTCAN 0x013E msCAN12 Port CAN Data Register PORTCAN.PCAN7 7 Port CAN Data Bit 7 (not available in 80QFP) PORTCAN.PCAN6 6 Port CAN Data Bit 6 (not available in 80QFP) PORTCAN.PCAN5 5 Port CAN Data Bit 5 (not available in 80QFP) PORTCAN.PCAN4 4 Port CAN Data Bit 4 (not available in 80QFP) PORTCAN.PCAN3 3 Port CAN Data Bit 3 (not available in 80QFP) PORTCAN.PCAN2 2 Port CAN Data Bit 2 (not available in 80QFP) PORTCAN.TxCAN 1 PORTCAN.RxCAN 0 DDRCAN 0x013F msCAN12 Port CAN Data Direction Register DDRCAN.DDCAN7 7 Data Direction Port CAN Bit 7 DDRCAN.DDCAN6 6 Data Direction Port CAN Bit 6 DDRCAN.DDCAN5 5 Data Direction Port CAN Bit 5 DDRCAN.DDCAN4 4 Data Direction Port CAN Bit 4 DDRCAN.DDCAN3 3 Data Direction Port CAN Bit 3 DDRCAN.DDCAN2 2 Data Direction Port CAN Bit 2 ATD1CTL2 0x01E2 ATD1 Control Register 2 ATD1CTL2.ADPU 7 ATD Disable ATD1CTL2.AFFC 6 ATD Fast Flag Clear All ATD1CTL2.AWAI 5 ATD Wait Mode ATD1CTL2.ASCIE 1 ATD Sequence Complete Interrupt Enable ATD1CTL2.ASCIF 0 ATD Sequence Complete Interrupt Flag ATD1CTL3 0x01E3 ATD1 Control Register 3 ATD1CTL3.FRZ1 1 Background Debug (Freeze) Enable 1 ATD1CTL3.FRZ0 0 Background Debug (Freeze) Enable 0 ATD1CTL4 0x01E4 ATD1 Control Register 4 ATD1CTL4.S10BM 7 10 bit Mode ATD1CTL4.SMP1 6 Select Sample Time 1 ATD1CTL4.SMP0 5 Select Sample Time 0 ATD1CTL4.PRS4 4 Select Divide-By Factor for ATD P-Clock Prescaler 4 ATD1CTL4.PRS3 3 Select Divide-By Factor for ATD P-Clock Prescaler 3 ATD1CTL4.PRS2 2 Select Divide-By Factor for ATD P-Clock Prescaler 2 ATD1CTL4.PRS1 1 Select Divide-By Factor for ATD P-Clock Prescaler 1 ATD1CTL4.PRS0 0 Select Divide-By Factor for ATD P-Clock Prescaler 0 ATD1CTL5 0x01E5 ATD1 Control Register 5 ATD1CTL5.S8CM 6 Select 8 Channel Mode ATD1CTL5.SCAN 5 Enable Continuous Channel Scan ATD1CTL5.MULT 4 Enable Multichannel Conversion ATD1CTL5.CD 3 Channel D Select for Conversion ATD1CTL5.CC 2 Channel C Select for Conversion ATD1CTL5.CB 1 Channel B Select for Conversion ATD1CTL5.CA 0 Channel A Select for Conversion ATD1STAT0 0x01E6 ATD1 Status Register 0 ATD1STAT0.SCF 7 Sequence Complete Flag ATD1STAT0.CC2 2 Conversion Counter 2 for Current Sequence of Four or Eight Conversions ATD1STAT0.CC1 1 Conversion Counter 1 for Current Sequence of Four or Eight Conversions ATD1STAT0.CC0 0 Conversion Counter 0 for Current Sequence of Four or Eight Conversions ATD1STAT1 0x01E7 ATD Status Register 1 ATD1STAT1.CCF7 7 Conversion Complete Flag 7 ATD1STAT1.CCF6 6 Conversion Complete Flag 6 ATD1STAT1.CCF5 5 Conversion Complete Flag 5 ATD1STAT1.CCF4 4 Conversion Complete Flag 4 ATD1STAT1.CCF3 3 Conversion Complete Flag 3 ATD1STAT1.CCF2 2 Conversion Complete Flag 2 ATD1STAT1.CCF1 1 Conversion Complete Flag 1 ATD1STAT1.CCF0 0 Conversion Complete Flag 0 ATD1TESTH 0x01E8 ATD1 Test Register H ATD1TESTH.SAR9 7 SAR Data 9 ATD1TESTH.SAR8 6 SAR Data 8 ATD1TESTH.SAR7 5 SAR Data 7 ATD1TESTH.SAR6 4 SAR Data 6 ATD1TESTH.SAR5 3 SAR Data 5 ATD1TESTH.SAR4 2 SAR Data 4 ATD1TESTH.SAR3 1 SAR Data 3 ATD1TESTH.SAR2 0 SAR Data 2 ATD1TESTL 0x01E9 ATD1 Test Register L ATD1TESTL.SAR1 7 SAR Data 1 ATD1TESTL.SAR0 6 SAR Data 0 ATD1TESTL.RST 5 Module Reset Bit ATD1TESTL.TSTOUT 4 Multiplex Output of TST ATD1TESTL.TST3 3 Test Bit 3 ATD1TESTL.TST2 2 Test Bit 2 ATD1TESTL.TST1 1 Test Bit 1 ATD1TESTL.TST0 0 Test Bit 0 RESERVED01EA 0x01EA RESERVED RESERVED01EB 0x01EB RESERVED RESERVED01EC 0x01EC RESERVED RESERVED01ED 0x01ED RESERVED RESERVED01EE 0x01EE RESERVED PORTAD1 0x01EF Port AD1 Data Input Register PORTAD1.PAD17 7 Port AD1 Data Input Bit 7 PORTAD1.PAD16 6 Port AD1 Data Input Bit 6 PORTAD1.PAD15 5 Port AD1 Data Input Bit 5 PORTAD1.PAD14 4 Port AD1 Data Input Bit 4 PORTAD1.PAD13 3 Port AD1 Data Input Bit 3 PORTAD1.PAD12 2 Port AD1 Data Input Bit 2 PORTAD1.PAD11 1 Port AD1 Data Input Bit 1 PORTAD1.PAD10 0 Port AD1 Data Input Bit 0 ADR10H 0x01F0 A/D Conversion Result Register High 0 ADR10L 0x01F1 A/D Conversion Result Register Low 0 ADR11H 0x01F2 A/D Conversion Result Register High 1 ADR11L 0x01F3 A/D Conversion Result Register Low 1 ADR12H 0x01F4 A/D Conversion Result Register High 2 ADR12L 0x01F5 A/D Conversion Result Register Low 2 ADR13H 0x01F6 A/D Conversion Result Register High 3 ADR13L 0x01F7 A/D Conversion Result Register Low 3 ADR14H 0x01F8 A/D Conversion Result Register High 4 ADR14L 0x01F9 A/D Conversion Result Register Low 4 ADR15H 0x01FA A/D Conversion Result Register High 5 ADR15L 0x01FB A/D Conversion Result Register Low 5 ADR16H 0x01FC A/D Conversion Result Register High 6 ADR16L 0x01FD A/D Conversion Result Register Low 6 ADR17H 0x01FE A/D Conversion Result Register High 7 ADR17L 0x01FF A/D Conversion Result Register Low 7 .68HC912DG128 ; http://e-www.motorola.com/brdata/PDFDB/docs/MC68HC912DG128.pdf ; MC68HC912DG128_D.pdf ; MEMORY MAP area DATA FSR_0 0x0000:0x0140 area DATA RxFG0 0x0140:0x0150 FOREGROUND RECEIVE BUFFER 0 area DATA Tx00 0x0150:0x0160 TRANSMIT BUFFER 00 area DATA Tx01 0x0160:0x0170 TRANSMIT BUFFER 01 area DATA Tx02 0x0170:0x0180 TRANSMIT BUFFER 02 area BSS RESERVED 0x0180:0x01E2 area DATA FSR_1 0x01E2:0x0200 area BSS RESERVED 0x0200:0x0300 area DATA FSR_2 0x0300:0x0340 area DATA RxFG1 0x0340:0x0350 FOREGROUND RECEIVE BUFFER 1 area DATA Tx10 0x0350:0x0360 TRANSMIT BUFFER 10 area DATA Tx11 0x0360:0x0370 TRANSMIT BUFFER 11 area DATA Tx12 0x0370:0x0380 TRANSMIT BUFFER 12 area BSS RESERVED 0x0380:0x0800 area DATA EEPROM 0x0800:0x1000 area BSS RESERVED 0x1000:0x2000 area DATA RAM 0x2000:0x4000 area DATA FLASH_EEPROM_1 0x4000:0x8000 16K Fixed Flash EEPROM area DATA FLASH_EEPROM_2 0x8000:0xA000 16K Page Window Eight 16K Flash EEPROM pages area DATA PROT_BOOT_1 0xA000:0xC000 Protected BOOT at odd programing pages area DATA FLASH_EEPROM_3 0xC000:0xE000 16K Fixed Flash EEPROM area DATA PROT_BOOT_2 0xE000:0xFF00 Protected BOOT area DATA USER_VEC 0xFF00:0x10000 ; Interrupt and reset vector assignments interrupt __RESET 0xFFFE Reset interrupt _COPCTL 0xFFFC Clock monitor fail reset interrupt COP_F_R 0xFFFA COP failure reset interrupt UIT 0xFFF8 Unimplemented instruction trap interrupt SWI 0xFFF6 SWI interrupt XIRQ 0xFFF4 XIRQ interrupt INTCR_IRQEN 0xFFF2 IRQ interrupt RTICTL_RTIE 0xFFF0 Real time interrupt interrupt TMSK1_C0I 0xFFEE Timer channel 0 interrupt TMSK1_C1I 0xFFEC Timer channel 1 interrupt TMSK1_C2I 0xFFEA Timer channel 2 interrupt TMSK1_C3I 0xFFE8 Timer channel 3 interrupt TMSK1_C4I 0xFFE6 Timer channel 4 interrupt TMSK1_C5I 0xFFE4 Timer channel 5 interrupt TMSK1_C6I 0xFFE2 Timer channel 6 interrupt TMSK1_C7I 0xFFE0 Timer channel 7 interrupt TMSK2_TOI 0xFFDE Timer overflow interrupt PACTL_PAOVI 0xFFDC Pulse accumulator overflow interrupt PACTL_PAI 0xFFDA Pulse accumulator input edge interrupt SP0CR1_SPIE 0xFFD8 SPI serial transfer complete interrupt _SC0CR2 0xFFD6 SCI 0 interrupt _SC1CR2 0xFFD4 SCI 1 interrupt ATDxCTL2_ASCIE 0xFFD2 ATD0 or ATD1 interrupt C0RIER_WUPIE 0xFFD0 MSCAN 0 wake-up interrupt KWIEJ_KWIEH 0xFFCE Key wake-up J or H interrupt MCCTL_MCZI 0xFFCC Modulus down counter underflow interrupt PBCTL_PBOVI 0xFFCA Pulse Accumulator B Overflow interrupt C0RIER 0xFFC8 MSCAN 0 errors interrupt C0RIER_RXFIE 0xFFC6 MSCAN 0 receive interrupt C0TCR_TXEIE 0xFFC4 MSCAN 0 transmit interrupt PLLCR_LOCKIE_LHIE 0xFFC2 CGM lock and limp home interrupt IBCR_IBIE 0xFFC0 IIC Bus interrupt C1RIER_WUPIE 0xFFBE MSCAN 1 wake-up interrupt C1RIER 0xFFBC MSCAN 1 errors interrupt C1RIER_RXFIE 0xFFBA MSCAN 1 receive interrupt C1TCR_TXEIE 0xFFB8 MSCAN 1 transmit ; INPUT/ OUTPUT PORTS PORTA 0x0000 Port A Data Register PORTA.PA7 7 Port A Data Bit 7 PORTA.PA6 6 Port A Data Bit 6 PORTA.PA5 5 Port A Data Bit 5 PORTA.PA4 4 Port A Data Bit 4 PORTA.PA3 3 Port A Data Bit 3 PORTA.PA2 2 Port A Data Bit 2 PORTA.PA1 1 Port A Data Bit 1 PORTA.PA0 0 Port A Data Bit 0 PORTB 0x0001 Port B Data Register PORTB.PB7 7 Port B Data Bit 7 PORTB.PB6 6 Port B Data Bit 6 PORTB.PB5 5 Port B Data Bit 5 PORTB.PB4 4 Port B Data Bit 4 PORTB.PB3 3 Port B Data Bit 3 PORTB.PB2 2 Port B Data Bit 2 PORTB.PB1 1 Port B Data Bit 1 PORTB.PB0 0 Port B Data Bit 0 DDRA 0x0002 Port A Data Direction Register DDRA.DDA7 7 Port A Data Direction Bit 7 DDRA.DDA6 6 Port A Data Direction Bit 6 DDRA.DDA5 5 Port A Data Direction Bit 5 DDRA.DDA4 4 Port A Data Direction Bit 4 DDRA.DDA3 3 Port A Data Direction Bit 3 DDRA.DDA2 2 Port A Data Direction Bit 2 DDRA.DDA1 1 Port A Data Direction Bit 1 DDRA.DDA0 0 Port A Data Direction Bit 0 DDRB 0x0003 Port B Data Direction Register DDRB.DDB7 7 Port B Data Direction Bit 7 DDRB.DDB6 6 Port B Data Direction Bit 6 DDRB.DDB5 5 Port B Data Direction Bit 5 DDRB.DDB4 4 Port B Data Direction Bit 4 DDRB.DDB3 3 Port B Data Direction Bit 3 DDRB.DDB2 2 Port B Data Direction Bit 2 DDRB.DDB1 1 Port B Data Direction Bit 1 DDRB.DDB0 0 Port B Data Direction Bit 0 RESERVED0004 0x0004 RESERVED RESERVED0005 0x0005 RESERVED RESERVED0006 0x0006 RESERVED RESERVED0007 0x0007 RESERVED PORTE 0x0008 Port E Data Register PORTE.PE7 7 Port E Data Bit 7 PORTE.PE6 6 Port E Data Bit 6 PORTE.PE5 5 Port E Data Bit 5 PORTE.PE4 4 Port E Data Bit 4 PORTE.PE3 3 Port E Data Bit 3 PORTE.PE2 2 Port E Data Bit 2 PORTE.PE1 1 Port E Data Bit 1 PORTE.PE0 0 Port E Data Bit 0 DDRE 0x0009 Port E Data Direction Register DDRE.DDE7 7 Port E Data Direction Bit 7 DDRE.DDE6 6 Port E Data Direction Bit 6 DDRE.DDE5 5 Port E Data Direction Bit 5 DDRE.DDE4 4 Port E Data Direction Bit 4 DDRE.DDE3 3 Port E Data Direction Bit 3 DDRE.DDE2 2 Port E Data Direction Bit 2 PEAR 0x000A Port E Assignment Register PEAR.NDBE 7 No Data Bus Enable PEAR.CGMTE 6 Clock Generator Module Testing Enable PEAR.PIPOE 5 Pipe Status Signal Output Enable PEAR.NECLK 4 No External E Clock PEAR.LSTRE 3 Low Strobe (LSTRB) Enable PEAR.RDWE 2 Read/Write Enable PEAR.CALE 1 Calibration Reference Enable PEAR.DBENE 0 DBE or Inverted E Clock on PE7 MODE 0x000B Mode Register MODE.SMODN 7 Mode Select Special MODE.MODB 6 Mode Select B MODE.MODA 5 Mode Select A MODE.ESTR 4 E Clock Stretch Enable MODE.IVIS 3 Internal Visibility MODE.EBSWAI 2 External Bus Module Stop in Wait Control MODE.EMK 1 Emulate Port K MODE.EME 0 PUCR 0x000C Pull-Up Control Register PUCR.PUPK 7 Pull-Up Port K Enable PUCR.PUPJ 6 Pull-Up or Pull-Down Port J Enable PUCR.PUPH 5 Pull-Up or Pull-Down Port H Enable PUCR.PUPE 4 Pull-Up Port E Enable PUCR.PUPB 1 Pull-Up Port B Enable PUCR.PUPA 0 Pull-Up Port A Enable RDRIV 0x000D Reduced Drive of I/O Lines RDRIV.RDPK 7 Reduced Drive of Port K RDRIV.RDPJ 6 Reduced Drive of Port J RDRIV.RDPH 5 Reduced Drive of Port H RDRIV.RDPE 4 Reduced Drive of Port E RDRIV.RDPB 1 Reduced Drive of Port B RDRIV.RDPA 0 Reduced Drive of Port A RESERVED000E 0x000E RESERVED RESERVED000F 0x000F RESERVED INITRM 0x0010 Initialization of Internal RAM Position Register INITRM.RAM15 7 Internal RAM map position 15 INITRM.RAM14 6 Internal RAM map position 14 INITRM.RAM13 5 Internal RAM map position 13 INITRG 0x0011 Initialization of Internal Register Position Register INITRG.REG15 7 Internal register map position 15 INITRG.REG14 6 Internal register map position 14 INITRG.REG13 5 Internal register map position 13 INITRG.REG12 4 Internal register map position 12 INITRG.REG11 3 Internal register map position 11 INITRG.MMSWAI 0 Memory Mapping Interface Stop in Wait Control INITEE 0x0012 Initialization of Internal EEPROM Position Register INITEE.EE15 7 Internal EEPROM map position 15 INITEE.EE14 6 Internal EEPROM map position 14 INITEE.EE13 5 Internal EEPROM map position 13 INITEE.EE12 4 Internal EEPROM map position 12 INITEE.EEON 0 internal EEPROM On (Enabled) MISC 0x0013 Miscellaneous Mapping Control Register MISC.ROMTST 7 FLASH EEPROM Test mode MISC.NDRF 6 Narrow Data Bus for Register-Following Map Space MISC.RFSTR1 5 Register Following Stretch 1 MISC.RFSTR0 4 Register Following Stretch 0 MISC.EXSTR1 3 External Access Stretch 1 MISC.EXSTR0 2 External Access Stretch 0 MISC.ROMHM 1 FLASH EEPROM only in second Half of Map MISC.ROMON 0 Enable FLASH EEPROM RTICTL 0x0014 Real-Time Interrupt Control Register RTICTL.RTIE 7 Real Time Interrupt Enable RTICTL.RSWAI 6 RTI and COP Stop While in Wait RTICTL.RSBCK 5 RTI and COP Stop While in Background Debug Mode RTICTL.RTBYP 3 Real Time Interrupt Divider Chain Bypass RTICTL.RTR2 2 Real-Time Interrupt Rate Select 2 RTICTL.RTR1 1 Real-Time Interrupt Rate Select 1 RTICTL.RTR0 0 Real-Time Interrupt Rate Select 0 RTIFLG 0x0015 Real Time Interrupt Flag Register RTIFLG.RTIF 7 Real Time Interrupt Flag COPCTL 0x0016 COP Control Register COPCTL.CME 7 Clock Monitor Enable COPCTL.FCME 6 Force Clock Monitor Enable COPCTL.FCMCOP 5 Force Clock Monitor Reset or COP Watchdog Reset COPCTL.WCOP 4 Window COP mode COPCTL.DISR 3 Disable Resets from COP Watchdog and Clock Monitor COPCTL.CR2 2 COP Watchdog Timer Rate select bit 2 COPCTL.CR1 1 COP Watchdog Timer Rate select bit 1 COPCTL.CR0 0 COP Watchdog Timer Rate select bit 0 COPRST 0x0017 Arm/Reset COP Timer Register ITST0 0x0018 Interrupt Test Register 0 ITST0.ITE6 7 ITST0.ITE8 6 ITST0.ITEA 5 ITST0.ITEC 4 ITST0.ITEE 3 ITST0.ITF0 2 ITST0.ITF2 1 ITST0.ITF4 0 ITST1 0x0019 Interrupt Test Register 1 ITST1.ITD6 7 ITST1.ITD8 6 ITST1.ITDA 5 ITST1.ITDC 4 ITST1.ITDE 3 ITST1.ITE0 2 ITST1.ITE2 1 ITST1.ITE4 0 ITST2 0x001A Interrupt Test Register 2 ITST2.ITC6 7 ITST2.ITC8 6 ITST2.ITCA 5 ITST2.ITCC 4 ITST2.ITCE 3 ITST2.ITD0 2 ITST2.ITD2 1 ITST2.ITD4 0 ITST3 0x001B Interrupt Test Register 3 ITST3.ITB6 7 ITST3.ITB8 6 ITST3.ITBA 5 ITST3.ITBC 4 ITST3.ITBE 3 ITST3.ITC0 2 ITST3.ITC2 1 ITST3.ITC4 0 RESERVED001C 0x001C RESERVED RESERVED001D 0x001D RESERVED INTCR 0x001E Interrupt Control Register INTCR.IRQE 7 IRQ Select Edge Sensitive Only INTCR.IRQEN 6 External IRQ Enable INTCR.DLY 5 Enable Oscillator Start-up Delay on Exit from STOP HPRIO 0x001F Highest Priority I Interrupt HPRIO.PSEL6 6 HPRIO.PSEL5 5 HPRIO.PSEL4 4 HPRIO.PSEL3 3 HPRIO.PSEL2 2 HPRIO.PSEL1 1 BRKCT0 0x0020 Breakpoint Control Register 0 BRKCT0.BKEN1 7 Breakpoint Mode Enable 1 BRKCT0.BKEN0 6 Breakpoint Mode Enable 0 BRKCT0.BKPM 5 Break on Program Addresses BRKCT0.BK1ALE 3 Breakpoint 1 Range Control BRKCT0.BK0ALE 2 Breakpoint 0 Range Control BRKCT1 0x0021 Breakpoint Control Register 1 BRKCT1.BKDBE 6 Enable Data Bus BRKCT1.BKMBH 5 Breakpoint Mask High BRKCT1.BKMBL 4 Breakpoint Mask Low BRKCT1.BK1RWE 3 R/W Compare Enable BRKCT1.BK1RW 2 R/W Compare Value BRKCT1.BK0RWE 1 R/W Compare Enable BRKCT1.BK0RW 0 R/W Compare Value BRKAH 0x0022 Breakpoint Address Register, High Byte BRKAL 0x0023 Breakpoint Address Register, Low Byte BRKDH 0x0024 Breakpoint Data Register, High Byte BRKDL 0x0025 Breakpoint Data Register, Low Byte RESERVED0026 0x0026 RESERVED RESERVED0027 0x0027 RESERVED PORTJ 0x0028 Port J Data Register PORTJ.PJ7 7 Port J Data Bit 7 PORTJ.PJ6 6 Port J Data Bit 6 PORTJ.PJ5 5 Port J Data Bit 5 PORTJ.PJ4 4 Port J Data Bit 4 PORTJ.PJ3 3 Port J Data Bit 3 PORTJ.PJ2 2 Port J Data Bit 2 PORTJ.PJ1 1 Port J Data Bit 1 PORTJ.PJ0 0 Port J Data Bit 0 PORTH 0x0029 Port H Data Register PORTH.PH7 7 Port H Data Bit 7 PORTH.PH6 6 Port H Data Bit 6 PORTH.PH5 5 Port H Data Bit 5 PORTH.PH4 4 Port H Data Bit 4 PORTH.PH3 3 Port H Data Bit 3 PORTH.PH2 2 Port H Data Bit 2 PORTH.PH1 1 Port H Data Bit 1 PORTH.PH0 0 Port H Data Bit 0 DDRJ 0x002A Port J Data Direction Register DDRJ.DDRJ7 7 Data Direction Port J Bit 7 DDRJ.DDRJ6 6 Data Direction Port J Bit 6 DDRJ.DDRJ5 5 Data Direction Port J Bit 5 DDRJ.DDRJ4 4 Data Direction Port J Bit 4 DDRJ.DDRJ3 3 Data Direction Port J Bit 3 DDRJ.DDRJ2 2 Data Direction Port J Bit 2 DDRJ.DDRJ1 1 Data Direction Port J Bit 1 DDRJ.DDRJ0 0 Data Direction Port J Bit 0 DDRH 0x002B Port J Data Direction Register DDRH.DDRH7 7 Data Direction Port H Bit 7 DDRH.DDRH6 6 Data Direction Port H Bit 6 DDRH.DDRH5 5 Data Direction Port H Bit 5 DDRH.DDRH4 4 Data Direction Port H Bit 4 DDRH.DDRH3 3 Data Direction Port H Bit 3 DDRH.DDRH2 2 Data Direction Port H Bit 2 DDRH.DDRH1 1 Data Direction Port H Bit 1 DDRH.DDRH0 0 Data Direction Port H Bit 0 KWIEJ 0x002C Key Wake-up Port J Interrupt Enable Register KWIEJ.KWIEJ7 7 Key Wake-up Port J Interrupt Enable 7 KWIEJ.KWIEJ6 6 Key Wake-up Port J Interrupt Enable 6 KWIEJ.KWIEJ5 5 Key Wake-up Port J Interrupt Enable 5 KWIEJ.KWIEJ4 4 Key Wake-up Port J Interrupt Enable 4 KWIEJ.KWIEJ3 3 Key Wake-up Port J Interrupt Enable 3 KWIEJ.KWIEJ2 2 Key Wake-up Port J Interrupt Enable 2 KWIEJ.KWIEJ1 1 Key Wake-up Port J Interrupt Enable 1 KWIEJ.KWIEJ0 0 Key Wake-up Port J Interrupt Enable 0 KWIEH 0x002D Key Wake-up Port H Interrupt Enable Register KWIEH.KWIEH7 7 Key Wake-up Port H Interrupt Enable 7 KWIEH.KWIEH6 6 Key Wake-up Port H Interrupt Enable 6 KWIEH.KWIEH5 5 Key Wake-up Port H Interrupt Enable 5 KWIEH.KWIEH4 4 Key Wake-up Port H Interrupt Enable 4 KWIEH.KWIEH3 3 Key Wake-up Port H Interrupt Enable 3 KWIEH.KWIEH2 2 Key Wake-up Port H Interrupt Enable 2 KWIEH.KWIEH1 1 Key Wake-up Port H Interrupt Enable 1 KWIEH.KWIEH0 0 Key Wake-up Port H Interrupt Enable 0 KWIFJ 0x002E Key Wake-up Port J Flag Register KWIFJ.KWIFJ7 7 Key Wake-up Port J Flag 7 KWIFJ.KWIFJ6 6 Key Wake-up Port J Flag 6 KWIFJ.KWIFJ5 5 Key Wake-up Port J Flag 5 KWIFJ.KWIFJ4 4 Key Wake-up Port J Flag 4 KWIFJ.KWIFJ3 3 Key Wake-up Port J Flag 3 KWIFJ.KWIFJ2 2 Key Wake-up Port J Flag 2 KWIFJ.KWIFJ1 1 Key Wake-up Port J Flag 1 KWIFJ.KWIFJ0 0 Key Wake-up Port J Flag 0 KWIFH 0x002F Key Wake-up Port H Flag Register KWIFH.KWIFH7 7 Key Wake-up Port H Flag 7 KWIFH.KWIFH6 6 Key Wake-up Port H Flag 6 KWIFH.KWIFH5 5 Key Wake-up Port H Flag 5 KWIFH.KWIFH4 4 Key Wake-up Port H Flag 4 KWIFH.KWIFH3 3 Key Wake-up Port H Flag 3 KWIFH.KWIFH2 2 Key Wake-up Port H Flag 2 KWIFH.KWIFH1 1 Key Wake-up Port H Flag 1 KWIFH.KWIFH0 0 Key Wake-up Port H Flag 0 KWPJ 0x0030 Key Wake-up Port J Polarity Register KWPJ.KWPJ7 7 Key Wake-up Port J Polarity Select 7 KWPJ.KWPJ6 6 Key Wake-up Port J Polarity Select 6 KWPJ.KWPJ5 5 Key Wake-up Port J Polarity Select 5 KWPJ.KWPJ4 4 Key Wake-up Port J Polarity Select 4 KWPJ.KWPJ3 3 Key Wake-up Port J Polarity Select 3 KWPJ.KWPJ2 2 Key Wake-up Port J Polarity Select 2 KWPJ.KWPJ1 1 Key Wake-up Port J Polarity Select 1 KWPJ.KWPJ0 0 Key Wake-up Port J Polarity Select 0 KWPH 0x0031 Key Wake-up Port H Polarity Register KWPH.KWPH7 7 Key Wake-up Port H Polarity Select 7 KWPH.KWPH6 6 Key Wake-up Port H Polarity Select 6 KWPH.KWPH5 5 Key Wake-up Port H Polarity Select 5 KWPH.KWPH4 4 Key Wake-up Port H Polarity Select 4 KWPH.KWPH3 3 Key Wake-up Port H Polarity Select 3 KWPH.KWPH2 2 Key Wake-up Port H Polarity Select 2 KWPH.KWPH1 1 Key Wake-up Port H Polarity Select 1 KWPH.KWPH0 0 Key Wake-up Port H Polarity Select 0 RESERVED0032 0x0032 RESERVED RESERVED0033 0x0033 RESERVED RESERVED0034 0x0034 RESERVED RESERVED0035 0x0035 RESERVED RESERVED0036 0x0036 RESERVED RESERVED0037 0x0037 RESERVED SYNR 0x0038 Synthesizer Register SYNR.SYN5 5 SYNR.SYN4 4 SYNR.SYN3 3 SYNR.SYN2 2 SYNR.SYN1 1 SYNR.SYN0 0 REFDV 0x0039 Reference Divider Register REFDV.REFDV2 2 REFDV.REFDV1 1 REFDV.REFDV0 0 CGTFLG 0x003A Clock Generator Test Register CGTFLG.TSTOUT7 7 CGTFLG.TSTOUT6 6 CGTFLG.TSTOUT5 5 CGTFLG.TSTOUT4 4 CGTFLG.TSTOUT3 3 CGTFLG.TSTOUT2 2 CGTFLG.TSTOUT1 1 CGTFLG.TSTOUT0 0 PLLFLG 0x003B PLL Flags PLLFLG.LOCKIF 7 PLL Lock Interrupt Flag PLLFLG.LOCK 6 Locked Phase Lock Loop Circuit PLLFLG.LHIF 1 Limp-Home Interrupt Flag PLLFLG.LHOME 0 Limp-Home Mode Status PLLCR 0x003C PLL Control Register PLLCR.LOCKIE 7 PLL LOCK Interrupt Enable PLLCR.PLLON 6 Phase Lock Loop On PLLCR.AUTO 5 Automatic Bandwidth Control PLLCR.ACQ 4 Not in Acquisition PLLCR.PSTP 2 Pseudo-STOP Enable PLLCR.LHIE 1 Limp-Home Interrupt Enable PLLCR.NOLHM 0 No Limp-Home Mode CLKSEL 0x003D Clock Generator Clock select Register CLKSEL.BCSP 6 Bus Clock Select PLL CLKSEL.BCSS 5 Bus Clock Select Slow CLKSEL.MCS 2 Module Clock Select SLOW 0x003E Slow mode Divider Register SLOW.SLDV5 5 SLOW.SLDV4 4 SLOW.SLDV3 3 SLOW.SLDV2 2 SLOW.SLDV1 1 SLOW.SLDV0 0 CGTCTL 0x003F CGTCTL CGTCTL.OPNLE 7 CGTCTL.TRK 6 CGTCTL.TSTCLKE 5 CGTCTL.TST4 4 CGTCTL.TST3 3 CGTCTL.TST2 2 CGTCTL.TST1 1 CGTCTL.TST0 0 PWCLK 0x0040 PWM Clocks and Concatenate PWCLK.CON23 7 Concatenate PWM Channels 2 and 3 PWCLK.CON01 6 Concatenate PWM Channels 0 and 1 PWCLK.PCKA2 5 Prescaler for Clock A 2 PWCLK.PCKA1 4 Prescaler for Clock A 1 PWCLK.PCKA0 3 Prescaler for Clock A 0 PWCLK.PCKB2 2 Prescaler for Clock B 2 PWCLK.PCKB1 1 Prescaler for Clock B 1 PWCLK.PCKB0 0 Prescaler for Clock B 0 PWPOL 0x0041 PWM Clock Select and Polarity PWPOL.PCLK3 7 PWM Channel 3 Clock Select PWPOL.PCLK2 6 PWM Channel 2 Clock Select PWPOL.PCLK1 5 PWM Channel 1 Clock Select PWPOL.PCLK0 4 PWM Channel 0 Clock Select PWPOL.PPOL3 3 PWM Channel 3 Polarity PWPOL.PPOL2 2 PWM Channel 2 Polarity PWPOL.PPOL1 1 PWM Channel 1 Polarity PWPOL.PPOL0 0 PWM Channel 0 Polarity PWEN 0x0042 PWM Enable PWEN.PWEN3 3 PWM Channel 3 Enable PWEN.PWEN2 2 PWM Channel 2 Enable PWEN.PWEN1 1 PWM Channel 1 Enable PWEN.PWEN0 0 PWM Channel 0 Enable PWPRES 0x0043 PWM Prescale Counter PWSCAL0 0x0044 PWM Scale Register 0 PWSCNT0 0x0045 PWM Scale Counter 0 Value PWSCAL1 0x0046 PWM Scale Register 1 PWSCNT1 0x0047 PWM Scale Counter 1 Value PWCNT0 0x0048 PWM Channel Counter 0 PWCNT1 0x0049 PWM Channel Counter 1 PWCNT2 0x004A PWM Channel Counter 2 PWCNT3 0x004B PWM Channel Counter 3 PWPER0 0x004C PWM Channel Period Register 0 PWPER1 0x004D PWM Channel Period Register 1 PWPER2 0x004E PWM Channel Period Register 2 PWPER3 0x004F PWM Channel Period Register 3 PWDTY0 0x0050 PWM Channel Duty Register 0 PWDTY1 0x0051 PWM Channel Duty Register 1 PWDTY2 0x0052 PWM Channel Duty Register 2 PWDTY3 0x0053 PWM Channel Duty Register 3 PWCTL 0x0054 PWM Control Register PWCTL.PSWAI 4 PWM Halts while in Wait Mode PWCTL.CENTR 3 Center-Aligned Output Mode PWCTL.RDPP 2 Reduced Drive of Port P PWCTL.PUPP 1 Pull-Up Port P Enable PWCTL.PSBCK 0 PWM Stops while in Background Mode PWTST 0x0055 PWM Special Mode Register ("Test") PWTST.DISCR 7 Disable Reset of Channel Counter on Write to Channel Counter PWTST.DISCP 6 Disable Compare Count Period PWTST.DISCAL 5 Disable Load of Scale-Counters on Write to the Associated Scale-Registers PORTP 0x0056 Port P Data Register PORTP.PP7 7 Port P Data Bit 7 PORTP.PP6 6 Port P Data Bit 6 PORTP.PP5 5 Port P Data Bit 5 PORTP.PP4 4 Port P Data Bit 4 PORTP.PP3 3 Port P Data Bit 3 PORTP.PP2 2 Port P Data Bit 2 PORTP.PP1 1 Port P Data Bit 1 PORTP.PP0 0 Port P Data Bit 0 DDRP 0x0057 Port P Data Direction Register DDRP.DDP7 7 Port P Data Direction Bit 7 DDRP.DDP6 6 Port P Data Direction Bit 6 DDRP.DDP5 5 Port P Data Direction Bit 5 DDRP.DDP4 4 Port P Data Direction Bit 4 DDRP.DDP3 3 Port P Data Direction Bit 3 DDRP.DDP2 2 Port P Data Direction Bit 2 DDRP.DDP1 1 Port P Data Direction Bit 1 DDRP.DDP0 0 Port P Data Direction Bit 0 RESERVED0058 0x0058 RESERVED RESERVED0059 0x0059 RESERVED RESERVED005A 0x005A RESERVED RESERVED005B 0x005B RESERVED RESERVED005C 0x005C RESERVED RESERVED005D 0x005D RESERVED RESERVED005E 0x005E RESERVED RESERVED005F 0x005F RESERVED RESERVED0060 0x0060 RESERVED RESERVED0061 0x0061 RESERVED ATD0CTL2 0x0062 ATD0 Control Register 2 ATD0CTL2.ADPU 7 ATD Disable ATD0CTL2.AFFC 6 ATD Fast Flag Clear All ATD0CTL2.ASWAI 5 ATD Wait Mode ATD0CTL2.ASCIE 1 ATD Sequence Complete Interrupt Enable ATD0CTL2.ASCIF 0 ATD Sequence Complete Interrupt Flag ATD0CTL3 0x0063 ATD0 Control Register 3 ATD0CTL3.FRZ1 1 Background Debug (Freeze) Enable 1 ATD0CTL3.FRZ0 0 Background Debug (Freeze) Enable 0 ATD0CTL4 0x0064 ATD0 Control Register 4 ATD0CTL4.RES10 7 10 bit Mode ATD0CTL4.SMP1 6 Select Sample Time 1 ATD0CTL4.SMP0 5 Select Sample Time 0 ATD0CTL4.PRS4 4 Select Divide-By Factor for ATD P-Clock Prescaler 4 ATD0CTL4.PRS3 3 Select Divide-By Factor for ATD P-Clock Prescaler 3 ATD0CTL4.PRS2 2 Select Divide-By Factor for ATD P-Clock Prescaler 2 ATD0CTL4.PRS1 1 Select Divide-By Factor for ATD P-Clock Prescaler 1 ATD0CTL4.PRS0 0 Select Divide-By Factor for ATD P-Clock Prescaler 0 ATD0CTL5 0x0065 ATD0 Control Register 5 ATD0CTL5.S8CM 6 Select 8 Channel Mode ATD0CTL5.SCAN 5 Enable Continuous Channel Scan ATD0CTL5.MULT 4 Enable Multichannel Conversion ATD0CTL5.CD 3 Channel Select for Conversion D ATD0CTL5.CC 2 Channel Select for Conversion C ATD0CTL5.CB 1 Channel Select for Conversion B ATD0CTL5.CA 0 Channel Select for Conversion A ATD0STAT0 0x0066 ATD0 Status Register ATD0STAT0.SCF 7 Sequence Complete Flag ATD0STAT0.CC2 2 Conversion Counter for Current Sequence of Four or Eight Conversions 2 ATD0STAT0.CC1 1 Conversion Counter for Current Sequence of Four or Eight Conversions 1 ATD0STAT0.CC0 0 Conversion Counter for Current Sequence of Four or Eight Conversions 0 ATD0STAT1 0x0067 ATD0 Status Register ATD0STAT1.CCF7 7 Conversion Complete Flag 7 ATD0STAT1.CCF6 6 Conversion Complete Flag 6 ATD0STAT1.CCF5 5 Conversion Complete Flag 5 ATD0STAT1.CCF4 4 Conversion Complete Flag 4 ATD0STAT1.CCF3 3 Conversion Complete Flag 3 ATD0STAT1.CCF2 2 Conversion Complete Flag 2 ATD0STAT1.CCF1 1 Conversion Complete Flag 1 ATD0STAT1.CCF0 0 Conversion Complete Flag 0 ATD0TESTH 0x0068 ATD0 Test Register ATD0TESTH.SAR9 7 SAR Data 9 ATD0TESTH.SAR8 6 SAR Data 8 ATD0TESTH.SAR7 5 SAR Data 7 ATD0TESTH.SAR6 4 SAR Data 6 ATD0TESTH.SAR5 3 SAR Data 5 ATD0TESTH.SAR4 2 SAR Data 4 ATD0TESTH.SAR3 1 SAR Data 3 ATD0TESTH.SAR2 0 SAR Data 2 ATD0TESTL 0x0069 ATD0 Test Register ATD0TESTL.SAR1 7 SAR Data 1 ATD0TESTL.SAR0 6 SAR Data 0 ATD0TESTL.RST 5 Module Reset Bit ATD0TESTL.TSTOUT 4 Multiplex Output of TST[3:0] (Factory Use) ATD0TESTL.TST3 3 Test Bit 3 ATD0TESTL.TST2 2 Test Bit 2 ATD0TESTL.TST1 1 Test Bit 1 ATD0TESTL.TST0 0 Test Bit 0 RESERVED006A 0x006A RESERVED RESERVED006B 0x006B RESERVED RESERVED006C 0x006C RESERVED RESERVED006D 0x006D RESERVED RESERVED006E 0x006E RESERVED PORTAD0 0x006F Port AD0 Data Input Register PORTAD0.PAD07 7 Port AD0 Data Input Bit 7 PORTAD0.PAD06 6 Port AD0 Data Input Bit 6 PORTAD0.PAD05 5 Port AD0 Data Input Bit 5 PORTAD0.PAD04 4 Port AD0 Data Input Bit 4 PORTAD0.PAD03 3 Port AD0 Data Input Bit 3 PORTAD0.PAD02 2 Port AD0 Data Input Bit 2 PORTAD0.PAD01 1 Port AD0 Data Input Bit 1 PORTAD0.PAD00 0 Port AD0 Data Input Bit 0 ADR00H 0x0070 A/D Conversion Result Register High 0 ADR00L 0x0071 A/D Conversion Result Register Low 0 ADR01H 0x0072 A/D Conversion Result Register High 1 ADR01L 0x0073 A/D Conversion Result Register Low 1 ADR02H 0x0074 A/D Conversion Result Register High 2 ADR02L 0x0075 A/D Conversion Result Register Low 2 ADR03H 0x0076 A/D Conversion Result Register High 3 ADR03L 0x0077 A/D Conversion Result Register Low 3 ADR04H 0x0078 A/D Conversion Result Register High 4 ADR04L 0x0079 A/D Conversion Result Register Low 4 ADR05H 0x007A A/D Conversion Result Register High 5 ADR05L 0x007B A/D Conversion Result Register Low 5 ADR06H 0x007C A/D Conversion Result Register High 6 ADR06L 0x007D A/D Conversion Result Register Low 6 ADR07H 0x007E A/D Conversion Result Register High 7 ADR07L 0x007F A/D Conversion Result Register Low 7 TIOS 0x0080 Timer Input Capture/Output Compare Select TIOS.IOS7 7 Input Capture or Output Compare Channel Configuration 7 TIOS.IOS6 6 Input Capture or Output Compare Channel Configuration 6 TIOS.IOS5 5 Input Capture or Output Compare Channel Configuration 5 TIOS.IOS4 4 Input Capture or Output Compare Channel Configuration 4 TIOS.IOS3 3 Input Capture or Output Compare Channel Configuration 3 TIOS.IOS2 2 Input Capture or Output Compare Channel Configuration 2 TIOS.IOS1 1 Input Capture or Output Compare Channel Configuration 1 TIOS.IOS0 0 Input Capture or Output Compare Channel Configuration 0 CFORC 0x0081 Timer Compare Force Register CFORC.FOC7 7 Force Output Compare Action for Channel 7 CFORC.FOC6 6 Force Output Compare Action for Channel 6 CFORC.FOC5 5 Force Output Compare Action for Channel 5 CFORC.FOC4 4 Force Output Compare Action for Channel 4 CFORC.FOC3 3 Force Output Compare Action for Channel 3 CFORC.FOC2 2 Force Output Compare Action for Channel 2 CFORC.FOC1 1 Force Output Compare Action for Channel 1 CFORC.FOC0 0 Force Output Compare Action for Channel 0 OC7M 0x0082 Output Compare 7 Mask Register OC7M.OC7M7 7 OC7M.OC7M6 6 OC7M.OC7M5 5 OC7M.OC7M4 4 OC7M.OC7M3 3 OC7M.OC7M2 2 OC7M.OC7M1 1 OC7M.OC7M0 0 OC7D 0x0083 Output Compare 7 Data Register OC7D.OC7D7 7 OC7D.OC7D6 6 OC7D.OC7D5 5 OC7D.OC7D4 4 OC7D.OC7D3 3 OC7D.OC7D2 2 OC7D.OC7D1 1 OC7D.OC7D0 0 TCNTH 0x0084 Timer Count Register High TCNTL 0x0085 Timer Count Register Low TSCR 0x0086 Timer System Control Register TSCR.TEN 7 Timer Enable TSCR.TSWAI 6 Timer Module Stops While in Wait TSCR.TSBCK 5 Timer and Modulus Counter Stop While in Background Mode TSCR.TFFCA 4 Timer Fast Flag Clear All RESERVED0087 0x0087 RESERVED TCTL1 0x0088 Timer Control Register 1 TCTL1.OM7 7 Output Mode 7 TCTL1.OL7 6 Output Level 7 TCTL1.OM6 5 Output Mode 6 TCTL1.OL6 4 Output Level 6 TCTL1.OM5 3 Output Mode 5 TCTL1.OL5 2 Output Level 5 TCTL1.OM4 1 Output Mode 4 TCTL1.OL4 0 Output Level 4 TCTL2 0x0089 Timer Control Register 2 TCTL2.OM3 7 Output Mode 3 TCTL2.OL3 6 Output Level 3 TCTL2.OM2 5 Output Mode 2 TCTL2.OL2 4 Output Level 2 TCTL2.OM1 3 Output Mode 1 TCTL2.OL1 2 Output Level 1 TCTL2.OM0 1 Output Mode 0 TCTL2.OL0 0 Output Level 0 TCTL3 0x008A Timer Control Register 3 TCTL3.EDG7B 7 Input Capture Edge Control 7B TCTL3.EDG7A 6 Input Capture Edge Control 7A TCTL3.EDG6B 5 Input Capture Edge Control 6B TCTL3.EDG6A 4 Input Capture Edge Control 6A TCTL3.EDG5B 3 Input Capture Edge Control 5B TCTL3.EDG5A 2 Input Capture Edge Control 5A TCTL3.EDG4B 1 Input Capture Edge Control 4B TCTL3.EDG4A 0 Input Capture Edge Control 4A TCTL4 0x008B Timer Control Register 4 TCTL4.EDG3B 7 Input Capture Edge Control 3B TCTL4.EDG3A 6 Input Capture Edge Control 3A TCTL4.EDG2B 5 Input Capture Edge Control 2B TCTL4.EDG2A 4 Input Capture Edge Control 2A TCTL4.EDG1B 3 Input Capture Edge Control 1B TCTL4.EDG1A 2 Input Capture Edge Control 1A TCTL4.EDG0B 1 Input Capture Edge Control 0B TCTL4.EDG0A 0 Input Capture Edge Control 0A TMSK1 0x008C Timer Interrupt Mask 1 TMSK1.C7I 7 Input Capture/Output Compare 7 Interrupt Enable TMSK1.C6I 6 Input Capture/Output Compare 6 Interrupt Enable TMSK1.C5I 5 Input Capture/Output Compare 5 Interrupt Enable TMSK1.C4I 4 Input Capture/Output Compare 4 Interrupt Enable TMSK1.C3I 3 Input Capture/Output Compare 3 Interrupt Enable TMSK1.C2I 2 Input Capture/Output Compare 2 Interrupt Enable TMSK1.C1I 1 Input Capture/Output Compare 1 Interrupt Enable TMSK1.C0I 0 Input Capture/Output Compare 0 Interrupt Enable TMSK2 0x008D Timer Interrupt Mask 2 TMSK2.TOI 7 Timer Overflow Interrupt Enable TMSK2.PUPT 5 Timer Port Pull-Up Resistor Enable TMSK2.RDPT 4 Timer Port Drive Reduction TMSK2.TCRE 3 Timer Counter Reset Enable TMSK2.PR2 2 Timer Prescaler Select 2 TMSK2.PR1 1 Timer Prescaler Select 1 TMSK2.PR0 0 Timer Prescaler Select 0 TFLG1 0x008E Main Timer Interrupt Flag 1 TFLG1.C7F 7 Input Capture/Output Compare Channel 7 Flag TFLG1.C6F 6 Input Capture/Output Compare Channel 6 Flag TFLG1.C5F 5 Input Capture/Output Compare Channel 5 Flag TFLG1.C4F 4 Input Capture/Output Compare Channel 4 Flag TFLG1.C3F 3 Input Capture/Output Compare Channel 3 Flag TFLG1.C2F 2 Input Capture/Output Compare Channel 2 Flag TFLG1.C1F 1 Input Capture/Output Compare Channel 1 Flag TFLG1.C0F 0 Input Capture/Output Compare Channel 0 Flag TFLG2 0x008F Main Timer Interrupt Flag 2 TFLG2.TOF 7 Timer Overflow Flag TC0H 0x0090 Timer Input Capture/Output Compare Register 0 High TC0L 0x0091 Timer Input Capture/Output Compare Register 0 Low TC1H 0x0092 Timer Input Capture/Output Compare Register 1 High TC1L 0x0093 Timer Input Capture/Output Compare Register 1 Low TC2H 0x0094 Timer Input Capture/Output Compare Register 2 High TC2L 0x0095 Timer Input Capture/Output Compare Register 2 Low TC3H 0x0096 Timer Input Capture/Output Compare Register 3 High TC3L 0x0097 Timer Input Capture/Output Compare Register 3 Low TC4H 0x0098 Timer Input Capture/Output Compare Register 4 High TC4L 0x0099 Timer Input Capture/Output Compare Register 4 Low TC5H 0x009A Timer Input Capture/Output Compare Register 5 High TC5L 0x009B Timer Input Capture/Output Compare Register 5 Low TC6H 0x009C Timer Input Capture/Output Compare Register 6 High TC6L 0x009D Timer Input Capture/Output Compare Register 6 Low TC7H 0x009E Timer Input Capture/Output Compare Register 7 High TC7L 0x009F Timer Input Capture/Output Compare Register 7 Low PACTL 0x00A0 16-Bit Pulse Accumulator A Control Register PACTL.PAEN 6 Pulse Accumulator A System Enable PACTL.PAMOD 5 Pulse Accumulator Mode PACTL.PEDGE 4 Pulse Accumulator Edge Control PACTL.CLK1 3 Clock Select Bit 1 PACTL.CLK0 2 Clock Select Bit 0 PACTL.PAOVI 1 Pulse Accumulator A Overflow Interrupt enable PACTL.PAI 0 Pulse Accumulator Input Interrupt enable PAFLG 0x00A1 Pulse Accumulator A Flag Register PAFLG.PAOVF 1 Pulse Accumulator A Overflow Flag PAFLG.PAIF 0 Pulse Accumulator Input edge Flag PACN3 0x00A2 Pulse Accumulators Count Register 3 PACN2 0x00A3 Pulse Accumulators Count Register 2 PACN1 0x00A4 Pulse Accumulators Count Register 1 PACN0 0x00A5 Pulse Accumulators Count Register 0 MCCTL 0x00A6 16-Bit Modulus Down-Counter Control Register MCCTL.MCZI 7 Modulus Counter Underflow Interrupt Enable MCCTL.MODMC 6 Modulus Mode Enable MCCTL.RDMCL 5 Read Modulus Down-Counter Load MCCTL.ICLAT 4 Input Capture Force Latch Action MCCTL.FLMC 3 Force Load Register into the Modulus Counter Count Register MCCTL.MCEN 2 Modulus Down-Counter Enable MCCTL.MCPR1 1 Modulus Counter Prescaler select 1 MCCTL.MCPR0 0 Modulus Counter Prescaler select 0 MCFLG 0x00A7 16-Bit Modulus Down-Counter FLAG Register MCFLG.MCZF 7 Modulus Counter Underflow Interrupt Flag MCFLG.POLF3 3 First Input Capture Polarity Status 3 MCFLG.POLF2 2 First Input Capture Polarity Status 2 MCFLG.POLF1 1 First Input Capture Polarity Status 1 MCFLG.POLF0 0 First Input Capture Polarity Status 0 ICPACR 0x00A8 Input Control Pulse Accumulators Control Register ICPACR.PA3EN 3 8-Bit Pulse Accumulator 3 Enable ICPACR.PA2EN 2 8-Bit Pulse Accumulator 2 Enable ICPACR.PA1EN 1 8-Bit Pulse Accumulator 1 Enable ICPACR.PA0EN 0 8-Bit Pulse Accumulator 0 Enable DLYCT 0x00A9 Delay Counter Control Register DLYCT.DLY1 1 Delay Counter Select 1 DLYCT.DLY0 0 Delay Counter Select 0 ICOVW 0x00AA Input Control Overwrite Register ICOVW.NOVW7 7 No Input Capture Overwrite 7 ICOVW.NOVW6 6 No Input Capture Overwrite 6 ICOVW.NOVW5 5 No Input Capture Overwrite 5 ICOVW.NOVW4 4 No Input Capture Overwrite 4 ICOVW.NOVW3 3 No Input Capture Overwrite 3 ICOVW.NOVW2 2 No Input Capture Overwrite 2 ICOVW.NOVW1 1 No Input Capture Overwrite 1 ICOVW.NOVW0 0 No Input Capture Overwrite 0 ICSYS 0x00AB Input Control System Control Register ICSYS.SH37 7 Share Input action of Input Capture Channels 3 and 7 ICSYS.SH26 6 Share Input action of Input Capture Channels 2 and 6 ICSYS.SH15 5 Share Input action of Input Capture Channels 1 and 5 ICSYS.SH04 4 Share Input action of Input Capture Channels 0 and 4 ICSYS.TFMOD 3 Timer Flag-setting Mode ICSYS.PACMX 2 8-Bit Pulse Accumulators Maximum Count ICSYS.BUFEN 1 IC Buffer Enable ICSYS.LATQ 0 Input Control Latch or Queue Mode Enable RESERVED00AC 0x00AC RESERVED TIMTST 0x00AD Timer Test Register TIMTST.TCBYP 1 Main Timer Divider Chain Bypass PORTT 0x00AE Port T Data Register PORTT.PT7 7 Port T Data Bit 7 PORTT.PT6 6 Port T Data Bit 6 PORTT.PT5 5 Port T Data Bit 5 PORTT.PT4 4 Port T Data Bit 4 PORTT.PT3 3 Port T Data Bit 3 PORTT.PT2 2 Port T Data Bit 2 PORTT.PT1 1 Port T Data Bit 1 PORTT.PT0 0 Port T Data Bit 0 DDRT 0x00AF Port T Data Direction Register DDRT.DDT7 7 Port T Data Direction Bit 7 DDRT.DDT6 6 Port T Data Direction Bit 6 DDRT.DDT5 5 Port T Data Direction Bit 5 DDRT.DDT4 4 Port T Data Direction Bit 4 DDRT.DDT3 3 Port T Data Direction Bit 3 DDRT.DDT2 2 Port T Data Direction Bit 2 DDRT.DDT1 1 Port T Data Direction Bit 1 DDRT.DDT0 0 Port T Data Direction Bit 0 PBCTL 0x00B0 16-Bit Pulse Accumulator B Control Register PBCTL.PBEN 6 Pulse Accumulator B System Enable PBCTL.PBOVI 1 Pulse Accumulator B Overflow Interrupt enable PBFLG 0x00B1 Pulse Accumulator B Flag Register PBFLG.PBOVF 1 Pulse Accumulator B Overflow Flag PA3H 0x00B2 8-Bit Pulse Accumulators Holding Register 3 PA2H 0x00B3 8-Bit Pulse Accumulators Holding Register 2 PA1H 0x00B4 8-Bit Pulse Accumulators Holding Register 1 PA0H 0x00B5 8-Bit Pulse Accumulators Holding Register 0 MCCNTH 0x00B6 Modulus Down-Counter Count Register High MCCNTL 0x00B7 Modulus Down-Counter Count Register Low TC0HH 0x00B8 Timer Input Capture Holding Register 0 High TC0HL 0x00B9 Timer Input Capture Holding Register 0 Low TC1HH 0x00BA Timer Input Capture Holding Register 1 High TC1HL 0x00BB Timer Input Capture Holding Register 1 Low TC2HH 0x00BC Timer Input Capture Holding Register 2 High TC2HL 0x00BD Timer Input Capture Holding Register 2 Low TC3HH 0x00BE Timer Input Capture Holding Register 3 High TC3HL 0x00BF Timer Input Capture Holding Register 3 Low SC0BDH 0x00C0 SCI Baud Rate Control Register High SC0BDH.BTST 7 Reserved for test function SC0BDH.BSPL 6 Reserved for test function SC0BDH.BRLD 5 Reserved for test function SC0BDH.SBR12 4 SC0BDH.SBR11 3 SC0BDH.SBR10 2 SC0BDH.SBR9 1 SC0BDH.SBR8 0 SC0BDL 0x00C1 SCI Baud Rate Control Register Low SC0BDL.SBR7 7 SC0BDL.SBR6 6 SC0BDL.SBR5 5 SC0BDL.SBR4 4 SC0BDL.SBR3 3 SC0BDL.SBR2 2 SC0BDL.SBR1 1 SC0BDL.SBR0 0 SC0CR1 0x00C2 SCI Control Register 1 SC0CR1.LOOPS 7 SCI LOOP Mode/Single Wire Mode Enable SC0CR1.WOMS 6 Wired-Or Mode for Serial Pins SC0CR1.RSRC 5 Receiver Source SC0CR1.M 4 Mode (select character format) SC0CR1.WAKE 3 Wake-up by Address Mark/Idle SC0CR1.ILT 2 Idle Line Type SC0CR1.PE 1 Parity Enable SC0CR1.PT 0 Parity Type SC0CR2 0x00C3 SCI Control Register 2 SC0CR2.TIE 7 Transmit Interrupt Enable SC0CR2.TCIE 6 Transmit Complete Interrupt Enable SC0CR2.RIE 5 Receiver Interrupt Enable SC0CR2.ILIE 4 Idle Line Interrupt Enable SC0CR2.TE 3 Transmitter Enable SC0CR2.RE 2 Receiver Enable SC0CR2.RWU 1 Receiver Wake-Up Control SC0CR2.SBK 0 Send Break SC0SR1 0x00C4 SCI Status Register 1 SC0SR1.TDRE 7 Transmit Data Register Empty Flag SC0SR1.TC 6 Transmit Complete Flag SC0SR1.RDRF 5 Receive Data Register Full Flag SC0SR1.IDLE 4 Idle Line Detected Flag SC0SR1.OR 3 Overrun Error Flag SC0SR1.NF 2 Noise Error Flag SC0SR1.FE 1 Framing Error Flag SC0SR1.PF 0 Parity Error Flag SC0SR2 0x00C5 SCI Status Register 2 SC0SR2.RAF 0 Receiver Active Flag SC0DRH 0x00C6 SCI Data Register High SC0DRH.R8 7 Receive Bit 8 SC0DRH.T8 6 Transmit Bit 8 SC0DRL 0x00C7 SCI Data Register Low SC0DRL.R7_T7 7 Receive/Transmit Data Bit 7 SC0DRL.R6_T6 6 Receive/Transmit Data Bit 6 SC0DRL.R5_T5 5 Receive/Transmit Data Bit 5 SC0DRL.R4_T4 4 Receive/Transmit Data Bit 4 SC0DRL.R3_T3 3 Receive/Transmit Data Bit 3 SC0DRL.R2_T2 2 Receive/Transmit Data Bit 2 SC0DRL.R1_T1 1 Receive/Transmit Data Bit 1 SC0DRL.R0_T0 0 Receive/Transmit Data Bit 0 SC1BDH 0x00C8 SCI Baud Rate Control Register High SC1BDH.BTST 7 Reserved for test function SC1BDH.BSPL 6 Reserved for test function SC1BDH.BRLD 5 Reserved for test function SC1BDH.SBR12 4 SC1BDH.SBR11 3 SC1BDH.SBR10 2 SC1BDH.SBR9 1 SC1BDH.SBR8 0 SC1BDL 0x00C9 SCI Baud Rate Control Register Low SC1BDL.SBR7 7 SC1BDL.SBR6 6 SC1BDL.SBR5 5 SC1BDL.SBR4 4 SC1BDL.SBR3 3 SC1BDL.SBR2 2 SC1BDL.SBR1 1 SC1BDL.SBR0 0 SC1CR1 0x00CA SCI Control Register 1 SC1CR1.LOOPS 7 SCI LOOP Mode/Single Wire Mode Enable SC1CR1.WOMS 6 Wired-Or Mode for Serial Pins SC1CR1.RSRC 5 Receiver Source SC1CR1.M 4 Mode (select character format) SC1CR1.WAKE 3 Wake-up by Address Mark/Idle SC1CR1.ILT 2 Idle Line Type SC1CR1.PE 1 Parity Enable SC1CR1.PT 0 Parity Type SC1CR2 0x00CB SCI Control Register 2 SC1CR2.TIE 7 Transmit Interrupt Enable SC1CR2.TCIE 6 Transmit Complete Interrupt Enable SC1CR2.RIE 5 Receiver Interrupt Enable SC1CR2.ILIE 4 Idle Line Interrupt Enable SC1CR2.TE 3 Transmitter Enable SC1CR2.RE 2 Receiver Enable SC1CR2.RWU 1 Receiver Wake-Up Control SC1CR2.SBK 0 Send Break SC1SR1 0x00CC SCI Status Register 1 SC1SR1.TDRE 7 Transmit Data Register Empty Flag SC1SR1.TC 6 Transmit Complete Flag SC1SR1.RDRF 5 Receive Data Register Full Flag SC1SR1.IDLE 4 Idle Line Detected Flag SC1SR1.OR 3 Overrun Error Flag SC1SR1.NF 2 Noise Error Flag SC1SR1.FE 1 Framing Error Flag SC1SR1.PF 0 Parity Error Flag SC1SR2 0x00CD SCI Status Register 2 SC1SR2.RAF 0 Receiver Active Flag SC1DRH 0x00CE SCI Data Register High SC1DRH.R8 7 Receive Bit 8 SC1DRH.T8 6 Transmit Bit 8 SC1DRL 0x00CF SCI Data Register Low SC1DRL.R7_T7 7 Receive/Transmit Data Bit 7 SC1DRL.R6_T6 6 Receive/Transmit Data Bit 6 SC1DRL.R5_T5 5 Receive/Transmit Data Bit 5 SC1DRL.R4_T4 4 Receive/Transmit Data Bit 4 SC1DRL.R3_T3 3 Receive/Transmit Data Bit 3 SC1DRL.R2_T2 2 Receive/Transmit Data Bit 2 SC1DRL.R1_T1 1 Receive/Transmit Data Bit 1 SC1DRL.R0_T0 0 Receive/Transmit Data Bit 0 SP0CR1 0x00D0 SPI Control Register 1 SP0CR1.SPIE 7 SPI Interrupt Enable SP0CR1.SPE 6 SPI System Enable SP0CR1.SWOM 5 Port S Wired-OR Mode SP0CR1.MSTR 4 SPI Master/Slave Mode Select SP0CR1.CPOL 3 SPI Clock Polarity SP0CR1.CPHA 2 Clock Phase SP0CR1.SSOE 1 Slave Select Output Enable SP0CR1.LSBF 0 SPI LSB First enable SP0CR2 0x00D1 SPI Control Register 2 SP0CR2.PUPS 3 Pull-Up Port S Enable SP0CR2.RDPS 2 Reduce Drive of Port S SP0CR2.SSWAI 1 Serial Interface Stop in WAIT mode SP0CR2.SPC0 0 Serial Pin Control 0 SP0BR 0x00D2 SPI Baud Rate Register SP0BR.SPR2 2 SPI Clock (SCK) Rate Select Bit 2 SP0BR.SPR1 1 SPI Clock (SCK) Rate Select Bit 1 SP0BR.SPR0 0 SPI Clock (SCK) Rate Select Bit 0 SP0SR 0x00D3 SPI Status Register SP0SR.SPIF 7 SPI Interrupt Request SP0SR.WCOL 6 Write Collision Status Flag SP0SR.MODF 4 SPI Mode Error Interrupt Status Flag RESERVED00D4 0x00D4 RESERVED SP0DR 0x00D5 SPI Data Register PORTS 0x00D6 Port S Data Register PORTS.PS7 7 Port S Data Bit 7 PORTS.PS6 6 Port S Data Bit 6 PORTS.PS5 5 Port S Data Bit 5 PORTS.PS4 4 Port S Data Bit 4 PORTS.PS3 3 Port S Data Bit 3 PORTS.PS2 2 Port S Data Bit 2 PORTS.PS1 1 Port S Data Bit 1 PORTS.PS0 0 Port S Data Bit 0 DDRS 0x00D7 Port S Data Direction Register DDRS.DDS7 7 Port S Data Direction Bit 7 DDRS.DDS6 6 Port S Data Direction Bit 6 DDRS.DDS5 5 Port S Data Direction Bit 5 DDRS.DDS4 4 Port S Data Direction Bit 4 DDRS.DDS3 3 Port S Data Direction Bit 3 DDRS.DDS2 2 Port S Data Direction Bit 2 DDRS.DDS1 1 Port S Data Direction Bit 1 DDRS.DDS0 0 Port S Data Direction Bit 0 RESERVED00D8 0x00D8 RESERVED RESERVED00D9 0x00D9 RESERVED RESERVED00DA 0x00DA RESERVED RESERVED00DB 0x00DB RESERVED RESERVED00DC 0x00DC RESERVED RESERVED00DD 0x00DD RESERVED RESERVED00DE 0x00DE RESERVED RESERVED00DF 0x00DF RESERVED IBAD 0x00E0 Bus Address Register IBAD.ADR7 7 Slave Address 7 IBAD.ADR6 6 Slave Address 6 IBAD.ADR5 5 Slave Address 5 IBAD.ADR4 4 Slave Address 4 IBAD.ADR3 3 Slave Address 3 IBAD.ADR2 2 Slave Address 2 IBAD.ADR1 1 Slave Address 1 IBFD 0x00E1 IIC Bus Frequency Divider Register IBFD.IBC5 5 IIC Bus Clock Rate 5 IBFD.IBC4 4 IIC Bus Clock Rate 4 IBFD.IBC3 3 IIC Bus Clock Rate 3 IBFD.IBC2 2 IIC Bus Clock Rate 2 IBFD.IBC1 1 IIC Bus Clock Rate 1 IBFD.IBC0 0 IIC Bus Clock Rate 0 IBCR 0x00E2 IIC Bus Control Register IBCR.IBEN 7 IIC Bus Enable IBCR.IBIE 6 IIC Bus Interrupt Enable IBCR.MS_SL 5 Master/Slave mode select bit IBCR.Tx_Rx 4 Transmit/Receive mode select bit IBCR.TXAK 3 Transmit Acknowledge enable IBCR.RSTA 2 Repeat Start IBCR.IBSWAI 0 IIC Stop in WAIT mode IBSR 0x00E3 IIC Bus Status Register IBSR.TCF 7 Data transferring bit IBSR.IAAS 6 Addressed as a slave bit IBSR.IBB 5 IIC Bus busy bit IBSR.IBAL 4 Arbitration Lost IBSR.SRW 2 Slave Read/Write IBSR.IBIF 1 IIC Bus Interrupt Flag IBSR.RXAK 0 Received Acknowledge IBDR 0x00E4 IIC Bus Data I/O Register IBDR.D7 7 IBDR.D6 6 IBDR.D5 5 IBDR.D4 4 IBDR.D3 3 IBDR.D2 2 IBDR.D1 1 IBDR.D0 0 IBPURD 0x00E5 Pull-Up and Reduced Drive for Port IB IBPURD.RDPIB 4 Reduced Drive of Port IB IBPURD.PUPIB 0 Pull-Up Port IB Enable PORTIB 0x00E6 Port Data IB Register PORTIB.PIB7 7 Port Data IB Register bit 7 PORTIB.PIB6 6 Port Data IB Register bit 6 PORTIB.PIB5 5 Port Data IB Register bit 5 PORTIB.PIB4 4 Port Data IB Register bit 4 PORTIB.PIB3 3 Port Data IB Register bit 3 PORTIB.PIB2 2 Port Data IB Register bit 2 PORTIB.PIB1 1 Port Data IB Register bit 1 PORTIB.PIB0 0 Port Data IB Register bit 0 DDRIB 0x00E7 Data Direction for Port IB Register DDRIB.DDRIB7 7 Port IB Data direction 7 DDRIB.DDRIB6 6 Port IB Data direction 6 DDRIB.DDRIB5 5 Port IB Data direction 5 DDRIB.DDRIB4 4 Port IB Data direction 4 DDRIB.DDRIB3 3 Port IB Data direction 3 DDRIB.DDRIB2 2 Port IB Data direction 2 DDRIB.DDRIB1 1 DDRIB.DDRIB0 0 RESERVED00E8 0x00E8 RESERVED RESERVED00E9 0x00E9 RESERVED RESERVED00EA 0x00EA RESERVED RESERVED00EB 0x00EB RESERVED RESERVED00EC 0x00EC RESERVED RESERVED00ED 0x00ED RESERVED RESERVED00EE 0x00EE RESERVED RESERVED00EF 0x00EF RESERVED EEMCR 0x00F0 EEPROM Module Configuration EEMCR.NOBDML 7 Background Debug Mode Lockout Disable EEMCR.NOSHW 6 SHADOW Byte Disable EEMCR.EESWAI 2 EEPROM Stops in Wait Mode EEMCR.PROTLCK 1 Block Protect Write Lock EEMCR.EERC 0 EEPROM Charge Pump Clock EEPROT 0x00F1 EEPROM Block Protect EEPROT.SHPROT 7 SHADOW Byte Protection EEPROT.BPROT5 5 EEPROM Block Protection 5 EEPROT.BPROT4 4 EEPROM Block Protection 4 EEPROT.BPROT3 3 EEPROM Block Protection 3 EEPROT.BPROT2 2 EEPROM Block Protection 2 EEPROT.BPROT1 1 EEPROM Block Protection 1 EEPROT.BPROT0 0 EEPROM Block Protection 0 EETST 0x00F2 EEPROM Test EETST.EEODD 7 Odd Row Programming EETST.EEVEN 6 Even Row Programming EETST.MARG 5 Program and Erase Voltage Margin Test Enable EETST.EECPD 4 Charge Pump Disable EETST.EECPRD 3 Charge Pump Ramp Disable EETST.EECPM 1 Charge Pump Monitor Enable EEPROG 0x00F3 EEPROM Control EEPROG.BULKP 7 Bulk Erase Protection EEPROG.BYTE 4 Byte and Aligned Word Erase EEPROG.ROW 3 Row or Bulk Erase (when BYTE = 0) EEPROG.ERASE 2 Erase Control EEPROG.EELAT 1 EEPROM Latch Control EEPROG.EEPGM 0 Program and Erase Enable FEELCK 0x00F4 Flash EEPROM Lock Control Register FEELCK.LOCK 0 Lock Register Bit FEEMCR 0x00F5 Flash EEPROM Module Configuration Register FEEMCR.BOOTP 0 Boot Protect FEETST 0x00F6 Flash EEPROM Module Test Register FEETST.FSTE 7 Stress Test Enable FEETST.GADR 6 Gate/Drain Stress Test Select FEETST.HVT 5 Stress Test High Voltage Status FEETST.FENLV 4 Enable Low Voltage FEETST.FDISVFP 3 Disable Status VFP Voltage Lock FEETST.VTCK 2 VT Check Test Enable FEETST.STRE 1 Spare Test Row Enable FEETST.MWPR 0 Multiple Word Programming FEECTL 0x00F7 Flash EEPROM Control Register FEECTL.FESWAI 4 Flash EEPROM Stop in Wait Control FEECTL.SVFP 3 Status VFP Voltage FEECTL.ERAS 2 Erase Control FEECTL.LAT 1 Latch Control FEECTL.ENPE 0 Enable Programming/Erase MTST0 0x00F8 Mapping Test Register 0 MTST0.MT07 7 MTST0.MT06 6 MTST0.MT05 5 MTST0.MT04 4 MTST0.MT03 3 MTST0.MT02 2 MTST0.MT01 1 MTST0.MT00 0 MTST1 0x00F9 Mapping Test Register 1 MTST1.MT0F 7 MTST1.MT0E 6 MTST1.MT0D 5 MTST1.MT0C 4 MTST1.MT0B 3 MTST1.MT0A 2 MTST1.MT09 1 MTST1.MT08 0 MTST2 0x00FA Mapping Test Register 2 MTST2.MT17 7 MTST2.MT16 6 MTST2.MT15 5 MTST2.MT14 4 MTST2.MT13 3 MTST2.MT12 2 MTST2.MT11 1 MTST2.MT10 0 MTST3 0x00FB Mapping Test Register 3 MTST3.MT1F 7 MTST3.MT1E 6 MTST3.MT1D 5 MTST3.MT1C 4 MTST3.MT1B 3 MTST3.MT1A 2 MTST3.MT19 1 MTST3.MT18 0 PORTK 0x00FC Port K Data Register PORTK.PK7 7 Port K Data Bit 7 PORTK.PK3 3 Port K Data Bit 3 PORTK.PK2 2 Port K Data Bit 2 PORTK.PK1 1 Port K Data Bit 1 PORTK.PK0 0 Port K Data Bit 0 DDRK 0x00FD Port K Data Direction Register DDRK.DDK7 7 Port K Data Direction Bit 7 DDRK.DDK3 3 Port K Data Direction Bit 3 DDRK.DDK2 2 Port K Data Direction Bit 2 DDRK.DDK1 1 Port K Data Direction Bit 1 DDRK.DDK0 0 Port K Data Direction Bit 0 RESERVED00FE 0x00FE RESERVED PPAGE 0x00FF Program Page Index Register PPAGE.PIX2 2 PPAGE.PIX1 1 PPAGE.PIX0 0 C0MCR0 0x0100 msCAN12 Module Control Register 0 C0MCR0.CSWAI 5 CAN Stops in Wait Mode C0MCR0.SYNCH 4 Synchronized Status C0MCR0.TLNKEN 3 Timer Enable C0MCR0.SLPAK 2 SLEEP Mode Acknowledge C0MCR0.SLPRQ 1 SLEEP request C0MCR0.SFTRES 0 SOFT_RESET C0MCR1 0x0101 msCAN12 Module Control Register 1 C0MCR1.LOOPB 2 Loop Back Self Test Mode C0MCR1.WUPM 1 Wake-Up Mode C0MCR1.CLKSRC 0 msCAN12 Clock Source C0BTR0 0x0102 msCAN12 Bus Timing Register 0 C0BTR0.SJW1 7 Synchronization Jump Width 1 C0BTR0.SJW0 6 Synchronization Jump Width 0 C0BTR0.BRP5 5 Baud Rate Prescaler 5 C0BTR0.BRP4 4 Baud Rate Prescaler 4 C0BTR0.BRP3 3 Baud Rate Prescaler 3 C0BTR0.BRP2 2 Baud Rate Prescaler 2 C0BTR0.BRP1 1 Baud Rate Prescaler 1 C0BTR0.BRP0 0 Baud Rate Prescaler 0 C0BTR1 0x0103 msCAN12 Bus Timing Register 1 C0BTR1.SAMP 7 Sampling C0BTR1.TSEG22 6 Time Segment 22 C0BTR1.TSEG21 5 Time Segment 21 C0BTR1.TSEG20 4 Time Segment 20 C0BTR1.TSEG13 3 Time Segment 13 C0BTR1.TSEG12 2 Time Segment 12 C0BTR1.TSEG11 1 Time Segment 11 C0BTR1.TSEG10 0 Time Segment 10 C0RFLG 0x0104 msCAN12 Receiver Flag Register C0RFLG.WUPIF 7 Wake-up Interrupt Flag C0RFLG.RWRNIF 6 Receiver Warning Interrupt Flag C0RFLG.TWRNIF 5 Transmitter Warning Interrupt Flag C0RFLG.RERRIF 4 Receiver Error Passive Interrupt Flag C0RFLG.TERRIF 3 Transmitter Error Passive Interrupt Flag C0RFLG.BOFFIF 2 BUSOFF Interrupt Flag C0RFLG.OVRIF 1 Overrun Interrupt Flag C0RFLG.RXF 0 Receive Buffer Full C0RIER 0x0105 msCAN12 Receiver Interrupt Enable Register C0RIER.WUPIE 7 Wake-up Interrupt Enable C0RIER.RWRNIE 6 Receiver Warning Interrupt Enable C0RIER.TWRNIE 5 Transmitter Warning Interrupt Enable C0RIER.RERRIE 4 Receiver Error Passive Interrupt Enable C0RIER.TERRIE 3 Transmitter Error Passive Interrupt Enable C0RIER.BOFFIE 2 BUSOFF Interrupt Enable C0RIER.OVRIE 1 Overrun Interrupt Enable C0RIER.RXFIE 0 Receiver Full Interrupt Enable C0TFLG 0x0106 msCAN12 Transmitter Flag Register C0TFLG.ABTAK2 6 Abort Acknowledge 2 C0TFLG.ABTAK1 5 Abort Acknowledge 1 C0TFLG.ABTAK0 4 Abort Acknowledge 0 C0TFLG.TXE2 2 Transmitter Buffer Empty 2 C0TFLG.TXE1 1 Transmitter Buffer Empty 1 C0TFLG.TXE0 0 Transmitter Buffer Empty 0 C0TCR 0x0107 msCAN12 Transmitter Control Register C0TCR.ABTRQ2 6 Abort Request 2 C0TCR.ABTRQ1 5 Abort Request 1 C0TCR.ABTRQ0 4 Abort Request 0 C0TCR.TXEIE2 2 Transmitter Empty Interrupt Enable 2 C0TCR.TXEIE1 1 Transmitter Empty Interrupt Enable 1 C0TCR.TXEIE0 0 Transmitter Empty Interrupt Enable 0 C0IDAC 0x0108 msCAN12 Identifier Acceptance Control Register C0IDAC.IDAM1 5 Identifier Acceptance Mode 1 C0IDAC.IDAM0 4 Identifier Acceptance Mode 0 C0IDAC.IDHIT2 2 Identifier Acceptance Hit Indicator 2 C0IDAC.IDHIT1 1 Identifier Acceptance Hit Indicator 1 C0IDAC.IDHIT0 0 Identifier Acceptance Hit Indicator 0 RESERVED0109 0x0109 RESERVED RESERVED010A 0x010A RESERVED RESERVED010B 0x010B RESERVED RESERVED010C 0x010C RESERVED RESERVED010D 0x010D RESERVED C0RXERR 0x010E msCAN12 Receive Error Counter C0RXERR.RXERR7 7 C0RXERR.RXERR6 6 C0RXERR.RXERR5 5 C0RXERR.RXERR4 4 C0RXERR.RXERR3 3 C0RXERR.RXERR2 2 C0RXERR.RXERR1 1 C0RXERR.RXERR0 0 C0TXERR 0x010F msCAN12 Transmit Error Counter C0TXERR.TXERR7 7 C0TXERR.TXERR6 6 C0TXERR.TXERR5 5 C0TXERR.TXERR4 4 C0TXERR.TXERR3 3 C0TXERR.TXERR2 2 C0TXERR.TXERR1 1 C0TXERR.TXERR0 0 C0IDAR0 0x0110 msCAN12 Identifier Acceptance Register 0 C0IDAR0.AC7 7 Acceptance Code Bit 7 C0IDAR0.AC6 6 Acceptance Code Bit 6 C0IDAR0.AC5 5 Acceptance Code Bit 5 C0IDAR0.AC4 4 Acceptance Code Bit 4 C0IDAR0.AC3 3 Acceptance Code Bit 3 C0IDAR0.AC2 2 Acceptance Code Bit 2 C0IDAR0.AC1 1 Acceptance Code Bit 1 C0IDAR0.AC0 0 Acceptance Code Bit 0 C0IDAR1 0x0111 msCAN12 Identifier Acceptance Register 1 C0IDAR1.AC7 7 Acceptance Code Bit 7 C0IDAR1.AC6 6 Acceptance Code Bit 6 C0IDAR1.AC5 5 Acceptance Code Bit 5 C0IDAR1.AC4 4 Acceptance Code Bit 4 C0IDAR1.AC3 3 Acceptance Code Bit 3 C0IDAR1.AC2 2 Acceptance Code Bit 2 C0IDAR1.AC1 1 Acceptance Code Bit 1 C0IDAR1.AC0 0 Acceptance Code Bit 0 C0IDAR2 0x0112 msCAN12 Identifier Acceptance Register 2 C0IDAR2.AC7 7 Acceptance Code Bit 7 C0IDAR2.AC6 6 Acceptance Code Bit 6 C0IDAR2.AC5 5 Acceptance Code Bit 5 C0IDAR2.AC4 4 Acceptance Code Bit 4 C0IDAR2.AC3 3 Acceptance Code Bit 3 C0IDAR2.AC2 2 Acceptance Code Bit 2 C0IDAR2.AC1 1 Acceptance Code Bit 1 C0IDAR2.AC0 0 Acceptance Code Bit 0 C0IDAR3 0x0113 msCAN12 Identifier Acceptance Register 3 C0IDAR3.AC7 7 Acceptance Code Bit 7 C0IDAR3.AC6 6 Acceptance Code Bit 6 C0IDAR3.AC5 5 Acceptance Code Bit 5 C0IDAR3.AC4 4 Acceptance Code Bit 4 C0IDAR3.AC3 3 Acceptance Code Bit 3 C0IDAR3.AC2 2 Acceptance Code Bit 2 C0IDAR3.AC1 1 Acceptance Code Bit 1 C0IDAR3.AC0 0 Acceptance Code Bit 0 C0IDMR0 0x0114 msCAN12 Identifier Mask Register 0 C0IDMR0.AM7 7 Acceptance Mask Bit 7 C0IDMR0.AM6 6 Acceptance Mask Bit 6 C0IDMR0.AM5 5 Acceptance Mask Bit 5 C0IDMR0.AM4 4 Acceptance Mask Bit 4 C0IDMR0.AM3 3 Acceptance Mask Bit 3 C0IDMR0.AM2 2 Acceptance Mask Bit 2 C0IDMR0.AM1 1 Acceptance Mask Bit 1 C0IDMR0.AM0 0 Acceptance Mask Bit 0 C0IDMR1 0x0115 msCAN12 Identifier Mask Register 1 C0IDMR1.AM7 7 Acceptance Mask Bit 7 C0IDMR1.AM6 6 Acceptance Mask Bit 6 C0IDMR1.AM5 5 Acceptance Mask Bit 5 C0IDMR1.AM4 4 Acceptance Mask Bit 4 C0IDMR1.AM3 3 Acceptance Mask Bit 3 C0IDMR1.AM2 2 Acceptance Mask Bit 2 C0IDMR1.AM1 1 Acceptance Mask Bit 1 C0IDMR1.AM0 0 Acceptance Mask Bit 0 C0IDMR2 0x0116 msCAN12 Identifier Mask Register 2 C0IDMR2.AM7 7 Acceptance Mask Bit 7 C0IDMR2.AM6 6 Acceptance Mask Bit 6 C0IDMR2.AM5 5 Acceptance Mask Bit 5 C0IDMR2.AM4 4 Acceptance Mask Bit 4 C0IDMR2.AM3 3 Acceptance Mask Bit 3 C0IDMR2.AM2 2 Acceptance Mask Bit 2 C0IDMR2.AM1 1 Acceptance Mask Bit 1 C0IDMR2.AM0 0 Acceptance Mask Bit 0 C0IDMR3 0x0117 msCAN12 Identifier Mask Register 3 C0IDMR3.AM7 7 Acceptance Mask Bit 7 C0IDMR3.AM6 6 Acceptance Mask Bit 6 C0IDMR3.AM5 5 Acceptance Mask Bit 5 C0IDMR3.AM4 4 Acceptance Mask Bit 4 C0IDMR3.AM3 3 Acceptance Mask Bit 3 C0IDMR3.AM2 2 Acceptance Mask Bit 2 C0IDMR3.AM1 1 Acceptance Mask Bit 1 C0IDMR3.AM0 0 Acceptance Mask Bit 0 C0IDAR4 0x0118 msCAN12 Identifier Acceptance Register 4 C0IDAR4.AC7 7 Acceptance Code Bit 7 C0IDAR4.AC6 6 Acceptance Code Bit 6 C0IDAR4.AC5 5 Acceptance Code Bit 5 C0IDAR4.AC4 4 Acceptance Code Bit 4 C0IDAR4.AC3 3 Acceptance Code Bit 3 C0IDAR4.AC2 2 Acceptance Code Bit 2 C0IDAR4.AC1 1 Acceptance Code Bit 1 C0IDAR4.AC0 0 Acceptance Code Bit 0 C0IDAR5 0x0119 msCAN12 Identifier Acceptance Register 5 C0IDAR5.AC7 7 Acceptance Code Bit 7 C0IDAR5.AC6 6 Acceptance Code Bit 6 C0IDAR5.AC5 5 Acceptance Code Bit 5 C0IDAR5.AC4 4 Acceptance Code Bit 4 C0IDAR5.AC3 3 Acceptance Code Bit 3 C0IDAR5.AC2 2 Acceptance Code Bit 2 C0IDAR5.AC1 1 Acceptance Code Bit 1 C0IDAR5.AC0 0 Acceptance Code Bit 0 C0IDAR6 0x011A msCAN12 Identifier Acceptance Register 6 C0IDAR6.AC7 7 Acceptance Code Bit 7 C0IDAR6.AC6 6 Acceptance Code Bit 6 C0IDAR6.AC5 5 Acceptance Code Bit 5 C0IDAR6.AC4 4 Acceptance Code Bit 4 C0IDAR6.AC3 3 Acceptance Code Bit 3 C0IDAR6.AC2 2 Acceptance Code Bit 2 C0IDAR6.AC1 1 Acceptance Code Bit 1 C0IDAR6.AC0 0 Acceptance Code Bit 0 C0IDAR7 0x011B msCAN12 Identifier Acceptance Register 7 C0IDAR7.AC7 7 Acceptance Code Bit 7 C0IDAR7.AC6 6 Acceptance Code Bit 6 C0IDAR7.AC5 5 Acceptance Code Bit 5 C0IDAR7.AC4 4 Acceptance Code Bit 4 C0IDAR7.AC3 3 Acceptance Code Bit 3 C0IDAR7.AC2 2 Acceptance Code Bit 2 C0IDAR7.AC1 1 Acceptance Code Bit 1 C0IDAR7.AC0 0 Acceptance Code Bit 0 C0IDMR4 0x011C msCAN12 Identifier Mask Register 4 C0IDMR4.AM7 7 Acceptance Mask Bit 7 C0IDMR4.AM6 6 Acceptance Mask Bit 6 C0IDMR4.AM5 5 Acceptance Mask Bit 5 C0IDMR4.AM4 4 Acceptance Mask Bit 4 C0IDMR4.AM3 3 Acceptance Mask Bit 3 C0IDMR4.AM2 2 Acceptance Mask Bit 2 C0IDMR4.AM1 1 Acceptance Mask Bit 1 C0IDMR4.AM0 0 Acceptance Mask Bit 0 C0IDMR5 0x011D msCAN12 Identifier Mask Register 5 C0IDMR5.AM7 7 Acceptance Mask Bit 7 C0IDMR5.AM6 6 Acceptance Mask Bit 6 C0IDMR5.AM5 5 Acceptance Mask Bit 5 C0IDMR5.AM4 4 Acceptance Mask Bit 4 C0IDMR5.AM3 3 Acceptance Mask Bit 3 C0IDMR5.AM2 2 Acceptance Mask Bit 2 C0IDMR5.AM1 1 Acceptance Mask Bit 1 C0IDMR5.AM0 0 Acceptance Mask Bit 0 C0IDMR6 0x011E msCAN12 Identifier Mask Register 6 C0IDMR6.AM7 7 Acceptance Mask Bit 7 C0IDMR6.AM6 6 Acceptance Mask Bit 6 C0IDMR6.AM5 5 Acceptance Mask Bit 5 C0IDMR6.AM4 4 Acceptance Mask Bit 4 C0IDMR6.AM3 3 Acceptance Mask Bit 3 C0IDMR6.AM2 2 Acceptance Mask Bit 2 C0IDMR6.AM1 1 Acceptance Mask Bit 1 C0IDMR6.AM0 0 Acceptance Mask Bit 0 C0IDMR7 0x011F msCAN12 Identifier Mask Register 7 C0IDMR7.AM7 7 Acceptance Mask Bit 7 C0IDMR7.AM6 6 Acceptance Mask Bit 6 C0IDMR7.AM5 5 Acceptance Mask Bit 5 C0IDMR7.AM4 4 Acceptance Mask Bit 4 C0IDMR7.AM3 3 Acceptance Mask Bit 3 C0IDMR7.AM2 2 Acceptance Mask Bit 2 C0IDMR7.AM1 1 Acceptance Mask Bit 1 C0IDMR7.AM0 0 Acceptance Mask Bit 0 RESERVED0120 0x0120 RESERVED RESERVED0121 0x0121 RESERVED RESERVED0122 0x0122 RESERVED RESERVED0123 0x0123 RESERVED RESERVED0124 0x0124 RESERVED RESERVED0125 0x0125 RESERVED RESERVED0126 0x0126 RESERVED RESERVED0127 0x0127 RESERVED RESERVED0128 0x0128 RESERVED RESERVED0129 0x0129 RESERVED RESERVED012A 0x012A RESERVED RESERVED012B 0x012B RESERVED RESERVED012C 0x012C RESERVED RESERVED012D 0x012D RESERVED RESERVED012E 0x012E RESERVED RESERVED012F 0x012F RESERVED RESERVED0130 0x0130 RESERVED RESERVED0131 0x0131 RESERVED RESERVED0132 0x0132 RESERVED RESERVED0133 0x0133 RESERVED RESERVED0134 0x0134 RESERVED RESERVED0135 0x0135 RESERVED RESERVED0136 0x0136 RESERVED RESERVED0137 0x0137 RESERVED RESERVED0138 0x0138 RESERVED RESERVED0139 0x0139 RESERVED RESERVED013A 0x013A RESERVED RESERVED013B 0x013B RESERVED RESERVED013C 0x013C RESERVED PCTLCAN0 0x013D msCAN12 Port CAN Control Register PCTLCAN0.PUPCAN 1 Pull-Up Enable Port CAN PCTLCAN0.RDPCAN 0 Reduced Drive Port CAN PORTCAN0 0x013E msCAN12 Port CAN Data Register PORTCAN0.PCAN7 7 Port CAN Data Bit 7 PORTCAN0.PCAN6 6 Port CAN Data Bit 6 PORTCAN0.PCAN5 5 Port CAN Data Bit 5 PORTCAN0.PCAN4 4 Port CAN Data Bit 4 PORTCAN0.PCAN3 3 Port CAN Data Bit 3 PORTCAN0.PCAN2 2 Port CAN Data Bit 2 PORTCAN0.TxCAN 1 PORTCAN0.RxCAN 0 DDRCAN0 0x013F msCAN12 Port CAN Data Direction Register DDRCAN0.DDCAN7 7 DDRCAN0.DDCAN6 6 DDRCAN0.DDCAN5 5 DDRCAN0.DDCAN4 4 DDRCAN0.DDCAN3 3 DDRCAN0.DDCAN2 2 ATD1CTL2 0x01E2 ATD1 Control Register 2 ATD1CTL2.ADPU 7 ATD Disable ATD1CTL2.AFFC 6 ATD Fast Flag Clear All ATD1CTL2.ASWAI 5 ATD Wait Mode ATD1CTL2.ASCIE 1 ATD Sequence Complete Interrupt Enable ATD1CTL2.ASCIF 0 ATD Sequence Complete Interrupt Flag ATD1CTL3 0x01E3 ATD1 Control Register 3 ATD1CTL3.FRZ1 1 Background Debug (Freeze) Enable 1 ATD1CTL3.FRZ0 0 Background Debug (Freeze) Enable 0 ATD1CTL4 0x01E4 ATD1 Control Register 4 ATD1CTL4.RES10 7 10 bit Mode ATD1CTL4.SMP1 6 Select Sample Time 1 ATD1CTL4.SMP0 5 Select Sample Time 0 ATD1CTL4.PRS4 4 Select Divide-By Factor for ATD P-Clock Prescaler 4 ATD1CTL4.PRS3 3 Select Divide-By Factor for ATD P-Clock Prescaler 3 ATD1CTL4.PRS2 2 Select Divide-By Factor for ATD P-Clock Prescaler 2 ATD1CTL4.PRS1 1 Select Divide-By Factor for ATD P-Clock Prescaler 1 ATD1CTL4.PRS0 0 Select Divide-By Factor for ATD P-Clock Prescaler 0 ATD1CTL5 0x01E5 ATD1 Control Register 5 ATD1CTL5.S8CM 6 Select 8 Channel Mode ATD1CTL5.SCAN 5 Enable Continuous Channel Scan ATD1CTL5.MULT 4 Enable Multichannel Conversion ATD1CTL5.CD 3 Channel Select for Conversion D ATD1CTL5.CC 2 Channel Select for Conversion C ATD1CTL5.CB 1 Channel Select for Conversion B ATD1CTL5.CA 0 Channel Select for Conversion A ATD1STAT0 0x01E6 ATD1 Status Register ATD1STAT0.SCF 7 Sequence Complete Flag ATD1STAT0.CC2 2 Conversion Counter for Current Sequence of Four or Eight Conversions 2 ATD1STAT0.CC1 1 Conversion Counter for Current Sequence of Four or Eight Conversions 1 ATD1STAT0.CC0 0 Conversion Counter for Current Sequence of Four or Eight Conversions 0 ATD1STAT1 0x01E7 ATD1 Status Register ATD1STAT1.CCF7 7 Conversion Complete Flag 7 ATD1STAT1.CCF6 6 Conversion Complete Flag 6 ATD1STAT1.CCF5 5 Conversion Complete Flag 5 ATD1STAT1.CCF4 4 Conversion Complete Flag 4 ATD1STAT1.CCF3 3 Conversion Complete Flag 3 ATD1STAT1.CCF2 2 Conversion Complete Flag 2 ATD1STAT1.CCF1 1 Conversion Complete Flag 1 ATD1STAT1.CCF0 0 Conversion Complete Flag 0 ATD1TESTH 0x01E8 ATD1 Test Register ATD1TESTH.SAR9 7 SAR Data 9 ATD1TESTH.SAR8 6 SAR Data 8 ATD1TESTH.SAR7 5 SAR Data 7 ATD1TESTH.SAR6 4 SAR Data 6 ATD1TESTH.SAR5 3 SAR Data 5 ATD1TESTH.SAR4 2 SAR Data 4 ATD1TESTH.SAR3 1 SAR Data 3 ATD1TESTH.SAR2 0 SAR Data 2 ATD1TESTL 0x01E9 ATD1 Test Register ATD1TESTL.SAR1 7 SAR Data 1 ATD1TESTL.SAR0 6 SAR Data 0 ATD1TESTL.RST 5 Module Reset Bit ATD1TESTL.TSTOUT 4 Multiplex Output of TST[3:0] (Factory Use) ATD1TESTL.TST3 3 Test Bit 3 ATD1TESTL.TST2 2 Test Bit 2 ATD1TESTL.TST1 1 Test Bit 1 ATD1TESTL.TST0 0 Test Bit 0 RESERVED01EA 0x01EA RESERVED RESERVED01EB 0x01EB RESERVED RESERVED01EC 0x01EC RESERVED RESERVED01ED 0x01ED RESERVED RESERVED01EE 0x01EE RESERVED PORTAD1 0x01EF Port AD1 Data Input Register PORTAD1.PAD17 7 Port AD1 Data Input Bit 7 PORTAD1.PAD16 6 Port AD1 Data Input Bit 6 PORTAD1.PAD15 5 Port AD1 Data Input Bit 5 PORTAD1.PAD14 4 Port AD1 Data Input Bit 4 PORTAD1.PAD13 3 Port AD1 Data Input Bit 3 PORTAD1.PAD12 2 Port AD1 Data Input Bit 2 PORTAD1.PAD11 1 Port AD1 Data Input Bit 1 PORTAD1.PAD10 0 Port AD1 Data Input Bit 0 ADR10H 0x01F0 A/D Conversion Result Register High 0 ADR10L 0x01F1 A/D Conversion Result Register Low 0 ADR11H 0x01F2 A/D Conversion Result Register High 1 ADR11L 0x01F3 A/D Conversion Result Register Low 1 ADR12H 0x01F4 A/D Conversion Result Register High 2 ADR12L 0x01F5 A/D Conversion Result Register Low 2 ADR13H 0x01F6 A/D Conversion Result Register High 3 ADR13L 0x01F7 A/D Conversion Result Register Low 3 ADR14H 0x01F8 A/D Conversion Result Register High 4 ADR14L 0x01F9 A/D Conversion Result Register Low 4 ADR15H 0x01FA A/D Conversion Result Register High 5 ADR15L 0x01FB A/D Conversion Result Register Low 5 ADR16H 0x01FC A/D Conversion Result Register High 6 ADR16L 0x01FD A/D Conversion Result Register Low 6 ADR17H 0x01FE A/D Conversion Result Register High 7 ADR17L 0x01FF A/D Conversion Result Register Low 7 C1MCR0 0x0300 msCAN12 Module Control Register 0 C1MCR0.CSWAI 5 CAN Stops in Wait Mode C1MCR0.SYNCH 4 Synchronized Status C1MCR0.TLNKEN 3 Timer Enable C1MCR0.SLPAK 2 SLEEP Mode Acknowledge C1MCR0.SLPRQ 1 SLEEP request C1MCR0.SFTRES 0 SOFT_RESET C1MCR1 0x0301 msCAN12 Module Control Register 1 C1MCR1.LOOPB 2 Loop Back Self Test Mode C1MCR1.WUPM 1 Wake-Up Mode C1MCR1.CLKSRC 0 msCAN12 Clock Source C1BTR0 0x0302 msCAN12 Bus Timing Register 0 C1BTR0.SJW1 7 Synchronization Jump Width 1 C1BTR0.SJW0 6 Synchronization Jump Width 0 C1BTR0.BRP5 5 Baud Rate Prescaler 5 C1BTR0.BRP4 4 Baud Rate Prescaler 4 C1BTR0.BRP3 3 Baud Rate Prescaler 3 C1BTR0.BRP2 2 Baud Rate Prescaler 2 C1BTR0.BRP1 1 Baud Rate Prescaler 1 C1BTR0.BRP0 0 Baud Rate Prescaler 0 C1BTR1 0x0303 msCAN12 Bus Timing Register 1 C1BTR1.SAMP 7 Sampling C1BTR1.TSEG22 6 Time Segment 22 C1BTR1.TSEG21 5 Time Segment 21 C1BTR1.TSEG20 4 Time Segment 20 C1BTR1.TSEG13 3 Time Segment 13 C1BTR1.TSEG12 2 Time Segment 12 C1BTR1.TSEG11 1 Time Segment 11 C1BTR1.TSEG10 0 Time Segment 10 C1RFLG 0x0304 msCAN12 Receiver Flag Register C1RFLG.WUPIF 7 Wake-up Interrupt Flag C1RFLG.RWRNIF 6 Receiver Warning Interrupt Flag C1RFLG.TWRNIF 5 Transmitter Warning Interrupt Flag C1RFLG.RERRIF 4 Receiver Error Passive Interrupt Flag C1RFLG.TERRIF 3 Transmitter Error Passive Interrupt Flag C1RFLG.BOFFIF 2 BUSOFF Interrupt Flag C1RFLG.OVRIF 1 Overrun Interrupt Flag C1RFLG.RXF 0 Receive Buffer Full C1RIER 0x0305 msCAN12 Receiver Interrupt Enable Register C1RIER.WUPIE 7 Wake-up Interrupt Enable C1RIER.RWRNIE 6 Receiver Warning Interrupt Enable C1RIER.TWRNIE 5 Transmitter Warning Interrupt Enable C1RIER.RERRIE 4 Receiver Error Passive Interrupt Enable C1RIER.TERRIE 3 Transmitter Error Passive Interrupt Enable C1RIER.BOFFIE 2 BUSOFF Interrupt Enable C1RIER.OVRIE 1 Overrun Interrupt Enable C1RIER.RXFIE 0 Receiver Full Interrupt Enable C1TFLG 0x0306 msCAN12 Transmitter Flag Register C1TFLG.ABTAK2 6 Abort Acknowledge 2 C1TFLG.ABTAK1 5 Abort Acknowledge 1 C1TFLG.ABTAK0 4 Abort Acknowledge 0 C1TFLG.TXE2 2 Transmitter Buffer Empty 2 C1TFLG.TXE1 1 Transmitter Buffer Empty 1 C1TFLG.TXE0 0 Transmitter Buffer Empty 0 C1TCR 0x0307 msCAN12 Transmitter Control Register C1TCR.ABTRQ2 6 Abort Request 2 C1TCR.ABTRQ1 5 Abort Request 1 C1TCR.ABTRQ0 4 Abort Request 0 C1TCR.TXEIE2 2 Transmitter Empty Interrupt Enable 2 C1TCR.TXEIE1 1 Transmitter Empty Interrupt Enable 1 C1TCR.TXEIE0 0 Transmitter Empty Interrupt Enable 0 C1IDAC 0x0308 msCAN12 Identifier Acceptance Control Register C1IDAC.IDAM1 5 Identifier Acceptance Mode 1 C1IDAC.IDAM0 4 Identifier Acceptance Mode 0 C1IDAC.IDHIT2 2 Identifier Acceptance Hit Indicator 2 C1IDAC.IDHIT1 1 Identifier Acceptance Hit Indicator 1 C1IDAC.IDHIT0 0 Identifier Acceptance Hit Indicator 0 RESERVED0309 0x0309 RESERVED RESERVED030A 0x030A RESERVED RESERVED030B 0x030B RESERVED RESERVED030C 0x030C RESERVED RESERVED030D 0x030D RESERVED C1RXERR 0x030E msCAN12 Receive Error Counter C1RXERR.RXERR7 7 C1RXERR.RXERR6 6 C1RXERR.RXERR5 5 C1RXERR.RXERR4 4 C1RXERR.RXERR3 3 C1RXERR.RXERR2 2 C1RXERR.RXERR1 1 C1RXERR.RXERR0 0 C1TXERR 0x030F msCAN12 Transmit Error Counter C1TXERR.TXERR7 7 C1TXERR.TXERR6 6 C1TXERR.TXERR5 5 C1TXERR.TXERR4 4 C1TXERR.TXERR3 3 C1TXERR.TXERR2 2 C1TXERR.TXERR1 1 C1TXERR.TXERR0 0 C1IDAR0 0x0310 msCAN12 Identifier Acceptance Register 0 C1IDAR0.AC7 7 Acceptance Code Bit 7 C1IDAR0.AC6 6 Acceptance Code Bit 6 C1IDAR0.AC5 5 Acceptance Code Bit 5 C1IDAR0.AC4 4 Acceptance Code Bit 4 C1IDAR0.AC3 3 Acceptance Code Bit 3 C1IDAR0.AC2 2 Acceptance Code Bit 2 C1IDAR0.AC1 1 Acceptance Code Bit 1 C1IDAR0.AC0 0 Acceptance Code Bit 0 C1IDAR1 0x0311 msCAN12 Identifier Acceptance Register 1 C1IDAR1.AC7 7 Acceptance Code Bit 7 C1IDAR1.AC6 6 Acceptance Code Bit 6 C1IDAR1.AC5 5 Acceptance Code Bit 5 C1IDAR1.AC4 4 Acceptance Code Bit 4 C1IDAR1.AC3 3 Acceptance Code Bit 3 C1IDAR1.AC2 2 Acceptance Code Bit 2 C1IDAR1.AC1 1 Acceptance Code Bit 1 C1IDAR1.AC0 0 Acceptance Code Bit 0 C1IDAR2 0x0312 msCAN12 Identifier Acceptance Register 2 C1IDAR2.AC7 7 Acceptance Code Bit 7 C1IDAR2.AC6 6 Acceptance Code Bit 6 C1IDAR2.AC5 5 Acceptance Code Bit 5 C1IDAR2.AC4 4 Acceptance Code Bit 4 C1IDAR2.AC3 3 Acceptance Code Bit 3 C1IDAR2.AC2 2 Acceptance Code Bit 2 C1IDAR2.AC1 1 Acceptance Code Bit 1 C1IDAR2.AC0 0 Acceptance Code Bit 0 C1IDAR3 0x0313 msCAN12 Identifier Acceptance Register 3 C1IDAR3.AC7 7 Acceptance Code Bit 7 C1IDAR3.AC6 6 Acceptance Code Bit 6 C1IDAR3.AC5 5 Acceptance Code Bit 5 C1IDAR3.AC4 4 Acceptance Code Bit 4 C1IDAR3.AC3 3 Acceptance Code Bit 3 C1IDAR3.AC2 2 Acceptance Code Bit 2 C1IDAR3.AC1 1 Acceptance Code Bit 1 C1IDAR3.AC0 0 Acceptance Code Bit 0 C1IDMR0 0x0314 msCAN12 Identifier Mask Register 0 C1IDMR0.AM7 7 Acceptance Mask Bit 7 C1IDMR0.AM6 6 Acceptance Mask Bit 6 C1IDMR0.AM5 5 Acceptance Mask Bit 5 C1IDMR0.AM4 4 Acceptance Mask Bit 4 C1IDMR0.AM3 3 Acceptance Mask Bit 3 C1IDMR0.AM2 2 Acceptance Mask Bit 2 C1IDMR0.AM1 1 Acceptance Mask Bit 1 C1IDMR0.AM0 0 Acceptance Mask Bit 0 C1IDMR1 0x0315 msCAN12 Identifier Mask Register 1 C1IDMR1.AM7 7 Acceptance Mask Bit 7 C1IDMR1.AM6 6 Acceptance Mask Bit 6 C1IDMR1.AM5 5 Acceptance Mask Bit 5 C1IDMR1.AM4 4 Acceptance Mask Bit 4 C1IDMR1.AM3 3 Acceptance Mask Bit 3 C1IDMR1.AM2 2 Acceptance Mask Bit 2 C1IDMR1.AM1 1 Acceptance Mask Bit 1 C1IDMR1.AM0 0 Acceptance Mask Bit 0 C1IDMR2 0x0316 msCAN12 Identifier Mask Register 2 C1IDMR2.AM7 7 Acceptance Mask Bit 7 C1IDMR2.AM6 6 Acceptance Mask Bit 6 C1IDMR2.AM5 5 Acceptance Mask Bit 5 C1IDMR2.AM4 4 Acceptance Mask Bit 4 C1IDMR2.AM3 3 Acceptance Mask Bit 3 C1IDMR2.AM2 2 Acceptance Mask Bit 2 C1IDMR2.AM1 1 Acceptance Mask Bit 1 C1IDMR2.AM0 0 Acceptance Mask Bit 0 C1IDMR3 0x0317 msCAN12 Identifier Mask Register 3 C1IDMR3.AM7 7 Acceptance Mask Bit 7 C1IDMR3.AM6 6 Acceptance Mask Bit 6 C1IDMR3.AM5 5 Acceptance Mask Bit 5 C1IDMR3.AM4 4 Acceptance Mask Bit 4 C1IDMR3.AM3 3 Acceptance Mask Bit 3 C1IDMR3.AM2 2 Acceptance Mask Bit 2 C1IDMR3.AM1 1 Acceptance Mask Bit 1 C1IDMR3.AM0 0 Acceptance Mask Bit 0 C1IDAR4 0x0318 msCAN12 Identifier Acceptance Register 4 C1IDAR4.AC7 7 Acceptance Code Bit 7 C1IDAR4.AC6 6 Acceptance Code Bit 6 C1IDAR4.AC5 5 Acceptance Code Bit 5 C1IDAR4.AC4 4 Acceptance Code Bit 4 C1IDAR4.AC3 3 Acceptance Code Bit 3 C1IDAR4.AC2 2 Acceptance Code Bit 2 C1IDAR4.AC1 1 Acceptance Code Bit 1 C1IDAR4.AC0 0 Acceptance Code Bit 0 C1IDAR5 0x0319 msCAN12 Identifier Acceptance Register 5 C1IDAR5.AC7 7 Acceptance Code Bit 7 C1IDAR5.AC6 6 Acceptance Code Bit 6 C1IDAR5.AC5 5 Acceptance Code Bit 5 C1IDAR5.AC4 4 Acceptance Code Bit 4 C1IDAR5.AC3 3 Acceptance Code Bit 3 C1IDAR5.AC2 2 Acceptance Code Bit 2 C1IDAR5.AC1 1 Acceptance Code Bit 1 C1IDAR5.AC0 0 Acceptance Code Bit 0 C1IDAR6 0x031A msCAN12 Identifier Acceptance Register 6 C1IDAR6.AC7 7 Acceptance Code Bit 7 C1IDAR6.AC6 6 Acceptance Code Bit 6 C1IDAR6.AC5 5 Acceptance Code Bit 5 C1IDAR6.AC4 4 Acceptance Code Bit 4 C1IDAR6.AC3 3 Acceptance Code Bit 3 C1IDAR6.AC2 2 Acceptance Code Bit 2 C1IDAR6.AC1 1 Acceptance Code Bit 1 C1IDAR6.AC0 0 Acceptance Code Bit 0 C1IDAR7 0x031B msCAN12 Identifier Acceptance Register 7 C1IDAR7.AC7 7 Acceptance Code Bit 7 C1IDAR7.AC6 6 Acceptance Code Bit 6 C1IDAR7.AC5 5 Acceptance Code Bit 5 C1IDAR7.AC4 4 Acceptance Code Bit 4 C1IDAR7.AC3 3 Acceptance Code Bit 3 C1IDAR7.AC2 2 Acceptance Code Bit 2 C1IDAR7.AC1 1 Acceptance Code Bit 1 C1IDAR7.AC0 0 Acceptance Code Bit 0 C1IDMR4 0x031C msCAN12 Identifier Mask Register 4 C1IDMR4.AM7 7 Acceptance Mask Bit 7 C1IDMR4.AM6 6 Acceptance Mask Bit 6 C1IDMR4.AM5 5 Acceptance Mask Bit 5 C1IDMR4.AM4 4 Acceptance Mask Bit 4 C1IDMR4.AM3 3 Acceptance Mask Bit 3 C1IDMR4.AM2 2 Acceptance Mask Bit 2 C1IDMR4.AM1 1 Acceptance Mask Bit 1 C1IDMR4.AM0 0 Acceptance Mask Bit 0 C1IDMR5 0x031D msCAN12 Identifier Mask Register 5 C1IDMR5.AM7 7 Acceptance Mask Bit 7 C1IDMR5.AM6 6 Acceptance Mask Bit 6 C1IDMR5.AM5 5 Acceptance Mask Bit 5 C1IDMR5.AM4 4 Acceptance Mask Bit 4 C1IDMR5.AM3 3 Acceptance Mask Bit 3 C1IDMR5.AM2 2 Acceptance Mask Bit 2 C1IDMR5.AM1 1 Acceptance Mask Bit 1 C1IDMR5.AM0 0 Acceptance Mask Bit 0 C1IDMR6 0x031E msCAN12 Identifier Mask Register 6 C1IDMR6.AM7 7 Acceptance Mask Bit 7 C1IDMR6.AM6 6 Acceptance Mask Bit 6 C1IDMR6.AM5 5 Acceptance Mask Bit 5 C1IDMR6.AM4 4 Acceptance Mask Bit 4 C1IDMR6.AM3 3 Acceptance Mask Bit 3 C1IDMR6.AM2 2 Acceptance Mask Bit 2 C1IDMR6.AM1 1 Acceptance Mask Bit 1 C1IDMR6.AM0 0 Acceptance Mask Bit 0 C1IDMR7 0x031F msCAN12 Identifier Mask Register 7 C1IDMR7.AM7 7 Acceptance Mask Bit 7 C1IDMR7.AM6 6 Acceptance Mask Bit 6 C1IDMR7.AM5 5 Acceptance Mask Bit 5 C1IDMR7.AM4 4 Acceptance Mask Bit 4 C1IDMR7.AM3 3 Acceptance Mask Bit 3 C1IDMR7.AM2 2 Acceptance Mask Bit 2 C1IDMR7.AM1 1 Acceptance Mask Bit 1 C1IDMR7.AM0 0 Acceptance Mask Bit 0 RESERVED0320 0x0320 RESERVED RESERVED0321 0x0321 RESERVED RESERVED0322 0x0322 RESERVED RESERVED0323 0x0323 RESERVED RESERVED0324 0x0324 RESERVED RESERVED0325 0x0325 RESERVED RESERVED0326 0x0326 RESERVED RESERVED0327 0x0327 RESERVED RESERVED0328 0x0328 RESERVED RESERVED0329 0x0329 RESERVED RESERVED032A 0x032A RESERVED RESERVED032B 0x032B RESERVED RESERVED032C 0x032C RESERVED RESERVED032D 0x032D RESERVED RESERVED032E 0x032E RESERVED RESERVED032F 0x032F RESERVED RESERVED0330 0x0330 RESERVED RESERVED0331 0x0331 RESERVED RESERVED0332 0x0332 RESERVED RESERVED0333 0x0333 RESERVED RESERVED0334 0x0334 RESERVED RESERVED0335 0x0335 RESERVED RESERVED0336 0x0336 RESERVED RESERVED0337 0x0337 RESERVED RESERVED0338 0x0338 RESERVED RESERVED0339 0x0339 RESERVED RESERVED033A 0x033A RESERVED RESERVED033B 0x033B RESERVED RESERVED033C 0x033C RESERVED PCTLCAN1 0x033D msCAN12 Port CAN Control Register PCTLCAN1.PUPCAN 1 Pull-Up Enable Port CAN PCTLCAN1.RDPCAN 0 Reduced Drive Port CAN PORTCAN1 0x033E msCAN12 Port CAN Data Register PORTCAN1.PCAN7 7 Port CAN Data Bit 7 PORTCAN1.PCAN6 6 Port CAN Data Bit 6 PORTCAN1.PCAN5 5 Port CAN Data Bit 5 PORTCAN1.PCAN4 4 Port CAN Data Bit 4 PORTCAN1.PCAN3 3 Port CAN Data Bit 3 PORTCAN1.PCAN2 2 Port CAN Data Bit 2 PORTCAN1.TxCAN 1 PORTCAN1.RxCAN 0 DDRCAN1 0x033F msCAN12 Port CAN Data Direction Register DDRCAN1.DDCAN7 7 DDRCAN1.DDCAN6 6 DDRCAN1.DDCAN5 5 DDRCAN1.DDCAN4 4 DDRCAN1.DDCAN3 3 DDRCAN1.DDCAN2 2 .68HC912DG128A ; http://e-www.motorola.com/brdata/PDFDB/docs/MC68HC912DT128A.pdf ; 68HC912DG_DT128A.pdf ; MEMORY MAP area DATA FSR_0 0x0000:0x0140 area DATA RxFG0 0x0140:0x0150 FOREGROUND RECEIVE BUFFER 0 area DATA Tx00 0x0150:0x0160 TRANSMIT BUFFER 00 area DATA Tx01 0x0160:0x0170 TRANSMIT BUFFER 01 area DATA Tx02 0x0170:0x0180 TRANSMIT BUFFER 02 area BSS RESERVED 0x0180:0x01E2 area DATA FSR_1 0x01E2:0x0200 area BSS RESERVED 0x0200:0x0300 area DATA FSR_2 0x0300:0x0340 area DATA RxFG1 0x0340:0x0350 FOREGROUND RECEIVE BUFFER 1 area DATA Tx10 0x0350:0x0360 TRANSMIT BUFFER 10 area DATA Tx11 0x0360:0x0370 TRANSMIT BUFFER 11 area DATA Tx12 0x0370:0x0380 TRANSMIT BUFFER 12 area BSS RESERVED 0x0380:0x0800 area DATA EEPROM 0x0800:0x1000 area BSS RESERVED 0x1000:0x2000 area DATA RAM 0x2000:0x4000 area DATA ROM 0x4000:0xFF00 Flash area DATA USER_VEC 0xFF00:0x10000 ; Interrupt and reset vector assignments interrupt _RESET 0xFFFE Reset interrupt _COPCTL 0xFFFC Clock monitor fail reset interrupt _COP_F_R 0xFFFA COP failure reset interrupt _UIT 0xFFF8 Unimplemented instruction trap interrupt _SWI 0xFFF6 SWI interrupt _XIRQ 0xFFF4 XIRQ interrupt _INTCR_IRQEN 0xFFF2 IRQ interrupt _RTICTL_RTIE 0xFFF0 Real time interrupt interrupt _TMSK1_C0I 0xFFEE Timer channel 0 interrupt _TMSK1_C1I 0xFFEC Timer channel 1 interrupt _TMSK1_C2I 0xFFEA Timer channel 2 interrupt _TMSK1_C3I 0xFFE8 Timer channel 3 interrupt _TMSK1_C4I 0xFFE6 Timer channel 4 interrupt _TMSK1_C5I 0xFFE4 Timer channel 5 interrupt _TMSK1_C6I 0xFFE2 Timer channel 6 interrupt _TMSK1_C7I 0xFFE0 Timer channel 7 interrupt _TMSK2_TOI 0xFFDE Timer overflow interrupt _PACTL_PAOVI 0xFFDC Pulse accumulator overflow interrupt _PACTL_PAI 0xFFDA Pulse accumulator input edge interrupt _SP0CR1_SPIE 0xFFD8 SPI serial transfer complete interrupt _SC0CR2 0xFFD6 SCI 0 interrupt _SC1CR2 0xFFD4 SCI 1 interrupt _ATDxCTL2_ASCIE 0xFFD2 ATD0 or ATD1 interrupt _C0RIER_WUPIE 0xFFD0 MSCAN 0 wake-up interrupt _KWIEJ_KWIEH 0xFFCE Key wake-up J or H interrupt _MCCTL_MCZI 0xFFCC Modulus down counter underflow interrupt _PBCTL_PBOVI 0xFFCA Pulse Accumulator B Overflow interrupt _C0RIER 0xFFC8 MSCAN 0 errors interrupt _C0RIER_RXFIE 0xFFC6 MSCAN 0 receive interrupt _C0TCR_TXEIE 0xFFC4 MSCAN 0 transmit interrupt _PLLCR_LOCKIE_LHIE 0xFFC2 CGM lock and limp home interrupt _IBCR_IBIE 0xFFC0 IIC Bus interrupt _C1RIER_WUPIE 0xFFBE MSCAN 1 wake-up interrupt _C1RIER 0xFFBC MSCAN 1 errors interrupt _C1RIER_RXFIE 0xFFBA MSCAN 1 receive interrupt _C1TCR_TXEIE 0xFFB8 MSCAN 1 transmit ; INPUT/ OUTPUT PORTS PORTA 0x0000 Port A Data Register PORTA.PA7 7 Port A Data Bit 7 PORTA.PA6 6 Port A Data Bit 6 PORTA.PA5 5 Port A Data Bit 5 PORTA.PA4 4 Port A Data Bit 4 PORTA.PA3 3 Port A Data Bit 3 PORTA.PA2 2 Port A Data Bit 2 PORTA.PA1 1 Port A Data Bit 1 PORTA.PA0 0 Port A Data Bit 0 PORTB 0x0001 Port B Data Register PORTB.PB7 7 Port B Data Bit 7 PORTB.PB6 6 Port B Data Bit 6 PORTB.PB5 5 Port B Data Bit 5 PORTB.PB4 4 Port B Data Bit 4 PORTB.PB3 3 Port B Data Bit 3 PORTB.PB2 2 Port B Data Bit 2 PORTB.PB1 1 Port B Data Bit 1 PORTB.PB0 0 Port B Data Bit 0 DDRA 0x0002 Port A Data Direction Register DDRA.DDA7 7 Port A Data Direction Bit 7 DDRA.DDA6 6 Port A Data Direction Bit 6 DDRA.DDA5 5 Port A Data Direction Bit 5 DDRA.DDA4 4 Port A Data Direction Bit 4 DDRA.DDA3 3 Port A Data Direction Bit 3 DDRA.DDA2 2 Port A Data Direction Bit 2 DDRA.DDA1 1 Port A Data Direction Bit 1 DDRA.DDA0 0 Port A Data Direction Bit 0 DDRB 0x0003 Port B Data Direction Register DDRB.DDB7 7 Port B Data Direction Bit 7 DDRB.DDB6 6 Port B Data Direction Bit 6 DDRB.DDB5 5 Port B Data Direction Bit 5 DDRB.DDB4 4 Port B Data Direction Bit 4 DDRB.DDB3 3 Port B Data Direction Bit 3 DDRB.DDB2 2 Port B Data Direction Bit 2 DDRB.DDB1 1 Port B Data Direction Bit 1 DDRB.DDB0 0 Port B Data Direction Bit 0 RESERVED0004 0x0004 RESERVED RESERVED0005 0x0005 RESERVED RESERVED0006 0x0006 RESERVED RESERVED0007 0x0007 RESERVED PORTE 0x0008 Port E Data Register PORTE.PE7 7 Port E Data Bit 7 PORTE.PE6 6 Port E Data Bit 6 PORTE.PE5 5 Port E Data Bit 5 PORTE.PE4 4 Port E Data Bit 4 PORTE.PE3 3 Port E Data Bit 3 PORTE.PE2 2 Port E Data Bit 2 PORTE.PE1 1 Port E Data Bit 1 PORTE.PE0 0 Port E Data Bit 0 DDRE 0x0009 Port E Data Direction Register DDRE.DDE7 7 Port E Data Direction Bit 7 DDRE.DDE6 6 Port E Data Direction Bit 6 DDRE.DDE5 5 Port E Data Direction Bit 5 DDRE.DDE4 4 Port E Data Direction Bit 4 DDRE.DDE3 3 Port E Data Direction Bit 3 DDRE.DDE2 2 Port E Data Direction Bit 2 PEAR 0x000A Port E Assignment Register PEAR.NDBE 7 No Data Bus Enable PEAR.CGMTE 6 Clock Generator Module Testing Enable PEAR.PIPOE 5 Pipe Status Signal Output Enable PEAR.NECLK 4 No External E Clock PEAR.LSTRE 3 Low Strobe (LSTRB) Enable PEAR.RDWE 2 Read/Write Enable PEAR.CALE 1 Calibration Reference Enable PEAR.DBENE 0 DBE or Inverted E Clock on PE7 MODE 0x000B Mode Register MODE.SMODN 7 Mode Select Special MODE.MODB 6 Mode Select B MODE.MODA 5 Mode Select A MODE.ESTR 4 E Clock Stretch Enable MODE.IVIS 3 Internal Visibility MODE.EBSWAI 2 External Bus Module Stop in Wait Control MODE.EMK 1 Emulate Port K MODE.EME 0 PUCR 0x000C Pull-Up Control Register PUCR.PUPK 7 Pull-Up Port K Enable PUCR.PUPJ 6 Pull-Up or Pull-Down Port J Enable PUCR.PUPH 5 Pull-Up or Pull-Down Port H Enable PUCR.PUPE 4 Pull-Up Port E Enable PUCR.PUPB 1 Pull-Up Port B Enable PUCR.PUPA 0 Pull-Up Port A Enable RDRIV 0x000D Reduced Drive of I/O Lines RDRIV.RDPK 7 Reduced Drive of Port K RDRIV.RDPJ 6 Reduced Drive of Port J RDRIV.RDPH 5 Reduced Drive of Port H RDRIV.RDPE 4 Reduced Drive of Port E RDRIV.RDPB 1 Reduced Drive of Port B RDRIV.RDPA 0 Reduced Drive of Port A RESERVED000E 0x000E RESERVED RESERVED000F 0x000F RESERVED INITRM 0x0010 Initialization of Internal RAM Position Register INITRM.RAM15 7 Internal RAM map position 15 INITRM.RAM14 6 Internal RAM map position 14 INITRM.RAM13 5 Internal RAM map position 13 INITRG 0x0011 Initialization of Internal Register Position Register INITRG.REG15 7 Internal register map position 15 INITRG.REG14 6 Internal register map position 14 INITRG.REG13 5 Internal register map position 13 INITRG.REG12 4 Internal register map position 12 INITRG.REG11 3 Internal register map position 11 INITEE 0x0012 Initialization of Internal EEPROM Position Register INITEE.EE15 7 Internal EEPROM map position 15 INITEE.EE14 6 Internal EEPROM map position 14 INITEE.EE13 5 Internal EEPROM map position 13 INITEE.EE12 4 Internal EEPROM map position 12 INITEE.EEON 0 internal EEPROM On (Enabled) MISC 0x0013 Miscellaneous Mapping Control Register MISC.ROMTST 7 FLASH EEPROM Test mode MISC.NDRF 6 Narrow Data Bus for Register-Following Map Space MISC.RFSTR1 5 Register Following Stretch 1 MISC.RFSTR0 4 Register Following Stretch 0 MISC.EXSTR1 3 External Access Stretch 1 MISC.EXSTR0 2 External Access Stretch 0 MISC.ROMHM 1 FLASH EEPROM only in second Half of Map MISC.ROMON 0 Enable FLASH EEPROM RTICTL 0x0014 Real-Time Interrupt Control Register RTICTL.RTIE 7 Real Time Interrupt Enable RTICTL.RSWAI 6 RTI and COP Stop While in Wait RTICTL.RSBCK 5 RTI and COP Stop While in Background Debug Mode RTICTL.RTBYP 3 Real Time Interrupt Divider Chain Bypass RTICTL.RTR2 2 Real-Time Interrupt Rate Select 2 RTICTL.RTR1 1 Real-Time Interrupt Rate Select 1 RTICTL.RTR0 0 Real-Time Interrupt Rate Select 0 RTIFLG 0x0015 Real Time Interrupt Flag Register RTIFLG.RTIF 7 Real Time Interrupt Flag COPCTL 0x0016 COP Control Register COPCTL.CME 7 Clock Monitor Enable COPCTL.FCME 6 Force Clock Monitor Enable COPCTL.FCMCOP 5 Force Clock Monitor Reset or COP Watchdog Reset COPCTL.WCOP 4 Window COP mode COPCTL.DISR 3 Disable Resets from COP Watchdog and Clock Monitor COPCTL.CR2 2 COP Watchdog Timer Rate select bit 2 COPCTL.CR1 1 COP Watchdog Timer Rate select bit 1 COPCTL.CR0 0 COP Watchdog Timer Rate select bit 0 COPRST 0x0017 Arm/Reset COP Timer Register ITST0 0x0018 Interrupt Test Register 0 ITST0.ITE6 7 ITST0.ITE8 6 ITST0.ITEA 5 ITST0.ITEC 4 ITST0.ITEE 3 ITST0.ITF0 2 ITST0.ITF2 1 ITST0.ITF4 0 ITST1 0x0019 Interrupt Test Register 1 ITST1.ITD6 7 ITST1.ITD8 6 ITST1.ITDA 5 ITST1.ITDC 4 ITST1.ITDE 3 ITST1.ITE0 2 ITST1.ITE2 1 ITST1.ITE4 0 ITST2 0x001A Interrupt Test Register 2 ITST2.ITC6 7 ITST2.ITC8 6 ITST2.ITCA 5 ITST2.ITCC 4 ITST2.ITCE 3 ITST2.ITD0 2 ITST2.ITD2 1 ITST2.ITD4 0 ITST3 0x001B Interrupt Test Register 3 ITST3.ITB6 7 ITST3.ITB8 6 ITST3.ITBA 5 ITST3.ITBC 4 ITST3.ITBE 3 ITST3.ITC0 2 ITST3.ITC2 1 ITST3.ITC4 0 RESERVED001C 0x001C RESERVED RESERVED001D 0x001D RESERVED INTCR 0x001E Interrupt Control Register INTCR.IRQE 7 IRQ Select Edge Sensitive Only INTCR.IRQEN 6 External IRQ Enable INTCR.DLY 5 Enable Oscillator Start-up Delay on Exit from STOP HPRIO 0x001F Highest Priority I Interrupt HPRIO.PSEL6 6 HPRIO.PSEL5 5 HPRIO.PSEL4 4 HPRIO.PSEL3 3 HPRIO.PSEL2 2 HPRIO.PSEL1 1 BRKCT0 0x0020 Breakpoint Control Register 0 BRKCT0.BKEN1 7 Breakpoint Mode Enable 1 BRKCT0.BKEN0 6 Breakpoint Mode Enable 0 BRKCT0.BKPM 5 Break on Program Addresses BRKCT0.BK1ALE 3 Breakpoint 1 Range Control BRKCT0.BK0ALE 2 Breakpoint 0 Range Control BRKCT1 0x0021 Breakpoint Control Register 1 BRKCT1.BKDBE 6 Enable Data Bus BRKCT1.BKMBH 5 Breakpoint Mask High BRKCT1.BKMBL 4 Breakpoint Mask Low BRKCT1.BK1RWE 3 R/W Compare Enable BRKCT1.BK1RW 2 R/W Compare Value BRKCT1.BK0RWE 1 R/W Compare Enable BRKCT1.BK0RW 0 R/W Compare Value BRKAH 0x0022 Breakpoint Address Register, High Byte BRKAL 0x0023 Breakpoint Address Register, Low Byte BRKDH 0x0024 Breakpoint Data Register, High Byte BRKDL 0x0025 Breakpoint Data Register, Low Byte RESERVED0026 0x0026 RESERVED RESERVED0027 0x0027 RESERVED PORTJ 0x0028 Port J Data Register PORTJ.PJ7 7 Port J Data Bit 7 PORTJ.PJ6 6 Port J Data Bit 6 PORTJ.PJ5 5 Port J Data Bit 5 PORTJ.PJ4 4 Port J Data Bit 4 PORTJ.PJ3 3 Port J Data Bit 3 PORTJ.PJ2 2 Port J Data Bit 2 PORTJ.PJ1 1 Port J Data Bit 1 PORTJ.PJ0 0 Port J Data Bit 0 PORTH 0x0029 Port H Data Register PORTH.PH7 7 Port H Data Bit 7 PORTH.PH6 6 Port H Data Bit 6 PORTH.PH5 5 Port H Data Bit 5 PORTH.PH4 4 Port H Data Bit 4 PORTH.PH3 3 Port H Data Bit 3 PORTH.PH2 2 Port H Data Bit 2 PORTH.PH1 1 Port H Data Bit 1 PORTH.PH0 0 Port H Data Bit 0 DDRJ 0x002A Port J Data Direction Register DDRJ.DDRJ7 7 Data Direction Port J Bit 7 DDRJ.DDRJ6 6 Data Direction Port J Bit 6 DDRJ.DDRJ5 5 Data Direction Port J Bit 5 DDRJ.DDRJ4 4 Data Direction Port J Bit 4 DDRJ.DDRJ3 3 Data Direction Port J Bit 3 DDRJ.DDRJ2 2 Data Direction Port J Bit 2 DDRJ.DDRJ1 1 Data Direction Port J Bit 1 DDRJ.DDRJ0 0 Data Direction Port J Bit 0 DDRH 0x002B Port J Data Direction Register DDRH.DDRH7 7 Data Direction Port H Bit 7 DDRH.DDRH6 6 Data Direction Port H Bit 6 DDRH.DDRH5 5 Data Direction Port H Bit 5 DDRH.DDRH4 4 Data Direction Port H Bit 4 DDRH.DDRH3 3 Data Direction Port H Bit 3 DDRH.DDRH2 2 Data Direction Port H Bit 2 DDRH.DDRH1 1 Data Direction Port H Bit 1 DDRH.DDRH0 0 Data Direction Port H Bit 0 KWIEJ 0x002C Key Wake-up Port J Interrupt Enable Register KWIEJ.KWIEJ7 7 Key Wake-up Port J Interrupt Enable 7 KWIEJ.KWIEJ6 6 Key Wake-up Port J Interrupt Enable 6 KWIEJ.KWIEJ5 5 Key Wake-up Port J Interrupt Enable 5 KWIEJ.KWIEJ4 4 Key Wake-up Port J Interrupt Enable 4 KWIEJ.KWIEJ3 3 Key Wake-up Port J Interrupt Enable 3 KWIEJ.KWIEJ2 2 Key Wake-up Port J Interrupt Enable 2 KWIEJ.KWIEJ1 1 Key Wake-up Port J Interrupt Enable 1 KWIEJ.KWIEJ0 0 Key Wake-up Port J Interrupt Enable 0 KWIEH 0x002D Key Wake-up Port H Interrupt Enable Register KWIEH.KWIEH7 7 Key Wake-up Port H Interrupt Enable 7 KWIEH.KWIEH6 6 Key Wake-up Port H Interrupt Enable 6 KWIEH.KWIEH5 5 Key Wake-up Port H Interrupt Enable 5 KWIEH.KWIEH4 4 Key Wake-up Port H Interrupt Enable 4 KWIEH.KWIEH3 3 Key Wake-up Port H Interrupt Enable 3 KWIEH.KWIEH2 2 Key Wake-up Port H Interrupt Enable 2 KWIEH.KWIEH1 1 Key Wake-up Port H Interrupt Enable 1 KWIEH.KWIEH0 0 Key Wake-up Port H Interrupt Enable 0 KWIFJ 0x002E Key Wake-up Port J Flag Register KWIFJ.KWIFJ7 7 Key Wake-up Port J Flag 7 KWIFJ.KWIFJ6 6 Key Wake-up Port J Flag 6 KWIFJ.KWIFJ5 5 Key Wake-up Port J Flag 5 KWIFJ.KWIFJ4 4 Key Wake-up Port J Flag 4 KWIFJ.KWIFJ3 3 Key Wake-up Port J Flag 3 KWIFJ.KWIFJ2 2 Key Wake-up Port J Flag 2 KWIFJ.KWIFJ1 1 Key Wake-up Port J Flag 1 KWIFJ.KWIFJ0 0 Key Wake-up Port J Flag 0 KWIFH 0x002F Key Wake-up Port H Flag Register KWIFH.KWIFH7 7 Key Wake-up Port H Flag 7 KWIFH.KWIFH6 6 Key Wake-up Port H Flag 6 KWIFH.KWIFH5 5 Key Wake-up Port H Flag 5 KWIFH.KWIFH4 4 Key Wake-up Port H Flag 4 KWIFH.KWIFH3 3 Key Wake-up Port H Flag 3 KWIFH.KWIFH2 2 Key Wake-up Port H Flag 2 KWIFH.KWIFH1 1 Key Wake-up Port H Flag 1 KWIFH.KWIFH0 0 Key Wake-up Port H Flag 0 KWPJ 0x0030 Key Wake-up Port J Polarity Register KWPJ.KWPJ7 7 Key Wake-up Port J Polarity Select 7 KWPJ.KWPJ6 6 Key Wake-up Port J Polarity Select 6 KWPJ.KWPJ5 5 Key Wake-up Port J Polarity Select 5 KWPJ.KWPJ4 4 Key Wake-up Port J Polarity Select 4 KWPJ.KWPJ3 3 Key Wake-up Port J Polarity Select 3 KWPJ.KWPJ2 2 Key Wake-up Port J Polarity Select 2 KWPJ.KWPJ1 1 Key Wake-up Port J Polarity Select 1 KWPJ.KWPJ0 0 Key Wake-up Port J Polarity Select 0 KWPH 0x0031 Key Wake-up Port H Polarity Register KWPH.KWPH7 7 Key Wake-up Port H Polarity Select 7 KWPH.KWPH6 6 Key Wake-up Port H Polarity Select 6 KWPH.KWPH5 5 Key Wake-up Port H Polarity Select 5 KWPH.KWPH4 4 Key Wake-up Port H Polarity Select 4 KWPH.KWPH3 3 Key Wake-up Port H Polarity Select 3 KWPH.KWPH2 2 Key Wake-up Port H Polarity Select 2 KWPH.KWPH1 1 Key Wake-up Port H Polarity Select 1 KWPH.KWPH0 0 Key Wake-up Port H Polarity Select 0 RESERVED0032 0x0032 RESERVED RESERVED0033 0x0033 RESERVED RESERVED0034 0x0034 RESERVED RESERVED0035 0x0035 RESERVED RESERVED0036 0x0036 RESERVED RESERVED0037 0x0037 RESERVED SYNR 0x0038 Synthesizer Register SYNR.SYN5 5 SYNR.SYN4 4 SYNR.SYN3 3 SYNR.SYN2 2 SYNR.SYN1 1 SYNR.SYN0 0 REFDV 0x0039 Reference Divider Register REFDV.REFDV2 2 REFDV.REFDV1 1 REFDV.REFDV0 0 CGTFLG 0x003A Clock Generator Test Register CGTFLG.TSTOUT7 7 CGTFLG.TSTOUT6 6 CGTFLG.TSTOUT5 5 CGTFLG.TSTOUT4 4 CGTFLG.TSTOUT3 3 CGTFLG.TSTOUT2 2 CGTFLG.TSTOUT1 1 CGTFLG.TSTOUT0 0 PLLFLG 0x003B PLL Flags PLLFLG.LOCKIF 7 PLL Lock Interrupt Flag PLLFLG.LOCK 6 Locked Phase Lock Loop Circuit PLLFLG.LHIF 1 Limp-Home Interrupt Flag PLLFLG.LHOME 0 Limp-Home Mode Status PLLCR 0x003C PLL Control Register PLLCR.LOCKIE 7 PLL LOCK Interrupt Enable PLLCR.PLLON 6 Phase Lock Loop On PLLCR.AUTO 5 Automatic Bandwidth Control PLLCR.ACQ 4 Not in Acquisition PLLCR.PSTP 2 Pseudo-STOP Enable PLLCR.LHIE 1 Limp-Home Interrupt Enable PLLCR.NOLHM 0 No Limp-Home Mode CLKSEL 0x003D Clock Generator Clock select Register CLKSEL.BCSP 6 Bus Clock Select PLL CLKSEL.BCSS 5 Bus Clock Select Slow CLKSEL.MCS 2 Module Clock Select SLOW 0x003E Slow mode Divider Register SLOW.SLDV5 5 SLOW.SLDV4 4 SLOW.SLDV3 3 SLOW.SLDV2 2 SLOW.SLDV1 1 SLOW.SLDV0 0 CGTCTL 0x003F CGTCTL CGTCTL.OPNLE 7 CGTCTL.TRK 6 CGTCTL.TSTCLKE 5 CGTCTL.TST4 4 CGTCTL.TST3 3 CGTCTL.TST2 2 CGTCTL.TST1 1 CGTCTL.TST0 0 PWCLK 0x0040 PWM Clocks and Concatenate PWCLK.CON23 7 Concatenate PWM Channels 2 and 3 PWCLK.CON01 6 Concatenate PWM Channels 0 and 1 PWCLK.PCKA2 5 Prescaler for Clock A 2 PWCLK.PCKA1 4 Prescaler for Clock A 1 PWCLK.PCKA0 3 Prescaler for Clock A 0 PWCLK.PCKB2 2 Prescaler for Clock B 2 PWCLK.PCKB1 1 Prescaler for Clock B 1 PWCLK.PCKB0 0 Prescaler for Clock B 0 PWPOL 0x0041 PWM Clock Select and Polarity PWPOL.PCLK3 7 PWM Channel 3 Clock Select PWPOL.PCLK2 6 PWM Channel 2 Clock Select PWPOL.PCLK1 5 PWM Channel 1 Clock Select PWPOL.PCLK0 4 PWM Channel 0 Clock Select PWPOL.PPOL3 3 PWM Channel 3 Polarity PWPOL.PPOL2 2 PWM Channel 2 Polarity PWPOL.PPOL1 1 PWM Channel 1 Polarity PWPOL.PPOL0 0 PWM Channel 0 Polarity PWEN 0x0042 PWM Enable PWEN.PWEN3 3 PWM Channel 3 Enable PWEN.PWEN2 2 PWM Channel 2 Enable PWEN.PWEN1 1 PWM Channel 1 Enable PWEN.PWEN0 0 PWM Channel 0 Enable PWPRES 0x0043 PWM Prescale Counter PWSCAL0 0x0044 PWM Scale Register 0 PWSCNT0 0x0045 PWM Scale Counter 0 Value PWSCAL1 0x0046 PWM Scale Register 1 PWSCNT1 0x0047 PWM Scale Counter 1 Value PWCNT0 0x0048 PWM Channel Counter 0 PWCNT1 0x0049 PWM Channel Counter 1 PWCNT2 0x004A PWM Channel Counter 2 PWCNT3 0x004B PWM Channel Counter 3 PWPER0 0x004C PWM Channel Period Register 0 PWPER1 0x004D PWM Channel Period Register 1 PWPER2 0x004E PWM Channel Period Register 2 PWPER3 0x004F PWM Channel Period Register 3 PWDTY0 0x0050 PWM Channel Duty Register 0 PWDTY1 0x0051 PWM Channel Duty Register 1 PWDTY2 0x0052 PWM Channel Duty Register 2 PWDTY3 0x0053 PWM Channel Duty Register 3 PWCTL 0x0054 PWM Control Register PWCTL.PSWAI 4 PWM Halts while in Wait Mode PWCTL.CENTR 3 Center-Aligned Output Mode PWCTL.RDPP 2 Reduced Drive of Port P PWCTL.PUPP 1 Pull-Up Port P Enable PWCTL.PSBCK 0 PWM Stops while in Background Mode PWTST 0x0055 PWM Special Mode Register ("Test") PWTST.DISCR 7 Disable Reset of Channel Counter on Write to Channel Counter PWTST.DISCP 6 Disable Compare Count Period PWTST.DISCAL 5 Disable Load of Scale-Counters on Write to the Associated Scale-Registers PORTP 0x0056 Port P Data Register PORTP.PP7 7 Port P Data Bit 7 PORTP.PP6 6 Port P Data Bit 6 PORTP.PP5 5 Port P Data Bit 5 PORTP.PP4 4 Port P Data Bit 4 PORTP.PP3 3 Port P Data Bit 3 PORTP.PP2 2 Port P Data Bit 2 PORTP.PP1 1 Port P Data Bit 1 PORTP.PP0 0 Port P Data Bit 0 DDRP 0x0057 Port P Data Direction Register DDRP.DDP7 7 Port P Data Direction Bit 7 DDRP.DDP6 6 Port P Data Direction Bit 6 DDRP.DDP5 5 Port P Data Direction Bit 5 DDRP.DDP4 4 Port P Data Direction Bit 4 DDRP.DDP3 3 Port P Data Direction Bit 3 DDRP.DDP2 2 Port P Data Direction Bit 2 DDRP.DDP1 1 Port P Data Direction Bit 1 DDRP.DDP0 0 Port P Data Direction Bit 0 RESERVED0058 0x0058 RESERVED RESERVED0059 0x0059 RESERVED RESERVED005A 0x005A RESERVED RESERVED005B 0x005B RESERVED RESERVED005C 0x005C RESERVED RESERVED005D 0x005D RESERVED RESERVED005E 0x005E RESERVED RESERVED005F 0x005F RESERVED RESERVED0060 0x0060 RESERVED RESERVED0061 0x0061 RESERVED ATD0CTL2 0x0062 ATD0 Control Register 2 ATD0CTL2.ADPU 7 ATD Disable ATD0CTL2.AFFC 6 ATD Fast Flag Clear All ATD0CTL2.ASWAI 5 ATD Wait Mode ATD0CTL2.DJM 4 Result Register Data Justification Mode ATD0CTL2.DSGN 3 Signed/Unsigned Result Data Mode ATD0CTL2.ASCIE 1 ATD Sequence Complete Interrupt Enable ATD0CTL2.ASCIF 0 ATD Sequence Complete Interrupt Flag ATD0CTL3 0x0063 ATD0 Control Register 3 ATD0CTL3.S1C 3 Conversion Sequence Length (Least Significant Bit) ATD0CTL3.FIFO 2 Result Register FIFO Mode ATD0CTL3.FRZ1 1 Background Debug (Freeze) Enable 1 ATD0CTL3.FRZ0 0 Background Debug (Freeze) Enable 0 ATD0CTL4 0x0064 ATD0 Control Register 4 ATD0CTL4.RES10 7 10 bit Mode ATD0CTL4.SMP1 6 Select Sample Time 1 ATD0CTL4.SMP0 5 Select Sample Time 0 ATD0CTL4.PRS4 4 Select Divide-By Factor for ATD P-Clock Prescaler 4 ATD0CTL4.PRS3 3 Select Divide-By Factor for ATD P-Clock Prescaler 3 ATD0CTL4.PRS2 2 Select Divide-By Factor for ATD P-Clock Prescaler 2 ATD0CTL4.PRS1 1 Select Divide-By Factor for ATD P-Clock Prescaler 1 ATD0CTL4.PRS0 0 Select Divide-By Factor for ATD P-Clock Prescaler 0 ATD0CTL5 0x0065 ATD0 Control Register 5 ATD0CTL5.S8CM 6 Select 8 Channel Mode ATD0CTL5.SCAN 5 Enable Continuous Channel Scan ATD0CTL5.MULT 4 Enable Multichannel Conversion ATD0CTL5.CD 3 Channel Select for Conversion D ATD0CTL5.CC 2 Channel Select for Conversion C ATD0CTL5.CB 1 Channel Select for Conversion B ATD0CTL5.CA 0 Channel Select for Conversion A ATD0STAT0 0x0066 ATD0 Status Register ATD0STAT0.SCF 7 Sequence Complete Flag ATD0STAT0.CC2 2 Conversion Counter for Current Sequence of Four or Eight Conversions 2 ATD0STAT0.CC1 1 Conversion Counter for Current Sequence of Four or Eight Conversions 1 ATD0STAT0.CC0 0 Conversion Counter for Current Sequence of Four or Eight Conversions 0 ATD0STAT1 0x0067 ATD0 Status Register ATD0STAT1.CCF7 7 Conversion Complete Flag 7 ATD0STAT1.CCF6 6 Conversion Complete Flag 6 ATD0STAT1.CCF5 5 Conversion Complete Flag 5 ATD0STAT1.CCF4 4 Conversion Complete Flag 4 ATD0STAT1.CCF3 3 Conversion Complete Flag 3 ATD0STAT1.CCF2 2 Conversion Complete Flag 2 ATD0STAT1.CCF1 1 Conversion Complete Flag 1 ATD0STAT1.CCF0 0 Conversion Complete Flag 0 ATD0TESTH 0x0068 ATD0 Test Register ATD0TESTH.SAR9 7 SAR Data 9 ATD0TESTH.SAR8 6 SAR Data 8 ATD0TESTH.SAR7 5 SAR Data 7 ATD0TESTH.SAR6 4 SAR Data 6 ATD0TESTH.SAR5 3 SAR Data 5 ATD0TESTH.SAR4 2 SAR Data 4 ATD0TESTH.SAR3 1 SAR Data 3 ATD0TESTH.SAR2 0 SAR Data 2 ATD0TESTL 0x0069 ATD0 Test Register ATD0TESTL.SAR1 7 SAR Data 1 ATD0TESTL.SAR0 6 SAR Data 0 ATD0TESTL.RST 5 Module Reset Bit ATD0TESTL.TSTOUT 4 Multiplex Output of TST[3:0] (Factory Use) ATD0TESTL.TST3 3 Test Bit 3 ATD0TESTL.TST2 2 Test Bit 2 ATD0TESTL.TST1 1 Test Bit 1 ATD0TESTL.TST0 0 Test Bit 0 RESERVED006A 0x006A RESERVED RESERVED006B 0x006B RESERVED RESERVED006C 0x006C RESERVED RESERVED006D 0x006D RESERVED RESERVED006E 0x006E RESERVED PORTAD0 0x006F Port AD0 Data Input Register PORTAD0.PAD07 7 Port AD0 Data Input Bit 7 PORTAD0.PAD06 6 Port AD0 Data Input Bit 6 PORTAD0.PAD05 5 Port AD0 Data Input Bit 5 PORTAD0.PAD04 4 Port AD0 Data Input Bit 4 PORTAD0.PAD03 3 Port AD0 Data Input Bit 3 PORTAD0.PAD02 2 Port AD0 Data Input Bit 2 PORTAD0.PAD01 1 Port AD0 Data Input Bit 1 PORTAD0.PAD00 0 Port AD0 Data Input Bit 0 ADR00H 0x0070 A/D Conversion Result Register High 0 ADR00L 0x0071 A/D Conversion Result Register Low 0 ADR01H 0x0072 A/D Conversion Result Register High 1 ADR01L 0x0073 A/D Conversion Result Register Low 1 ADR02H 0x0074 A/D Conversion Result Register High 2 ADR02L 0x0075 A/D Conversion Result Register Low 2 ADR03H 0x0076 A/D Conversion Result Register High 3 ADR03L 0x0077 A/D Conversion Result Register Low 3 ADR04H 0x0078 A/D Conversion Result Register High 4 ADR04L 0x0079 A/D Conversion Result Register Low 4 ADR05H 0x007A A/D Conversion Result Register High 5 ADR05L 0x007B A/D Conversion Result Register Low 5 ADR06H 0x007C A/D Conversion Result Register High 6 ADR06L 0x007D A/D Conversion Result Register Low 6 ADR07H 0x007E A/D Conversion Result Register High 7 ADR07L 0x007F A/D Conversion Result Register Low 7 TIOS 0x0080 Timer Input Capture/Output Compare Select TIOS.IOS7 7 Input Capture or Output Compare Channel Configuration 7 TIOS.IOS6 6 Input Capture or Output Compare Channel Configuration 6 TIOS.IOS5 5 Input Capture or Output Compare Channel Configuration 5 TIOS.IOS4 4 Input Capture or Output Compare Channel Configuration 4 TIOS.IOS3 3 Input Capture or Output Compare Channel Configuration 3 TIOS.IOS2 2 Input Capture or Output Compare Channel Configuration 2 TIOS.IOS1 1 Input Capture or Output Compare Channel Configuration 1 TIOS.IOS0 0 Input Capture or Output Compare Channel Configuration 0 CFORC 0x0081 Timer Compare Force Register CFORC.FOC7 7 Force Output Compare Action for Channel 7 CFORC.FOC6 6 Force Output Compare Action for Channel 6 CFORC.FOC5 5 Force Output Compare Action for Channel 5 CFORC.FOC4 4 Force Output Compare Action for Channel 4 CFORC.FOC3 3 Force Output Compare Action for Channel 3 CFORC.FOC2 2 Force Output Compare Action for Channel 2 CFORC.FOC1 1 Force Output Compare Action for Channel 1 CFORC.FOC0 0 Force Output Compare Action for Channel 0 OC7M 0x0082 Output Compare 7 Mask Register OC7M.OC7M7 7 OC7M.OC7M6 6 OC7M.OC7M5 5 OC7M.OC7M4 4 OC7M.OC7M3 3 OC7M.OC7M2 2 OC7M.OC7M1 1 OC7M.OC7M0 0 OC7D 0x0083 Output Compare 7 Data Register OC7D.OC7D7 7 OC7D.OC7D6 6 OC7D.OC7D5 5 OC7D.OC7D4 4 OC7D.OC7D3 3 OC7D.OC7D2 2 OC7D.OC7D1 1 OC7D.OC7D0 0 TCNTH 0x0084 Timer Count Register High TCNTL 0x0085 Timer Count Register Low TSCR 0x0086 Timer System Control Register TSCR.TEN 7 Timer Enable TSCR.TSWAI 6 Timer Module Stops While in Wait TSCR.TSBCK 5 Timer and Modulus Counter Stop While in Background Mode TSCR.TFFCA 4 Timer Fast Flag Clear All RESERVED0087 0x0087 RESERVED TCTL1 0x0088 Timer Control Register 1 TCTL1.OM7 7 Output Mode 7 TCTL1.OL7 6 Output Level 7 TCTL1.OM6 5 Output Mode 6 TCTL1.OL6 4 Output Level 6 TCTL1.OM5 3 Output Mode 5 TCTL1.OL5 2 Output Level 5 TCTL1.OM4 1 Output Mode 4 TCTL1.OL4 0 Output Level 4 TCTL2 0x0089 Timer Control Register 2 TCTL2.OM3 7 Output Mode 3 TCTL2.OL3 6 Output Level 3 TCTL2.OM2 5 Output Mode 2 TCTL2.OL2 4 Output Level 2 TCTL2.OM1 3 Output Mode 1 TCTL2.OL1 2 Output Level 1 TCTL2.OM0 1 Output Mode 0 TCTL2.OL0 0 Output Level 0 TCTL3 0x008A Timer Control Register 3 TCTL3.EDG7B 7 Input Capture Edge Control 7B TCTL3.EDG7A 6 Input Capture Edge Control 7A TCTL3.EDG6B 5 Input Capture Edge Control 6B TCTL3.EDG6A 4 Input Capture Edge Control 6A TCTL3.EDG5B 3 Input Capture Edge Control 5B TCTL3.EDG5A 2 Input Capture Edge Control 5A TCTL3.EDG4B 1 Input Capture Edge Control 4B TCTL3.EDG4A 0 Input Capture Edge Control 4A TCTL4 0x008B Timer Control Register 4 TCTL4.EDG3B 7 Input Capture Edge Control 3B TCTL4.EDG3A 6 Input Capture Edge Control 3A TCTL4.EDG2B 5 Input Capture Edge Control 2B TCTL4.EDG2A 4 Input Capture Edge Control 2A TCTL4.EDG1B 3 Input Capture Edge Control 1B TCTL4.EDG1A 2 Input Capture Edge Control 1A TCTL4.EDG0B 1 Input Capture Edge Control 0B TCTL4.EDG0A 0 Input Capture Edge Control 0A TMSK1 0x008C Timer Interrupt Mask 1 TMSK1.C7I 7 Input Capture/Output Compare 7 Interrupt Enable TMSK1.C6I 6 Input Capture/Output Compare 6 Interrupt Enable TMSK1.C5I 5 Input Capture/Output Compare 5 Interrupt Enable TMSK1.C4I 4 Input Capture/Output Compare 4 Interrupt Enable TMSK1.C3I 3 Input Capture/Output Compare 3 Interrupt Enable TMSK1.C2I 2 Input Capture/Output Compare 2 Interrupt Enable TMSK1.C1I 1 Input Capture/Output Compare 1 Interrupt Enable TMSK1.C0I 0 Input Capture/Output Compare 0 Interrupt Enable TMSK2 0x008D Timer Interrupt Mask 2 TMSK2.TOI 7 Timer Overflow Interrupt Enable TMSK2.PUPT 5 Timer Port Pull-Up Resistor Enable TMSK2.RDPT 4 Timer Port Drive Reduction TMSK2.TCRE 3 Timer Counter Reset Enable TMSK2.PR2 2 Timer Prescaler Select 2 TMSK2.PR1 1 Timer Prescaler Select 1 TMSK2.PR0 0 Timer Prescaler Select 0 TFLG1 0x008E Main Timer Interrupt Flag 1 TFLG1.C7F 7 Input Capture/Output Compare Channel 7 Flag TFLG1.C6F 6 Input Capture/Output Compare Channel 6 Flag TFLG1.C5F 5 Input Capture/Output Compare Channel 5 Flag TFLG1.C4F 4 Input Capture/Output Compare Channel 4 Flag TFLG1.C3F 3 Input Capture/Output Compare Channel 3 Flag TFLG1.C2F 2 Input Capture/Output Compare Channel 2 Flag TFLG1.C1F 1 Input Capture/Output Compare Channel 1 Flag TFLG1.C0F 0 Input Capture/Output Compare Channel 0 Flag TFLG2 0x008F Main Timer Interrupt Flag 2 TFLG2.TOF 7 Timer Overflow Flag TC0H 0x0090 Timer Input Capture/Output Compare Register 0 High TC0L 0x0091 Timer Input Capture/Output Compare Register 0 Low TC1H 0x0092 Timer Input Capture/Output Compare Register 1 High TC1L 0x0093 Timer Input Capture/Output Compare Register 1 Low TC2H 0x0094 Timer Input Capture/Output Compare Register 2 High TC2L 0x0095 Timer Input Capture/Output Compare Register 2 Low TC3H 0x0096 Timer Input Capture/Output Compare Register 3 High TC3L 0x0097 Timer Input Capture/Output Compare Register 3 Low TC4H 0x0098 Timer Input Capture/Output Compare Register 4 High TC4L 0x0099 Timer Input Capture/Output Compare Register 4 Low TC5H 0x009A Timer Input Capture/Output Compare Register 5 High TC5L 0x009B Timer Input Capture/Output Compare Register 5 Low TC6H 0x009C Timer Input Capture/Output Compare Register 6 High TC6L 0x009D Timer Input Capture/Output Compare Register 6 Low TC7H 0x009E Timer Input Capture/Output Compare Register 7 High TC7L 0x009F Timer Input Capture/Output Compare Register 7 Low PACTL 0x00A0 16-Bit Pulse Accumulator A Control Register PACTL.PAEN 6 Pulse Accumulator A System Enable PACTL.PAMOD 5 Pulse Accumulator Mode PACTL.PEDGE 4 Pulse Accumulator Edge Control PACTL.CLK1 3 Clock Select Bit 1 PACTL.CLK0 2 Clock Select Bit 0 PACTL.PAOVI 1 Pulse Accumulator A Overflow Interrupt enable PACTL.PAI 0 Pulse Accumulator Input Interrupt enable PAFLG 0x00A1 Pulse Accumulator A Flag Register PAFLG.PAOVF 1 Pulse Accumulator A Overflow Flag PAFLG.PAIF 0 Pulse Accumulator Input edge Flag PACN3 0x00A2 Pulse Accumulators Count Register 3 PACN2 0x00A3 Pulse Accumulators Count Register 2 PACN1 0x00A4 Pulse Accumulators Count Register 1 PACN0 0x00A5 Pulse Accumulators Count Register 0 MCCTL 0x00A6 16-Bit Modulus Down-Counter Control Register MCCTL.MCZI 7 Modulus Counter Underflow Interrupt Enable MCCTL.MODMC 6 Modulus Mode Enable MCCTL.RDMCL 5 Read Modulus Down-Counter Load MCCTL.ICLAT 4 Input Capture Force Latch Action MCCTL.FLMC 3 Force Load Register into the Modulus Counter Count Register MCCTL.MCEN 2 Modulus Down-Counter Enable MCCTL.MCPR1 1 Modulus Counter Prescaler select 1 MCCTL.MCPR0 0 Modulus Counter Prescaler select 0 MCFLG 0x00A7 16-Bit Modulus Down-Counter FLAG Register MCFLG.MCZF 7 Modulus Counter Underflow Interrupt Flag MCFLG.POLF3 3 First Input Capture Polarity Status 3 MCFLG.POLF2 2 First Input Capture Polarity Status 2 MCFLG.POLF1 1 First Input Capture Polarity Status 1 MCFLG.POLF0 0 First Input Capture Polarity Status 0 ICPACR 0x00A8 Input Control Pulse Accumulators Control Register ICPACR.PA3EN 3 8-Bit Pulse Accumulator 3 Enable ICPACR.PA2EN 2 8-Bit Pulse Accumulator 2 Enable ICPACR.PA1EN 1 8-Bit Pulse Accumulator 1 Enable ICPACR.PA0EN 0 8-Bit Pulse Accumulator 0 Enable DLYCT 0x00A9 Delay Counter Control Register DLYCT.DLY1 1 Delay Counter Select 1 DLYCT.DLY0 0 Delay Counter Select 0 ICOVW 0x00AA Input Control Overwrite Register ICOVW.NOVW7 7 No Input Capture Overwrite 7 ICOVW.NOVW6 6 No Input Capture Overwrite 6 ICOVW.NOVW5 5 No Input Capture Overwrite 5 ICOVW.NOVW4 4 No Input Capture Overwrite 4 ICOVW.NOVW3 3 No Input Capture Overwrite 3 ICOVW.NOVW2 2 No Input Capture Overwrite 2 ICOVW.NOVW1 1 No Input Capture Overwrite 1 ICOVW.NOVW0 0 No Input Capture Overwrite 0 ICSYS 0x00AB Input Control System Control Register ICSYS.SH37 7 Share Input action of Input Capture Channels 3 and 7 ICSYS.SH26 6 Share Input action of Input Capture Channels 2 and 6 ICSYS.SH15 5 Share Input action of Input Capture Channels 1 and 5 ICSYS.SH04 4 Share Input action of Input Capture Channels 0 and 4 ICSYS.TFMOD 3 Timer Flag-setting Mode ICSYS.PACMX 2 8-Bit Pulse Accumulators Maximum Count ICSYS.BUFEN 1 IC Buffer Enable ICSYS.LATQ 0 Input Control Latch or Queue Mode Enable RESERVED00AC 0x00AC RESERVED TIMTST 0x00AD Timer Test Register TIMTST.TCBYP 1 Main Timer Divider Chain Bypass PORTT 0x00AE Port T Data Register PORTT.PT7 7 Port T Data Bit 7 PORTT.PT6 6 Port T Data Bit 6 PORTT.PT5 5 Port T Data Bit 5 PORTT.PT4 4 Port T Data Bit 4 PORTT.PT3 3 Port T Data Bit 3 PORTT.PT2 2 Port T Data Bit 2 PORTT.PT1 1 Port T Data Bit 1 PORTT.PT0 0 Port T Data Bit 0 DDRT 0x00AF Port T Data Direction Register DDRT.DDT7 7 Port T Data Direction Bit 7 DDRT.DDT6 6 Port T Data Direction Bit 6 DDRT.DDT5 5 Port T Data Direction Bit 5 DDRT.DDT4 4 Port T Data Direction Bit 4 DDRT.DDT3 3 Port T Data Direction Bit 3 DDRT.DDT2 2 Port T Data Direction Bit 2 DDRT.DDT1 1 Port T Data Direction Bit 1 DDRT.DDT0 0 Port T Data Direction Bit 0 PBCTL 0x00B0 16-Bit Pulse Accumulator B Control Register PBCTL.PBEN 6 Pulse Accumulator B System Enable PBCTL.PBOVI 1 Pulse Accumulator B Overflow Interrupt enable PBFLG 0x00B1 Pulse Accumulator B Flag Register PBFLG.PBOVF 1 Pulse Accumulator B Overflow Flag PA3H 0x00B2 8-Bit Pulse Accumulators Holding Register 3 PA2H 0x00B3 8-Bit Pulse Accumulators Holding Register 2 PA1H 0x00B4 8-Bit Pulse Accumulators Holding Register 1 PA0H 0x00B5 8-Bit Pulse Accumulators Holding Register 0 MCCNTH 0x00B6 Modulus Down-Counter Count Register High MCCNTL 0x00B7 Modulus Down-Counter Count Register Low TC0HH 0x00B8 Timer Input Capture Holding Register 0 High TC0HL 0x00B9 Timer Input Capture Holding Register 0 Low TC1HH 0x00BA Timer Input Capture Holding Register 1 High TC1HL 0x00BB Timer Input Capture Holding Register 1 Low TC2HH 0x00BC Timer Input Capture Holding Register 2 High TC2HL 0x00BD Timer Input Capture Holding Register 2 Low TC3HH 0x00BE Timer Input Capture Holding Register 3 High TC3HL 0x00BF Timer Input Capture Holding Register 3 Low SC0BDH 0x00C0 SCI Baud Rate Control Register High SC0BDH.BTST 7 Reserved for test function SC0BDH.BSPL 6 Reserved for test function SC0BDH.BRLD 5 Reserved for test function SC0BDH.SBR12 4 SC0BDH.SBR11 3 SC0BDH.SBR10 2 SC0BDH.SBR9 1 SC0BDH.SBR8 0 SC0BDL 0x00C1 SCI Baud Rate Control Register Low SC0BDL.SBR7 7 SC0BDL.SBR6 6 SC0BDL.SBR5 5 SC0BDL.SBR4 4 SC0BDL.SBR3 3 SC0BDL.SBR2 2 SC0BDL.SBR1 1 SC0BDL.SBR0 0 SC0CR1 0x00C2 SCI Control Register 1 SC0CR1.LOOPS 7 SCI LOOP Mode/Single Wire Mode Enable SC0CR1.WOMS 6 Wired-Or Mode for Serial Pins SC0CR1.RSRC 5 Receiver Source SC0CR1.M 4 Mode (select character format) SC0CR1.WAKE 3 Wake-up by Address Mark/Idle SC0CR1.ILT 2 Idle Line Type SC0CR1.PE 1 Parity Enable SC0CR1.PT 0 Parity Type SC0CR2 0x00C3 SCI Control Register 2 SC0CR2.TIE 7 Transmit Interrupt Enable SC0CR2.TCIE 6 Transmit Complete Interrupt Enable SC0CR2.RIE 5 Receiver Interrupt Enable SC0CR2.ILIE 4 Idle Line Interrupt Enable SC0CR2.TE 3 Transmitter Enable SC0CR2.RE 2 Receiver Enable SC0CR2.RWU 1 Receiver Wake-Up Control SC0CR2.SBK 0 Send Break SC0SR1 0x00C4 SCI Status Register 1 SC0SR1.TDRE 7 Transmit Data Register Empty Flag SC0SR1.TC 6 Transmit Complete Flag SC0SR1.RDRF 5 Receive Data Register Full Flag SC0SR1.IDLE 4 Idle Line Detected Flag SC0SR1.OR 3 Overrun Error Flag SC0SR1.NF 2 Noise Error Flag SC0SR1.FE 1 Framing Error Flag SC0SR1.PF 0 Parity Error Flag SC0SR2 0x00C5 SCI Status Register 2 SC0SR2.RAF 0 Receiver Active Flag SC0DRH 0x00C6 SCI Data Register High SC0DRH.R8 7 Receive Bit 8 SC0DRH.T8 6 Transmit Bit 8 SC0DRL 0x00C7 SCI Data Register Low SC0DRL.R7_T7 7 Receive/Transmit Data Bit 7 SC0DRL.R6_T6 6 Receive/Transmit Data Bit 6 SC0DRL.R5_T5 5 Receive/Transmit Data Bit 5 SC0DRL.R4_T4 4 Receive/Transmit Data Bit 4 SC0DRL.R3_T3 3 Receive/Transmit Data Bit 3 SC0DRL.R2_T2 2 Receive/Transmit Data Bit 2 SC0DRL.R1_T1 1 Receive/Transmit Data Bit 1 SC0DRL.R0_T0 0 Receive/Transmit Data Bit 0 SC1BDH 0x00C8 SCI Baud Rate Control Register High SC1BDH.BTST 7 Reserved for test function SC1BDH.BSPL 6 Reserved for test function SC1BDH.BRLD 5 Reserved for test function SC1BDH.SBR12 4 SC1BDH.SBR11 3 SC1BDH.SBR10 2 SC1BDH.SBR9 1 SC1BDH.SBR8 0 SC1BDL 0x00C9 SCI Baud Rate Control Register Low SC1BDL.SBR7 7 SC1BDL.SBR6 6 SC1BDL.SBR5 5 SC1BDL.SBR4 4 SC1BDL.SBR3 3 SC1BDL.SBR2 2 SC1BDL.SBR1 1 SC1BDL.SBR0 0 SC1CR1 0x00CA SCI Control Register 1 SC1CR1.LOOPS 7 SCI LOOP Mode/Single Wire Mode Enable SC1CR1.WOMS 6 Wired-Or Mode for Serial Pins SC1CR1.RSRC 5 Receiver Source SC1CR1.M 4 Mode (select character format) SC1CR1.WAKE 3 Wake-up by Address Mark/Idle SC1CR1.ILT 2 Idle Line Type SC1CR1.PE 1 Parity Enable SC1CR1.PT 0 Parity Type SC1CR2 0x00CB SCI Control Register 2 SC1CR2.TIE 7 Transmit Interrupt Enable SC1CR2.TCIE 6 Transmit Complete Interrupt Enable SC1CR2.RIE 5 Receiver Interrupt Enable SC1CR2.ILIE 4 Idle Line Interrupt Enable SC1CR2.TE 3 Transmitter Enable SC1CR2.RE 2 Receiver Enable SC1CR2.RWU 1 Receiver Wake-Up Control SC1CR2.SBK 0 Send Break SC1SR1 0x00CC SCI Status Register 1 SC1SR1.TDRE 7 Transmit Data Register Empty Flag SC1SR1.TC 6 Transmit Complete Flag SC1SR1.RDRF 5 Receive Data Register Full Flag SC1SR1.IDLE 4 Idle Line Detected Flag SC1SR1.OR 3 Overrun Error Flag SC1SR1.NF 2 Noise Error Flag SC1SR1.FE 1 Framing Error Flag SC1SR1.PF 0 Parity Error Flag SC1SR2 0x00CD SCI Status Register 2 SC1SR2.RAF 0 Receiver Active Flag SC1DRH 0x00CE SCI Data Register High SC1DRH.R8 7 Receive Bit 8 SC1DRH.T8 6 Transmit Bit 8 SC1DRL 0x00CF SCI Data Register Low SC1DRL.R7_T7 7 Receive/Transmit Data Bit 7 SC1DRL.R6_T6 6 Receive/Transmit Data Bit 6 SC1DRL.R5_T5 5 Receive/Transmit Data Bit 5 SC1DRL.R4_T4 4 Receive/Transmit Data Bit 4 SC1DRL.R3_T3 3 Receive/Transmit Data Bit 3 SC1DRL.R2_T2 2 Receive/Transmit Data Bit 2 SC1DRL.R1_T1 1 Receive/Transmit Data Bit 1 SC1DRL.R0_T0 0 Receive/Transmit Data Bit 0 SP0CR1 0x00D0 SPI Control Register 1 SP0CR1.SPIE 7 SPI Interrupt Enable SP0CR1.SPE 6 SPI System Enable SP0CR1.SWOM 5 Port S Wired-OR Mode SP0CR1.MSTR 4 SPI Master/Slave Mode Select SP0CR1.CPOL 3 SPI Clock Polarity SP0CR1.CPHA 2 Clock Phase SP0CR1.SSOE 1 Slave Select Output Enable SP0CR1.LSBF 0 SPI LSB First enable SP0CR2 0x00D1 SPI Control Register 2 SP0CR2.PUPS 3 Pull-Up Port S Enable SP0CR2.RDPS 2 Reduce Drive of Port S SP0CR2.SSWAI 1 Serial Interface Stop in WAIT mode SP0CR2.SPC0 0 Serial Pin Control 0 SP0BR 0x00D2 SPI Baud Rate Register SP0BR.SPR2 2 SPI Clock (SCK) Rate Select Bit 2 SP0BR.SPR1 1 SPI Clock (SCK) Rate Select Bit 1 SP0BR.SPR0 0 SPI Clock (SCK) Rate Select Bit 0 SP0SR 0x00D3 SPI Status Register SP0SR.SPIF 7 SPI Interrupt Request SP0SR.WCOL 6 Write Collision Status Flag SP0SR.MODF 4 SPI Mode Error Interrupt Status Flag RESERVED00D4 0x00D4 RESERVED SP0DR 0x00D5 SPI Data Register PORTS 0x00D6 Port S Data Register PORTS.PS7 7 Port S Data Bit 7 PORTS.PS6 6 Port S Data Bit 6 PORTS.PS5 5 Port S Data Bit 5 PORTS.PS4 4 Port S Data Bit 4 PORTS.PS3 3 Port S Data Bit 3 PORTS.PS2 2 Port S Data Bit 2 PORTS.PS1 1 Port S Data Bit 1 PORTS.PS0 0 Port S Data Bit 0 DDRS 0x00D7 Port S Data Direction Register DDRS.DDS7 7 Port S Data Direction Bit 7 DDRS.DDS6 6 Port S Data Direction Bit 6 DDRS.DDS5 5 Port S Data Direction Bit 5 DDRS.DDS4 4 Port S Data Direction Bit 4 DDRS.DDS3 3 Port S Data Direction Bit 3 DDRS.DDS2 2 Port S Data Direction Bit 2 DDRS.DDS1 1 Port S Data Direction Bit 1 DDRS.DDS0 0 Port S Data Direction Bit 0 RESERVED00D8 0x00D8 RESERVED RESERVED00D9 0x00D9 RESERVED RESERVED00DA 0x00DA RESERVED RESERVED00DB 0x00DB RESERVED RESERVED00DC 0x00DC RESERVED RESERVED00DD 0x00DD RESERVED RESERVED00DE 0x00DE RESERVED RESERVED00DF 0x00DF RESERVED IBAD 0x00E0 Bus Address Register IBAD.ADR7 7 Slave Address 7 IBAD.ADR6 6 Slave Address 6 IBAD.ADR5 5 Slave Address 5 IBAD.ADR4 4 Slave Address 4 IBAD.ADR3 3 Slave Address 3 IBAD.ADR2 2 Slave Address 2 IBAD.ADR1 1 Slave Address 1 IBFD 0x00E1 IIC Bus Frequency Divider Register IBFD.IBC5 5 IIC Bus Clock Rate 5 IBFD.IBC4 4 IIC Bus Clock Rate 4 IBFD.IBC3 3 IIC Bus Clock Rate 3 IBFD.IBC2 2 IIC Bus Clock Rate 2 IBFD.IBC1 1 IIC Bus Clock Rate 1 IBFD.IBC0 0 IIC Bus Clock Rate 0 IBCR 0x00E2 IIC Bus Control Register IBCR.IBEN 7 IIC Bus Enable IBCR.IBIE 6 IIC Bus Interrupt Enable IBCR.MS_SL 5 Master/Slave mode select bit IBCR.Tx_Rx 4 Transmit/Receive mode select bit IBCR.TXAK 3 Transmit Acknowledge enable IBCR.RSTA 2 Repeat Start IBCR.IBSWAI 0 IIC Stop in WAIT mode IBSR 0x00E3 IIC Bus Status Register IBSR.TCF 7 Data transferring bit IBSR.IAAS 6 Addressed as a slave bit IBSR.IBB 5 IIC Bus busy bit IBSR.IBAL 4 Arbitration Lost IBSR.SRW 2 Slave Read/Write IBSR.IBIF 1 IIC Bus Interrupt Flag IBSR.RXAK 0 Received Acknowledge IBDR 0x00E4 IIC Bus Data I/O Register IBDR.D7 7 IBDR.D6 6 IBDR.D5 5 IBDR.D4 4 IBDR.D3 3 IBDR.D2 2 IBDR.D1 1 IBDR.D0 0 IBPURD 0x00E5 Pull-Up and Reduced Drive for Port IB IBPURD.RDPIB 4 Reduced Drive of Port IB IBPURD.PUPIB 0 Pull-Up Port IB Enable PORTIB 0x00E6 Port Data IB Register PORTIB.PIB7 7 Port Data IB Register bit 7 PORTIB.PIB6 6 Port Data IB Register bit 6 PORTIB.PIB5 5 Port Data IB Register bit 5 PORTIB.PIB4 4 Port Data IB Register bit 4 PORTIB.PIB3 3 Port Data IB Register bit 3 PORTIB.PIB2 2 Port Data IB Register bit 2 PORTIB.PIB1 1 Port Data IB Register bit 1 PORTIB.PIB0 0 Port Data IB Register bit 0 DDRIB 0x00E7 Data Direction for Port IB Register DDRIB.DDRIB7 7 Port IB Data direction 7 DDRIB.DDRIB6 6 Port IB Data direction 6 DDRIB.DDRIB5 5 Port IB Data direction 5 DDRIB.DDRIB4 4 Port IB Data direction 4 DDRIB.DDRIB3 3 Port IB Data direction 3 DDRIB.DDRIB2 2 Port IB Data direction 2 DDRIB.DDRIB1 1 DDRIB.DDRIB0 0 RESERVED00E8 0x00E8 RESERVED RESERVED00E9 0x00E9 RESERVED RESERVED00EA 0x00EA RESERVED RESERVED00EB 0x00EB RESERVED RESERVED00EC 0x00EC RESERVED RESERVED00ED 0x00ED RESERVED EEDIVH 0x00EE EEPROM Modulus Divider High EEDIVH.EEDIV9 1 Prescaler divider 9 EEDIVH.EEDIV8 0 Prescaler divider 8 EEDIVL 0x00EF EEPROM Modulus Divider Low EEDIVL.EEDIV7 7 Prescaler divider 7 EEDIVL.EEDIV6 6 Prescaler divider 6 EEDIVL.EEDIV5 5 Prescaler divider 5 EEDIVL.EEDIV4 4 Prescaler divider 4 EEDIVL.EEDIV3 3 Prescaler divider 3 EEDIVL.EEDIV2 2 Prescaler divider 2 EEDIVL.EEDIV1 1 Prescaler divider 1 EEDIVL.EEDIV0 0 Prescaler divider 0 EEMCR 0x00F0 EEPROM Module Configuration EEMCR.NOBDML 7 Background Debug Mode Lockout Disable EEMCR.NOSHW 6 SHADOW Byte Disable EEMCR.EESWAI 2 EEPROM Stops in Wait Mode EEMCR.PROTLCK 1 Block Protect Write Lock EEMCR.EERC 0 EEPROM Charge Pump Clock EEPROT 0x00F1 EEPROM Block Protect EEPROT.SHPROT 7 SHADOW Byte Protection EEPROT.BPROT5 5 EEPROM Block Protection 5 EEPROT.BPROT4 4 EEPROM Block Protection 4 EEPROT.BPROT3 3 EEPROM Block Protection 3 EEPROT.BPROT2 2 EEPROM Block Protection 2 EEPROT.BPROT1 1 EEPROM Block Protection 1 EEPROT.BPROT0 0 EEPROM Block Protection 0 EETST 0x00F2 EEPROM Test EETST.EREVTN 6 EETST.ETMSD 2 EETST.ETMR 1 EETST.ETMSE 0 EEPROG 0x00F3 EEPROM Control EEPROG.BULKP 7 Bulk Erase Protection EEPROG..AUTO 5 Automatic shutdown of program/erase operation EEPROG.BYTE 4 Byte and Aligned Word Erase EEPROG.ROW 3 Row or Bulk Erase (when BYTE = 0) EEPROG.ERASE 2 Erase Control EEPROG.EELAT 1 EEPROM Latch Control EEPROG.EEPGM 0 Program and Erase Enable FEELCK 0x00F4 Flash EEPROM Lock Control Register FEELCK.LOCK 0 Lock Register Bit FEEMCR 0x00F5 Flash EEPROM Module Configuration Register FEEMCR.BOOTP 0 Boot Protect FEETST 0x00F6 FEETST FEETST.STRE 7 FEETST.REVTUN 6 FEETST.TMSD 2 FEETST.TMR 1 FEETST.TMSE 0 FEECTL 0x00F7 Flash EEPROM Control Register FEECTL.FEESWAI 4 Flash EEPROM Stop in Wait Control FEECTL.HVEN 3 High-Voltage Enable FEECTL.ERAS 1 Erase Control FEECTL.PGM 0 Program Control MTST0 0x00F8 Mapping Test Register 0 MTST0.MT07 7 MTST0.MT06 6 MTST0.MT05 5 MTST0.MT04 4 MTST0.MT03 3 MTST0.MT02 2 MTST0.MT01 1 MTST0.MT00 0 MTST1 0x00F9 Mapping Test Register 1 MTST1.MT0F 7 MTST1.MT0E 6 MTST1.MT0D 5 MTST1.MT0C 4 MTST1.MT0B 3 MTST1.MT0A 2 MTST1.MT09 1 MTST1.MT08 0 MTST2 0x00FA Mapping Test Register 2 MTST2.MT17 7 MTST2.MT16 6 MTST2.MT15 5 MTST2.MT14 4 MTST2.MT13 3 MTST2.MT12 2 MTST2.MT11 1 MTST2.MT10 0 MTST3 0x00FB Mapping Test Register 3 MTST3.MT1F 7 MTST3.MT1E 6 MTST3.MT1D 5 MTST3.MT1C 4 MTST3.MT1B 3 MTST3.MT1A 2 MTST3.MT19 1 MTST3.MT18 0 PORTK 0x00FC Port K Data Register PORTK.PK7 7 Port K Data Bit 7 PORTK.PK3 3 Port K Data Bit 3 PORTK.PK2 2 Port K Data Bit 2 PORTK.PK1 1 Port K Data Bit 1 PORTK.PK0 0 Port K Data Bit 0 DDRK 0x00FD Port K Data Direction Register DDRK.DDK7 7 Port K Data Direction Bit 7 DDRK.DDK3 3 Port K Data Direction Bit 3 DDRK.DDK2 2 Port K Data Direction Bit 2 DDRK.DDK1 1 Port K Data Direction Bit 1 DDRK.DDK0 0 Port K Data Direction Bit 0 RESERVED00FE 0x00FE RESERVED PPAGE 0x00FF Program Page Index Register PPAGE.PIX2 2 PPAGE.PIX1 1 PPAGE.PIX0 0 C0MCR0 0x0100 msCAN12 Module Control Register 0 C0MCR0.CSWAI 5 CAN Stops in Wait Mode C0MCR0.SYNCH 4 Synchronized Status C0MCR0.TLNKEN 3 Timer Enable C0MCR0.SLPAK 2 SLEEP Mode Acknowledge C0MCR0.SLPRQ 1 SLEEP request C0MCR0.SFTRES 0 SOFT_RESET C0MCR1 0x0101 msCAN12 Module Control Register 1 C0MCR1.LOOPB 2 Loop Back Self Test Mode C0MCR1.WUPM 1 Wake-Up Mode C0MCR1.CLKSRC 0 msCAN12 Clock Source C0BTR0 0x0102 msCAN12 Bus Timing Register 0 C0BTR0.SJW1 7 Synchronization Jump Width 1 C0BTR0.SJW0 6 Synchronization Jump Width 0 C0BTR0.BRP5 5 Baud Rate Prescaler 5 C0BTR0.BRP4 4 Baud Rate Prescaler 4 C0BTR0.BRP3 3 Baud Rate Prescaler 3 C0BTR0.BRP2 2 Baud Rate Prescaler 2 C0BTR0.BRP1 1 Baud Rate Prescaler 1 C0BTR0.BRP0 0 Baud Rate Prescaler 0 C0BTR1 0x0103 msCAN12 Bus Timing Register 1 C0BTR1.SAMP 7 Sampling C0BTR1.TSEG22 6 Time Segment 22 C0BTR1.TSEG21 5 Time Segment 21 C0BTR1.TSEG20 4 Time Segment 20 C0BTR1.TSEG13 3 Time Segment 13 C0BTR1.TSEG12 2 Time Segment 12 C0BTR1.TSEG11 1 Time Segment 11 C0BTR1.TSEG10 0 Time Segment 10 C0RFLG 0x0104 msCAN12 Receiver Flag Register C0RFLG.WUPIF 7 Wake-up Interrupt Flag C0RFLG.RWRNIF 6 Receiver Warning Interrupt Flag C0RFLG.TWRNIF 5 Transmitter Warning Interrupt Flag C0RFLG.RERRIF 4 Receiver Error Passive Interrupt Flag C0RFLG.TERRIF 3 Transmitter Error Passive Interrupt Flag C0RFLG.BOFFIF 2 BUSOFF Interrupt Flag C0RFLG.OVRIF 1 Overrun Interrupt Flag C0RFLG.RXF 0 Receive Buffer Full C0RIER 0x0105 msCAN12 Receiver Interrupt Enable Register C0RIER.WUPIE 7 Wake-up Interrupt Enable C0RIER.RWRNIE 6 Receiver Warning Interrupt Enable C0RIER.TWRNIE 5 Transmitter Warning Interrupt Enable C0RIER.RERRIE 4 Receiver Error Passive Interrupt Enable C0RIER.TERRIE 3 Transmitter Error Passive Interrupt Enable C0RIER.BOFFIE 2 BUSOFF Interrupt Enable C0RIER.OVRIE 1 Overrun Interrupt Enable C0RIER.RXFIE 0 Receiver Full Interrupt Enable C0TFLG 0x0106 msCAN12 Transmitter Flag Register C0TFLG.ABTAK2 6 Abort Acknowledge 2 C0TFLG.ABTAK1 5 Abort Acknowledge 1 C0TFLG.ABTAK0 4 Abort Acknowledge 0 C0TFLG.TXE2 2 Transmitter Buffer Empty 2 C0TFLG.TXE1 1 Transmitter Buffer Empty 1 C0TFLG.TXE0 0 Transmitter Buffer Empty 0 C0TCR 0x0107 msCAN12 Transmitter Control Register C0TCR.ABTRQ2 6 Abort Request 2 C0TCR.ABTRQ1 5 Abort Request 1 C0TCR.ABTRQ0 4 Abort Request 0 C0TCR.TXEIE2 2 Transmitter Empty Interrupt Enable 2 C0TCR.TXEIE1 1 Transmitter Empty Interrupt Enable 1 C0TCR.TXEIE0 0 Transmitter Empty Interrupt Enable 0 C0IDAC 0x0108 msCAN12 Identifier Acceptance Control Register C0IDAC.IDAM1 5 Identifier Acceptance Mode 1 C0IDAC.IDAM0 4 Identifier Acceptance Mode 0 C0IDAC.IDHIT2 2 Identifier Acceptance Hit Indicator 2 C0IDAC.IDHIT1 1 Identifier Acceptance Hit Indicator 1 C0IDAC.IDHIT0 0 Identifier Acceptance Hit Indicator 0 RESERVED0109 0x0109 RESERVED RESERVED010A 0x010A RESERVED RESERVED010B 0x010B RESERVED RESERVED010C 0x010C RESERVED RESERVED010D 0x010D RESERVED C0RXERR 0x010E msCAN12 Receive Error Counter C0RXERR.RXERR7 7 C0RXERR.RXERR6 6 C0RXERR.RXERR5 5 C0RXERR.RXERR4 4 C0RXERR.RXERR3 3 C0RXERR.RXERR2 2 C0RXERR.RXERR1 1 C0RXERR.RXERR0 0 C0TXERR 0x010F msCAN12 Transmit Error Counter C0TXERR.TXERR7 7 C0TXERR.TXERR6 6 C0TXERR.TXERR5 5 C0TXERR.TXERR4 4 C0TXERR.TXERR3 3 C0TXERR.TXERR2 2 C0TXERR.TXERR1 1 C0TXERR.TXERR0 0 C0IDAR0 0x0110 msCAN12 Identifier Acceptance Register 0 C0IDAR0.AC7 7 Acceptance Code Bit 7 C0IDAR0.AC6 6 Acceptance Code Bit 6 C0IDAR0.AC5 5 Acceptance Code Bit 5 C0IDAR0.AC4 4 Acceptance Code Bit 4 C0IDAR0.AC3 3 Acceptance Code Bit 3 C0IDAR0.AC2 2 Acceptance Code Bit 2 C0IDAR0.AC1 1 Acceptance Code Bit 1 C0IDAR0.AC0 0 Acceptance Code Bit 0 C0IDAR1 0x0111 msCAN12 Identifier Acceptance Register 1 C0IDAR1.AC7 7 Acceptance Code Bit 7 C0IDAR1.AC6 6 Acceptance Code Bit 6 C0IDAR1.AC5 5 Acceptance Code Bit 5 C0IDAR1.AC4 4 Acceptance Code Bit 4 C0IDAR1.AC3 3 Acceptance Code Bit 3 C0IDAR1.AC2 2 Acceptance Code Bit 2 C0IDAR1.AC1 1 Acceptance Code Bit 1 C0IDAR1.AC0 0 Acceptance Code Bit 0 C0IDAR2 0x0112 msCAN12 Identifier Acceptance Register 2 C0IDAR2.AC7 7 Acceptance Code Bit 7 C0IDAR2.AC6 6 Acceptance Code Bit 6 C0IDAR2.AC5 5 Acceptance Code Bit 5 C0IDAR2.AC4 4 Acceptance Code Bit 4 C0IDAR2.AC3 3 Acceptance Code Bit 3 C0IDAR2.AC2 2 Acceptance Code Bit 2 C0IDAR2.AC1 1 Acceptance Code Bit 1 C0IDAR2.AC0 0 Acceptance Code Bit 0 C0IDAR3 0x0113 msCAN12 Identifier Acceptance Register 3 C0IDAR3.AC7 7 Acceptance Code Bit 7 C0IDAR3.AC6 6 Acceptance Code Bit 6 C0IDAR3.AC5 5 Acceptance Code Bit 5 C0IDAR3.AC4 4 Acceptance Code Bit 4 C0IDAR3.AC3 3 Acceptance Code Bit 3 C0IDAR3.AC2 2 Acceptance Code Bit 2 C0IDAR3.AC1 1 Acceptance Code Bit 1 C0IDAR3.AC0 0 Acceptance Code Bit 0 C0IDMR0 0x0114 msCAN12 Identifier Mask Register 0 C0IDMR0.AM7 7 Acceptance Mask Bit 7 C0IDMR0.AM6 6 Acceptance Mask Bit 6 C0IDMR0.AM5 5 Acceptance Mask Bit 5 C0IDMR0.AM4 4 Acceptance Mask Bit 4 C0IDMR0.AM3 3 Acceptance Mask Bit 3 C0IDMR0.AM2 2 Acceptance Mask Bit 2 C0IDMR0.AM1 1 Acceptance Mask Bit 1 C0IDMR0.AM0 0 Acceptance Mask Bit 0 C0IDMR1 0x0115 msCAN12 Identifier Mask Register 1 C0IDMR1.AM7 7 Acceptance Mask Bit 7 C0IDMR1.AM6 6 Acceptance Mask Bit 6 C0IDMR1.AM5 5 Acceptance Mask Bit 5 C0IDMR1.AM4 4 Acceptance Mask Bit 4 C0IDMR1.AM3 3 Acceptance Mask Bit 3 C0IDMR1.AM2 2 Acceptance Mask Bit 2 C0IDMR1.AM1 1 Acceptance Mask Bit 1 C0IDMR1.AM0 0 Acceptance Mask Bit 0 C0IDMR2 0x0116 msCAN12 Identifier Mask Register 2 C0IDMR2.AM7 7 Acceptance Mask Bit 7 C0IDMR2.AM6 6 Acceptance Mask Bit 6 C0IDMR2.AM5 5 Acceptance Mask Bit 5 C0IDMR2.AM4 4 Acceptance Mask Bit 4 C0IDMR2.AM3 3 Acceptance Mask Bit 3 C0IDMR2.AM2 2 Acceptance Mask Bit 2 C0IDMR2.AM1 1 Acceptance Mask Bit 1 C0IDMR2.AM0 0 Acceptance Mask Bit 0 C0IDMR3 0x0117 msCAN12 Identifier Mask Register 3 C0IDMR3.AM7 7 Acceptance Mask Bit 7 C0IDMR3.AM6 6 Acceptance Mask Bit 6 C0IDMR3.AM5 5 Acceptance Mask Bit 5 C0IDMR3.AM4 4 Acceptance Mask Bit 4 C0IDMR3.AM3 3 Acceptance Mask Bit 3 C0IDMR3.AM2 2 Acceptance Mask Bit 2 C0IDMR3.AM1 1 Acceptance Mask Bit 1 C0IDMR3.AM0 0 Acceptance Mask Bit 0 C0IDAR4 0x0118 msCAN12 Identifier Acceptance Register 4 C0IDAR4.AC7 7 Acceptance Code Bit 7 C0IDAR4.AC6 6 Acceptance Code Bit 6 C0IDAR4.AC5 5 Acceptance Code Bit 5 C0IDAR4.AC4 4 Acceptance Code Bit 4 C0IDAR4.AC3 3 Acceptance Code Bit 3 C0IDAR4.AC2 2 Acceptance Code Bit 2 C0IDAR4.AC1 1 Acceptance Code Bit 1 C0IDAR4.AC0 0 Acceptance Code Bit 0 C0IDAR5 0x0119 msCAN12 Identifier Acceptance Register 5 C0IDAR5.AC7 7 Acceptance Code Bit 7 C0IDAR5.AC6 6 Acceptance Code Bit 6 C0IDAR5.AC5 5 Acceptance Code Bit 5 C0IDAR5.AC4 4 Acceptance Code Bit 4 C0IDAR5.AC3 3 Acceptance Code Bit 3 C0IDAR5.AC2 2 Acceptance Code Bit 2 C0IDAR5.AC1 1 Acceptance Code Bit 1 C0IDAR5.AC0 0 Acceptance Code Bit 0 C0IDAR6 0x011A msCAN12 Identifier Acceptance Register 6 C0IDAR6.AC7 7 Acceptance Code Bit 7 C0IDAR6.AC6 6 Acceptance Code Bit 6 C0IDAR6.AC5 5 Acceptance Code Bit 5 C0IDAR6.AC4 4 Acceptance Code Bit 4 C0IDAR6.AC3 3 Acceptance Code Bit 3 C0IDAR6.AC2 2 Acceptance Code Bit 2 C0IDAR6.AC1 1 Acceptance Code Bit 1 C0IDAR6.AC0 0 Acceptance Code Bit 0 C0IDAR7 0x011B msCAN12 Identifier Acceptance Register 7 C0IDAR7.AC7 7 Acceptance Code Bit 7 C0IDAR7.AC6 6 Acceptance Code Bit 6 C0IDAR7.AC5 5 Acceptance Code Bit 5 C0IDAR7.AC4 4 Acceptance Code Bit 4 C0IDAR7.AC3 3 Acceptance Code Bit 3 C0IDAR7.AC2 2 Acceptance Code Bit 2 C0IDAR7.AC1 1 Acceptance Code Bit 1 C0IDAR7.AC0 0 Acceptance Code Bit 0 C0IDMR4 0x011C msCAN12 Identifier Mask Register 4 C0IDMR4.AM7 7 Acceptance Mask Bit 7 C0IDMR4.AM6 6 Acceptance Mask Bit 6 C0IDMR4.AM5 5 Acceptance Mask Bit 5 C0IDMR4.AM4 4 Acceptance Mask Bit 4 C0IDMR4.AM3 3 Acceptance Mask Bit 3 C0IDMR4.AM2 2 Acceptance Mask Bit 2 C0IDMR4.AM1 1 Acceptance Mask Bit 1 C0IDMR4.AM0 0 Acceptance Mask Bit 0 C0IDMR5 0x011D msCAN12 Identifier Mask Register 5 C0IDMR5.AM7 7 Acceptance Mask Bit 7 C0IDMR5.AM6 6 Acceptance Mask Bit 6 C0IDMR5.AM5 5 Acceptance Mask Bit 5 C0IDMR5.AM4 4 Acceptance Mask Bit 4 C0IDMR5.AM3 3 Acceptance Mask Bit 3 C0IDMR5.AM2 2 Acceptance Mask Bit 2 C0IDMR5.AM1 1 Acceptance Mask Bit 1 C0IDMR5.AM0 0 Acceptance Mask Bit 0 C0IDMR6 0x011E msCAN12 Identifier Mask Register 6 C0IDMR6.AM7 7 Acceptance Mask Bit 7 C0IDMR6.AM6 6 Acceptance Mask Bit 6 C0IDMR6.AM5 5 Acceptance Mask Bit 5 C0IDMR6.AM4 4 Acceptance Mask Bit 4 C0IDMR6.AM3 3 Acceptance Mask Bit 3 C0IDMR6.AM2 2 Acceptance Mask Bit 2 C0IDMR6.AM1 1 Acceptance Mask Bit 1 C0IDMR6.AM0 0 Acceptance Mask Bit 0 C0IDMR7 0x011F msCAN12 Identifier Mask Register 7 C0IDMR7.AM7 7 Acceptance Mask Bit 7 C0IDMR7.AM6 6 Acceptance Mask Bit 6 C0IDMR7.AM5 5 Acceptance Mask Bit 5 C0IDMR7.AM4 4 Acceptance Mask Bit 4 C0IDMR7.AM3 3 Acceptance Mask Bit 3 C0IDMR7.AM2 2 Acceptance Mask Bit 2 C0IDMR7.AM1 1 Acceptance Mask Bit 1 C0IDMR7.AM0 0 Acceptance Mask Bit 0 RESERVED0120 0x0120 RESERVED RESERVED0121 0x0121 RESERVED RESERVED0122 0x0122 RESERVED RESERVED0123 0x0123 RESERVED RESERVED0124 0x0124 RESERVED RESERVED0125 0x0125 RESERVED RESERVED0126 0x0126 RESERVED RESERVED0127 0x0127 RESERVED RESERVED0128 0x0128 RESERVED RESERVED0129 0x0129 RESERVED RESERVED012A 0x012A RESERVED RESERVED012B 0x012B RESERVED RESERVED012C 0x012C RESERVED RESERVED012D 0x012D RESERVED RESERVED012E 0x012E RESERVED RESERVED012F 0x012F RESERVED RESERVED0130 0x0130 RESERVED RESERVED0131 0x0131 RESERVED RESERVED0132 0x0132 RESERVED RESERVED0133 0x0133 RESERVED RESERVED0134 0x0134 RESERVED RESERVED0135 0x0135 RESERVED RESERVED0136 0x0136 RESERVED RESERVED0137 0x0137 RESERVED RESERVED0138 0x0138 RESERVED RESERVED0139 0x0139 RESERVED RESERVED013A 0x013A RESERVED RESERVED013B 0x013B RESERVED RESERVED013C 0x013C RESERVED PCTLCAN0 0x013D msCAN12 Port CAN Control Register PCTLCAN0.PUPCAN 1 Pull-Up Enable Port CAN PCTLCAN0.RDPCAN 0 Reduced Drive Port CAN PORTCAN0 0x013E msCAN12 Port CAN Data Register PORTCAN0.PCAN7 7 Port CAN Data Bit 7 PORTCAN0.PCAN6 6 Port CAN Data Bit 6 PORTCAN0.PCAN5 5 Port CAN Data Bit 5 PORTCAN0.PCAN4 4 Port CAN Data Bit 4 PORTCAN0.PCAN3 3 Port CAN Data Bit 3 PORTCAN0.PCAN2 2 Port CAN Data Bit 2 PORTCAN0.TxCAN 1 PORTCAN0.RxCAN 0 DDRCAN0 0x013F msCAN12 Port CAN Data Direction Register DDRCAN0.DDCAN7 7 DDRCAN0.DDCAN6 6 DDRCAN0.DDCAN5 5 DDRCAN0.DDCAN4 4 DDRCAN0.DDCAN3 3 DDRCAN0.DDCAN2 2 ATD1CTL2 0x01E2 ATD1 Control Register 2 ATD1CTL2.ADPU 7 ATD Disable ATD1CTL2.AFFC 6 ATD Fast Flag Clear All ATD1CTL2.ASWAI 5 ATD Wait Mode ATD1CTL2.DJM 4 Result Register Data Justification Mode ATD1CTL2.DSGN 3 Signed/Unsigned Result Data Mode ATD1CTL2.ASCIE 1 ATD Sequence Complete Interrupt Enable ATD1CTL2.ASCIF 0 ATD Sequence Complete Interrupt Flag ATD1CTL3 0x01E3 ATD1 Control Register 3 ATD1CTL3.S1C 3 Conversion Sequence Length (Least Significant Bit) ATD1CTL3.FIFO 2 Result Register FIFO Mode ATD1CTL3.FRZ1 1 Background Debug (Freeze) Enable 1 ATD1CTL3.FRZ0 0 Background Debug (Freeze) Enable 0 ATD1CTL4 0x01E4 ATD1 Control Register 4 ATD1CTL4.RES10 7 10 bit Mode ATD1CTL4.SMP1 6 Select Sample Time 1 ATD1CTL4.SMP0 5 Select Sample Time 0 ATD1CTL4.PRS4 4 Select Divide-By Factor for ATD P-Clock Prescaler 4 ATD1CTL4.PRS3 3 Select Divide-By Factor for ATD P-Clock Prescaler 3 ATD1CTL4.PRS2 2 Select Divide-By Factor for ATD P-Clock Prescaler 2 ATD1CTL4.PRS1 1 Select Divide-By Factor for ATD P-Clock Prescaler 1 ATD1CTL4.PRS0 0 Select Divide-By Factor for ATD P-Clock Prescaler 0 ATD1CTL5 0x01E5 ATD1 Control Register 5 ATD1CTL5.S8CM 6 Select 8 Channel Mode ATD1CTL5.SCAN 5 Enable Continuous Channel Scan ATD1CTL5.MULT 4 Enable Multichannel Conversion ATD1CTL5.CD 3 Channel Select for Conversion D ATD1CTL5.CC 2 Channel Select for Conversion C ATD1CTL5.CB 1 Channel Select for Conversion B ATD1CTL5.CA 0 Channel Select for Conversion A ATD1STAT0 0x01E6 ATD1 Status Register ATD1STAT0.SCF 7 Sequence Complete Flag ATD1STAT0.CC2 2 Conversion Counter for Current Sequence of Four or Eight Conversions 2 ATD1STAT0.CC1 1 Conversion Counter for Current Sequence of Four or Eight Conversions 1 ATD1STAT0.CC0 0 Conversion Counter for Current Sequence of Four or Eight Conversions 0 ATD1STAT1 0x01E7 ATD1 Status Register ATD1STAT1.CCF7 7 Conversion Complete Flag 7 ATD1STAT1.CCF6 6 Conversion Complete Flag 6 ATD1STAT1.CCF5 5 Conversion Complete Flag 5 ATD1STAT1.CCF4 4 Conversion Complete Flag 4 ATD1STAT1.CCF3 3 Conversion Complete Flag 3 ATD1STAT1.CCF2 2 Conversion Complete Flag 2 ATD1STAT1.CCF1 1 Conversion Complete Flag 1 ATD1STAT1.CCF0 0 Conversion Complete Flag 0 ATD1TESTH 0x01E8 ATD1 Test Register ATD1TESTH.SAR9 7 SAR Data 9 ATD1TESTH.SAR8 6 SAR Data 8 ATD1TESTH.SAR7 5 SAR Data 7 ATD1TESTH.SAR6 4 SAR Data 6 ATD1TESTH.SAR5 3 SAR Data 5 ATD1TESTH.SAR4 2 SAR Data 4 ATD1TESTH.SAR3 1 SAR Data 3 ATD1TESTH.SAR2 0 SAR Data 2 ATD1TESTL 0x01E9 ATD1 Test Register ATD1TESTL.SAR1 7 SAR Data 1 ATD1TESTL.SAR0 6 SAR Data 0 ATD1TESTL.RST 5 Module Reset Bit ATD1TESTL.TSTOUT 4 Multiplex Output of TST[3:0] (Factory Use) ATD1TESTL.TST3 3 Test Bit 3 ATD1TESTL.TST2 2 Test Bit 2 ATD1TESTL.TST1 1 Test Bit 1 ATD1TESTL.TST0 0 Test Bit 0 RESERVED01EA 0x01EA RESERVED RESERVED01EB 0x01EB RESERVED RESERVED01EC 0x01EC RESERVED RESERVED01ED 0x01ED RESERVED RESERVED01EE 0x01EE RESERVED PORTAD1 0x01EF Port AD1 Data Input Register PORTAD1.PAD17 7 Port AD1 Data Input Bit 7 PORTAD1.PAD16 6 Port AD1 Data Input Bit 6 PORTAD1.PAD15 5 Port AD1 Data Input Bit 5 PORTAD1.PAD14 4 Port AD1 Data Input Bit 4 PORTAD1.PAD13 3 Port AD1 Data Input Bit 3 PORTAD1.PAD12 2 Port AD1 Data Input Bit 2 PORTAD1.PAD11 1 Port AD1 Data Input Bit 1 PORTAD1.PAD10 0 Port AD1 Data Input Bit 0 ADR10H 0x01F0 A/D Conversion Result Register High 0 ADR10L 0x01F1 A/D Conversion Result Register Low 0 ADR11H 0x01F2 A/D Conversion Result Register High 1 ADR11L 0x01F3 A/D Conversion Result Register Low 1 ADR12H 0x01F4 A/D Conversion Result Register High 2 ADR12L 0x01F5 A/D Conversion Result Register Low 2 ADR13H 0x01F6 A/D Conversion Result Register High 3 ADR13L 0x01F7 A/D Conversion Result Register Low 3 ADR14H 0x01F8 A/D Conversion Result Register High 4 ADR14L 0x01F9 A/D Conversion Result Register Low 4 ADR15H 0x01FA A/D Conversion Result Register High 5 ADR15L 0x01FB A/D Conversion Result Register Low 5 ADR16H 0x01FC A/D Conversion Result Register High 6 ADR16L 0x01FD A/D Conversion Result Register Low 6 ADR17H 0x01FE A/D Conversion Result Register High 7 ADR17L 0x01FF A/D Conversion Result Register Low 7 C1MCR0 0x0300 msCAN12 Module Control Register 0 C1MCR0.CSWAI 5 CAN Stops in Wait Mode C1MCR0.SYNCH 4 Synchronized Status C1MCR0.TLNKEN 3 Timer Enable C1MCR0.SLPAK 2 SLEEP Mode Acknowledge C1MCR0.SLPRQ 1 SLEEP request C1MCR0.SFTRES 0 SOFT_RESET C1MCR1 0x0301 msCAN12 Module Control Register 1 C1MCR1.LOOPB 2 Loop Back Self Test Mode C1MCR1.WUPM 1 Wake-Up Mode C1MCR1.CLKSRC 0 msCAN12 Clock Source C1BTR0 0x0302 msCAN12 Bus Timing Register 0 C1BTR0.SJW1 7 Synchronization Jump Width 1 C1BTR0.SJW0 6 Synchronization Jump Width 0 C1BTR0.BRP5 5 Baud Rate Prescaler 5 C1BTR0.BRP4 4 Baud Rate Prescaler 4 C1BTR0.BRP3 3 Baud Rate Prescaler 3 C1BTR0.BRP2 2 Baud Rate Prescaler 2 C1BTR0.BRP1 1 Baud Rate Prescaler 1 C1BTR0.BRP0 0 Baud Rate Prescaler 0 C1BTR1 0x0303 msCAN12 Bus Timing Register 1 C1BTR1.SAMP 7 Sampling C1BTR1.TSEG22 6 Time Segment 22 C1BTR1.TSEG21 5 Time Segment 21 C1BTR1.TSEG20 4 Time Segment 20 C1BTR1.TSEG13 3 Time Segment 13 C1BTR1.TSEG12 2 Time Segment 12 C1BTR1.TSEG11 1 Time Segment 11 C1BTR1.TSEG10 0 Time Segment 10 C1RFLG 0x0304 msCAN12 Receiver Flag Register C1RFLG.WUPIF 7 Wake-up Interrupt Flag C1RFLG.RWRNIF 6 Receiver Warning Interrupt Flag C1RFLG.TWRNIF 5 Transmitter Warning Interrupt Flag C1RFLG.RERRIF 4 Receiver Error Passive Interrupt Flag C1RFLG.TERRIF 3 Transmitter Error Passive Interrupt Flag C1RFLG.BOFFIF 2 BUSOFF Interrupt Flag C1RFLG.OVRIF 1 Overrun Interrupt Flag C1RFLG.RXF 0 Receive Buffer Full C1RIER 0x0305 msCAN12 Receiver Interrupt Enable Register C1RIER.WUPIE 7 Wake-up Interrupt Enable C1RIER.RWRNIE 6 Receiver Warning Interrupt Enable C1RIER.TWRNIE 5 Transmitter Warning Interrupt Enable C1RIER.RERRIE 4 Receiver Error Passive Interrupt Enable C1RIER.TERRIE 3 Transmitter Error Passive Interrupt Enable C1RIER.BOFFIE 2 BUSOFF Interrupt Enable C1RIER.OVRIE 1 Overrun Interrupt Enable C1RIER.RXFIE 0 Receiver Full Interrupt Enable C1TFLG 0x0306 msCAN12 Transmitter Flag Register C1TFLG.ABTAK2 6 Abort Acknowledge 2 C1TFLG.ABTAK1 5 Abort Acknowledge 1 C1TFLG.ABTAK0 4 Abort Acknowledge 0 C1TFLG.TXE2 2 Transmitter Buffer Empty 2 C1TFLG.TXE1 1 Transmitter Buffer Empty 1 C1TFLG.TXE0 0 Transmitter Buffer Empty 0 C1TCR 0x0307 msCAN12 Transmitter Control Register C1TCR.ABTRQ2 6 Abort Request 2 C1TCR.ABTRQ1 5 Abort Request 1 C1TCR.ABTRQ0 4 Abort Request 0 C1TCR.TXEIE2 2 Transmitter Empty Interrupt Enable 2 C1TCR.TXEIE1 1 Transmitter Empty Interrupt Enable 1 C1TCR.TXEIE0 0 Transmitter Empty Interrupt Enable 0 C1IDAC 0x0308 msCAN12 Identifier Acceptance Control Register C1IDAC.IDAM1 5 Identifier Acceptance Mode 1 C1IDAC.IDAM0 4 Identifier Acceptance Mode 0 C1IDAC.IDHIT2 2 Identifier Acceptance Hit Indicator 2 C1IDAC.IDHIT1 1 Identifier Acceptance Hit Indicator 1 C1IDAC.IDHIT0 0 Identifier Acceptance Hit Indicator 0 RESERVED0309 0x0309 RESERVED RESERVED030A 0x030A RESERVED RESERVED030B 0x030B RESERVED RESERVED030C 0x030C RESERVED RESERVED030D 0x030D RESERVED C1RXERR 0x030E msCAN12 Receive Error Counter C1RXERR.RXERR7 7 C1RXERR.RXERR6 6 C1RXERR.RXERR5 5 C1RXERR.RXERR4 4 C1RXERR.RXERR3 3 C1RXERR.RXERR2 2 C1RXERR.RXERR1 1 C1RXERR.RXERR0 0 C1TXERR 0x030F msCAN12 Transmit Error Counter C1TXERR.TXERR7 7 C1TXERR.TXERR6 6 C1TXERR.TXERR5 5 C1TXERR.TXERR4 4 C1TXERR.TXERR3 3 C1TXERR.TXERR2 2 C1TXERR.TXERR1 1 C1TXERR.TXERR0 0 C1IDAR0 0x0310 msCAN12 Identifier Acceptance Register 0 C1IDAR0.AC7 7 Acceptance Code Bit 7 C1IDAR0.AC6 6 Acceptance Code Bit 6 C1IDAR0.AC5 5 Acceptance Code Bit 5 C1IDAR0.AC4 4 Acceptance Code Bit 4 C1IDAR0.AC3 3 Acceptance Code Bit 3 C1IDAR0.AC2 2 Acceptance Code Bit 2 C1IDAR0.AC1 1 Acceptance Code Bit 1 C1IDAR0.AC0 0 Acceptance Code Bit 0 C1IDAR1 0x0311 msCAN12 Identifier Acceptance Register 1 C1IDAR1.AC7 7 Acceptance Code Bit 7 C1IDAR1.AC6 6 Acceptance Code Bit 6 C1IDAR1.AC5 5 Acceptance Code Bit 5 C1IDAR1.AC4 4 Acceptance Code Bit 4 C1IDAR1.AC3 3 Acceptance Code Bit 3 C1IDAR1.AC2 2 Acceptance Code Bit 2 C1IDAR1.AC1 1 Acceptance Code Bit 1 C1IDAR1.AC0 0 Acceptance Code Bit 0 C1IDAR2 0x0312 msCAN12 Identifier Acceptance Register 2 C1IDAR2.AC7 7 Acceptance Code Bit 7 C1IDAR2.AC6 6 Acceptance Code Bit 6 C1IDAR2.AC5 5 Acceptance Code Bit 5 C1IDAR2.AC4 4 Acceptance Code Bit 4 C1IDAR2.AC3 3 Acceptance Code Bit 3 C1IDAR2.AC2 2 Acceptance Code Bit 2 C1IDAR2.AC1 1 Acceptance Code Bit 1 C1IDAR2.AC0 0 Acceptance Code Bit 0 C1IDAR3 0x0313 msCAN12 Identifier Acceptance Register 3 C1IDAR3.AC7 7 Acceptance Code Bit 7 C1IDAR3.AC6 6 Acceptance Code Bit 6 C1IDAR3.AC5 5 Acceptance Code Bit 5 C1IDAR3.AC4 4 Acceptance Code Bit 4 C1IDAR3.AC3 3 Acceptance Code Bit 3 C1IDAR3.AC2 2 Acceptance Code Bit 2 C1IDAR3.AC1 1 Acceptance Code Bit 1 C1IDAR3.AC0 0 Acceptance Code Bit 0 C1IDMR0 0x0314 msCAN12 Identifier Mask Register 0 C1IDMR0.AM7 7 Acceptance Mask Bit 7 C1IDMR0.AM6 6 Acceptance Mask Bit 6 C1IDMR0.AM5 5 Acceptance Mask Bit 5 C1IDMR0.AM4 4 Acceptance Mask Bit 4 C1IDMR0.AM3 3 Acceptance Mask Bit 3 C1IDMR0.AM2 2 Acceptance Mask Bit 2 C1IDMR0.AM1 1 Acceptance Mask Bit 1 C1IDMR0.AM0 0 Acceptance Mask Bit 0 C1IDMR1 0x0315 msCAN12 Identifier Mask Register 1 C1IDMR1.AM7 7 Acceptance Mask Bit 7 C1IDMR1.AM6 6 Acceptance Mask Bit 6 C1IDMR1.AM5 5 Acceptance Mask Bit 5 C1IDMR1.AM4 4 Acceptance Mask Bit 4 C1IDMR1.AM3 3 Acceptance Mask Bit 3 C1IDMR1.AM2 2 Acceptance Mask Bit 2 C1IDMR1.AM1 1 Acceptance Mask Bit 1 C1IDMR1.AM0 0 Acceptance Mask Bit 0 C1IDMR2 0x0316 msCAN12 Identifier Mask Register 2 C1IDMR2.AM7 7 Acceptance Mask Bit 7 C1IDMR2.AM6 6 Acceptance Mask Bit 6 C1IDMR2.AM5 5 Acceptance Mask Bit 5 C1IDMR2.AM4 4 Acceptance Mask Bit 4 C1IDMR2.AM3 3 Acceptance Mask Bit 3 C1IDMR2.AM2 2 Acceptance Mask Bit 2 C1IDMR2.AM1 1 Acceptance Mask Bit 1 C1IDMR2.AM0 0 Acceptance Mask Bit 0 C1IDMR3 0x0317 msCAN12 Identifier Mask Register 3 C1IDMR3.AM7 7 Acceptance Mask Bit 7 C1IDMR3.AM6 6 Acceptance Mask Bit 6 C1IDMR3.AM5 5 Acceptance Mask Bit 5 C1IDMR3.AM4 4 Acceptance Mask Bit 4 C1IDMR3.AM3 3 Acceptance Mask Bit 3 C1IDMR3.AM2 2 Acceptance Mask Bit 2 C1IDMR3.AM1 1 Acceptance Mask Bit 1 C1IDMR3.AM0 0 Acceptance Mask Bit 0 C1IDAR4 0x0318 msCAN12 Identifier Acceptance Register 4 C1IDAR4.AC7 7 Acceptance Code Bit 7 C1IDAR4.AC6 6 Acceptance Code Bit 6 C1IDAR4.AC5 5 Acceptance Code Bit 5 C1IDAR4.AC4 4 Acceptance Code Bit 4 C1IDAR4.AC3 3 Acceptance Code Bit 3 C1IDAR4.AC2 2 Acceptance Code Bit 2 C1IDAR4.AC1 1 Acceptance Code Bit 1 C1IDAR4.AC0 0 Acceptance Code Bit 0 C1IDAR5 0x0319 msCAN12 Identifier Acceptance Register 5 C1IDAR5.AC7 7 Acceptance Code Bit 7 C1IDAR5.AC6 6 Acceptance Code Bit 6 C1IDAR5.AC5 5 Acceptance Code Bit 5 C1IDAR5.AC4 4 Acceptance Code Bit 4 C1IDAR5.AC3 3 Acceptance Code Bit 3 C1IDAR5.AC2 2 Acceptance Code Bit 2 C1IDAR5.AC1 1 Acceptance Code Bit 1 C1IDAR5.AC0 0 Acceptance Code Bit 0 C1IDAR6 0x031A msCAN12 Identifier Acceptance Register 6 C1IDAR6.AC7 7 Acceptance Code Bit 7 C1IDAR6.AC6 6 Acceptance Code Bit 6 C1IDAR6.AC5 5 Acceptance Code Bit 5 C1IDAR6.AC4 4 Acceptance Code Bit 4 C1IDAR6.AC3 3 Acceptance Code Bit 3 C1IDAR6.AC2 2 Acceptance Code Bit 2 C1IDAR6.AC1 1 Acceptance Code Bit 1 C1IDAR6.AC0 0 Acceptance Code Bit 0 C1IDAR7 0x031B msCAN12 Identifier Acceptance Register 7 C1IDAR7.AC7 7 Acceptance Code Bit 7 C1IDAR7.AC6 6 Acceptance Code Bit 6 C1IDAR7.AC5 5 Acceptance Code Bit 5 C1IDAR7.AC4 4 Acceptance Code Bit 4 C1IDAR7.AC3 3 Acceptance Code Bit 3 C1IDAR7.AC2 2 Acceptance Code Bit 2 C1IDAR7.AC1 1 Acceptance Code Bit 1 C1IDAR7.AC0 0 Acceptance Code Bit 0 C1IDMR4 0x031C msCAN12 Identifier Mask Register 4 C1IDMR4.AM7 7 Acceptance Mask Bit 7 C1IDMR4.AM6 6 Acceptance Mask Bit 6 C1IDMR4.AM5 5 Acceptance Mask Bit 5 C1IDMR4.AM4 4 Acceptance Mask Bit 4 C1IDMR4.AM3 3 Acceptance Mask Bit 3 C1IDMR4.AM2 2 Acceptance Mask Bit 2 C1IDMR4.AM1 1 Acceptance Mask Bit 1 C1IDMR4.AM0 0 Acceptance Mask Bit 0 C1IDMR5 0x031D msCAN12 Identifier Mask Register 5 C1IDMR5.AM7 7 Acceptance Mask Bit 7 C1IDMR5.AM6 6 Acceptance Mask Bit 6 C1IDMR5.AM5 5 Acceptance Mask Bit 5 C1IDMR5.AM4 4 Acceptance Mask Bit 4 C1IDMR5.AM3 3 Acceptance Mask Bit 3 C1IDMR5.AM2 2 Acceptance Mask Bit 2 C1IDMR5.AM1 1 Acceptance Mask Bit 1 C1IDMR5.AM0 0 Acceptance Mask Bit 0 C1IDMR6 0x031E msCAN12 Identifier Mask Register 6 C1IDMR6.AM7 7 Acceptance Mask Bit 7 C1IDMR6.AM6 6 Acceptance Mask Bit 6 C1IDMR6.AM5 5 Acceptance Mask Bit 5 C1IDMR6.AM4 4 Acceptance Mask Bit 4 C1IDMR6.AM3 3 Acceptance Mask Bit 3 C1IDMR6.AM2 2 Acceptance Mask Bit 2 C1IDMR6.AM1 1 Acceptance Mask Bit 1 C1IDMR6.AM0 0 Acceptance Mask Bit 0 C1IDMR7 0x031F msCAN12 Identifier Mask Register 7 C1IDMR7.AM7 7 Acceptance Mask Bit 7 C1IDMR7.AM6 6 Acceptance Mask Bit 6 C1IDMR7.AM5 5 Acceptance Mask Bit 5 C1IDMR7.AM4 4 Acceptance Mask Bit 4 C1IDMR7.AM3 3 Acceptance Mask Bit 3 C1IDMR7.AM2 2 Acceptance Mask Bit 2 C1IDMR7.AM1 1 Acceptance Mask Bit 1 C1IDMR7.AM0 0 Acceptance Mask Bit 0 RESERVED0320 0x0320 RESERVED RESERVED0321 0x0321 RESERVED RESERVED0322 0x0322 RESERVED RESERVED0323 0x0323 RESERVED RESERVED0324 0x0324 RESERVED RESERVED0325 0x0325 RESERVED RESERVED0326 0x0326 RESERVED RESERVED0327 0x0327 RESERVED RESERVED0328 0x0328 RESERVED RESERVED0329 0x0329 RESERVED RESERVED032A 0x032A RESERVED RESERVED032B 0x032B RESERVED RESERVED032C 0x032C RESERVED RESERVED032D 0x032D RESERVED RESERVED032E 0x032E RESERVED RESERVED032F 0x032F RESERVED RESERVED0330 0x0330 RESERVED RESERVED0331 0x0331 RESERVED RESERVED0332 0x0332 RESERVED RESERVED0333 0x0333 RESERVED RESERVED0334 0x0334 RESERVED RESERVED0335 0x0335 RESERVED RESERVED0336 0x0336 RESERVED RESERVED0337 0x0337 RESERVED RESERVED0338 0x0338 RESERVED RESERVED0339 0x0339 RESERVED RESERVED033A 0x033A RESERVED RESERVED033B 0x033B RESERVED RESERVED033C 0x033C RESERVED PCTLCAN1 0x033D msCAN12 Port CAN Control Register PCTLCAN1.PUPCAN 1 Pull-Up Enable Port CAN PCTLCAN1.RDPCAN 0 Reduced Drive Port CAN PORTCAN1 0x033E msCAN12 Port CAN Data Register PORTCAN1.PCAN7 7 Port CAN Data Bit 7 PORTCAN1.PCAN6 6 Port CAN Data Bit 6 PORTCAN1.PCAN5 5 Port CAN Data Bit 5 PORTCAN1.PCAN4 4 Port CAN Data Bit 4 PORTCAN1.PCAN3 3 Port CAN Data Bit 3 PORTCAN1.PCAN2 2 Port CAN Data Bit 2 PORTCAN1.TxCAN 1 PORTCAN1.RxCAN 0 DDRCAN1 0x033F msCAN12 Port CAN Data Direction Register DDRCAN1.DDCAN7 7 DDRCAN1.DDCAN6 6 DDRCAN1.DDCAN5 5 DDRCAN1.DDCAN4 4 DDRCAN1.DDCAN3 3 DDRCAN1.DDCAN2 2 .68HC912DG128C ; MEMORY MAP area DATA FSR_0 0x0000:0x0140 area DATA RxFG0 0x0140:0x0150 FOREGROUND RECEIVE BUFFER 0 area DATA Tx00 0x0150:0x0160 TRANSMIT BUFFER 00 area DATA Tx01 0x0160:0x0170 TRANSMIT BUFFER 01 area DATA Tx02 0x0170:0x0180 TRANSMIT BUFFER 02 area BSS RESERVED 0x0180:0x01E2 area DATA FSR_1 0x01E2:0x0200 area BSS RESERVED 0x0200:0x0300 area DATA FSR_2 0x0300:0x0340 area DATA RxFG1 0x0340:0x0350 FOREGROUND RECEIVE BUFFER 1 area DATA Tx10 0x0350:0x0360 TRANSMIT BUFFER 10 area DATA Tx11 0x0360:0x0370 TRANSMIT BUFFER 11 area DATA Tx12 0x0370:0x0380 TRANSMIT BUFFER 12 area BSS RESERVED 0x0380:0x0800 area DATA EEPROM 0x0800:0x1000 area BSS RESERVED 0x1000:0x2000 area DATA RAM 0x2000:0x4000 area DATA ROM 0x4000:0xFF00 Flash area DATA USER_VEC 0xFF00:0x10000 ; Interrupt and reset vector assignments interrupt _RESET 0xFFFE Reset interrupt _COPCTL 0xFFFC Clock monitor fail reset interrupt _COP_F_R 0xFFFA COP failure reset interrupt _UIT 0xFFF8 Unimplemented instruction trap interrupt _SWI 0xFFF6 SWI interrupt _XIRQ 0xFFF4 XIRQ interrupt _INTCR_IRQEN 0xFFF2 IRQ interrupt _RTICTL_RTIE 0xFFF0 Real time interrupt interrupt _TMSK1_C0I 0xFFEE Timer channel 0 interrupt _TMSK1_C1I 0xFFEC Timer channel 1 interrupt _TMSK1_C2I 0xFFEA Timer channel 2 interrupt _TMSK1_C3I 0xFFE8 Timer channel 3 interrupt _TMSK1_C4I 0xFFE6 Timer channel 4 interrupt _TMSK1_C5I 0xFFE4 Timer channel 5 interrupt _TMSK1_C6I 0xFFE2 Timer channel 6 interrupt _TMSK1_C7I 0xFFE0 Timer channel 7 interrupt _TMSK2_TOI 0xFFDE Timer overflow interrupt _PACTL_PAOVI 0xFFDC Pulse accumulator overflow interrupt _PACTL_PAI 0xFFDA Pulse accumulator input edge interrupt _SP0CR1_SPIE 0xFFD8 SPI serial transfer complete interrupt _SC0CR2 0xFFD6 SCI 0 interrupt _SC1CR2 0xFFD4 SCI 1 interrupt _ATDxCTL2_ASCIE 0xFFD2 ATD0 or ATD1 interrupt _C0RIER_WUPIE 0xFFD0 MSCAN 0 wake-up interrupt _KWIEJ_KWIEH 0xFFCE Key wake-up J or H interrupt _MCCTL_MCZI 0xFFCC Modulus down counter underflow interrupt _PBCTL_PBOVI 0xFFCA Pulse Accumulator B Overflow interrupt _C0RIER 0xFFC8 MSCAN 0 errors interrupt _C0RIER_RXFIE 0xFFC6 MSCAN 0 receive interrupt _C0TCR_TXEIE 0xFFC4 MSCAN 0 transmit interrupt _PLLCR_LOCKIE_LHIE 0xFFC2 CGM lock and limp home interrupt _IBCR_IBIE 0xFFC0 IIC Bus interrupt _C1RIER_WUPIE 0xFFBE MSCAN 1 wake-up interrupt _C1RIER 0xFFBC MSCAN 1 errors interrupt _C1RIER_RXFIE 0xFFBA MSCAN 1 receive interrupt _C1TCR_TXEIE 0xFFB8 MSCAN 1 transmit ; INPUT/ OUTPUT PORTS PORTA 0x0000 Port A Data Register PORTA.PA7 7 Port A Data Bit 7 PORTA.PA6 6 Port A Data Bit 6 PORTA.PA5 5 Port A Data Bit 5 PORTA.PA4 4 Port A Data Bit 4 PORTA.PA3 3 Port A Data Bit 3 PORTA.PA2 2 Port A Data Bit 2 PORTA.PA1 1 Port A Data Bit 1 PORTA.PA0 0 Port A Data Bit 0 PORTB 0x0001 Port B Data Register PORTB.PB7 7 Port B Data Bit 7 PORTB.PB6 6 Port B Data Bit 6 PORTB.PB5 5 Port B Data Bit 5 PORTB.PB4 4 Port B Data Bit 4 PORTB.PB3 3 Port B Data Bit 3 PORTB.PB2 2 Port B Data Bit 2 PORTB.PB1 1 Port B Data Bit 1 PORTB.PB0 0 Port B Data Bit 0 DDRA 0x0002 Port A Data Direction Register DDRA.DDA7 7 Port A Data Direction Bit 7 DDRA.DDA6 6 Port A Data Direction Bit 6 DDRA.DDA5 5 Port A Data Direction Bit 5 DDRA.DDA4 4 Port A Data Direction Bit 4 DDRA.DDA3 3 Port A Data Direction Bit 3 DDRA.DDA2 2 Port A Data Direction Bit 2 DDRA.DDA1 1 Port A Data Direction Bit 1 DDRA.DDA0 0 Port A Data Direction Bit 0 DDRB 0x0003 Port B Data Direction Register DDRB.DDB7 7 Port B Data Direction Bit 7 DDRB.DDB6 6 Port B Data Direction Bit 6 DDRB.DDB5 5 Port B Data Direction Bit 5 DDRB.DDB4 4 Port B Data Direction Bit 4 DDRB.DDB3 3 Port B Data Direction Bit 3 DDRB.DDB2 2 Port B Data Direction Bit 2 DDRB.DDB1 1 Port B Data Direction Bit 1 DDRB.DDB0 0 Port B Data Direction Bit 0 RESERVED0004 0x0004 RESERVED RESERVED0005 0x0005 RESERVED RESERVED0006 0x0006 RESERVED RESERVED0007 0x0007 RESERVED PORTE 0x0008 Port E Data Register PORTE.PE7 7 Port E Data Bit 7 PORTE.PE6 6 Port E Data Bit 6 PORTE.PE5 5 Port E Data Bit 5 PORTE.PE4 4 Port E Data Bit 4 PORTE.PE3 3 Port E Data Bit 3 PORTE.PE2 2 Port E Data Bit 2 PORTE.PE1 1 Port E Data Bit 1 PORTE.PE0 0 Port E Data Bit 0 DDRE 0x0009 Port E Data Direction Register DDRE.DDE7 7 Port E Data Direction Bit 7 DDRE.DDE6 6 Port E Data Direction Bit 6 DDRE.DDE5 5 Port E Data Direction Bit 5 DDRE.DDE4 4 Port E Data Direction Bit 4 DDRE.DDE3 3 Port E Data Direction Bit 3 DDRE.DDE2 2 Port E Data Direction Bit 2 PEAR 0x000A Port E Assignment Register PEAR.NDBE 7 No Data Bus Enable PEAR.CGMTE 6 Clock Generator Module Testing Enable PEAR.PIPOE 5 Pipe Status Signal Output Enable PEAR.NECLK 4 No External E Clock PEAR.LSTRE 3 Low Strobe (LSTRB) Enable PEAR.RDWE 2 Read/Write Enable PEAR.CALE 1 Calibration Reference Enable PEAR.DBENE 0 DBE or Inverted E Clock on PE7 MODE 0x000B Mode Register MODE.SMODN 7 Mode Select Special MODE.MODB 6 Mode Select B MODE.MODA 5 Mode Select A MODE.ESTR 4 E Clock Stretch Enable MODE.IVIS 3 Internal Visibility MODE.EBSWAI 2 External Bus Module Stop in Wait Control MODE.EMK 1 Emulate Port K MODE.EME 0 PUCR 0x000C Pull-Up Control Register PUCR.PUPK 7 Pull-Up Port K Enable PUCR.PUPJ 6 Pull-Up or Pull-Down Port J Enable PUCR.PUPH 5 Pull-Up or Pull-Down Port H Enable PUCR.PUPE 4 Pull-Up Port E Enable PUCR.PUPB 1 Pull-Up Port B Enable PUCR.PUPA 0 Pull-Up Port A Enable RDRIV 0x000D Reduced Drive of I/O Lines RDRIV.RDPK 7 Reduced Drive of Port K RDRIV.RDPJ 6 Reduced Drive of Port J RDRIV.RDPH 5 Reduced Drive of Port H RDRIV.RDPE 4 Reduced Drive of Port E RDRIV.RDPB 1 Reduced Drive of Port B RDRIV.RDPA 0 Reduced Drive of Port A RESERVED000E 0x000E RESERVED RESERVED000F 0x000F RESERVED INITRM 0x0010 Initialization of Internal RAM Position Register INITRM.RAM15 7 Internal RAM map position 15 INITRM.RAM14 6 Internal RAM map position 14 INITRM.RAM13 5 Internal RAM map position 13 INITRG 0x0011 Initialization of Internal Register Position Register INITRG.REG15 7 Internal register map position 15 INITRG.REG14 6 Internal register map position 14 INITRG.REG13 5 Internal register map position 13 INITRG.REG12 4 Internal register map position 12 INITRG.REG11 3 Internal register map position 11 INITEE 0x0012 Initialization of Internal EEPROM Position Register INITEE.EE15 7 Internal EEPROM map position 15 INITEE.EE14 6 Internal EEPROM map position 14 INITEE.EE13 5 Internal EEPROM map position 13 INITEE.EE12 4 Internal EEPROM map position 12 INITEE.EEON 0 internal EEPROM On (Enabled) MISC 0x0013 Miscellaneous Mapping Control Register MISC.ROMTST 7 FLASH EEPROM Test mode MISC.NDRF 6 Narrow Data Bus for Register-Following Map Space MISC.RFSTR1 5 Register Following Stretch 1 MISC.RFSTR0 4 Register Following Stretch 0 MISC.EXSTR1 3 External Access Stretch 1 MISC.EXSTR0 2 External Access Stretch 0 MISC.ROMHM 1 FLASH EEPROM only in second Half of Map MISC.ROMON 0 Enable FLASH EEPROM RTICTL 0x0014 Real-Time Interrupt Control Register RTICTL.RTIE 7 Real Time Interrupt Enable RTICTL.RSWAI 6 RTI and COP Stop While in Wait RTICTL.RSBCK 5 RTI and COP Stop While in Background Debug Mode RTICTL.RTBYP 3 Real Time Interrupt Divider Chain Bypass RTICTL.RTR2 2 Real-Time Interrupt Rate Select 2 RTICTL.RTR1 1 Real-Time Interrupt Rate Select 1 RTICTL.RTR0 0 Real-Time Interrupt Rate Select 0 RTIFLG 0x0015 Real Time Interrupt Flag Register RTIFLG.RTIF 7 Real Time Interrupt Flag COPCTL 0x0016 COP Control Register COPCTL.CME 7 Clock Monitor Enable COPCTL.FCME 6 Force Clock Monitor Enable COPCTL.FCMCOP 5 Force Clock Monitor Reset or COP Watchdog Reset COPCTL.WCOP 4 Window COP mode COPCTL.DISR 3 Disable Resets from COP Watchdog and Clock Monitor COPCTL.CR2 2 COP Watchdog Timer Rate select bit 2 COPCTL.CR1 1 COP Watchdog Timer Rate select bit 1 COPCTL.CR0 0 COP Watchdog Timer Rate select bit 0 COPRST 0x0017 Arm/Reset COP Timer Register ITST0 0x0018 Interrupt Test Register 0 ITST0.ITE6 7 ITST0.ITE8 6 ITST0.ITEA 5 ITST0.ITEC 4 ITST0.ITEE 3 ITST0.ITF0 2 ITST0.ITF2 1 ITST0.ITF4 0 ITST1 0x0019 Interrupt Test Register 1 ITST1.ITD6 7 ITST1.ITD8 6 ITST1.ITDA 5 ITST1.ITDC 4 ITST1.ITDE 3 ITST1.ITE0 2 ITST1.ITE2 1 ITST1.ITE4 0 ITST2 0x001A Interrupt Test Register 2 ITST2.ITC6 7 ITST2.ITC8 6 ITST2.ITCA 5 ITST2.ITCC 4 ITST2.ITCE 3 ITST2.ITD0 2 ITST2.ITD2 1 ITST2.ITD4 0 ITST3 0x001B Interrupt Test Register 3 ITST3.ITB6 7 ITST3.ITB8 6 ITST3.ITBA 5 ITST3.ITBC 4 ITST3.ITBE 3 ITST3.ITC0 2 ITST3.ITC2 1 ITST3.ITC4 0 RESERVED001C 0x001C RESERVED RESERVED001D 0x001D RESERVED INTCR 0x001E Interrupt Control Register INTCR.IRQE 7 IRQ Select Edge Sensitive Only INTCR.IRQEN 6 External IRQ Enable INTCR.DLY 5 Enable Oscillator Start-up Delay on Exit from STOP HPRIO 0x001F Highest Priority I Interrupt HPRIO.PSEL6 6 HPRIO.PSEL5 5 HPRIO.PSEL4 4 HPRIO.PSEL3 3 HPRIO.PSEL2 2 HPRIO.PSEL1 1 BRKCT0 0x0020 Breakpoint Control Register 0 BRKCT0.BKEN1 7 Breakpoint Mode Enable 1 BRKCT0.BKEN0 6 Breakpoint Mode Enable 0 BRKCT0.BKPM 5 Break on Program Addresses BRKCT0.BK1ALE 3 Breakpoint 1 Range Control BRKCT0.BK0ALE 2 Breakpoint 0 Range Control BRKCT1 0x0021 Breakpoint Control Register 1 BRKCT1.BKDBE 6 Enable Data Bus BRKCT1.BKMBH 5 Breakpoint Mask High BRKCT1.BKMBL 4 Breakpoint Mask Low BRKCT1.BK1RWE 3 R/W Compare Enable BRKCT1.BK1RW 2 R/W Compare Value BRKCT1.BK0RWE 1 R/W Compare Enable BRKCT1.BK0RW 0 R/W Compare Value BRKAH 0x0022 Breakpoint Address Register, High Byte BRKAL 0x0023 Breakpoint Address Register, Low Byte BRKDH 0x0024 Breakpoint Data Register, High Byte BRKDL 0x0025 Breakpoint Data Register, Low Byte RESERVED0026 0x0026 RESERVED RESERVED0027 0x0027 RESERVED PORTJ 0x0028 Port J Data Register PORTJ.PJ7 7 Port J Data Bit 7 PORTJ.PJ6 6 Port J Data Bit 6 PORTJ.PJ5 5 Port J Data Bit 5 PORTJ.PJ4 4 Port J Data Bit 4 PORTJ.PJ3 3 Port J Data Bit 3 PORTJ.PJ2 2 Port J Data Bit 2 PORTJ.PJ1 1 Port J Data Bit 1 PORTJ.PJ0 0 Port J Data Bit 0 PORTH 0x0029 Port H Data Register PORTH.PH7 7 Port H Data Bit 7 PORTH.PH6 6 Port H Data Bit 6 PORTH.PH5 5 Port H Data Bit 5 PORTH.PH4 4 Port H Data Bit 4 PORTH.PH3 3 Port H Data Bit 3 PORTH.PH2 2 Port H Data Bit 2 PORTH.PH1 1 Port H Data Bit 1 PORTH.PH0 0 Port H Data Bit 0 DDRJ 0x002A Port J Data Direction Register DDRJ.DDRJ7 7 Data Direction Port J Bit 7 DDRJ.DDRJ6 6 Data Direction Port J Bit 6 DDRJ.DDRJ5 5 Data Direction Port J Bit 5 DDRJ.DDRJ4 4 Data Direction Port J Bit 4 DDRJ.DDRJ3 3 Data Direction Port J Bit 3 DDRJ.DDRJ2 2 Data Direction Port J Bit 2 DDRJ.DDRJ1 1 Data Direction Port J Bit 1 DDRJ.DDRJ0 0 Data Direction Port J Bit 0 DDRH 0x002B Port J Data Direction Register DDRH.DDRH7 7 Data Direction Port H Bit 7 DDRH.DDRH6 6 Data Direction Port H Bit 6 DDRH.DDRH5 5 Data Direction Port H Bit 5 DDRH.DDRH4 4 Data Direction Port H Bit 4 DDRH.DDRH3 3 Data Direction Port H Bit 3 DDRH.DDRH2 2 Data Direction Port H Bit 2 DDRH.DDRH1 1 Data Direction Port H Bit 1 DDRH.DDRH0 0 Data Direction Port H Bit 0 KWIEJ 0x002C Key Wake-up Port J Interrupt Enable Register KWIEJ.KWIEJ7 7 Key Wake-up Port J Interrupt Enable 7 KWIEJ.KWIEJ6 6 Key Wake-up Port J Interrupt Enable 6 KWIEJ.KWIEJ5 5 Key Wake-up Port J Interrupt Enable 5 KWIEJ.KWIEJ4 4 Key Wake-up Port J Interrupt Enable 4 KWIEJ.KWIEJ3 3 Key Wake-up Port J Interrupt Enable 3 KWIEJ.KWIEJ2 2 Key Wake-up Port J Interrupt Enable 2 KWIEJ.KWIEJ1 1 Key Wake-up Port J Interrupt Enable 1 KWIEJ.KWIEJ0 0 Key Wake-up Port J Interrupt Enable 0 KWIEH 0x002D Key Wake-up Port H Interrupt Enable Register KWIEH.KWIEH7 7 Key Wake-up Port H Interrupt Enable 7 KWIEH.KWIEH6 6 Key Wake-up Port H Interrupt Enable 6 KWIEH.KWIEH5 5 Key Wake-up Port H Interrupt Enable 5 KWIEH.KWIEH4 4 Key Wake-up Port H Interrupt Enable 4 KWIEH.KWIEH3 3 Key Wake-up Port H Interrupt Enable 3 KWIEH.KWIEH2 2 Key Wake-up Port H Interrupt Enable 2 KWIEH.KWIEH1 1 Key Wake-up Port H Interrupt Enable 1 KWIEH.KWIEH0 0 Key Wake-up Port H Interrupt Enable 0 KWIFJ 0x002E Key Wake-up Port J Flag Register KWIFJ.KWIFJ7 7 Key Wake-up Port J Flag 7 KWIFJ.KWIFJ6 6 Key Wake-up Port J Flag 6 KWIFJ.KWIFJ5 5 Key Wake-up Port J Flag 5 KWIFJ.KWIFJ4 4 Key Wake-up Port J Flag 4 KWIFJ.KWIFJ3 3 Key Wake-up Port J Flag 3 KWIFJ.KWIFJ2 2 Key Wake-up Port J Flag 2 KWIFJ.KWIFJ1 1 Key Wake-up Port J Flag 1 KWIFJ.KWIFJ0 0 Key Wake-up Port J Flag 0 KWIFH 0x002F Key Wake-up Port H Flag Register KWIFH.KWIFH7 7 Key Wake-up Port H Flag 7 KWIFH.KWIFH6 6 Key Wake-up Port H Flag 6 KWIFH.KWIFH5 5 Key Wake-up Port H Flag 5 KWIFH.KWIFH4 4 Key Wake-up Port H Flag 4 KWIFH.KWIFH3 3 Key Wake-up Port H Flag 3 KWIFH.KWIFH2 2 Key Wake-up Port H Flag 2 KWIFH.KWIFH1 1 Key Wake-up Port H Flag 1 KWIFH.KWIFH0 0 Key Wake-up Port H Flag 0 KWPJ 0x0030 Key Wake-up Port J Polarity Register KWPJ.KWPJ7 7 Key Wake-up Port J Polarity Select 7 KWPJ.KWPJ6 6 Key Wake-up Port J Polarity Select 6 KWPJ.KWPJ5 5 Key Wake-up Port J Polarity Select 5 KWPJ.KWPJ4 4 Key Wake-up Port J Polarity Select 4 KWPJ.KWPJ3 3 Key Wake-up Port J Polarity Select 3 KWPJ.KWPJ2 2 Key Wake-up Port J Polarity Select 2 KWPJ.KWPJ1 1 Key Wake-up Port J Polarity Select 1 KWPJ.KWPJ0 0 Key Wake-up Port J Polarity Select 0 KWPH 0x0031 Key Wake-up Port H Polarity Register KWPH.KWPH7 7 Key Wake-up Port H Polarity Select 7 KWPH.KWPH6 6 Key Wake-up Port H Polarity Select 6 KWPH.KWPH5 5 Key Wake-up Port H Polarity Select 5 KWPH.KWPH4 4 Key Wake-up Port H Polarity Select 4 KWPH.KWPH3 3 Key Wake-up Port H Polarity Select 3 KWPH.KWPH2 2 Key Wake-up Port H Polarity Select 2 KWPH.KWPH1 1 Key Wake-up Port H Polarity Select 1 KWPH.KWPH0 0 Key Wake-up Port H Polarity Select 0 RESERVED0032 0x0032 RESERVED RESERVED0033 0x0033 RESERVED RESERVED0034 0x0034 RESERVED RESERVED0035 0x0035 RESERVED RESERVED0036 0x0036 RESERVED RESERVED0037 0x0037 RESERVED SYNR 0x0038 Synthesizer Register SYNR.SYN5 5 SYNR.SYN4 4 SYNR.SYN3 3 SYNR.SYN2 2 SYNR.SYN1 1 SYNR.SYN0 0 REFDV 0x0039 Reference Divider Register REFDV.REFDV2 2 REFDV.REFDV1 1 REFDV.REFDV0 0 CGTFLG 0x003A Clock Generator Test Register CGTFLG.TSTOUT7 7 CGTFLG.TSTOUT6 6 CGTFLG.TSTOUT5 5 CGTFLG.TSTOUT4 4 CGTFLG.TSTOUT3 3 CGTFLG.TSTOUT2 2 CGTFLG.TSTOUT1 1 CGTFLG.TSTOUT0 0 PLLFLG 0x003B PLL Flags PLLFLG.LOCKIF 7 PLL Lock Interrupt Flag PLLFLG.LOCK 6 Locked Phase Lock Loop Circuit PLLFLG.LHIF 1 Limp-Home Interrupt Flag PLLFLG.LHOME 0 Limp-Home Mode Status PLLCR 0x003C PLL Control Register PLLCR.LOCKIE 7 PLL LOCK Interrupt Enable PLLCR.PLLON 6 Phase Lock Loop On PLLCR.AUTO 5 Automatic Bandwidth Control PLLCR.ACQ 4 Not in Acquisition PLLCR.PSTP 2 Pseudo-STOP Enable PLLCR.LHIE 1 Limp-Home Interrupt Enable PLLCR.NOLHM 0 No Limp-Home Mode CLKSEL 0x003D Clock Generator Clock select Register CLKSEL.BCSP 6 Bus Clock Select PLL CLKSEL.BCSS 5 Bus Clock Select Slow CLKSEL.MCS 2 Module Clock Select SLOW 0x003E Slow mode Divider Register SLOW.SLDV5 5 SLOW.SLDV4 4 SLOW.SLDV3 3 SLOW.SLDV2 2 SLOW.SLDV1 1 SLOW.SLDV0 0 CGTCTL 0x003F CGTCTL CGTCTL.OPNLE 7 CGTCTL.TRK 6 CGTCTL.TSTCLKE 5 CGTCTL.TST4 4 CGTCTL.TST3 3 CGTCTL.TST2 2 CGTCTL.TST1 1 CGTCTL.TST0 0 PWCLK 0x0040 PWM Clocks and Concatenate PWCLK.CON23 7 Concatenate PWM Channels 2 and 3 PWCLK.CON01 6 Concatenate PWM Channels 0 and 1 PWCLK.PCKA2 5 Prescaler for Clock A 2 PWCLK.PCKA1 4 Prescaler for Clock A 1 PWCLK.PCKA0 3 Prescaler for Clock A 0 PWCLK.PCKB2 2 Prescaler for Clock B 2 PWCLK.PCKB1 1 Prescaler for Clock B 1 PWCLK.PCKB0 0 Prescaler for Clock B 0 PWPOL 0x0041 PWM Clock Select and Polarity PWPOL.PCLK3 7 PWM Channel 3 Clock Select PWPOL.PCLK2 6 PWM Channel 2 Clock Select PWPOL.PCLK1 5 PWM Channel 1 Clock Select PWPOL.PCLK0 4 PWM Channel 0 Clock Select PWPOL.PPOL3 3 PWM Channel 3 Polarity PWPOL.PPOL2 2 PWM Channel 2 Polarity PWPOL.PPOL1 1 PWM Channel 1 Polarity PWPOL.PPOL0 0 PWM Channel 0 Polarity PWEN 0x0042 PWM Enable PWEN.PWEN3 3 PWM Channel 3 Enable PWEN.PWEN2 2 PWM Channel 2 Enable PWEN.PWEN1 1 PWM Channel 1 Enable PWEN.PWEN0 0 PWM Channel 0 Enable PWPRES 0x0043 PWM Prescale Counter PWSCAL0 0x0044 PWM Scale Register 0 PWSCNT0 0x0045 PWM Scale Counter 0 Value PWSCAL1 0x0046 PWM Scale Register 1 PWSCNT1 0x0047 PWM Scale Counter 1 Value PWCNT0 0x0048 PWM Channel Counter 0 PWCNT1 0x0049 PWM Channel Counter 1 PWCNT2 0x004A PWM Channel Counter 2 PWCNT3 0x004B PWM Channel Counter 3 PWPER0 0x004C PWM Channel Period Register 0 PWPER1 0x004D PWM Channel Period Register 1 PWPER2 0x004E PWM Channel Period Register 2 PWPER3 0x004F PWM Channel Period Register 3 PWDTY0 0x0050 PWM Channel Duty Register 0 PWDTY1 0x0051 PWM Channel Duty Register 1 PWDTY2 0x0052 PWM Channel Duty Register 2 PWDTY3 0x0053 PWM Channel Duty Register 3 PWCTL 0x0054 PWM Control Register PWCTL.PSWAI 4 PWM Halts while in Wait Mode PWCTL.CENTR 3 Center-Aligned Output Mode PWCTL.RDPP 2 Reduced Drive of Port P PWCTL.PUPP 1 Pull-Up Port P Enable PWCTL.PSBCK 0 PWM Stops while in Background Mode PWTST 0x0055 PWM Special Mode Register ("Test") PWTST.DISCR 7 Disable Reset of Channel Counter on Write to Channel Counter PWTST.DISCP 6 Disable Compare Count Period PWTST.DISCAL 5 Disable Load of Scale-Counters on Write to the Associated Scale-Registers PORTP 0x0056 Port P Data Register PORTP.PP7 7 Port P Data Bit 7 PORTP.PP6 6 Port P Data Bit 6 PORTP.PP5 5 Port P Data Bit 5 PORTP.PP4 4 Port P Data Bit 4 PORTP.PP3 3 Port P Data Bit 3 PORTP.PP2 2 Port P Data Bit 2 PORTP.PP1 1 Port P Data Bit 1 PORTP.PP0 0 Port P Data Bit 0 DDRP 0x0057 Port P Data Direction Register DDRP.DDP7 7 Port P Data Direction Bit 7 DDRP.DDP6 6 Port P Data Direction Bit 6 DDRP.DDP5 5 Port P Data Direction Bit 5 DDRP.DDP4 4 Port P Data Direction Bit 4 DDRP.DDP3 3 Port P Data Direction Bit 3 DDRP.DDP2 2 Port P Data Direction Bit 2 DDRP.DDP1 1 Port P Data Direction Bit 1 DDRP.DDP0 0 Port P Data Direction Bit 0 RESERVED0058 0x0058 RESERVED RESERVED0059 0x0059 RESERVED RESERVED005A 0x005A RESERVED RESERVED005B 0x005B RESERVED RESERVED005C 0x005C RESERVED RESERVED005D 0x005D RESERVED RESERVED005E 0x005E RESERVED RESERVED005F 0x005F RESERVED RESERVED0060 0x0060 RESERVED RESERVED0061 0x0061 RESERVED ATD0CTL2 0x0062 ATD0 Control Register 2 ATD0CTL2.ADPU 7 ATD Disable ATD0CTL2.AFFC 6 ATD Fast Flag Clear All ATD0CTL2.ASWAI 5 ATD Wait Mode ATD0CTL2.DJM 4 Result Register Data Justification Mode ATD0CTL2.DSGN 3 Signed/Unsigned Result Data Mode ATD0CTL2.ASCIE 1 ATD Sequence Complete Interrupt Enable ATD0CTL2.ASCIF 0 ATD Sequence Complete Interrupt Flag ATD0CTL3 0x0063 ATD0 Control Register 3 ATD0CTL3.S1C 3 Conversion Sequence Length (Least Significant Bit) ATD0CTL3.FIFO 2 Result Register FIFO Mode ATD0CTL3.FRZ1 1 Background Debug (Freeze) Enable 1 ATD0CTL3.FRZ0 0 Background Debug (Freeze) Enable 0 ATD0CTL4 0x0064 ATD0 Control Register 4 ATD0CTL4.RES10 7 10 bit Mode ATD0CTL4.SMP1 6 Select Sample Time 1 ATD0CTL4.SMP0 5 Select Sample Time 0 ATD0CTL4.PRS4 4 Select Divide-By Factor for ATD P-Clock Prescaler 4 ATD0CTL4.PRS3 3 Select Divide-By Factor for ATD P-Clock Prescaler 3 ATD0CTL4.PRS2 2 Select Divide-By Factor for ATD P-Clock Prescaler 2 ATD0CTL4.PRS1 1 Select Divide-By Factor for ATD P-Clock Prescaler 1 ATD0CTL4.PRS0 0 Select Divide-By Factor for ATD P-Clock Prescaler 0 ATD0CTL5 0x0065 ATD0 Control Register 5 ATD0CTL5.S8CM 6 Select 8 Channel Mode ATD0CTL5.SCAN 5 Enable Continuous Channel Scan ATD0CTL5.MULT 4 Enable Multichannel Conversion ATD0CTL5.CD 3 Channel Select for Conversion D ATD0CTL5.CC 2 Channel Select for Conversion C ATD0CTL5.CB 1 Channel Select for Conversion B ATD0CTL5.CA 0 Channel Select for Conversion A ATD0STAT0 0x0066 ATD0 Status Register ATD0STAT0.SCF 7 Sequence Complete Flag ATD0STAT0.CC2 2 Conversion Counter for Current Sequence of Four or Eight Conversions 2 ATD0STAT0.CC1 1 Conversion Counter for Current Sequence of Four or Eight Conversions 1 ATD0STAT0.CC0 0 Conversion Counter for Current Sequence of Four or Eight Conversions 0 ATD0STAT1 0x0067 ATD0 Status Register ATD0STAT1.CCF7 7 Conversion Complete Flag 7 ATD0STAT1.CCF6 6 Conversion Complete Flag 6 ATD0STAT1.CCF5 5 Conversion Complete Flag 5 ATD0STAT1.CCF4 4 Conversion Complete Flag 4 ATD0STAT1.CCF3 3 Conversion Complete Flag 3 ATD0STAT1.CCF2 2 Conversion Complete Flag 2 ATD0STAT1.CCF1 1 Conversion Complete Flag 1 ATD0STAT1.CCF0 0 Conversion Complete Flag 0 ATD0TESTH 0x0068 ATD0 Test Register ATD0TESTH.SAR9 7 SAR Data 9 ATD0TESTH.SAR8 6 SAR Data 8 ATD0TESTH.SAR7 5 SAR Data 7 ATD0TESTH.SAR6 4 SAR Data 6 ATD0TESTH.SAR5 3 SAR Data 5 ATD0TESTH.SAR4 2 SAR Data 4 ATD0TESTH.SAR3 1 SAR Data 3 ATD0TESTH.SAR2 0 SAR Data 2 ATD0TESTL 0x0069 ATD0 Test Register ATD0TESTL.SAR1 7 SAR Data 1 ATD0TESTL.SAR0 6 SAR Data 0 ATD0TESTL.RST 5 Module Reset Bit ATD0TESTL.TSTOUT 4 Multiplex Output of TST[3:0] (Factory Use) ATD0TESTL.TST3 3 Test Bit 3 ATD0TESTL.TST2 2 Test Bit 2 ATD0TESTL.TST1 1 Test Bit 1 ATD0TESTL.TST0 0 Test Bit 0 RESERVED006A 0x006A RESERVED RESERVED006B 0x006B RESERVED RESERVED006C 0x006C RESERVED RESERVED006D 0x006D RESERVED RESERVED006E 0x006E RESERVED PORTAD0 0x006F Port AD0 Data Input Register PORTAD0.PAD07 7 Port AD0 Data Input Bit 7 PORTAD0.PAD06 6 Port AD0 Data Input Bit 6 PORTAD0.PAD05 5 Port AD0 Data Input Bit 5 PORTAD0.PAD04 4 Port AD0 Data Input Bit 4 PORTAD0.PAD03 3 Port AD0 Data Input Bit 3 PORTAD0.PAD02 2 Port AD0 Data Input Bit 2 PORTAD0.PAD01 1 Port AD0 Data Input Bit 1 PORTAD0.PAD00 0 Port AD0 Data Input Bit 0 ADR00H 0x0070 A/D Conversion Result Register High 0 ADR00L 0x0071 A/D Conversion Result Register Low 0 ADR01H 0x0072 A/D Conversion Result Register High 1 ADR01L 0x0073 A/D Conversion Result Register Low 1 ADR02H 0x0074 A/D Conversion Result Register High 2 ADR02L 0x0075 A/D Conversion Result Register Low 2 ADR03H 0x0076 A/D Conversion Result Register High 3 ADR03L 0x0077 A/D Conversion Result Register Low 3 ADR04H 0x0078 A/D Conversion Result Register High 4 ADR04L 0x0079 A/D Conversion Result Register Low 4 ADR05H 0x007A A/D Conversion Result Register High 5 ADR05L 0x007B A/D Conversion Result Register Low 5 ADR06H 0x007C A/D Conversion Result Register High 6 ADR06L 0x007D A/D Conversion Result Register Low 6 ADR07H 0x007E A/D Conversion Result Register High 7 ADR07L 0x007F A/D Conversion Result Register Low 7 TIOS 0x0080 Timer Input Capture/Output Compare Select TIOS.IOS7 7 Input Capture or Output Compare Channel Configuration 7 TIOS.IOS6 6 Input Capture or Output Compare Channel Configuration 6 TIOS.IOS5 5 Input Capture or Output Compare Channel Configuration 5 TIOS.IOS4 4 Input Capture or Output Compare Channel Configuration 4 TIOS.IOS3 3 Input Capture or Output Compare Channel Configuration 3 TIOS.IOS2 2 Input Capture or Output Compare Channel Configuration 2 TIOS.IOS1 1 Input Capture or Output Compare Channel Configuration 1 TIOS.IOS0 0 Input Capture or Output Compare Channel Configuration 0 CFORC 0x0081 Timer Compare Force Register CFORC.FOC7 7 Force Output Compare Action for Channel 7 CFORC.FOC6 6 Force Output Compare Action for Channel 6 CFORC.FOC5 5 Force Output Compare Action for Channel 5 CFORC.FOC4 4 Force Output Compare Action for Channel 4 CFORC.FOC3 3 Force Output Compare Action for Channel 3 CFORC.FOC2 2 Force Output Compare Action for Channel 2 CFORC.FOC1 1 Force Output Compare Action for Channel 1 CFORC.FOC0 0 Force Output Compare Action for Channel 0 OC7M 0x0082 Output Compare 7 Mask Register OC7M.OC7M7 7 OC7M.OC7M6 6 OC7M.OC7M5 5 OC7M.OC7M4 4 OC7M.OC7M3 3 OC7M.OC7M2 2 OC7M.OC7M1 1 OC7M.OC7M0 0 OC7D 0x0083 Output Compare 7 Data Register OC7D.OC7D7 7 OC7D.OC7D6 6 OC7D.OC7D5 5 OC7D.OC7D4 4 OC7D.OC7D3 3 OC7D.OC7D2 2 OC7D.OC7D1 1 OC7D.OC7D0 0 TCNTH 0x0084 Timer Count Register High TCNTL 0x0085 Timer Count Register Low TSCR 0x0086 Timer System Control Register TSCR.TEN 7 Timer Enable TSCR.TSWAI 6 Timer Module Stops While in Wait TSCR.TSBCK 5 Timer and Modulus Counter Stop While in Background Mode TSCR.TFFCA 4 Timer Fast Flag Clear All RESERVED0087 0x0087 RESERVED TCTL1 0x0088 Timer Control Register 1 TCTL1.OM7 7 Output Mode 7 TCTL1.OL7 6 Output Level 7 TCTL1.OM6 5 Output Mode 6 TCTL1.OL6 4 Output Level 6 TCTL1.OM5 3 Output Mode 5 TCTL1.OL5 2 Output Level 5 TCTL1.OM4 1 Output Mode 4 TCTL1.OL4 0 Output Level 4 TCTL2 0x0089 Timer Control Register 2 TCTL2.OM3 7 Output Mode 3 TCTL2.OL3 6 Output Level 3 TCTL2.OM2 5 Output Mode 2 TCTL2.OL2 4 Output Level 2 TCTL2.OM1 3 Output Mode 1 TCTL2.OL1 2 Output Level 1 TCTL2.OM0 1 Output Mode 0 TCTL2.OL0 0 Output Level 0 TCTL3 0x008A Timer Control Register 3 TCTL3.EDG7B 7 Input Capture Edge Control 7B TCTL3.EDG7A 6 Input Capture Edge Control 7A TCTL3.EDG6B 5 Input Capture Edge Control 6B TCTL3.EDG6A 4 Input Capture Edge Control 6A TCTL3.EDG5B 3 Input Capture Edge Control 5B TCTL3.EDG5A 2 Input Capture Edge Control 5A TCTL3.EDG4B 1 Input Capture Edge Control 4B TCTL3.EDG4A 0 Input Capture Edge Control 4A TCTL4 0x008B Timer Control Register 4 TCTL4.EDG3B 7 Input Capture Edge Control 3B TCTL4.EDG3A 6 Input Capture Edge Control 3A TCTL4.EDG2B 5 Input Capture Edge Control 2B TCTL4.EDG2A 4 Input Capture Edge Control 2A TCTL4.EDG1B 3 Input Capture Edge Control 1B TCTL4.EDG1A 2 Input Capture Edge Control 1A TCTL4.EDG0B 1 Input Capture Edge Control 0B TCTL4.EDG0A 0 Input Capture Edge Control 0A TMSK1 0x008C Timer Interrupt Mask 1 TMSK1.C7I 7 Input Capture/Output Compare 7 Interrupt Enable TMSK1.C6I 6 Input Capture/Output Compare 6 Interrupt Enable TMSK1.C5I 5 Input Capture/Output Compare 5 Interrupt Enable TMSK1.C4I 4 Input Capture/Output Compare 4 Interrupt Enable TMSK1.C3I 3 Input Capture/Output Compare 3 Interrupt Enable TMSK1.C2I 2 Input Capture/Output Compare 2 Interrupt Enable TMSK1.C1I 1 Input Capture/Output Compare 1 Interrupt Enable TMSK1.C0I 0 Input Capture/Output Compare 0 Interrupt Enable TMSK2 0x008D Timer Interrupt Mask 2 TMSK2.TOI 7 Timer Overflow Interrupt Enable TMSK2.PUPT 5 Timer Port Pull-Up Resistor Enable TMSK2.RDPT 4 Timer Port Drive Reduction TMSK2.TCRE 3 Timer Counter Reset Enable TMSK2.PR2 2 Timer Prescaler Select 2 TMSK2.PR1 1 Timer Prescaler Select 1 TMSK2.PR0 0 Timer Prescaler Select 0 TFLG1 0x008E Main Timer Interrupt Flag 1 TFLG1.C7F 7 Input Capture/Output Compare Channel 7 Flag TFLG1.C6F 6 Input Capture/Output Compare Channel 6 Flag TFLG1.C5F 5 Input Capture/Output Compare Channel 5 Flag TFLG1.C4F 4 Input Capture/Output Compare Channel 4 Flag TFLG1.C3F 3 Input Capture/Output Compare Channel 3 Flag TFLG1.C2F 2 Input Capture/Output Compare Channel 2 Flag TFLG1.C1F 1 Input Capture/Output Compare Channel 1 Flag TFLG1.C0F 0 Input Capture/Output Compare Channel 0 Flag TFLG2 0x008F Main Timer Interrupt Flag 2 TFLG2.TOF 7 Timer Overflow Flag TC0H 0x0090 Timer Input Capture/Output Compare Register 0 High TC0L 0x0091 Timer Input Capture/Output Compare Register 0 Low TC1H 0x0092 Timer Input Capture/Output Compare Register 1 High TC1L 0x0093 Timer Input Capture/Output Compare Register 1 Low TC2H 0x0094 Timer Input Capture/Output Compare Register 2 High TC2L 0x0095 Timer Input Capture/Output Compare Register 2 Low TC3H 0x0096 Timer Input Capture/Output Compare Register 3 High TC3L 0x0097 Timer Input Capture/Output Compare Register 3 Low TC4H 0x0098 Timer Input Capture/Output Compare Register 4 High TC4L 0x0099 Timer Input Capture/Output Compare Register 4 Low TC5H 0x009A Timer Input Capture/Output Compare Register 5 High TC5L 0x009B Timer Input Capture/Output Compare Register 5 Low TC6H 0x009C Timer Input Capture/Output Compare Register 6 High TC6L 0x009D Timer Input Capture/Output Compare Register 6 Low TC7H 0x009E Timer Input Capture/Output Compare Register 7 High TC7L 0x009F Timer Input Capture/Output Compare Register 7 Low PACTL 0x00A0 16-Bit Pulse Accumulator A Control Register PACTL.PAEN 6 Pulse Accumulator A System Enable PACTL.PAMOD 5 Pulse Accumulator Mode PACTL.PEDGE 4 Pulse Accumulator Edge Control PACTL.CLK1 3 Clock Select Bit 1 PACTL.CLK0 2 Clock Select Bit 0 PACTL.PAOVI 1 Pulse Accumulator A Overflow Interrupt enable PACTL.PAI 0 Pulse Accumulator Input Interrupt enable PAFLG 0x00A1 Pulse Accumulator A Flag Register PAFLG.PAOVF 1 Pulse Accumulator A Overflow Flag PAFLG.PAIF 0 Pulse Accumulator Input edge Flag PACN3 0x00A2 Pulse Accumulators Count Register 3 PACN2 0x00A3 Pulse Accumulators Count Register 2 PACN1 0x00A4 Pulse Accumulators Count Register 1 PACN0 0x00A5 Pulse Accumulators Count Register 0 MCCTL 0x00A6 16-Bit Modulus Down-Counter Control Register MCCTL.MCZI 7 Modulus Counter Underflow Interrupt Enable MCCTL.MODMC 6 Modulus Mode Enable MCCTL.RDMCL 5 Read Modulus Down-Counter Load MCCTL.ICLAT 4 Input Capture Force Latch Action MCCTL.FLMC 3 Force Load Register into the Modulus Counter Count Register MCCTL.MCEN 2 Modulus Down-Counter Enable MCCTL.MCPR1 1 Modulus Counter Prescaler select 1 MCCTL.MCPR0 0 Modulus Counter Prescaler select 0 MCFLG 0x00A7 16-Bit Modulus Down-Counter FLAG Register MCFLG.MCZF 7 Modulus Counter Underflow Interrupt Flag MCFLG.POLF3 3 First Input Capture Polarity Status 3 MCFLG.POLF2 2 First Input Capture Polarity Status 2 MCFLG.POLF1 1 First Input Capture Polarity Status 1 MCFLG.POLF0 0 First Input Capture Polarity Status 0 ICPACR 0x00A8 Input Control Pulse Accumulators Control Register ICPACR.PA3EN 3 8-Bit Pulse Accumulator 3 Enable ICPACR.PA2EN 2 8-Bit Pulse Accumulator 2 Enable ICPACR.PA1EN 1 8-Bit Pulse Accumulator 1 Enable ICPACR.PA0EN 0 8-Bit Pulse Accumulator 0 Enable DLYCT 0x00A9 Delay Counter Control Register DLYCT.DLY1 1 Delay Counter Select 1 DLYCT.DLY0 0 Delay Counter Select 0 ICOVW 0x00AA Input Control Overwrite Register ICOVW.NOVW7 7 No Input Capture Overwrite 7 ICOVW.NOVW6 6 No Input Capture Overwrite 6 ICOVW.NOVW5 5 No Input Capture Overwrite 5 ICOVW.NOVW4 4 No Input Capture Overwrite 4 ICOVW.NOVW3 3 No Input Capture Overwrite 3 ICOVW.NOVW2 2 No Input Capture Overwrite 2 ICOVW.NOVW1 1 No Input Capture Overwrite 1 ICOVW.NOVW0 0 No Input Capture Overwrite 0 ICSYS 0x00AB Input Control System Control Register ICSYS.SH37 7 Share Input action of Input Capture Channels 3 and 7 ICSYS.SH26 6 Share Input action of Input Capture Channels 2 and 6 ICSYS.SH15 5 Share Input action of Input Capture Channels 1 and 5 ICSYS.SH04 4 Share Input action of Input Capture Channels 0 and 4 ICSYS.TFMOD 3 Timer Flag-setting Mode ICSYS.PACMX 2 8-Bit Pulse Accumulators Maximum Count ICSYS.BUFEN 1 IC Buffer Enable ICSYS.LATQ 0 Input Control Latch or Queue Mode Enable RESERVED00AC 0x00AC RESERVED TIMTST 0x00AD Timer Test Register TIMTST.TCBYP 1 Main Timer Divider Chain Bypass PORTT 0x00AE Port T Data Register PORTT.PT7 7 Port T Data Bit 7 PORTT.PT6 6 Port T Data Bit 6 PORTT.PT5 5 Port T Data Bit 5 PORTT.PT4 4 Port T Data Bit 4 PORTT.PT3 3 Port T Data Bit 3 PORTT.PT2 2 Port T Data Bit 2 PORTT.PT1 1 Port T Data Bit 1 PORTT.PT0 0 Port T Data Bit 0 DDRT 0x00AF Port T Data Direction Register DDRT.DDT7 7 Port T Data Direction Bit 7 DDRT.DDT6 6 Port T Data Direction Bit 6 DDRT.DDT5 5 Port T Data Direction Bit 5 DDRT.DDT4 4 Port T Data Direction Bit 4 DDRT.DDT3 3 Port T Data Direction Bit 3 DDRT.DDT2 2 Port T Data Direction Bit 2 DDRT.DDT1 1 Port T Data Direction Bit 1 DDRT.DDT0 0 Port T Data Direction Bit 0 PBCTL 0x00B0 16-Bit Pulse Accumulator B Control Register PBCTL.PBEN 6 Pulse Accumulator B System Enable PBCTL.PBOVI 1 Pulse Accumulator B Overflow Interrupt enable PBFLG 0x00B1 Pulse Accumulator B Flag Register PBFLG.PBOVF 1 Pulse Accumulator B Overflow Flag PA3H 0x00B2 8-Bit Pulse Accumulators Holding Register 3 PA2H 0x00B3 8-Bit Pulse Accumulators Holding Register 2 PA1H 0x00B4 8-Bit Pulse Accumulators Holding Register 1 PA0H 0x00B5 8-Bit Pulse Accumulators Holding Register 0 MCCNTH 0x00B6 Modulus Down-Counter Count Register High MCCNTL 0x00B7 Modulus Down-Counter Count Register Low TC0HH 0x00B8 Timer Input Capture Holding Register 0 High TC0HL 0x00B9 Timer Input Capture Holding Register 0 Low TC1HH 0x00BA Timer Input Capture Holding Register 1 High TC1HL 0x00BB Timer Input Capture Holding Register 1 Low TC2HH 0x00BC Timer Input Capture Holding Register 2 High TC2HL 0x00BD Timer Input Capture Holding Register 2 Low TC3HH 0x00BE Timer Input Capture Holding Register 3 High TC3HL 0x00BF Timer Input Capture Holding Register 3 Low SC0BDH 0x00C0 SCI Baud Rate Control Register High SC0BDH.BTST 7 Reserved for test function SC0BDH.BSPL 6 Reserved for test function SC0BDH.BRLD 5 Reserved for test function SC0BDH.SBR12 4 SC0BDH.SBR11 3 SC0BDH.SBR10 2 SC0BDH.SBR9 1 SC0BDH.SBR8 0 SC0BDL 0x00C1 SCI Baud Rate Control Register Low SC0BDL.SBR7 7 SC0BDL.SBR6 6 SC0BDL.SBR5 5 SC0BDL.SBR4 4 SC0BDL.SBR3 3 SC0BDL.SBR2 2 SC0BDL.SBR1 1 SC0BDL.SBR0 0 SC0CR1 0x00C2 SCI Control Register 1 SC0CR1.LOOPS 7 SCI LOOP Mode/Single Wire Mode Enable SC0CR1.WOMS 6 Wired-Or Mode for Serial Pins SC0CR1.RSRC 5 Receiver Source SC0CR1.M 4 Mode (select character format) SC0CR1.WAKE 3 Wake-up by Address Mark/Idle SC0CR1.ILT 2 Idle Line Type SC0CR1.PE 1 Parity Enable SC0CR1.PT 0 Parity Type SC0CR2 0x00C3 SCI Control Register 2 SC0CR2.TIE 7 Transmit Interrupt Enable SC0CR2.TCIE 6 Transmit Complete Interrupt Enable SC0CR2.RIE 5 Receiver Interrupt Enable SC0CR2.ILIE 4 Idle Line Interrupt Enable SC0CR2.TE 3 Transmitter Enable SC0CR2.RE 2 Receiver Enable SC0CR2.RWU 1 Receiver Wake-Up Control SC0CR2.SBK 0 Send Break SC0SR1 0x00C4 SCI Status Register 1 SC0SR1.TDRE 7 Transmit Data Register Empty Flag SC0SR1.TC 6 Transmit Complete Flag SC0SR1.RDRF 5 Receive Data Register Full Flag SC0SR1.IDLE 4 Idle Line Detected Flag SC0SR1.OR 3 Overrun Error Flag SC0SR1.NF 2 Noise Error Flag SC0SR1.FE 1 Framing Error Flag SC0SR1.PF 0 Parity Error Flag SC0SR2 0x00C5 SCI Status Register 2 SC0SR2.RAF 0 Receiver Active Flag SC0DRH 0x00C6 SCI Data Register High SC0DRH.R8 7 Receive Bit 8 SC0DRH.T8 6 Transmit Bit 8 SC0DRL 0x00C7 SCI Data Register Low SC0DRL.R7_T7 7 Receive/Transmit Data Bit 7 SC0DRL.R6_T6 6 Receive/Transmit Data Bit 6 SC0DRL.R5_T5 5 Receive/Transmit Data Bit 5 SC0DRL.R4_T4 4 Receive/Transmit Data Bit 4 SC0DRL.R3_T3 3 Receive/Transmit Data Bit 3 SC0DRL.R2_T2 2 Receive/Transmit Data Bit 2 SC0DRL.R1_T1 1 Receive/Transmit Data Bit 1 SC0DRL.R0_T0 0 Receive/Transmit Data Bit 0 SC1BDH 0x00C8 SCI Baud Rate Control Register High SC1BDH.BTST 7 Reserved for test function SC1BDH.BSPL 6 Reserved for test function SC1BDH.BRLD 5 Reserved for test function SC1BDH.SBR12 4 SC1BDH.SBR11 3 SC1BDH.SBR10 2 SC1BDH.SBR9 1 SC1BDH.SBR8 0 SC1BDL 0x00C9 SCI Baud Rate Control Register Low SC1BDL.SBR7 7 SC1BDL.SBR6 6 SC1BDL.SBR5 5 SC1BDL.SBR4 4 SC1BDL.SBR3 3 SC1BDL.SBR2 2 SC1BDL.SBR1 1 SC1BDL.SBR0 0 SC1CR1 0x00CA SCI Control Register 1 SC1CR1.LOOPS 7 SCI LOOP Mode/Single Wire Mode Enable SC1CR1.WOMS 6 Wired-Or Mode for Serial Pins SC1CR1.RSRC 5 Receiver Source SC1CR1.M 4 Mode (select character format) SC1CR1.WAKE 3 Wake-up by Address Mark/Idle SC1CR1.ILT 2 Idle Line Type SC1CR1.PE 1 Parity Enable SC1CR1.PT 0 Parity Type SC1CR2 0x00CB SCI Control Register 2 SC1CR2.TIE 7 Transmit Interrupt Enable SC1CR2.TCIE 6 Transmit Complete Interrupt Enable SC1CR2.RIE 5 Receiver Interrupt Enable SC1CR2.ILIE 4 Idle Line Interrupt Enable SC1CR2.TE 3 Transmitter Enable SC1CR2.RE 2 Receiver Enable SC1CR2.RWU 1 Receiver Wake-Up Control SC1CR2.SBK 0 Send Break SC1SR1 0x00CC SCI Status Register 1 SC1SR1.TDRE 7 Transmit Data Register Empty Flag SC1SR1.TC 6 Transmit Complete Flag SC1SR1.RDRF 5 Receive Data Register Full Flag SC1SR1.IDLE 4 Idle Line Detected Flag SC1SR1.OR 3 Overrun Error Flag SC1SR1.NF 2 Noise Error Flag SC1SR1.FE 1 Framing Error Flag SC1SR1.PF 0 Parity Error Flag SC1SR2 0x00CD SCI Status Register 2 SC1SR2.RAF 0 Receiver Active Flag SC1DRH 0x00CE SCI Data Register High SC1DRH.R8 7 Receive Bit 8 SC1DRH.T8 6 Transmit Bit 8 SC1DRL 0x00CF SCI Data Register Low SC1DRL.R7_T7 7 Receive/Transmit Data Bit 7 SC1DRL.R6_T6 6 Receive/Transmit Data Bit 6 SC1DRL.R5_T5 5 Receive/Transmit Data Bit 5 SC1DRL.R4_T4 4 Receive/Transmit Data Bit 4 SC1DRL.R3_T3 3 Receive/Transmit Data Bit 3 SC1DRL.R2_T2 2 Receive/Transmit Data Bit 2 SC1DRL.R1_T1 1 Receive/Transmit Data Bit 1 SC1DRL.R0_T0 0 Receive/Transmit Data Bit 0 SP0CR1 0x00D0 SPI Control Register 1 SP0CR1.SPIE 7 SPI Interrupt Enable SP0CR1.SPE 6 SPI System Enable SP0CR1.SWOM 5 Port S Wired-OR Mode SP0CR1.MSTR 4 SPI Master/Slave Mode Select SP0CR1.CPOL 3 SPI Clock Polarity SP0CR1.CPHA 2 Clock Phase SP0CR1.SSOE 1 Slave Select Output Enable SP0CR1.LSBF 0 SPI LSB First enable SP0CR2 0x00D1 SPI Control Register 2 SP0CR2.PUPS 3 Pull-Up Port S Enable SP0CR2.RDPS 2 Reduce Drive of Port S SP0CR2.SSWAI 1 Serial Interface Stop in WAIT mode SP0CR2.SPC0 0 Serial Pin Control 0 SP0BR 0x00D2 SPI Baud Rate Register SP0BR.SPR2 2 SPI Clock (SCK) Rate Select Bit 2 SP0BR.SPR1 1 SPI Clock (SCK) Rate Select Bit 1 SP0BR.SPR0 0 SPI Clock (SCK) Rate Select Bit 0 SP0SR 0x00D3 SPI Status Register SP0SR.SPIF 7 SPI Interrupt Request SP0SR.WCOL 6 Write Collision Status Flag SP0SR.MODF 4 SPI Mode Error Interrupt Status Flag RESERVED00D4 0x00D4 RESERVED SP0DR 0x00D5 SPI Data Register PORTS 0x00D6 Port S Data Register PORTS.PS7 7 Port S Data Bit 7 PORTS.PS6 6 Port S Data Bit 6 PORTS.PS5 5 Port S Data Bit 5 PORTS.PS4 4 Port S Data Bit 4 PORTS.PS3 3 Port S Data Bit 3 PORTS.PS2 2 Port S Data Bit 2 PORTS.PS1 1 Port S Data Bit 1 PORTS.PS0 0 Port S Data Bit 0 DDRS 0x00D7 Port S Data Direction Register DDRS.DDS7 7 Port S Data Direction Bit 7 DDRS.DDS6 6 Port S Data Direction Bit 6 DDRS.DDS5 5 Port S Data Direction Bit 5 DDRS.DDS4 4 Port S Data Direction Bit 4 DDRS.DDS3 3 Port S Data Direction Bit 3 DDRS.DDS2 2 Port S Data Direction Bit 2 DDRS.DDS1 1 Port S Data Direction Bit 1 DDRS.DDS0 0 Port S Data Direction Bit 0 RESERVED00D8 0x00D8 RESERVED RESERVED00D9 0x00D9 RESERVED RESERVED00DA 0x00DA RESERVED RESERVED00DB 0x00DB RESERVED RESERVED00DC 0x00DC RESERVED RESERVED00DD 0x00DD RESERVED RESERVED00DE 0x00DE RESERVED RESERVED00DF 0x00DF RESERVED IBAD 0x00E0 Bus Address Register IBAD.ADR7 7 Slave Address 7 IBAD.ADR6 6 Slave Address 6 IBAD.ADR5 5 Slave Address 5 IBAD.ADR4 4 Slave Address 4 IBAD.ADR3 3 Slave Address 3 IBAD.ADR2 2 Slave Address 2 IBAD.ADR1 1 Slave Address 1 IBFD 0x00E1 IIC Bus Frequency Divider Register IBFD.IBC5 5 IIC Bus Clock Rate 5 IBFD.IBC4 4 IIC Bus Clock Rate 4 IBFD.IBC3 3 IIC Bus Clock Rate 3 IBFD.IBC2 2 IIC Bus Clock Rate 2 IBFD.IBC1 1 IIC Bus Clock Rate 1 IBFD.IBC0 0 IIC Bus Clock Rate 0 IBCR 0x00E2 IIC Bus Control Register IBCR.IBEN 7 IIC Bus Enable IBCR.IBIE 6 IIC Bus Interrupt Enable IBCR.MS_SL 5 Master/Slave mode select bit IBCR.Tx_Rx 4 Transmit/Receive mode select bit IBCR.TXAK 3 Transmit Acknowledge enable IBCR.RSTA 2 Repeat Start IBCR.IBSWAI 0 IIC Stop in WAIT mode IBSR 0x00E3 IIC Bus Status Register IBSR.TCF 7 Data transferring bit IBSR.IAAS 6 Addressed as a slave bit IBSR.IBB 5 IIC Bus busy bit IBSR.IBAL 4 Arbitration Lost IBSR.SRW 2 Slave Read/Write IBSR.IBIF 1 IIC Bus Interrupt Flag IBSR.RXAK 0 Received Acknowledge IBDR 0x00E4 IIC Bus Data I/O Register IBDR.D7 7 IBDR.D6 6 IBDR.D5 5 IBDR.D4 4 IBDR.D3 3 IBDR.D2 2 IBDR.D1 1 IBDR.D0 0 IBPURD 0x00E5 Pull-Up and Reduced Drive for Port IB IBPURD.RDPIB 4 Reduced Drive of Port IB IBPURD.PUPIB 0 Pull-Up Port IB Enable PORTIB 0x00E6 Port Data IB Register PORTIB.PIB7 7 Port Data IB Register bit 7 PORTIB.PIB6 6 Port Data IB Register bit 6 PORTIB.PIB5 5 Port Data IB Register bit 5 PORTIB.PIB4 4 Port Data IB Register bit 4 PORTIB.PIB3 3 Port Data IB Register bit 3 PORTIB.PIB2 2 Port Data IB Register bit 2 PORTIB.PIB1 1 Port Data IB Register bit 1 PORTIB.PIB0 0 Port Data IB Register bit 0 DDRIB 0x00E7 Data Direction for Port IB Register DDRIB.DDRIB7 7 Port IB Data direction 7 DDRIB.DDRIB6 6 Port IB Data direction 6 DDRIB.DDRIB5 5 Port IB Data direction 5 DDRIB.DDRIB4 4 Port IB Data direction 4 DDRIB.DDRIB3 3 Port IB Data direction 3 DDRIB.DDRIB2 2 Port IB Data direction 2 DDRIB.DDRIB1 1 DDRIB.DDRIB0 0 RESERVED00E8 0x00E8 RESERVED RESERVED00E9 0x00E9 RESERVED RESERVED00EA 0x00EA RESERVED RESERVED00EB 0x00EB RESERVED RESERVED00EC 0x00EC RESERVED RESERVED00ED 0x00ED RESERVED EEDIVH 0x00EE EEPROM Modulus Divider High EEDIVH.EEDIV9 1 Prescaler divider 9 EEDIVH.EEDIV8 0 Prescaler divider 8 EEDIVL 0x00EF EEPROM Modulus Divider Low EEDIVL.EEDIV7 7 Prescaler divider 7 EEDIVL.EEDIV6 6 Prescaler divider 6 EEDIVL.EEDIV5 5 Prescaler divider 5 EEDIVL.EEDIV4 4 Prescaler divider 4 EEDIVL.EEDIV3 3 Prescaler divider 3 EEDIVL.EEDIV2 2 Prescaler divider 2 EEDIVL.EEDIV1 1 Prescaler divider 1 EEDIVL.EEDIV0 0 Prescaler divider 0 EEMCR 0x00F0 EEPROM Module Configuration EEMCR.NOBDML 7 Background Debug Mode Lockout Disable EEMCR.NOSHW 6 SHADOW Byte Disable EEMCR.EESWAI 2 EEPROM Stops in Wait Mode EEMCR.PROTLCK 1 Block Protect Write Lock EEMCR.EERC 0 EEPROM Charge Pump Clock EEPROT 0x00F1 EEPROM Block Protect EEPROT.SHPROT 7 SHADOW Byte Protection EEPROT.BPROT5 5 EEPROM Block Protection 5 EEPROT.BPROT4 4 EEPROM Block Protection 4 EEPROT.BPROT3 3 EEPROM Block Protection 3 EEPROT.BPROT2 2 EEPROM Block Protection 2 EEPROT.BPROT1 1 EEPROM Block Protection 1 EEPROT.BPROT0 0 EEPROM Block Protection 0 EETST 0x00F2 EEPROM Test EETST.EREVTN 6 EETST.ETMSD 2 EETST.ETMR 1 EETST.ETMSE 0 EEPROG 0x00F3 EEPROM Control EEPROG.BULKP 7 Bulk Erase Protection EEPROG..AUTO 5 Automatic shutdown of program/erase operation EEPROG.BYTE 4 Byte and Aligned Word Erase EEPROG.ROW 3 Row or Bulk Erase (when BYTE = 0) EEPROG.ERASE 2 Erase Control EEPROG.EELAT 1 EEPROM Latch Control EEPROG.EEPGM 0 Program and Erase Enable FEELCK 0x00F4 Flash EEPROM Lock Control Register FEELCK.LOCK 0 Lock Register Bit FEEMCR 0x00F5 Flash EEPROM Module Configuration Register FEEMCR.BOOTP 0 Boot Protect FEETST 0x00F6 FEETST FEETST.STRE 7 FEETST.REVTUN 6 FEETST.TMSD 2 FEETST.TMR 1 FEETST.TMSE 0 FEECTL 0x00F7 Flash EEPROM Control Register FEECTL.FEESWAI 4 Flash EEPROM Stop in Wait Control FEECTL.HVEN 3 High-Voltage Enable FEECTL.ERAS 1 Erase Control FEECTL.PGM 0 Program Control MTST0 0x00F8 Mapping Test Register 0 MTST0.MT07 7 MTST0.MT06 6 MTST0.MT05 5 MTST0.MT04 4 MTST0.MT03 3 MTST0.MT02 2 MTST0.MT01 1 MTST0.MT00 0 MTST1 0x00F9 Mapping Test Register 1 MTST1.MT0F 7 MTST1.MT0E 6 MTST1.MT0D 5 MTST1.MT0C 4 MTST1.MT0B 3 MTST1.MT0A 2 MTST1.MT09 1 MTST1.MT08 0 MTST2 0x00FA Mapping Test Register 2 MTST2.MT17 7 MTST2.MT16 6 MTST2.MT15 5 MTST2.MT14 4 MTST2.MT13 3 MTST2.MT12 2 MTST2.MT11 1 MTST2.MT10 0 MTST3 0x00FB Mapping Test Register 3 MTST3.MT1F 7 MTST3.MT1E 6 MTST3.MT1D 5 MTST3.MT1C 4 MTST3.MT1B 3 MTST3.MT1A 2 MTST3.MT19 1 MTST3.MT18 0 PORTK 0x00FC Port K Data Register PORTK.PK7 7 Port K Data Bit 7 PORTK.PK3 3 Port K Data Bit 3 PORTK.PK2 2 Port K Data Bit 2 PORTK.PK1 1 Port K Data Bit 1 PORTK.PK0 0 Port K Data Bit 0 DDRK 0x00FD Port K Data Direction Register DDRK.DDK7 7 Port K Data Direction Bit 7 DDRK.DDK3 3 Port K Data Direction Bit 3 DDRK.DDK2 2 Port K Data Direction Bit 2 DDRK.DDK1 1 Port K Data Direction Bit 1 DDRK.DDK0 0 Port K Data Direction Bit 0 RESERVED00FE 0x00FE RESERVED PPAGE 0x00FF Program Page Index Register PPAGE.PIX2 2 PPAGE.PIX1 1 PPAGE.PIX0 0 C0MCR0 0x0100 msCAN12 Module Control Register 0 C0MCR0.CSWAI 5 CAN Stops in Wait Mode C0MCR0.SYNCH 4 Synchronized Status C0MCR0.TLNKEN 3 Timer Enable C0MCR0.SLPAK 2 SLEEP Mode Acknowledge C0MCR0.SLPRQ 1 SLEEP request C0MCR0.SFTRES 0 SOFT_RESET C0MCR1 0x0101 msCAN12 Module Control Register 1 C0MCR1.LOOPB 2 Loop Back Self Test Mode C0MCR1.WUPM 1 Wake-Up Mode C0MCR1.CLKSRC 0 msCAN12 Clock Source C0BTR0 0x0102 msCAN12 Bus Timing Register 0 C0BTR0.SJW1 7 Synchronization Jump Width 1 C0BTR0.SJW0 6 Synchronization Jump Width 0 C0BTR0.BRP5 5 Baud Rate Prescaler 5 C0BTR0.BRP4 4 Baud Rate Prescaler 4 C0BTR0.BRP3 3 Baud Rate Prescaler 3 C0BTR0.BRP2 2 Baud Rate Prescaler 2 C0BTR0.BRP1 1 Baud Rate Prescaler 1 C0BTR0.BRP0 0 Baud Rate Prescaler 0 C0BTR1 0x0103 msCAN12 Bus Timing Register 1 C0BTR1.SAMP 7 Sampling C0BTR1.TSEG22 6 Time Segment 22 C0BTR1.TSEG21 5 Time Segment 21 C0BTR1.TSEG20 4 Time Segment 20 C0BTR1.TSEG13 3 Time Segment 13 C0BTR1.TSEG12 2 Time Segment 12 C0BTR1.TSEG11 1 Time Segment 11 C0BTR1.TSEG10 0 Time Segment 10 C0RFLG 0x0104 msCAN12 Receiver Flag Register C0RFLG.WUPIF 7 Wake-up Interrupt Flag C0RFLG.RWRNIF 6 Receiver Warning Interrupt Flag C0RFLG.TWRNIF 5 Transmitter Warning Interrupt Flag C0RFLG.RERRIF 4 Receiver Error Passive Interrupt Flag C0RFLG.TERRIF 3 Transmitter Error Passive Interrupt Flag C0RFLG.BOFFIF 2 BUSOFF Interrupt Flag C0RFLG.OVRIF 1 Overrun Interrupt Flag C0RFLG.RXF 0 Receive Buffer Full C0RIER 0x0105 msCAN12 Receiver Interrupt Enable Register C0RIER.WUPIE 7 Wake-up Interrupt Enable C0RIER.RWRNIE 6 Receiver Warning Interrupt Enable C0RIER.TWRNIE 5 Transmitter Warning Interrupt Enable C0RIER.RERRIE 4 Receiver Error Passive Interrupt Enable C0RIER.TERRIE 3 Transmitter Error Passive Interrupt Enable C0RIER.BOFFIE 2 BUSOFF Interrupt Enable C0RIER.OVRIE 1 Overrun Interrupt Enable C0RIER.RXFIE 0 Receiver Full Interrupt Enable C0TFLG 0x0106 msCAN12 Transmitter Flag Register C0TFLG.ABTAK2 6 Abort Acknowledge 2 C0TFLG.ABTAK1 5 Abort Acknowledge 1 C0TFLG.ABTAK0 4 Abort Acknowledge 0 C0TFLG.TXE2 2 Transmitter Buffer Empty 2 C0TFLG.TXE1 1 Transmitter Buffer Empty 1 C0TFLG.TXE0 0 Transmitter Buffer Empty 0 C0TCR 0x0107 msCAN12 Transmitter Control Register C0TCR.ABTRQ2 6 Abort Request 2 C0TCR.ABTRQ1 5 Abort Request 1 C0TCR.ABTRQ0 4 Abort Request 0 C0TCR.TXEIE2 2 Transmitter Empty Interrupt Enable 2 C0TCR.TXEIE1 1 Transmitter Empty Interrupt Enable 1 C0TCR.TXEIE0 0 Transmitter Empty Interrupt Enable 0 C0IDAC 0x0108 msCAN12 Identifier Acceptance Control Register C0IDAC.IDAM1 5 Identifier Acceptance Mode 1 C0IDAC.IDAM0 4 Identifier Acceptance Mode 0 C0IDAC.IDHIT2 2 Identifier Acceptance Hit Indicator 2 C0IDAC.IDHIT1 1 Identifier Acceptance Hit Indicator 1 C0IDAC.IDHIT0 0 Identifier Acceptance Hit Indicator 0 RESERVED0109 0x0109 RESERVED RESERVED010A 0x010A RESERVED RESERVED010B 0x010B RESERVED RESERVED010C 0x010C RESERVED RESERVED010D 0x010D RESERVED C0RXERR 0x010E msCAN12 Receive Error Counter C0RXERR.RXERR7 7 C0RXERR.RXERR6 6 C0RXERR.RXERR5 5 C0RXERR.RXERR4 4 C0RXERR.RXERR3 3 C0RXERR.RXERR2 2 C0RXERR.RXERR1 1 C0RXERR.RXERR0 0 C0TXERR 0x010F msCAN12 Transmit Error Counter C0TXERR.TXERR7 7 C0TXERR.TXERR6 6 C0TXERR.TXERR5 5 C0TXERR.TXERR4 4 C0TXERR.TXERR3 3 C0TXERR.TXERR2 2 C0TXERR.TXERR1 1 C0TXERR.TXERR0 0 C0IDAR0 0x0110 msCAN12 Identifier Acceptance Register 0 C0IDAR0.AC7 7 Acceptance Code Bit 7 C0IDAR0.AC6 6 Acceptance Code Bit 6 C0IDAR0.AC5 5 Acceptance Code Bit 5 C0IDAR0.AC4 4 Acceptance Code Bit 4 C0IDAR0.AC3 3 Acceptance Code Bit 3 C0IDAR0.AC2 2 Acceptance Code Bit 2 C0IDAR0.AC1 1 Acceptance Code Bit 1 C0IDAR0.AC0 0 Acceptance Code Bit 0 C0IDAR1 0x0111 msCAN12 Identifier Acceptance Register 1 C0IDAR1.AC7 7 Acceptance Code Bit 7 C0IDAR1.AC6 6 Acceptance Code Bit 6 C0IDAR1.AC5 5 Acceptance Code Bit 5 C0IDAR1.AC4 4 Acceptance Code Bit 4 C0IDAR1.AC3 3 Acceptance Code Bit 3 C0IDAR1.AC2 2 Acceptance Code Bit 2 C0IDAR1.AC1 1 Acceptance Code Bit 1 C0IDAR1.AC0 0 Acceptance Code Bit 0 C0IDAR2 0x0112 msCAN12 Identifier Acceptance Register 2 C0IDAR2.AC7 7 Acceptance Code Bit 7 C0IDAR2.AC6 6 Acceptance Code Bit 6 C0IDAR2.AC5 5 Acceptance Code Bit 5 C0IDAR2.AC4 4 Acceptance Code Bit 4 C0IDAR2.AC3 3 Acceptance Code Bit 3 C0IDAR2.AC2 2 Acceptance Code Bit 2 C0IDAR2.AC1 1 Acceptance Code Bit 1 C0IDAR2.AC0 0 Acceptance Code Bit 0 C0IDAR3 0x0113 msCAN12 Identifier Acceptance Register 3 C0IDAR3.AC7 7 Acceptance Code Bit 7 C0IDAR3.AC6 6 Acceptance Code Bit 6 C0IDAR3.AC5 5 Acceptance Code Bit 5 C0IDAR3.AC4 4 Acceptance Code Bit 4 C0IDAR3.AC3 3 Acceptance Code Bit 3 C0IDAR3.AC2 2 Acceptance Code Bit 2 C0IDAR3.AC1 1 Acceptance Code Bit 1 C0IDAR3.AC0 0 Acceptance Code Bit 0 C0IDMR0 0x0114 msCAN12 Identifier Mask Register 0 C0IDMR0.AM7 7 Acceptance Mask Bit 7 C0IDMR0.AM6 6 Acceptance Mask Bit 6 C0IDMR0.AM5 5 Acceptance Mask Bit 5 C0IDMR0.AM4 4 Acceptance Mask Bit 4 C0IDMR0.AM3 3 Acceptance Mask Bit 3 C0IDMR0.AM2 2 Acceptance Mask Bit 2 C0IDMR0.AM1 1 Acceptance Mask Bit 1 C0IDMR0.AM0 0 Acceptance Mask Bit 0 C0IDMR1 0x0115 msCAN12 Identifier Mask Register 1 C0IDMR1.AM7 7 Acceptance Mask Bit 7 C0IDMR1.AM6 6 Acceptance Mask Bit 6 C0IDMR1.AM5 5 Acceptance Mask Bit 5 C0IDMR1.AM4 4 Acceptance Mask Bit 4 C0IDMR1.AM3 3 Acceptance Mask Bit 3 C0IDMR1.AM2 2 Acceptance Mask Bit 2 C0IDMR1.AM1 1 Acceptance Mask Bit 1 C0IDMR1.AM0 0 Acceptance Mask Bit 0 C0IDMR2 0x0116 msCAN12 Identifier Mask Register 2 C0IDMR2.AM7 7 Acceptance Mask Bit 7 C0IDMR2.AM6 6 Acceptance Mask Bit 6 C0IDMR2.AM5 5 Acceptance Mask Bit 5 C0IDMR2.AM4 4 Acceptance Mask Bit 4 C0IDMR2.AM3 3 Acceptance Mask Bit 3 C0IDMR2.AM2 2 Acceptance Mask Bit 2 C0IDMR2.AM1 1 Acceptance Mask Bit 1 C0IDMR2.AM0 0 Acceptance Mask Bit 0 C0IDMR3 0x0117 msCAN12 Identifier Mask Register 3 C0IDMR3.AM7 7 Acceptance Mask Bit 7 C0IDMR3.AM6 6 Acceptance Mask Bit 6 C0IDMR3.AM5 5 Acceptance Mask Bit 5 C0IDMR3.AM4 4 Acceptance Mask Bit 4 C0IDMR3.AM3 3 Acceptance Mask Bit 3 C0IDMR3.AM2 2 Acceptance Mask Bit 2 C0IDMR3.AM1 1 Acceptance Mask Bit 1 C0IDMR3.AM0 0 Acceptance Mask Bit 0 C0IDAR4 0x0118 msCAN12 Identifier Acceptance Register 4 C0IDAR4.AC7 7 Acceptance Code Bit 7 C0IDAR4.AC6 6 Acceptance Code Bit 6 C0IDAR4.AC5 5 Acceptance Code Bit 5 C0IDAR4.AC4 4 Acceptance Code Bit 4 C0IDAR4.AC3 3 Acceptance Code Bit 3 C0IDAR4.AC2 2 Acceptance Code Bit 2 C0IDAR4.AC1 1 Acceptance Code Bit 1 C0IDAR4.AC0 0 Acceptance Code Bit 0 C0IDAR5 0x0119 msCAN12 Identifier Acceptance Register 5 C0IDAR5.AC7 7 Acceptance Code Bit 7 C0IDAR5.AC6 6 Acceptance Code Bit 6 C0IDAR5.AC5 5 Acceptance Code Bit 5 C0IDAR5.AC4 4 Acceptance Code Bit 4 C0IDAR5.AC3 3 Acceptance Code Bit 3 C0IDAR5.AC2 2 Acceptance Code Bit 2 C0IDAR5.AC1 1 Acceptance Code Bit 1 C0IDAR5.AC0 0 Acceptance Code Bit 0 C0IDAR6 0x011A msCAN12 Identifier Acceptance Register 6 C0IDAR6.AC7 7 Acceptance Code Bit 7 C0IDAR6.AC6 6 Acceptance Code Bit 6 C0IDAR6.AC5 5 Acceptance Code Bit 5 C0IDAR6.AC4 4 Acceptance Code Bit 4 C0IDAR6.AC3 3 Acceptance Code Bit 3 C0IDAR6.AC2 2 Acceptance Code Bit 2 C0IDAR6.AC1 1 Acceptance Code Bit 1 C0IDAR6.AC0 0 Acceptance Code Bit 0 C0IDAR7 0x011B msCAN12 Identifier Acceptance Register 7 C0IDAR7.AC7 7 Acceptance Code Bit 7 C0IDAR7.AC6 6 Acceptance Code Bit 6 C0IDAR7.AC5 5 Acceptance Code Bit 5 C0IDAR7.AC4 4 Acceptance Code Bit 4 C0IDAR7.AC3 3 Acceptance Code Bit 3 C0IDAR7.AC2 2 Acceptance Code Bit 2 C0IDAR7.AC1 1 Acceptance Code Bit 1 C0IDAR7.AC0 0 Acceptance Code Bit 0 C0IDMR4 0x011C msCAN12 Identifier Mask Register 4 C0IDMR4.AM7 7 Acceptance Mask Bit 7 C0IDMR4.AM6 6 Acceptance Mask Bit 6 C0IDMR4.AM5 5 Acceptance Mask Bit 5 C0IDMR4.AM4 4 Acceptance Mask Bit 4 C0IDMR4.AM3 3 Acceptance Mask Bit 3 C0IDMR4.AM2 2 Acceptance Mask Bit 2 C0IDMR4.AM1 1 Acceptance Mask Bit 1 C0IDMR4.AM0 0 Acceptance Mask Bit 0 C0IDMR5 0x011D msCAN12 Identifier Mask Register 5 C0IDMR5.AM7 7 Acceptance Mask Bit 7 C0IDMR5.AM6 6 Acceptance Mask Bit 6 C0IDMR5.AM5 5 Acceptance Mask Bit 5 C0IDMR5.AM4 4 Acceptance Mask Bit 4 C0IDMR5.AM3 3 Acceptance Mask Bit 3 C0IDMR5.AM2 2 Acceptance Mask Bit 2 C0IDMR5.AM1 1 Acceptance Mask Bit 1 C0IDMR5.AM0 0 Acceptance Mask Bit 0 C0IDMR6 0x011E msCAN12 Identifier Mask Register 6 C0IDMR6.AM7 7 Acceptance Mask Bit 7 C0IDMR6.AM6 6 Acceptance Mask Bit 6 C0IDMR6.AM5 5 Acceptance Mask Bit 5 C0IDMR6.AM4 4 Acceptance Mask Bit 4 C0IDMR6.AM3 3 Acceptance Mask Bit 3 C0IDMR6.AM2 2 Acceptance Mask Bit 2 C0IDMR6.AM1 1 Acceptance Mask Bit 1 C0IDMR6.AM0 0 Acceptance Mask Bit 0 C0IDMR7 0x011F msCAN12 Identifier Mask Register 7 C0IDMR7.AM7 7 Acceptance Mask Bit 7 C0IDMR7.AM6 6 Acceptance Mask Bit 6 C0IDMR7.AM5 5 Acceptance Mask Bit 5 C0IDMR7.AM4 4 Acceptance Mask Bit 4 C0IDMR7.AM3 3 Acceptance Mask Bit 3 C0IDMR7.AM2 2 Acceptance Mask Bit 2 C0IDMR7.AM1 1 Acceptance Mask Bit 1 C0IDMR7.AM0 0 Acceptance Mask Bit 0 RESERVED0120 0x0120 RESERVED RESERVED0121 0x0121 RESERVED RESERVED0122 0x0122 RESERVED RESERVED0123 0x0123 RESERVED RESERVED0124 0x0124 RESERVED RESERVED0125 0x0125 RESERVED RESERVED0126 0x0126 RESERVED RESERVED0127 0x0127 RESERVED RESERVED0128 0x0128 RESERVED RESERVED0129 0x0129 RESERVED RESERVED012A 0x012A RESERVED RESERVED012B 0x012B RESERVED RESERVED012C 0x012C RESERVED RESERVED012D 0x012D RESERVED RESERVED012E 0x012E RESERVED RESERVED012F 0x012F RESERVED RESERVED0130 0x0130 RESERVED RESERVED0131 0x0131 RESERVED RESERVED0132 0x0132 RESERVED RESERVED0133 0x0133 RESERVED RESERVED0134 0x0134 RESERVED RESERVED0135 0x0135 RESERVED RESERVED0136 0x0136 RESERVED RESERVED0137 0x0137 RESERVED RESERVED0138 0x0138 RESERVED RESERVED0139 0x0139 RESERVED RESERVED013A 0x013A RESERVED RESERVED013B 0x013B RESERVED RESERVED013C 0x013C RESERVED PCTLCAN0 0x013D msCAN12 Port CAN Control Register PCTLCAN0.PUPCAN 1 Pull-Up Enable Port CAN PCTLCAN0.RDPCAN 0 Reduced Drive Port CAN PORTCAN0 0x013E msCAN12 Port CAN Data Register PORTCAN0.PCAN7 7 Port CAN Data Bit 7 PORTCAN0.PCAN6 6 Port CAN Data Bit 6 PORTCAN0.PCAN5 5 Port CAN Data Bit 5 PORTCAN0.PCAN4 4 Port CAN Data Bit 4 PORTCAN0.PCAN3 3 Port CAN Data Bit 3 PORTCAN0.PCAN2 2 Port CAN Data Bit 2 PORTCAN0.TxCAN 1 PORTCAN0.RxCAN 0 DDRCAN0 0x013F msCAN12 Port CAN Data Direction Register DDRCAN0.DDCAN7 7 DDRCAN0.DDCAN6 6 DDRCAN0.DDCAN5 5 DDRCAN0.DDCAN4 4 DDRCAN0.DDCAN3 3 DDRCAN0.DDCAN2 2 ATD1CTL2 0x01E2 ATD1 Control Register 2 ATD1CTL2.ADPU 7 ATD Disable ATD1CTL2.AFFC 6 ATD Fast Flag Clear All ATD1CTL2.ASWAI 5 ATD Wait Mode ATD1CTL2.DJM 4 Result Register Data Justification Mode ATD1CTL2.DSGN 3 Signed/Unsigned Result Data Mode ATD1CTL2.ASCIE 1 ATD Sequence Complete Interrupt Enable ATD1CTL2.ASCIF 0 ATD Sequence Complete Interrupt Flag ATD1CTL3 0x01E3 ATD1 Control Register 3 ATD1CTL3.S1C 3 Conversion Sequence Length (Least Significant Bit) ATD1CTL3.FIFO 2 Result Register FIFO Mode ATD1CTL3.FRZ1 1 Background Debug (Freeze) Enable 1 ATD1CTL3.FRZ0 0 Background Debug (Freeze) Enable 0 ATD1CTL4 0x01E4 ATD1 Control Register 4 ATD1CTL4.RES10 7 10 bit Mode ATD1CTL4.SMP1 6 Select Sample Time 1 ATD1CTL4.SMP0 5 Select Sample Time 0 ATD1CTL4.PRS4 4 Select Divide-By Factor for ATD P-Clock Prescaler 4 ATD1CTL4.PRS3 3 Select Divide-By Factor for ATD P-Clock Prescaler 3 ATD1CTL4.PRS2 2 Select Divide-By Factor for ATD P-Clock Prescaler 2 ATD1CTL4.PRS1 1 Select Divide-By Factor for ATD P-Clock Prescaler 1 ATD1CTL4.PRS0 0 Select Divide-By Factor for ATD P-Clock Prescaler 0 ATD1CTL5 0x01E5 ATD1 Control Register 5 ATD1CTL5.S8CM 6 Select 8 Channel Mode ATD1CTL5.SCAN 5 Enable Continuous Channel Scan ATD1CTL5.MULT 4 Enable Multichannel Conversion ATD1CTL5.CD 3 Channel Select for Conversion D ATD1CTL5.CC 2 Channel Select for Conversion C ATD1CTL5.CB 1 Channel Select for Conversion B ATD1CTL5.CA 0 Channel Select for Conversion A ATD1STAT0 0x01E6 ATD1 Status Register ATD1STAT0.SCF 7 Sequence Complete Flag ATD1STAT0.CC2 2 Conversion Counter for Current Sequence of Four or Eight Conversions 2 ATD1STAT0.CC1 1 Conversion Counter for Current Sequence of Four or Eight Conversions 1 ATD1STAT0.CC0 0 Conversion Counter for Current Sequence of Four or Eight Conversions 0 ATD1STAT1 0x01E7 ATD1 Status Register ATD1STAT1.CCF7 7 Conversion Complete Flag 7 ATD1STAT1.CCF6 6 Conversion Complete Flag 6 ATD1STAT1.CCF5 5 Conversion Complete Flag 5 ATD1STAT1.CCF4 4 Conversion Complete Flag 4 ATD1STAT1.CCF3 3 Conversion Complete Flag 3 ATD1STAT1.CCF2 2 Conversion Complete Flag 2 ATD1STAT1.CCF1 1 Conversion Complete Flag 1 ATD1STAT1.CCF0 0 Conversion Complete Flag 0 ATD1TESTH 0x01E8 ATD1 Test Register ATD1TESTH.SAR9 7 SAR Data 9 ATD1TESTH.SAR8 6 SAR Data 8 ATD1TESTH.SAR7 5 SAR Data 7 ATD1TESTH.SAR6 4 SAR Data 6 ATD1TESTH.SAR5 3 SAR Data 5 ATD1TESTH.SAR4 2 SAR Data 4 ATD1TESTH.SAR3 1 SAR Data 3 ATD1TESTH.SAR2 0 SAR Data 2 ATD1TESTL 0x01E9 ATD1 Test Register ATD1TESTL.SAR1 7 SAR Data 1 ATD1TESTL.SAR0 6 SAR Data 0 ATD1TESTL.RST 5 Module Reset Bit ATD1TESTL.TSTOUT 4 Multiplex Output of TST[3:0] (Factory Use) ATD1TESTL.TST3 3 Test Bit 3 ATD1TESTL.TST2 2 Test Bit 2 ATD1TESTL.TST1 1 Test Bit 1 ATD1TESTL.TST0 0 Test Bit 0 RESERVED01EA 0x01EA RESERVED RESERVED01EB 0x01EB RESERVED RESERVED01EC 0x01EC RESERVED RESERVED01ED 0x01ED RESERVED RESERVED01EE 0x01EE RESERVED PORTAD1 0x01EF Port AD1 Data Input Register PORTAD1.PAD17 7 Port AD1 Data Input Bit 7 PORTAD1.PAD16 6 Port AD1 Data Input Bit 6 PORTAD1.PAD15 5 Port AD1 Data Input Bit 5 PORTAD1.PAD14 4 Port AD1 Data Input Bit 4 PORTAD1.PAD13 3 Port AD1 Data Input Bit 3 PORTAD1.PAD12 2 Port AD1 Data Input Bit 2 PORTAD1.PAD11 1 Port AD1 Data Input Bit 1 PORTAD1.PAD10 0 Port AD1 Data Input Bit 0 ADR10H 0x01F0 A/D Conversion Result Register High 0 ADR10L 0x01F1 A/D Conversion Result Register Low 0 ADR11H 0x01F2 A/D Conversion Result Register High 1 ADR11L 0x01F3 A/D Conversion Result Register Low 1 ADR12H 0x01F4 A/D Conversion Result Register High 2 ADR12L 0x01F5 A/D Conversion Result Register Low 2 ADR13H 0x01F6 A/D Conversion Result Register High 3 ADR13L 0x01F7 A/D Conversion Result Register Low 3 ADR14H 0x01F8 A/D Conversion Result Register High 4 ADR14L 0x01F9 A/D Conversion Result Register Low 4 ADR15H 0x01FA A/D Conversion Result Register High 5 ADR15L 0x01FB A/D Conversion Result Register Low 5 ADR16H 0x01FC A/D Conversion Result Register High 6 ADR16L 0x01FD A/D Conversion Result Register Low 6 ADR17H 0x01FE A/D Conversion Result Register High 7 ADR17L 0x01FF A/D Conversion Result Register Low 7 C1MCR0 0x0300 msCAN12 Module Control Register 0 C1MCR0.CSWAI 5 CAN Stops in Wait Mode C1MCR0.SYNCH 4 Synchronized Status C1MCR0.TLNKEN 3 Timer Enable C1MCR0.SLPAK 2 SLEEP Mode Acknowledge C1MCR0.SLPRQ 1 SLEEP request C1MCR0.SFTRES 0 SOFT_RESET C1MCR1 0x0301 msCAN12 Module Control Register 1 C1MCR1.LOOPB 2 Loop Back Self Test Mode C1MCR1.WUPM 1 Wake-Up Mode C1MCR1.CLKSRC 0 msCAN12 Clock Source C1BTR0 0x0302 msCAN12 Bus Timing Register 0 C1BTR0.SJW1 7 Synchronization Jump Width 1 C1BTR0.SJW0 6 Synchronization Jump Width 0 C1BTR0.BRP5 5 Baud Rate Prescaler 5 C1BTR0.BRP4 4 Baud Rate Prescaler 4 C1BTR0.BRP3 3 Baud Rate Prescaler 3 C1BTR0.BRP2 2 Baud Rate Prescaler 2 C1BTR0.BRP1 1 Baud Rate Prescaler 1 C1BTR0.BRP0 0 Baud Rate Prescaler 0 C1BTR1 0x0303 msCAN12 Bus Timing Register 1 C1BTR1.SAMP 7 Sampling C1BTR1.TSEG22 6 Time Segment 22 C1BTR1.TSEG21 5 Time Segment 21 C1BTR1.TSEG20 4 Time Segment 20 C1BTR1.TSEG13 3 Time Segment 13 C1BTR1.TSEG12 2 Time Segment 12 C1BTR1.TSEG11 1 Time Segment 11 C1BTR1.TSEG10 0 Time Segment 10 C1RFLG 0x0304 msCAN12 Receiver Flag Register C1RFLG.WUPIF 7 Wake-up Interrupt Flag C1RFLG.RWRNIF 6 Receiver Warning Interrupt Flag C1RFLG.TWRNIF 5 Transmitter Warning Interrupt Flag C1RFLG.RERRIF 4 Receiver Error Passive Interrupt Flag C1RFLG.TERRIF 3 Transmitter Error Passive Interrupt Flag C1RFLG.BOFFIF 2 BUSOFF Interrupt Flag C1RFLG.OVRIF 1 Overrun Interrupt Flag C1RFLG.RXF 0 Receive Buffer Full C1RIER 0x0305 msCAN12 Receiver Interrupt Enable Register C1RIER.WUPIE 7 Wake-up Interrupt Enable C1RIER.RWRNIE 6 Receiver Warning Interrupt Enable C1RIER.TWRNIE 5 Transmitter Warning Interrupt Enable C1RIER.RERRIE 4 Receiver Error Passive Interrupt Enable C1RIER.TERRIE 3 Transmitter Error Passive Interrupt Enable C1RIER.BOFFIE 2 BUSOFF Interrupt Enable C1RIER.OVRIE 1 Overrun Interrupt Enable C1RIER.RXFIE 0 Receiver Full Interrupt Enable C1TFLG 0x0306 msCAN12 Transmitter Flag Register C1TFLG.ABTAK2 6 Abort Acknowledge 2 C1TFLG.ABTAK1 5 Abort Acknowledge 1 C1TFLG.ABTAK0 4 Abort Acknowledge 0 C1TFLG.TXE2 2 Transmitter Buffer Empty 2 C1TFLG.TXE1 1 Transmitter Buffer Empty 1 C1TFLG.TXE0 0 Transmitter Buffer Empty 0 C1TCR 0x0307 msCAN12 Transmitter Control Register C1TCR.ABTRQ2 6 Abort Request 2 C1TCR.ABTRQ1 5 Abort Request 1 C1TCR.ABTRQ0 4 Abort Request 0 C1TCR.TXEIE2 2 Transmitter Empty Interrupt Enable 2 C1TCR.TXEIE1 1 Transmitter Empty Interrupt Enable 1 C1TCR.TXEIE0 0 Transmitter Empty Interrupt Enable 0 C1IDAC 0x0308 msCAN12 Identifier Acceptance Control Register C1IDAC.IDAM1 5 Identifier Acceptance Mode 1 C1IDAC.IDAM0 4 Identifier Acceptance Mode 0 C1IDAC.IDHIT2 2 Identifier Acceptance Hit Indicator 2 C1IDAC.IDHIT1 1 Identifier Acceptance Hit Indicator 1 C1IDAC.IDHIT0 0 Identifier Acceptance Hit Indicator 0 RESERVED0309 0x0309 RESERVED RESERVED030A 0x030A RESERVED RESERVED030B 0x030B RESERVED RESERVED030C 0x030C RESERVED RESERVED030D 0x030D RESERVED C1RXERR 0x030E msCAN12 Receive Error Counter C1RXERR.RXERR7 7 C1RXERR.RXERR6 6 C1RXERR.RXERR5 5 C1RXERR.RXERR4 4 C1RXERR.RXERR3 3 C1RXERR.RXERR2 2 C1RXERR.RXERR1 1 C1RXERR.RXERR0 0 C1TXERR 0x030F msCAN12 Transmit Error Counter C1TXERR.TXERR7 7 C1TXERR.TXERR6 6 C1TXERR.TXERR5 5 C1TXERR.TXERR4 4 C1TXERR.TXERR3 3 C1TXERR.TXERR2 2 C1TXERR.TXERR1 1 C1TXERR.TXERR0 0 C1IDAR0 0x0310 msCAN12 Identifier Acceptance Register 0 C1IDAR0.AC7 7 Acceptance Code Bit 7 C1IDAR0.AC6 6 Acceptance Code Bit 6 C1IDAR0.AC5 5 Acceptance Code Bit 5 C1IDAR0.AC4 4 Acceptance Code Bit 4 C1IDAR0.AC3 3 Acceptance Code Bit 3 C1IDAR0.AC2 2 Acceptance Code Bit 2 C1IDAR0.AC1 1 Acceptance Code Bit 1 C1IDAR0.AC0 0 Acceptance Code Bit 0 C1IDAR1 0x0311 msCAN12 Identifier Acceptance Register 1 C1IDAR1.AC7 7 Acceptance Code Bit 7 C1IDAR1.AC6 6 Acceptance Code Bit 6 C1IDAR1.AC5 5 Acceptance Code Bit 5 C1IDAR1.AC4 4 Acceptance Code Bit 4 C1IDAR1.AC3 3 Acceptance Code Bit 3 C1IDAR1.AC2 2 Acceptance Code Bit 2 C1IDAR1.AC1 1 Acceptance Code Bit 1 C1IDAR1.AC0 0 Acceptance Code Bit 0 C1IDAR2 0x0312 msCAN12 Identifier Acceptance Register 2 C1IDAR2.AC7 7 Acceptance Code Bit 7 C1IDAR2.AC6 6 Acceptance Code Bit 6 C1IDAR2.AC5 5 Acceptance Code Bit 5 C1IDAR2.AC4 4 Acceptance Code Bit 4 C1IDAR2.AC3 3 Acceptance Code Bit 3 C1IDAR2.AC2 2 Acceptance Code Bit 2 C1IDAR2.AC1 1 Acceptance Code Bit 1 C1IDAR2.AC0 0 Acceptance Code Bit 0 C1IDAR3 0x0313 msCAN12 Identifier Acceptance Register 3 C1IDAR3.AC7 7 Acceptance Code Bit 7 C1IDAR3.AC6 6 Acceptance Code Bit 6 C1IDAR3.AC5 5 Acceptance Code Bit 5 C1IDAR3.AC4 4 Acceptance Code Bit 4 C1IDAR3.AC3 3 Acceptance Code Bit 3 C1IDAR3.AC2 2 Acceptance Code Bit 2 C1IDAR3.AC1 1 Acceptance Code Bit 1 C1IDAR3.AC0 0 Acceptance Code Bit 0 C1IDMR0 0x0314 msCAN12 Identifier Mask Register 0 C1IDMR0.AM7 7 Acceptance Mask Bit 7 C1IDMR0.AM6 6 Acceptance Mask Bit 6 C1IDMR0.AM5 5 Acceptance Mask Bit 5 C1IDMR0.AM4 4 Acceptance Mask Bit 4 C1IDMR0.AM3 3 Acceptance Mask Bit 3 C1IDMR0.AM2 2 Acceptance Mask Bit 2 C1IDMR0.AM1 1 Acceptance Mask Bit 1 C1IDMR0.AM0 0 Acceptance Mask Bit 0 C1IDMR1 0x0315 msCAN12 Identifier Mask Register 1 C1IDMR1.AM7 7 Acceptance Mask Bit 7 C1IDMR1.AM6 6 Acceptance Mask Bit 6 C1IDMR1.AM5 5 Acceptance Mask Bit 5 C1IDMR1.AM4 4 Acceptance Mask Bit 4 C1IDMR1.AM3 3 Acceptance Mask Bit 3 C1IDMR1.AM2 2 Acceptance Mask Bit 2 C1IDMR1.AM1 1 Acceptance Mask Bit 1 C1IDMR1.AM0 0 Acceptance Mask Bit 0 C1IDMR2 0x0316 msCAN12 Identifier Mask Register 2 C1IDMR2.AM7 7 Acceptance Mask Bit 7 C1IDMR2.AM6 6 Acceptance Mask Bit 6 C1IDMR2.AM5 5 Acceptance Mask Bit 5 C1IDMR2.AM4 4 Acceptance Mask Bit 4 C1IDMR2.AM3 3 Acceptance Mask Bit 3 C1IDMR2.AM2 2 Acceptance Mask Bit 2 C1IDMR2.AM1 1 Acceptance Mask Bit 1 C1IDMR2.AM0 0 Acceptance Mask Bit 0 C1IDMR3 0x0317 msCAN12 Identifier Mask Register 3 C1IDMR3.AM7 7 Acceptance Mask Bit 7 C1IDMR3.AM6 6 Acceptance Mask Bit 6 C1IDMR3.AM5 5 Acceptance Mask Bit 5 C1IDMR3.AM4 4 Acceptance Mask Bit 4 C1IDMR3.AM3 3 Acceptance Mask Bit 3 C1IDMR3.AM2 2 Acceptance Mask Bit 2 C1IDMR3.AM1 1 Acceptance Mask Bit 1 C1IDMR3.AM0 0 Acceptance Mask Bit 0 C1IDAR4 0x0318 msCAN12 Identifier Acceptance Register 4 C1IDAR4.AC7 7 Acceptance Code Bit 7 C1IDAR4.AC6 6 Acceptance Code Bit 6 C1IDAR4.AC5 5 Acceptance Code Bit 5 C1IDAR4.AC4 4 Acceptance Code Bit 4 C1IDAR4.AC3 3 Acceptance Code Bit 3 C1IDAR4.AC2 2 Acceptance Code Bit 2 C1IDAR4.AC1 1 Acceptance Code Bit 1 C1IDAR4.AC0 0 Acceptance Code Bit 0 C1IDAR5 0x0319 msCAN12 Identifier Acceptance Register 5 C1IDAR5.AC7 7 Acceptance Code Bit 7 C1IDAR5.AC6 6 Acceptance Code Bit 6 C1IDAR5.AC5 5 Acceptance Code Bit 5 C1IDAR5.AC4 4 Acceptance Code Bit 4 C1IDAR5.AC3 3 Acceptance Code Bit 3 C1IDAR5.AC2 2 Acceptance Code Bit 2 C1IDAR5.AC1 1 Acceptance Code Bit 1 C1IDAR5.AC0 0 Acceptance Code Bit 0 C1IDAR6 0x031A msCAN12 Identifier Acceptance Register 6 C1IDAR6.AC7 7 Acceptance Code Bit 7 C1IDAR6.AC6 6 Acceptance Code Bit 6 C1IDAR6.AC5 5 Acceptance Code Bit 5 C1IDAR6.AC4 4 Acceptance Code Bit 4 C1IDAR6.AC3 3 Acceptance Code Bit 3 C1IDAR6.AC2 2 Acceptance Code Bit 2 C1IDAR6.AC1 1 Acceptance Code Bit 1 C1IDAR6.AC0 0 Acceptance Code Bit 0 C1IDAR7 0x031B msCAN12 Identifier Acceptance Register 7 C1IDAR7.AC7 7 Acceptance Code Bit 7 C1IDAR7.AC6 6 Acceptance Code Bit 6 C1IDAR7.AC5 5 Acceptance Code Bit 5 C1IDAR7.AC4 4 Acceptance Code Bit 4 C1IDAR7.AC3 3 Acceptance Code Bit 3 C1IDAR7.AC2 2 Acceptance Code Bit 2 C1IDAR7.AC1 1 Acceptance Code Bit 1 C1IDAR7.AC0 0 Acceptance Code Bit 0 C1IDMR4 0x031C msCAN12 Identifier Mask Register 4 C1IDMR4.AM7 7 Acceptance Mask Bit 7 C1IDMR4.AM6 6 Acceptance Mask Bit 6 C1IDMR4.AM5 5 Acceptance Mask Bit 5 C1IDMR4.AM4 4 Acceptance Mask Bit 4 C1IDMR4.AM3 3 Acceptance Mask Bit 3 C1IDMR4.AM2 2 Acceptance Mask Bit 2 C1IDMR4.AM1 1 Acceptance Mask Bit 1 C1IDMR4.AM0 0 Acceptance Mask Bit 0 C1IDMR5 0x031D msCAN12 Identifier Mask Register 5 C1IDMR5.AM7 7 Acceptance Mask Bit 7 C1IDMR5.AM6 6 Acceptance Mask Bit 6 C1IDMR5.AM5 5 Acceptance Mask Bit 5 C1IDMR5.AM4 4 Acceptance Mask Bit 4 C1IDMR5.AM3 3 Acceptance Mask Bit 3 C1IDMR5.AM2 2 Acceptance Mask Bit 2 C1IDMR5.AM1 1 Acceptance Mask Bit 1 C1IDMR5.AM0 0 Acceptance Mask Bit 0 C1IDMR6 0x031E msCAN12 Identifier Mask Register 6 C1IDMR6.AM7 7 Acceptance Mask Bit 7 C1IDMR6.AM6 6 Acceptance Mask Bit 6 C1IDMR6.AM5 5 Acceptance Mask Bit 5 C1IDMR6.AM4 4 Acceptance Mask Bit 4 C1IDMR6.AM3 3 Acceptance Mask Bit 3 C1IDMR6.AM2 2 Acceptance Mask Bit 2 C1IDMR6.AM1 1 Acceptance Mask Bit 1 C1IDMR6.AM0 0 Acceptance Mask Bit 0 C1IDMR7 0x031F msCAN12 Identifier Mask Register 7 C1IDMR7.AM7 7 Acceptance Mask Bit 7 C1IDMR7.AM6 6 Acceptance Mask Bit 6 C1IDMR7.AM5 5 Acceptance Mask Bit 5 C1IDMR7.AM4 4 Acceptance Mask Bit 4 C1IDMR7.AM3 3 Acceptance Mask Bit 3 C1IDMR7.AM2 2 Acceptance Mask Bit 2 C1IDMR7.AM1 1 Acceptance Mask Bit 1 C1IDMR7.AM0 0 Acceptance Mask Bit 0 RESERVED0320 0x0320 RESERVED RESERVED0321 0x0321 RESERVED RESERVED0322 0x0322 RESERVED RESERVED0323 0x0323 RESERVED RESERVED0324 0x0324 RESERVED RESERVED0325 0x0325 RESERVED RESERVED0326 0x0326 RESERVED RESERVED0327 0x0327 RESERVED RESERVED0328 0x0328 RESERVED RESERVED0329 0x0329 RESERVED RESERVED032A 0x032A RESERVED RESERVED032B 0x032B RESERVED RESERVED032C 0x032C RESERVED RESERVED032D 0x032D RESERVED RESERVED032E 0x032E RESERVED RESERVED032F 0x032F RESERVED RESERVED0330 0x0330 RESERVED RESERVED0331 0x0331 RESERVED RESERVED0332 0x0332 RESERVED RESERVED0333 0x0333 RESERVED RESERVED0334 0x0334 RESERVED RESERVED0335 0x0335 RESERVED RESERVED0336 0x0336 RESERVED RESERVED0337 0x0337 RESERVED RESERVED0338 0x0338 RESERVED RESERVED0339 0x0339 RESERVED RESERVED033A 0x033A RESERVED RESERVED033B 0x033B RESERVED RESERVED033C 0x033C RESERVED PCTLCAN1 0x033D msCAN12 Port CAN Control Register PCTLCAN1.PUPCAN 1 Pull-Up Enable Port CAN PCTLCAN1.RDPCAN 0 Reduced Drive Port CAN PORTCAN1 0x033E msCAN12 Port CAN Data Register PORTCAN1.PCAN7 7 Port CAN Data Bit 7 PORTCAN1.PCAN6 6 Port CAN Data Bit 6 PORTCAN1.PCAN5 5 Port CAN Data Bit 5 PORTCAN1.PCAN4 4 Port CAN Data Bit 4 PORTCAN1.PCAN3 3 Port CAN Data Bit 3 PORTCAN1.PCAN2 2 Port CAN Data Bit 2 PORTCAN1.TxCAN 1 PORTCAN1.RxCAN 0 DDRCAN1 0x033F msCAN12 Port CAN Data Direction Register DDRCAN1.DDCAN7 7 DDRCAN1.DDCAN6 6 DDRCAN1.DDCAN5 5 DDRCAN1.DDCAN4 4 DDRCAN1.DDCAN3 3 DDRCAN1.DDCAN2 2 .68HC912DG128P ; MEMORY MAP area DATA FSR_0 0x0000:0x0140 area DATA RxFG0 0x0140:0x0150 FOREGROUND RECEIVE BUFFER 0 area DATA Tx00 0x0150:0x0160 TRANSMIT BUFFER 00 area DATA Tx01 0x0160:0x0170 TRANSMIT BUFFER 01 area DATA Tx02 0x0170:0x0180 TRANSMIT BUFFER 02 area BSS RESERVED 0x0180:0x01E2 area DATA FSR_1 0x01E2:0x0200 area BSS RESERVED 0x0200:0x0300 area DATA FSR_2 0x0300:0x0340 area DATA RxFG1 0x0340:0x0350 FOREGROUND RECEIVE BUFFER 1 area DATA Tx10 0x0350:0x0360 TRANSMIT BUFFER 10 area DATA Tx11 0x0360:0x0370 TRANSMIT BUFFER 11 area DATA Tx12 0x0370:0x0380 TRANSMIT BUFFER 12 area BSS RESERVED 0x0380:0x0800 area DATA EEPROM 0x0800:0x1000 area BSS RESERVED 0x1000:0x2000 area DATA RAM 0x2000:0x4000 area DATA ROM 0x4000:0xFF00 Flash area DATA USER_VEC 0xFF00:0x10000 ; Interrupt and reset vector assignments interrupt _RESET 0xFFFE Reset interrupt _COPCTL 0xFFFC Clock monitor fail reset interrupt _COP_F_R 0xFFFA COP failure reset interrupt _UIT 0xFFF8 Unimplemented instruction trap interrupt _SWI 0xFFF6 SWI interrupt _XIRQ 0xFFF4 XIRQ interrupt _INTCR_IRQEN 0xFFF2 IRQ interrupt _RTICTL_RTIE 0xFFF0 Real time interrupt interrupt _TMSK1_C0I 0xFFEE Timer channel 0 interrupt _TMSK1_C1I 0xFFEC Timer channel 1 interrupt _TMSK1_C2I 0xFFEA Timer channel 2 interrupt _TMSK1_C3I 0xFFE8 Timer channel 3 interrupt _TMSK1_C4I 0xFFE6 Timer channel 4 interrupt _TMSK1_C5I 0xFFE4 Timer channel 5 interrupt _TMSK1_C6I 0xFFE2 Timer channel 6 interrupt _TMSK1_C7I 0xFFE0 Timer channel 7 interrupt _TMSK2_TOI 0xFFDE Timer overflow interrupt _PACTL_PAOVI 0xFFDC Pulse accumulator overflow interrupt _PACTL_PAI 0xFFDA Pulse accumulator input edge interrupt _SP0CR1_SPIE 0xFFD8 SPI serial transfer complete interrupt _SC0CR2 0xFFD6 SCI 0 interrupt _SC1CR2 0xFFD4 SCI 1 interrupt _ATDxCTL2_ASCIE 0xFFD2 ATD0 or ATD1 interrupt _C0RIER_WUPIE 0xFFD0 MSCAN 0 wake-up interrupt _KWIEJ_KWIEH 0xFFCE Key wake-up J or H interrupt _MCCTL_MCZI 0xFFCC Modulus down counter underflow interrupt _PBCTL_PBOVI 0xFFCA Pulse Accumulator B Overflow interrupt _C0RIER 0xFFC8 MSCAN 0 errors interrupt _C0RIER_RXFIE 0xFFC6 MSCAN 0 receive interrupt _C0TCR_TXEIE 0xFFC4 MSCAN 0 transmit interrupt _PLLCR_LOCKIE_LHIE 0xFFC2 CGM lock and limp home interrupt _IBCR_IBIE 0xFFC0 IIC Bus interrupt _C1RIER_WUPIE 0xFFBE MSCAN 1 wake-up interrupt _C1RIER 0xFFBC MSCAN 1 errors interrupt _C1RIER_RXFIE 0xFFBA MSCAN 1 receive interrupt _C1TCR_TXEIE 0xFFB8 MSCAN 1 transmit ; INPUT/ OUTPUT PORTS PORTA 0x0000 Port A Data Register PORTA.PA7 7 Port A Data Bit 7 PORTA.PA6 6 Port A Data Bit 6 PORTA.PA5 5 Port A Data Bit 5 PORTA.PA4 4 Port A Data Bit 4 PORTA.PA3 3 Port A Data Bit 3 PORTA.PA2 2 Port A Data Bit 2 PORTA.PA1 1 Port A Data Bit 1 PORTA.PA0 0 Port A Data Bit 0 PORTB 0x0001 Port B Data Register PORTB.PB7 7 Port B Data Bit 7 PORTB.PB6 6 Port B Data Bit 6 PORTB.PB5 5 Port B Data Bit 5 PORTB.PB4 4 Port B Data Bit 4 PORTB.PB3 3 Port B Data Bit 3 PORTB.PB2 2 Port B Data Bit 2 PORTB.PB1 1 Port B Data Bit 1 PORTB.PB0 0 Port B Data Bit 0 DDRA 0x0002 Port A Data Direction Register DDRA.DDA7 7 Port A Data Direction Bit 7 DDRA.DDA6 6 Port A Data Direction Bit 6 DDRA.DDA5 5 Port A Data Direction Bit 5 DDRA.DDA4 4 Port A Data Direction Bit 4 DDRA.DDA3 3 Port A Data Direction Bit 3 DDRA.DDA2 2 Port A Data Direction Bit 2 DDRA.DDA1 1 Port A Data Direction Bit 1 DDRA.DDA0 0 Port A Data Direction Bit 0 DDRB 0x0003 Port B Data Direction Register DDRB.DDB7 7 Port B Data Direction Bit 7 DDRB.DDB6 6 Port B Data Direction Bit 6 DDRB.DDB5 5 Port B Data Direction Bit 5 DDRB.DDB4 4 Port B Data Direction Bit 4 DDRB.DDB3 3 Port B Data Direction Bit 3 DDRB.DDB2 2 Port B Data Direction Bit 2 DDRB.DDB1 1 Port B Data Direction Bit 1 DDRB.DDB0 0 Port B Data Direction Bit 0 RESERVED0004 0x0004 RESERVED RESERVED0005 0x0005 RESERVED RESERVED0006 0x0006 RESERVED RESERVED0007 0x0007 RESERVED PORTE 0x0008 Port E Data Register PORTE.PE7 7 Port E Data Bit 7 PORTE.PE6 6 Port E Data Bit 6 PORTE.PE5 5 Port E Data Bit 5 PORTE.PE4 4 Port E Data Bit 4 PORTE.PE3 3 Port E Data Bit 3 PORTE.PE2 2 Port E Data Bit 2 PORTE.PE1 1 Port E Data Bit 1 PORTE.PE0 0 Port E Data Bit 0 DDRE 0x0009 Port E Data Direction Register DDRE.DDE7 7 Port E Data Direction Bit 7 DDRE.DDE6 6 Port E Data Direction Bit 6 DDRE.DDE5 5 Port E Data Direction Bit 5 DDRE.DDE4 4 Port E Data Direction Bit 4 DDRE.DDE3 3 Port E Data Direction Bit 3 DDRE.DDE2 2 Port E Data Direction Bit 2 PEAR 0x000A Port E Assignment Register PEAR.NDBE 7 No Data Bus Enable PEAR.CGMTE 6 Clock Generator Module Testing Enable PEAR.PIPOE 5 Pipe Status Signal Output Enable PEAR.NECLK 4 No External E Clock PEAR.LSTRE 3 Low Strobe (LSTRB) Enable PEAR.RDWE 2 Read/Write Enable PEAR.CALE 1 Calibration Reference Enable PEAR.DBENE 0 DBE or Inverted E Clock on PE7 MODE 0x000B Mode Register MODE.SMODN 7 Mode Select Special MODE.MODB 6 Mode Select B MODE.MODA 5 Mode Select A MODE.ESTR 4 E Clock Stretch Enable MODE.IVIS 3 Internal Visibility MODE.EBSWAI 2 External Bus Module Stop in Wait Control MODE.EMK 1 Emulate Port K MODE.EME 0 PUCR 0x000C Pull-Up Control Register PUCR.PUPK 7 Pull-Up Port K Enable PUCR.PUPJ 6 Pull-Up or Pull-Down Port J Enable PUCR.PUPH 5 Pull-Up or Pull-Down Port H Enable PUCR.PUPE 4 Pull-Up Port E Enable PUCR.PUPB 1 Pull-Up Port B Enable PUCR.PUPA 0 Pull-Up Port A Enable RDRIV 0x000D Reduced Drive of I/O Lines RDRIV.RDPK 7 Reduced Drive of Port K RDRIV.RDPJ 6 Reduced Drive of Port J RDRIV.RDPH 5 Reduced Drive of Port H RDRIV.RDPE 4 Reduced Drive of Port E RDRIV.RDPB 1 Reduced Drive of Port B RDRIV.RDPA 0 Reduced Drive of Port A RESERVED000E 0x000E RESERVED RESERVED000F 0x000F RESERVED INITRM 0x0010 Initialization of Internal RAM Position Register INITRM.RAM15 7 Internal RAM map position 15 INITRM.RAM14 6 Internal RAM map position 14 INITRM.RAM13 5 Internal RAM map position 13 INITRG 0x0011 Initialization of Internal Register Position Register INITRG.REG15 7 Internal register map position 15 INITRG.REG14 6 Internal register map position 14 INITRG.REG13 5 Internal register map position 13 INITRG.REG12 4 Internal register map position 12 INITRG.REG11 3 Internal register map position 11 INITEE 0x0012 Initialization of Internal EEPROM Position Register INITEE.EE15 7 Internal EEPROM map position 15 INITEE.EE14 6 Internal EEPROM map position 14 INITEE.EE13 5 Internal EEPROM map position 13 INITEE.EE12 4 Internal EEPROM map position 12 INITEE.EEON 0 internal EEPROM On (Enabled) MISC 0x0013 Miscellaneous Mapping Control Register MISC.ROMTST 7 FLASH EEPROM Test mode MISC.NDRF 6 Narrow Data Bus for Register-Following Map Space MISC.RFSTR1 5 Register Following Stretch 1 MISC.RFSTR0 4 Register Following Stretch 0 MISC.EXSTR1 3 External Access Stretch 1 MISC.EXSTR0 2 External Access Stretch 0 MISC.ROMHM 1 FLASH EEPROM only in second Half of Map MISC.ROMON 0 Enable FLASH EEPROM RTICTL 0x0014 Real-Time Interrupt Control Register RTICTL.RTIE 7 Real Time Interrupt Enable RTICTL.RSWAI 6 RTI and COP Stop While in Wait RTICTL.RSBCK 5 RTI and COP Stop While in Background Debug Mode RTICTL.RTBYP 3 Real Time Interrupt Divider Chain Bypass RTICTL.RTR2 2 Real-Time Interrupt Rate Select 2 RTICTL.RTR1 1 Real-Time Interrupt Rate Select 1 RTICTL.RTR0 0 Real-Time Interrupt Rate Select 0 RTIFLG 0x0015 Real Time Interrupt Flag Register RTIFLG.RTIF 7 Real Time Interrupt Flag COPCTL 0x0016 COP Control Register COPCTL.CME 7 Clock Monitor Enable COPCTL.FCME 6 Force Clock Monitor Enable COPCTL.FCMCOP 5 Force Clock Monitor Reset or COP Watchdog Reset COPCTL.WCOP 4 Window COP mode COPCTL.DISR 3 Disable Resets from COP Watchdog and Clock Monitor COPCTL.CR2 2 COP Watchdog Timer Rate select bit 2 COPCTL.CR1 1 COP Watchdog Timer Rate select bit 1 COPCTL.CR0 0 COP Watchdog Timer Rate select bit 0 COPRST 0x0017 Arm/Reset COP Timer Register ITST0 0x0018 Interrupt Test Register 0 ITST0.ITE6 7 ITST0.ITE8 6 ITST0.ITEA 5 ITST0.ITEC 4 ITST0.ITEE 3 ITST0.ITF0 2 ITST0.ITF2 1 ITST0.ITF4 0 ITST1 0x0019 Interrupt Test Register 1 ITST1.ITD6 7 ITST1.ITD8 6 ITST1.ITDA 5 ITST1.ITDC 4 ITST1.ITDE 3 ITST1.ITE0 2 ITST1.ITE2 1 ITST1.ITE4 0 ITST2 0x001A Interrupt Test Register 2 ITST2.ITC6 7 ITST2.ITC8 6 ITST2.ITCA 5 ITST2.ITCC 4 ITST2.ITCE 3 ITST2.ITD0 2 ITST2.ITD2 1 ITST2.ITD4 0 ITST3 0x001B Interrupt Test Register 3 ITST3.ITB6 7 ITST3.ITB8 6 ITST3.ITBA 5 ITST3.ITBC 4 ITST3.ITBE 3 ITST3.ITC0 2 ITST3.ITC2 1 ITST3.ITC4 0 RESERVED001C 0x001C RESERVED RESERVED001D 0x001D RESERVED INTCR 0x001E Interrupt Control Register INTCR.IRQE 7 IRQ Select Edge Sensitive Only INTCR.IRQEN 6 External IRQ Enable INTCR.DLY 5 Enable Oscillator Start-up Delay on Exit from STOP HPRIO 0x001F Highest Priority I Interrupt HPRIO.PSEL6 6 HPRIO.PSEL5 5 HPRIO.PSEL4 4 HPRIO.PSEL3 3 HPRIO.PSEL2 2 HPRIO.PSEL1 1 BRKCT0 0x0020 Breakpoint Control Register 0 BRKCT0.BKEN1 7 Breakpoint Mode Enable 1 BRKCT0.BKEN0 6 Breakpoint Mode Enable 0 BRKCT0.BKPM 5 Break on Program Addresses BRKCT0.BK1ALE 3 Breakpoint 1 Range Control BRKCT0.BK0ALE 2 Breakpoint 0 Range Control BRKCT1 0x0021 Breakpoint Control Register 1 BRKCT1.BKDBE 6 Enable Data Bus BRKCT1.BKMBH 5 Breakpoint Mask High BRKCT1.BKMBL 4 Breakpoint Mask Low BRKCT1.BK1RWE 3 R/W Compare Enable BRKCT1.BK1RW 2 R/W Compare Value BRKCT1.BK0RWE 1 R/W Compare Enable BRKCT1.BK0RW 0 R/W Compare Value BRKAH 0x0022 Breakpoint Address Register, High Byte BRKAL 0x0023 Breakpoint Address Register, Low Byte BRKDH 0x0024 Breakpoint Data Register, High Byte BRKDL 0x0025 Breakpoint Data Register, Low Byte RESERVED0026 0x0026 RESERVED RESERVED0027 0x0027 RESERVED PORTJ 0x0028 Port J Data Register PORTJ.PJ7 7 Port J Data Bit 7 PORTJ.PJ6 6 Port J Data Bit 6 PORTJ.PJ5 5 Port J Data Bit 5 PORTJ.PJ4 4 Port J Data Bit 4 PORTJ.PJ3 3 Port J Data Bit 3 PORTJ.PJ2 2 Port J Data Bit 2 PORTJ.PJ1 1 Port J Data Bit 1 PORTJ.PJ0 0 Port J Data Bit 0 PORTH 0x0029 Port H Data Register PORTH.PH7 7 Port H Data Bit 7 PORTH.PH6 6 Port H Data Bit 6 PORTH.PH5 5 Port H Data Bit 5 PORTH.PH4 4 Port H Data Bit 4 PORTH.PH3 3 Port H Data Bit 3 PORTH.PH2 2 Port H Data Bit 2 PORTH.PH1 1 Port H Data Bit 1 PORTH.PH0 0 Port H Data Bit 0 DDRJ 0x002A Port J Data Direction Register DDRJ.DDRJ7 7 Data Direction Port J Bit 7 DDRJ.DDRJ6 6 Data Direction Port J Bit 6 DDRJ.DDRJ5 5 Data Direction Port J Bit 5 DDRJ.DDRJ4 4 Data Direction Port J Bit 4 DDRJ.DDRJ3 3 Data Direction Port J Bit 3 DDRJ.DDRJ2 2 Data Direction Port J Bit 2 DDRJ.DDRJ1 1 Data Direction Port J Bit 1 DDRJ.DDRJ0 0 Data Direction Port J Bit 0 DDRH 0x002B Port J Data Direction Register DDRH.DDRH7 7 Data Direction Port H Bit 7 DDRH.DDRH6 6 Data Direction Port H Bit 6 DDRH.DDRH5 5 Data Direction Port H Bit 5 DDRH.DDRH4 4 Data Direction Port H Bit 4 DDRH.DDRH3 3 Data Direction Port H Bit 3 DDRH.DDRH2 2 Data Direction Port H Bit 2 DDRH.DDRH1 1 Data Direction Port H Bit 1 DDRH.DDRH0 0 Data Direction Port H Bit 0 KWIEJ 0x002C Key Wake-up Port J Interrupt Enable Register KWIEJ.KWIEJ7 7 Key Wake-up Port J Interrupt Enable 7 KWIEJ.KWIEJ6 6 Key Wake-up Port J Interrupt Enable 6 KWIEJ.KWIEJ5 5 Key Wake-up Port J Interrupt Enable 5 KWIEJ.KWIEJ4 4 Key Wake-up Port J Interrupt Enable 4 KWIEJ.KWIEJ3 3 Key Wake-up Port J Interrupt Enable 3 KWIEJ.KWIEJ2 2 Key Wake-up Port J Interrupt Enable 2 KWIEJ.KWIEJ1 1 Key Wake-up Port J Interrupt Enable 1 KWIEJ.KWIEJ0 0 Key Wake-up Port J Interrupt Enable 0 KWIEH 0x002D Key Wake-up Port H Interrupt Enable Register KWIEH.KWIEH7 7 Key Wake-up Port H Interrupt Enable 7 KWIEH.KWIEH6 6 Key Wake-up Port H Interrupt Enable 6 KWIEH.KWIEH5 5 Key Wake-up Port H Interrupt Enable 5 KWIEH.KWIEH4 4 Key Wake-up Port H Interrupt Enable 4 KWIEH.KWIEH3 3 Key Wake-up Port H Interrupt Enable 3 KWIEH.KWIEH2 2 Key Wake-up Port H Interrupt Enable 2 KWIEH.KWIEH1 1 Key Wake-up Port H Interrupt Enable 1 KWIEH.KWIEH0 0 Key Wake-up Port H Interrupt Enable 0 KWIFJ 0x002E Key Wake-up Port J Flag Register KWIFJ.KWIFJ7 7 Key Wake-up Port J Flag 7 KWIFJ.KWIFJ6 6 Key Wake-up Port J Flag 6 KWIFJ.KWIFJ5 5 Key Wake-up Port J Flag 5 KWIFJ.KWIFJ4 4 Key Wake-up Port J Flag 4 KWIFJ.KWIFJ3 3 Key Wake-up Port J Flag 3 KWIFJ.KWIFJ2 2 Key Wake-up Port J Flag 2 KWIFJ.KWIFJ1 1 Key Wake-up Port J Flag 1 KWIFJ.KWIFJ0 0 Key Wake-up Port J Flag 0 KWIFH 0x002F Key Wake-up Port H Flag Register KWIFH.KWIFH7 7 Key Wake-up Port H Flag 7 KWIFH.KWIFH6 6 Key Wake-up Port H Flag 6 KWIFH.KWIFH5 5 Key Wake-up Port H Flag 5 KWIFH.KWIFH4 4 Key Wake-up Port H Flag 4 KWIFH.KWIFH3 3 Key Wake-up Port H Flag 3 KWIFH.KWIFH2 2 Key Wake-up Port H Flag 2 KWIFH.KWIFH1 1 Key Wake-up Port H Flag 1 KWIFH.KWIFH0 0 Key Wake-up Port H Flag 0 KWPJ 0x0030 Key Wake-up Port J Polarity Register KWPJ.KWPJ7 7 Key Wake-up Port J Polarity Select 7 KWPJ.KWPJ6 6 Key Wake-up Port J Polarity Select 6 KWPJ.KWPJ5 5 Key Wake-up Port J Polarity Select 5 KWPJ.KWPJ4 4 Key Wake-up Port J Polarity Select 4 KWPJ.KWPJ3 3 Key Wake-up Port J Polarity Select 3 KWPJ.KWPJ2 2 Key Wake-up Port J Polarity Select 2 KWPJ.KWPJ1 1 Key Wake-up Port J Polarity Select 1 KWPJ.KWPJ0 0 Key Wake-up Port J Polarity Select 0 KWPH 0x0031 Key Wake-up Port H Polarity Register KWPH.KWPH7 7 Key Wake-up Port H Polarity Select 7 KWPH.KWPH6 6 Key Wake-up Port H Polarity Select 6 KWPH.KWPH5 5 Key Wake-up Port H Polarity Select 5 KWPH.KWPH4 4 Key Wake-up Port H Polarity Select 4 KWPH.KWPH3 3 Key Wake-up Port H Polarity Select 3 KWPH.KWPH2 2 Key Wake-up Port H Polarity Select 2 KWPH.KWPH1 1 Key Wake-up Port H Polarity Select 1 KWPH.KWPH0 0 Key Wake-up Port H Polarity Select 0 RESERVED0032 0x0032 RESERVED RESERVED0033 0x0033 RESERVED RESERVED0034 0x0034 RESERVED RESERVED0035 0x0035 RESERVED RESERVED0036 0x0036 RESERVED RESERVED0037 0x0037 RESERVED SYNR 0x0038 Synthesizer Register SYNR.SYN5 5 SYNR.SYN4 4 SYNR.SYN3 3 SYNR.SYN2 2 SYNR.SYN1 1 SYNR.SYN0 0 REFDV 0x0039 Reference Divider Register REFDV.REFDV2 2 REFDV.REFDV1 1 REFDV.REFDV0 0 CGTFLG 0x003A Clock Generator Test Register CGTFLG.TSTOUT7 7 CGTFLG.TSTOUT6 6 CGTFLG.TSTOUT5 5 CGTFLG.TSTOUT4 4 CGTFLG.TSTOUT3 3 CGTFLG.TSTOUT2 2 CGTFLG.TSTOUT1 1 CGTFLG.TSTOUT0 0 PLLFLG 0x003B PLL Flags PLLFLG.LOCKIF 7 PLL Lock Interrupt Flag PLLFLG.LOCK 6 Locked Phase Lock Loop Circuit PLLFLG.LHIF 1 Limp-Home Interrupt Flag PLLFLG.LHOME 0 Limp-Home Mode Status PLLCR 0x003C PLL Control Register PLLCR.LOCKIE 7 PLL LOCK Interrupt Enable PLLCR.PLLON 6 Phase Lock Loop On PLLCR.AUTO 5 Automatic Bandwidth Control PLLCR.ACQ 4 Not in Acquisition PLLCR.PSTP 2 Pseudo-STOP Enable PLLCR.LHIE 1 Limp-Home Interrupt Enable PLLCR.NOLHM 0 No Limp-Home Mode CLKSEL 0x003D Clock Generator Clock select Register CLKSEL.BCSP 6 Bus Clock Select PLL CLKSEL.BCSS 5 Bus Clock Select Slow CLKSEL.MCS 2 Module Clock Select SLOW 0x003E Slow mode Divider Register SLOW.SLDV5 5 SLOW.SLDV4 4 SLOW.SLDV3 3 SLOW.SLDV2 2 SLOW.SLDV1 1 SLOW.SLDV0 0 CGTCTL 0x003F CGTCTL CGTCTL.OPNLE 7 CGTCTL.TRK 6 CGTCTL.TSTCLKE 5 CGTCTL.TST4 4 CGTCTL.TST3 3 CGTCTL.TST2 2 CGTCTL.TST1 1 CGTCTL.TST0 0 PWCLK 0x0040 PWM Clocks and Concatenate PWCLK.CON23 7 Concatenate PWM Channels 2 and 3 PWCLK.CON01 6 Concatenate PWM Channels 0 and 1 PWCLK.PCKA2 5 Prescaler for Clock A 2 PWCLK.PCKA1 4 Prescaler for Clock A 1 PWCLK.PCKA0 3 Prescaler for Clock A 0 PWCLK.PCKB2 2 Prescaler for Clock B 2 PWCLK.PCKB1 1 Prescaler for Clock B 1 PWCLK.PCKB0 0 Prescaler for Clock B 0 PWPOL 0x0041 PWM Clock Select and Polarity PWPOL.PCLK3 7 PWM Channel 3 Clock Select PWPOL.PCLK2 6 PWM Channel 2 Clock Select PWPOL.PCLK1 5 PWM Channel 1 Clock Select PWPOL.PCLK0 4 PWM Channel 0 Clock Select PWPOL.PPOL3 3 PWM Channel 3 Polarity PWPOL.PPOL2 2 PWM Channel 2 Polarity PWPOL.PPOL1 1 PWM Channel 1 Polarity PWPOL.PPOL0 0 PWM Channel 0 Polarity PWEN 0x0042 PWM Enable PWEN.PWEN3 3 PWM Channel 3 Enable PWEN.PWEN2 2 PWM Channel 2 Enable PWEN.PWEN1 1 PWM Channel 1 Enable PWEN.PWEN0 0 PWM Channel 0 Enable PWPRES 0x0043 PWM Prescale Counter PWSCAL0 0x0044 PWM Scale Register 0 PWSCNT0 0x0045 PWM Scale Counter 0 Value PWSCAL1 0x0046 PWM Scale Register 1 PWSCNT1 0x0047 PWM Scale Counter 1 Value PWCNT0 0x0048 PWM Channel Counter 0 PWCNT1 0x0049 PWM Channel Counter 1 PWCNT2 0x004A PWM Channel Counter 2 PWCNT3 0x004B PWM Channel Counter 3 PWPER0 0x004C PWM Channel Period Register 0 PWPER1 0x004D PWM Channel Period Register 1 PWPER2 0x004E PWM Channel Period Register 2 PWPER3 0x004F PWM Channel Period Register 3 PWDTY0 0x0050 PWM Channel Duty Register 0 PWDTY1 0x0051 PWM Channel Duty Register 1 PWDTY2 0x0052 PWM Channel Duty Register 2 PWDTY3 0x0053 PWM Channel Duty Register 3 PWCTL 0x0054 PWM Control Register PWCTL.PSWAI 4 PWM Halts while in Wait Mode PWCTL.CENTR 3 Center-Aligned Output Mode PWCTL.RDPP 2 Reduced Drive of Port P PWCTL.PUPP 1 Pull-Up Port P Enable PWCTL.PSBCK 0 PWM Stops while in Background Mode PWTST 0x0055 PWM Special Mode Register ("Test") PWTST.DISCR 7 Disable Reset of Channel Counter on Write to Channel Counter PWTST.DISCP 6 Disable Compare Count Period PWTST.DISCAL 5 Disable Load of Scale-Counters on Write to the Associated Scale-Registers PORTP 0x0056 Port P Data Register PORTP.PP7 7 Port P Data Bit 7 PORTP.PP6 6 Port P Data Bit 6 PORTP.PP5 5 Port P Data Bit 5 PORTP.PP4 4 Port P Data Bit 4 PORTP.PP3 3 Port P Data Bit 3 PORTP.PP2 2 Port P Data Bit 2 PORTP.PP1 1 Port P Data Bit 1 PORTP.PP0 0 Port P Data Bit 0 DDRP 0x0057 Port P Data Direction Register DDRP.DDP7 7 Port P Data Direction Bit 7 DDRP.DDP6 6 Port P Data Direction Bit 6 DDRP.DDP5 5 Port P Data Direction Bit 5 DDRP.DDP4 4 Port P Data Direction Bit 4 DDRP.DDP3 3 Port P Data Direction Bit 3 DDRP.DDP2 2 Port P Data Direction Bit 2 DDRP.DDP1 1 Port P Data Direction Bit 1 DDRP.DDP0 0 Port P Data Direction Bit 0 RESERVED0058 0x0058 RESERVED RESERVED0059 0x0059 RESERVED RESERVED005A 0x005A RESERVED RESERVED005B 0x005B RESERVED RESERVED005C 0x005C RESERVED RESERVED005D 0x005D RESERVED RESERVED005E 0x005E RESERVED RESERVED005F 0x005F RESERVED RESERVED0060 0x0060 RESERVED RESERVED0061 0x0061 RESERVED ATD0CTL2 0x0062 ATD0 Control Register 2 ATD0CTL2.ADPU 7 ATD Disable ATD0CTL2.AFFC 6 ATD Fast Flag Clear All ATD0CTL2.ASWAI 5 ATD Wait Mode ATD0CTL2.DJM 4 Result Register Data Justification Mode ATD0CTL2.DSGN 3 Signed/Unsigned Result Data Mode ATD0CTL2.ASCIE 1 ATD Sequence Complete Interrupt Enable ATD0CTL2.ASCIF 0 ATD Sequence Complete Interrupt Flag ATD0CTL3 0x0063 ATD0 Control Register 3 ATD0CTL3.S1C 3 Conversion Sequence Length (Least Significant Bit) ATD0CTL3.FIFO 2 Result Register FIFO Mode ATD0CTL3.FRZ1 1 Background Debug (Freeze) Enable 1 ATD0CTL3.FRZ0 0 Background Debug (Freeze) Enable 0 ATD0CTL4 0x0064 ATD0 Control Register 4 ATD0CTL4.RES10 7 10 bit Mode ATD0CTL4.SMP1 6 Select Sample Time 1 ATD0CTL4.SMP0 5 Select Sample Time 0 ATD0CTL4.PRS4 4 Select Divide-By Factor for ATD P-Clock Prescaler 4 ATD0CTL4.PRS3 3 Select Divide-By Factor for ATD P-Clock Prescaler 3 ATD0CTL4.PRS2 2 Select Divide-By Factor for ATD P-Clock Prescaler 2 ATD0CTL4.PRS1 1 Select Divide-By Factor for ATD P-Clock Prescaler 1 ATD0CTL4.PRS0 0 Select Divide-By Factor for ATD P-Clock Prescaler 0 ATD0CTL5 0x0065 ATD0 Control Register 5 ATD0CTL5.S8CM 6 Select 8 Channel Mode ATD0CTL5.SCAN 5 Enable Continuous Channel Scan ATD0CTL5.MULT 4 Enable Multichannel Conversion ATD0CTL5.CD 3 Channel Select for Conversion D ATD0CTL5.CC 2 Channel Select for Conversion C ATD0CTL5.CB 1 Channel Select for Conversion B ATD0CTL5.CA 0 Channel Select for Conversion A ATD0STAT0 0x0066 ATD0 Status Register ATD0STAT0.SCF 7 Sequence Complete Flag ATD0STAT0.CC2 2 Conversion Counter for Current Sequence of Four or Eight Conversions 2 ATD0STAT0.CC1 1 Conversion Counter for Current Sequence of Four or Eight Conversions 1 ATD0STAT0.CC0 0 Conversion Counter for Current Sequence of Four or Eight Conversions 0 ATD0STAT1 0x0067 ATD0 Status Register ATD0STAT1.CCF7 7 Conversion Complete Flag 7 ATD0STAT1.CCF6 6 Conversion Complete Flag 6 ATD0STAT1.CCF5 5 Conversion Complete Flag 5 ATD0STAT1.CCF4 4 Conversion Complete Flag 4 ATD0STAT1.CCF3 3 Conversion Complete Flag 3 ATD0STAT1.CCF2 2 Conversion Complete Flag 2 ATD0STAT1.CCF1 1 Conversion Complete Flag 1 ATD0STAT1.CCF0 0 Conversion Complete Flag 0 ATD0TESTH 0x0068 ATD0 Test Register ATD0TESTH.SAR9 7 SAR Data 9 ATD0TESTH.SAR8 6 SAR Data 8 ATD0TESTH.SAR7 5 SAR Data 7 ATD0TESTH.SAR6 4 SAR Data 6 ATD0TESTH.SAR5 3 SAR Data 5 ATD0TESTH.SAR4 2 SAR Data 4 ATD0TESTH.SAR3 1 SAR Data 3 ATD0TESTH.SAR2 0 SAR Data 2 ATD0TESTL 0x0069 ATD0 Test Register ATD0TESTL.SAR1 7 SAR Data 1 ATD0TESTL.SAR0 6 SAR Data 0 ATD0TESTL.RST 5 Module Reset Bit ATD0TESTL.TSTOUT 4 Multiplex Output of TST[3:0] (Factory Use) ATD0TESTL.TST3 3 Test Bit 3 ATD0TESTL.TST2 2 Test Bit 2 ATD0TESTL.TST1 1 Test Bit 1 ATD0TESTL.TST0 0 Test Bit 0 RESERVED006A 0x006A RESERVED RESERVED006B 0x006B RESERVED RESERVED006C 0x006C RESERVED RESERVED006D 0x006D RESERVED RESERVED006E 0x006E RESERVED PORTAD0 0x006F Port AD0 Data Input Register PORTAD0.PAD07 7 Port AD0 Data Input Bit 7 PORTAD0.PAD06 6 Port AD0 Data Input Bit 6 PORTAD0.PAD05 5 Port AD0 Data Input Bit 5 PORTAD0.PAD04 4 Port AD0 Data Input Bit 4 PORTAD0.PAD03 3 Port AD0 Data Input Bit 3 PORTAD0.PAD02 2 Port AD0 Data Input Bit 2 PORTAD0.PAD01 1 Port AD0 Data Input Bit 1 PORTAD0.PAD00 0 Port AD0 Data Input Bit 0 ADR00H 0x0070 A/D Conversion Result Register High 0 ADR00L 0x0071 A/D Conversion Result Register Low 0 ADR01H 0x0072 A/D Conversion Result Register High 1 ADR01L 0x0073 A/D Conversion Result Register Low 1 ADR02H 0x0074 A/D Conversion Result Register High 2 ADR02L 0x0075 A/D Conversion Result Register Low 2 ADR03H 0x0076 A/D Conversion Result Register High 3 ADR03L 0x0077 A/D Conversion Result Register Low 3 ADR04H 0x0078 A/D Conversion Result Register High 4 ADR04L 0x0079 A/D Conversion Result Register Low 4 ADR05H 0x007A A/D Conversion Result Register High 5 ADR05L 0x007B A/D Conversion Result Register Low 5 ADR06H 0x007C A/D Conversion Result Register High 6 ADR06L 0x007D A/D Conversion Result Register Low 6 ADR07H 0x007E A/D Conversion Result Register High 7 ADR07L 0x007F A/D Conversion Result Register Low 7 TIOS 0x0080 Timer Input Capture/Output Compare Select TIOS.IOS7 7 Input Capture or Output Compare Channel Configuration 7 TIOS.IOS6 6 Input Capture or Output Compare Channel Configuration 6 TIOS.IOS5 5 Input Capture or Output Compare Channel Configuration 5 TIOS.IOS4 4 Input Capture or Output Compare Channel Configuration 4 TIOS.IOS3 3 Input Capture or Output Compare Channel Configuration 3 TIOS.IOS2 2 Input Capture or Output Compare Channel Configuration 2 TIOS.IOS1 1 Input Capture or Output Compare Channel Configuration 1 TIOS.IOS0 0 Input Capture or Output Compare Channel Configuration 0 CFORC 0x0081 Timer Compare Force Register CFORC.FOC7 7 Force Output Compare Action for Channel 7 CFORC.FOC6 6 Force Output Compare Action for Channel 6 CFORC.FOC5 5 Force Output Compare Action for Channel 5 CFORC.FOC4 4 Force Output Compare Action for Channel 4 CFORC.FOC3 3 Force Output Compare Action for Channel 3 CFORC.FOC2 2 Force Output Compare Action for Channel 2 CFORC.FOC1 1 Force Output Compare Action for Channel 1 CFORC.FOC0 0 Force Output Compare Action for Channel 0 OC7M 0x0082 Output Compare 7 Mask Register OC7M.OC7M7 7 OC7M.OC7M6 6 OC7M.OC7M5 5 OC7M.OC7M4 4 OC7M.OC7M3 3 OC7M.OC7M2 2 OC7M.OC7M1 1 OC7M.OC7M0 0 OC7D 0x0083 Output Compare 7 Data Register OC7D.OC7D7 7 OC7D.OC7D6 6 OC7D.OC7D5 5 OC7D.OC7D4 4 OC7D.OC7D3 3 OC7D.OC7D2 2 OC7D.OC7D1 1 OC7D.OC7D0 0 TCNTH 0x0084 Timer Count Register High TCNTL 0x0085 Timer Count Register Low TSCR 0x0086 Timer System Control Register TSCR.TEN 7 Timer Enable TSCR.TSWAI 6 Timer Module Stops While in Wait TSCR.TSBCK 5 Timer and Modulus Counter Stop While in Background Mode TSCR.TFFCA 4 Timer Fast Flag Clear All RESERVED0087 0x0087 RESERVED TCTL1 0x0088 Timer Control Register 1 TCTL1.OM7 7 Output Mode 7 TCTL1.OL7 6 Output Level 7 TCTL1.OM6 5 Output Mode 6 TCTL1.OL6 4 Output Level 6 TCTL1.OM5 3 Output Mode 5 TCTL1.OL5 2 Output Level 5 TCTL1.OM4 1 Output Mode 4 TCTL1.OL4 0 Output Level 4 TCTL2 0x0089 Timer Control Register 2 TCTL2.OM3 7 Output Mode 3 TCTL2.OL3 6 Output Level 3 TCTL2.OM2 5 Output Mode 2 TCTL2.OL2 4 Output Level 2 TCTL2.OM1 3 Output Mode 1 TCTL2.OL1 2 Output Level 1 TCTL2.OM0 1 Output Mode 0 TCTL2.OL0 0 Output Level 0 TCTL3 0x008A Timer Control Register 3 TCTL3.EDG7B 7 Input Capture Edge Control 7B TCTL3.EDG7A 6 Input Capture Edge Control 7A TCTL3.EDG6B 5 Input Capture Edge Control 6B TCTL3.EDG6A 4 Input Capture Edge Control 6A TCTL3.EDG5B 3 Input Capture Edge Control 5B TCTL3.EDG5A 2 Input Capture Edge Control 5A TCTL3.EDG4B 1 Input Capture Edge Control 4B TCTL3.EDG4A 0 Input Capture Edge Control 4A TCTL4 0x008B Timer Control Register 4 TCTL4.EDG3B 7 Input Capture Edge Control 3B TCTL4.EDG3A 6 Input Capture Edge Control 3A TCTL4.EDG2B 5 Input Capture Edge Control 2B TCTL4.EDG2A 4 Input Capture Edge Control 2A TCTL4.EDG1B 3 Input Capture Edge Control 1B TCTL4.EDG1A 2 Input Capture Edge Control 1A TCTL4.EDG0B 1 Input Capture Edge Control 0B TCTL4.EDG0A 0 Input Capture Edge Control 0A TMSK1 0x008C Timer Interrupt Mask 1 TMSK1.C7I 7 Input Capture/Output Compare 7 Interrupt Enable TMSK1.C6I 6 Input Capture/Output Compare 6 Interrupt Enable TMSK1.C5I 5 Input Capture/Output Compare 5 Interrupt Enable TMSK1.C4I 4 Input Capture/Output Compare 4 Interrupt Enable TMSK1.C3I 3 Input Capture/Output Compare 3 Interrupt Enable TMSK1.C2I 2 Input Capture/Output Compare 2 Interrupt Enable TMSK1.C1I 1 Input Capture/Output Compare 1 Interrupt Enable TMSK1.C0I 0 Input Capture/Output Compare 0 Interrupt Enable TMSK2 0x008D Timer Interrupt Mask 2 TMSK2.TOI 7 Timer Overflow Interrupt Enable TMSK2.PUPT 5 Timer Port Pull-Up Resistor Enable TMSK2.RDPT 4 Timer Port Drive Reduction TMSK2.TCRE 3 Timer Counter Reset Enable TMSK2.PR2 2 Timer Prescaler Select 2 TMSK2.PR1 1 Timer Prescaler Select 1 TMSK2.PR0 0 Timer Prescaler Select 0 TFLG1 0x008E Main Timer Interrupt Flag 1 TFLG1.C7F 7 Input Capture/Output Compare Channel 7 Flag TFLG1.C6F 6 Input Capture/Output Compare Channel 6 Flag TFLG1.C5F 5 Input Capture/Output Compare Channel 5 Flag TFLG1.C4F 4 Input Capture/Output Compare Channel 4 Flag TFLG1.C3F 3 Input Capture/Output Compare Channel 3 Flag TFLG1.C2F 2 Input Capture/Output Compare Channel 2 Flag TFLG1.C1F 1 Input Capture/Output Compare Channel 1 Flag TFLG1.C0F 0 Input Capture/Output Compare Channel 0 Flag TFLG2 0x008F Main Timer Interrupt Flag 2 TFLG2.TOF 7 Timer Overflow Flag TC0H 0x0090 Timer Input Capture/Output Compare Register 0 High TC0L 0x0091 Timer Input Capture/Output Compare Register 0 Low TC1H 0x0092 Timer Input Capture/Output Compare Register 1 High TC1L 0x0093 Timer Input Capture/Output Compare Register 1 Low TC2H 0x0094 Timer Input Capture/Output Compare Register 2 High TC2L 0x0095 Timer Input Capture/Output Compare Register 2 Low TC3H 0x0096 Timer Input Capture/Output Compare Register 3 High TC3L 0x0097 Timer Input Capture/Output Compare Register 3 Low TC4H 0x0098 Timer Input Capture/Output Compare Register 4 High TC4L 0x0099 Timer Input Capture/Output Compare Register 4 Low TC5H 0x009A Timer Input Capture/Output Compare Register 5 High TC5L 0x009B Timer Input Capture/Output Compare Register 5 Low TC6H 0x009C Timer Input Capture/Output Compare Register 6 High TC6L 0x009D Timer Input Capture/Output Compare Register 6 Low TC7H 0x009E Timer Input Capture/Output Compare Register 7 High TC7L 0x009F Timer Input Capture/Output Compare Register 7 Low PACTL 0x00A0 16-Bit Pulse Accumulator A Control Register PACTL.PAEN 6 Pulse Accumulator A System Enable PACTL.PAMOD 5 Pulse Accumulator Mode PACTL.PEDGE 4 Pulse Accumulator Edge Control PACTL.CLK1 3 Clock Select Bit 1 PACTL.CLK0 2 Clock Select Bit 0 PACTL.PAOVI 1 Pulse Accumulator A Overflow Interrupt enable PACTL.PAI 0 Pulse Accumulator Input Interrupt enable PAFLG 0x00A1 Pulse Accumulator A Flag Register PAFLG.PAOVF 1 Pulse Accumulator A Overflow Flag PAFLG.PAIF 0 Pulse Accumulator Input edge Flag PACN3 0x00A2 Pulse Accumulators Count Register 3 PACN2 0x00A3 Pulse Accumulators Count Register 2 PACN1 0x00A4 Pulse Accumulators Count Register 1 PACN0 0x00A5 Pulse Accumulators Count Register 0 MCCTL 0x00A6 16-Bit Modulus Down-Counter Control Register MCCTL.MCZI 7 Modulus Counter Underflow Interrupt Enable MCCTL.MODMC 6 Modulus Mode Enable MCCTL.RDMCL 5 Read Modulus Down-Counter Load MCCTL.ICLAT 4 Input Capture Force Latch Action MCCTL.FLMC 3 Force Load Register into the Modulus Counter Count Register MCCTL.MCEN 2 Modulus Down-Counter Enable MCCTL.MCPR1 1 Modulus Counter Prescaler select 1 MCCTL.MCPR0 0 Modulus Counter Prescaler select 0 MCFLG 0x00A7 16-Bit Modulus Down-Counter FLAG Register MCFLG.MCZF 7 Modulus Counter Underflow Interrupt Flag MCFLG.POLF3 3 First Input Capture Polarity Status 3 MCFLG.POLF2 2 First Input Capture Polarity Status 2 MCFLG.POLF1 1 First Input Capture Polarity Status 1 MCFLG.POLF0 0 First Input Capture Polarity Status 0 ICPACR 0x00A8 Input Control Pulse Accumulators Control Register ICPACR.PA3EN 3 8-Bit Pulse Accumulator 3 Enable ICPACR.PA2EN 2 8-Bit Pulse Accumulator 2 Enable ICPACR.PA1EN 1 8-Bit Pulse Accumulator 1 Enable ICPACR.PA0EN 0 8-Bit Pulse Accumulator 0 Enable DLYCT 0x00A9 Delay Counter Control Register DLYCT.DLY1 1 Delay Counter Select 1 DLYCT.DLY0 0 Delay Counter Select 0 ICOVW 0x00AA Input Control Overwrite Register ICOVW.NOVW7 7 No Input Capture Overwrite 7 ICOVW.NOVW6 6 No Input Capture Overwrite 6 ICOVW.NOVW5 5 No Input Capture Overwrite 5 ICOVW.NOVW4 4 No Input Capture Overwrite 4 ICOVW.NOVW3 3 No Input Capture Overwrite 3 ICOVW.NOVW2 2 No Input Capture Overwrite 2 ICOVW.NOVW1 1 No Input Capture Overwrite 1 ICOVW.NOVW0 0 No Input Capture Overwrite 0 ICSYS 0x00AB Input Control System Control Register ICSYS.SH37 7 Share Input action of Input Capture Channels 3 and 7 ICSYS.SH26 6 Share Input action of Input Capture Channels 2 and 6 ICSYS.SH15 5 Share Input action of Input Capture Channels 1 and 5 ICSYS.SH04 4 Share Input action of Input Capture Channels 0 and 4 ICSYS.TFMOD 3 Timer Flag-setting Mode ICSYS.PACMX 2 8-Bit Pulse Accumulators Maximum Count ICSYS.BUFEN 1 IC Buffer Enable ICSYS.LATQ 0 Input Control Latch or Queue Mode Enable RESERVED00AC 0x00AC RESERVED TIMTST 0x00AD Timer Test Register TIMTST.TCBYP 1 Main Timer Divider Chain Bypass PORTT 0x00AE Port T Data Register PORTT.PT7 7 Port T Data Bit 7 PORTT.PT6 6 Port T Data Bit 6 PORTT.PT5 5 Port T Data Bit 5 PORTT.PT4 4 Port T Data Bit 4 PORTT.PT3 3 Port T Data Bit 3 PORTT.PT2 2 Port T Data Bit 2 PORTT.PT1 1 Port T Data Bit 1 PORTT.PT0 0 Port T Data Bit 0 DDRT 0x00AF Port T Data Direction Register DDRT.DDT7 7 Port T Data Direction Bit 7 DDRT.DDT6 6 Port T Data Direction Bit 6 DDRT.DDT5 5 Port T Data Direction Bit 5 DDRT.DDT4 4 Port T Data Direction Bit 4 DDRT.DDT3 3 Port T Data Direction Bit 3 DDRT.DDT2 2 Port T Data Direction Bit 2 DDRT.DDT1 1 Port T Data Direction Bit 1 DDRT.DDT0 0 Port T Data Direction Bit 0 PBCTL 0x00B0 16-Bit Pulse Accumulator B Control Register PBCTL.PBEN 6 Pulse Accumulator B System Enable PBCTL.PBOVI 1 Pulse Accumulator B Overflow Interrupt enable PBFLG 0x00B1 Pulse Accumulator B Flag Register PBFLG.PBOVF 1 Pulse Accumulator B Overflow Flag PA3H 0x00B2 8-Bit Pulse Accumulators Holding Register 3 PA2H 0x00B3 8-Bit Pulse Accumulators Holding Register 2 PA1H 0x00B4 8-Bit Pulse Accumulators Holding Register 1 PA0H 0x00B5 8-Bit Pulse Accumulators Holding Register 0 MCCNTH 0x00B6 Modulus Down-Counter Count Register High MCCNTL 0x00B7 Modulus Down-Counter Count Register Low TC0HH 0x00B8 Timer Input Capture Holding Register 0 High TC0HL 0x00B9 Timer Input Capture Holding Register 0 Low TC1HH 0x00BA Timer Input Capture Holding Register 1 High TC1HL 0x00BB Timer Input Capture Holding Register 1 Low TC2HH 0x00BC Timer Input Capture Holding Register 2 High TC2HL 0x00BD Timer Input Capture Holding Register 2 Low TC3HH 0x00BE Timer Input Capture Holding Register 3 High TC3HL 0x00BF Timer Input Capture Holding Register 3 Low SC0BDH 0x00C0 SCI Baud Rate Control Register High SC0BDH.BTST 7 Reserved for test function SC0BDH.BSPL 6 Reserved for test function SC0BDH.BRLD 5 Reserved for test function SC0BDH.SBR12 4 SC0BDH.SBR11 3 SC0BDH.SBR10 2 SC0BDH.SBR9 1 SC0BDH.SBR8 0 SC0BDL 0x00C1 SCI Baud Rate Control Register Low SC0BDL.SBR7 7 SC0BDL.SBR6 6 SC0BDL.SBR5 5 SC0BDL.SBR4 4 SC0BDL.SBR3 3 SC0BDL.SBR2 2 SC0BDL.SBR1 1 SC0BDL.SBR0 0 SC0CR1 0x00C2 SCI Control Register 1 SC0CR1.LOOPS 7 SCI LOOP Mode/Single Wire Mode Enable SC0CR1.WOMS 6 Wired-Or Mode for Serial Pins SC0CR1.RSRC 5 Receiver Source SC0CR1.M 4 Mode (select character format) SC0CR1.WAKE 3 Wake-up by Address Mark/Idle SC0CR1.ILT 2 Idle Line Type SC0CR1.PE 1 Parity Enable SC0CR1.PT 0 Parity Type SC0CR2 0x00C3 SCI Control Register 2 SC0CR2.TIE 7 Transmit Interrupt Enable SC0CR2.TCIE 6 Transmit Complete Interrupt Enable SC0CR2.RIE 5 Receiver Interrupt Enable SC0CR2.ILIE 4 Idle Line Interrupt Enable SC0CR2.TE 3 Transmitter Enable SC0CR2.RE 2 Receiver Enable SC0CR2.RWU 1 Receiver Wake-Up Control SC0CR2.SBK 0 Send Break SC0SR1 0x00C4 SCI Status Register 1 SC0SR1.TDRE 7 Transmit Data Register Empty Flag SC0SR1.TC 6 Transmit Complete Flag SC0SR1.RDRF 5 Receive Data Register Full Flag SC0SR1.IDLE 4 Idle Line Detected Flag SC0SR1.OR 3 Overrun Error Flag SC0SR1.NF 2 Noise Error Flag SC0SR1.FE 1 Framing Error Flag SC0SR1.PF 0 Parity Error Flag SC0SR2 0x00C5 SCI Status Register 2 SC0SR2.RAF 0 Receiver Active Flag SC0DRH 0x00C6 SCI Data Register High SC0DRH.R8 7 Receive Bit 8 SC0DRH.T8 6 Transmit Bit 8 SC0DRL 0x00C7 SCI Data Register Low SC0DRL.R7_T7 7 Receive/Transmit Data Bit 7 SC0DRL.R6_T6 6 Receive/Transmit Data Bit 6 SC0DRL.R5_T5 5 Receive/Transmit Data Bit 5 SC0DRL.R4_T4 4 Receive/Transmit Data Bit 4 SC0DRL.R3_T3 3 Receive/Transmit Data Bit 3 SC0DRL.R2_T2 2 Receive/Transmit Data Bit 2 SC0DRL.R1_T1 1 Receive/Transmit Data Bit 1 SC0DRL.R0_T0 0 Receive/Transmit Data Bit 0 SC1BDH 0x00C8 SCI Baud Rate Control Register High SC1BDH.BTST 7 Reserved for test function SC1BDH.BSPL 6 Reserved for test function SC1BDH.BRLD 5 Reserved for test function SC1BDH.SBR12 4 SC1BDH.SBR11 3 SC1BDH.SBR10 2 SC1BDH.SBR9 1 SC1BDH.SBR8 0 SC1BDL 0x00C9 SCI Baud Rate Control Register Low SC1BDL.SBR7 7 SC1BDL.SBR6 6 SC1BDL.SBR5 5 SC1BDL.SBR4 4 SC1BDL.SBR3 3 SC1BDL.SBR2 2 SC1BDL.SBR1 1 SC1BDL.SBR0 0 SC1CR1 0x00CA SCI Control Register 1 SC1CR1.LOOPS 7 SCI LOOP Mode/Single Wire Mode Enable SC1CR1.WOMS 6 Wired-Or Mode for Serial Pins SC1CR1.RSRC 5 Receiver Source SC1CR1.M 4 Mode (select character format) SC1CR1.WAKE 3 Wake-up by Address Mark/Idle SC1CR1.ILT 2 Idle Line Type SC1CR1.PE 1 Parity Enable SC1CR1.PT 0 Parity Type SC1CR2 0x00CB SCI Control Register 2 SC1CR2.TIE 7 Transmit Interrupt Enable SC1CR2.TCIE 6 Transmit Complete Interrupt Enable SC1CR2.RIE 5 Receiver Interrupt Enable SC1CR2.ILIE 4 Idle Line Interrupt Enable SC1CR2.TE 3 Transmitter Enable SC1CR2.RE 2 Receiver Enable SC1CR2.RWU 1 Receiver Wake-Up Control SC1CR2.SBK 0 Send Break SC1SR1 0x00CC SCI Status Register 1 SC1SR1.TDRE 7 Transmit Data Register Empty Flag SC1SR1.TC 6 Transmit Complete Flag SC1SR1.RDRF 5 Receive Data Register Full Flag SC1SR1.IDLE 4 Idle Line Detected Flag SC1SR1.OR 3 Overrun Error Flag SC1SR1.NF 2 Noise Error Flag SC1SR1.FE 1 Framing Error Flag SC1SR1.PF 0 Parity Error Flag SC1SR2 0x00CD SCI Status Register 2 SC1SR2.RAF 0 Receiver Active Flag SC1DRH 0x00CE SCI Data Register High SC1DRH.R8 7 Receive Bit 8 SC1DRH.T8 6 Transmit Bit 8 SC1DRL 0x00CF SCI Data Register Low SC1DRL.R7_T7 7 Receive/Transmit Data Bit 7 SC1DRL.R6_T6 6 Receive/Transmit Data Bit 6 SC1DRL.R5_T5 5 Receive/Transmit Data Bit 5 SC1DRL.R4_T4 4 Receive/Transmit Data Bit 4 SC1DRL.R3_T3 3 Receive/Transmit Data Bit 3 SC1DRL.R2_T2 2 Receive/Transmit Data Bit 2 SC1DRL.R1_T1 1 Receive/Transmit Data Bit 1 SC1DRL.R0_T0 0 Receive/Transmit Data Bit 0 SP0CR1 0x00D0 SPI Control Register 1 SP0CR1.SPIE 7 SPI Interrupt Enable SP0CR1.SPE 6 SPI System Enable SP0CR1.SWOM 5 Port S Wired-OR Mode SP0CR1.MSTR 4 SPI Master/Slave Mode Select SP0CR1.CPOL 3 SPI Clock Polarity SP0CR1.CPHA 2 Clock Phase SP0CR1.SSOE 1 Slave Select Output Enable SP0CR1.LSBF 0 SPI LSB First enable SP0CR2 0x00D1 SPI Control Register 2 SP0CR2.PUPS 3 Pull-Up Port S Enable SP0CR2.RDPS 2 Reduce Drive of Port S SP0CR2.SSWAI 1 Serial Interface Stop in WAIT mode SP0CR2.SPC0 0 Serial Pin Control 0 SP0BR 0x00D2 SPI Baud Rate Register SP0BR.SPR2 2 SPI Clock (SCK) Rate Select Bit 2 SP0BR.SPR1 1 SPI Clock (SCK) Rate Select Bit 1 SP0BR.SPR0 0 SPI Clock (SCK) Rate Select Bit 0 SP0SR 0x00D3 SPI Status Register SP0SR.SPIF 7 SPI Interrupt Request SP0SR.WCOL 6 Write Collision Status Flag SP0SR.MODF 4 SPI Mode Error Interrupt Status Flag RESERVED00D4 0x00D4 RESERVED SP0DR 0x00D5 SPI Data Register PORTS 0x00D6 Port S Data Register PORTS.PS7 7 Port S Data Bit 7 PORTS.PS6 6 Port S Data Bit 6 PORTS.PS5 5 Port S Data Bit 5 PORTS.PS4 4 Port S Data Bit 4 PORTS.PS3 3 Port S Data Bit 3 PORTS.PS2 2 Port S Data Bit 2 PORTS.PS1 1 Port S Data Bit 1 PORTS.PS0 0 Port S Data Bit 0 DDRS 0x00D7 Port S Data Direction Register DDRS.DDS7 7 Port S Data Direction Bit 7 DDRS.DDS6 6 Port S Data Direction Bit 6 DDRS.DDS5 5 Port S Data Direction Bit 5 DDRS.DDS4 4 Port S Data Direction Bit 4 DDRS.DDS3 3 Port S Data Direction Bit 3 DDRS.DDS2 2 Port S Data Direction Bit 2 DDRS.DDS1 1 Port S Data Direction Bit 1 DDRS.DDS0 0 Port S Data Direction Bit 0 RESERVED00D8 0x00D8 RESERVED RESERVED00D9 0x00D9 RESERVED RESERVED00DA 0x00DA RESERVED RESERVED00DB 0x00DB RESERVED RESERVED00DC 0x00DC RESERVED RESERVED00DD 0x00DD RESERVED RESERVED00DE 0x00DE RESERVED RESERVED00DF 0x00DF RESERVED IBAD 0x00E0 Bus Address Register IBAD.ADR7 7 Slave Address 7 IBAD.ADR6 6 Slave Address 6 IBAD.ADR5 5 Slave Address 5 IBAD.ADR4 4 Slave Address 4 IBAD.ADR3 3 Slave Address 3 IBAD.ADR2 2 Slave Address 2 IBAD.ADR1 1 Slave Address 1 IBFD 0x00E1 IIC Bus Frequency Divider Register IBFD.IBC5 5 IIC Bus Clock Rate 5 IBFD.IBC4 4 IIC Bus Clock Rate 4 IBFD.IBC3 3 IIC Bus Clock Rate 3 IBFD.IBC2 2 IIC Bus Clock Rate 2 IBFD.IBC1 1 IIC Bus Clock Rate 1 IBFD.IBC0 0 IIC Bus Clock Rate 0 IBCR 0x00E2 IIC Bus Control Register IBCR.IBEN 7 IIC Bus Enable IBCR.IBIE 6 IIC Bus Interrupt Enable IBCR.MS_SL 5 Master/Slave mode select bit IBCR.Tx_Rx 4 Transmit/Receive mode select bit IBCR.TXAK 3 Transmit Acknowledge enable IBCR.RSTA 2 Repeat Start IBCR.IBSWAI 0 IIC Stop in WAIT mode IBSR 0x00E3 IIC Bus Status Register IBSR.TCF 7 Data transferring bit IBSR.IAAS 6 Addressed as a slave bit IBSR.IBB 5 IIC Bus busy bit IBSR.IBAL 4 Arbitration Lost IBSR.SRW 2 Slave Read/Write IBSR.IBIF 1 IIC Bus Interrupt Flag IBSR.RXAK 0 Received Acknowledge IBDR 0x00E4 IIC Bus Data I/O Register IBDR.D7 7 IBDR.D6 6 IBDR.D5 5 IBDR.D4 4 IBDR.D3 3 IBDR.D2 2 IBDR.D1 1 IBDR.D0 0 IBPURD 0x00E5 Pull-Up and Reduced Drive for Port IB IBPURD.RDPIB 4 Reduced Drive of Port IB IBPURD.PUPIB 0 Pull-Up Port IB Enable PORTIB 0x00E6 Port Data IB Register PORTIB.PIB7 7 Port Data IB Register bit 7 PORTIB.PIB6 6 Port Data IB Register bit 6 PORTIB.PIB5 5 Port Data IB Register bit 5 PORTIB.PIB4 4 Port Data IB Register bit 4 PORTIB.PIB3 3 Port Data IB Register bit 3 PORTIB.PIB2 2 Port Data IB Register bit 2 PORTIB.PIB1 1 Port Data IB Register bit 1 PORTIB.PIB0 0 Port Data IB Register bit 0 DDRIB 0x00E7 Data Direction for Port IB Register DDRIB.DDRIB7 7 Port IB Data direction 7 DDRIB.DDRIB6 6 Port IB Data direction 6 DDRIB.DDRIB5 5 Port IB Data direction 5 DDRIB.DDRIB4 4 Port IB Data direction 4 DDRIB.DDRIB3 3 Port IB Data direction 3 DDRIB.DDRIB2 2 Port IB Data direction 2 DDRIB.DDRIB1 1 DDRIB.DDRIB0 0 RESERVED00E8 0x00E8 RESERVED RESERVED00E9 0x00E9 RESERVED RESERVED00EA 0x00EA RESERVED RESERVED00EB 0x00EB RESERVED RESERVED00EC 0x00EC RESERVED RESERVED00ED 0x00ED RESERVED EEDIVH 0x00EE EEPROM Modulus Divider High EEDIVH.EEDIV9 1 Prescaler divider 9 EEDIVH.EEDIV8 0 Prescaler divider 8 EEDIVL 0x00EF EEPROM Modulus Divider Low EEDIVL.EEDIV7 7 Prescaler divider 7 EEDIVL.EEDIV6 6 Prescaler divider 6 EEDIVL.EEDIV5 5 Prescaler divider 5 EEDIVL.EEDIV4 4 Prescaler divider 4 EEDIVL.EEDIV3 3 Prescaler divider 3 EEDIVL.EEDIV2 2 Prescaler divider 2 EEDIVL.EEDIV1 1 Prescaler divider 1 EEDIVL.EEDIV0 0 Prescaler divider 0 EEMCR 0x00F0 EEPROM Module Configuration EEMCR.NOBDML 7 Background Debug Mode Lockout Disable EEMCR.NOSHW 6 SHADOW Byte Disable EEMCR.EESWAI 2 EEPROM Stops in Wait Mode EEMCR.PROTLCK 1 Block Protect Write Lock EEMCR.EERC 0 EEPROM Charge Pump Clock EEPROT 0x00F1 EEPROM Block Protect EEPROT.SHPROT 7 SHADOW Byte Protection EEPROT.BPROT5 5 EEPROM Block Protection 5 EEPROT.BPROT4 4 EEPROM Block Protection 4 EEPROT.BPROT3 3 EEPROM Block Protection 3 EEPROT.BPROT2 2 EEPROM Block Protection 2 EEPROT.BPROT1 1 EEPROM Block Protection 1 EEPROT.BPROT0 0 EEPROM Block Protection 0 EETST 0x00F2 EEPROM Test EETST.EREVTN 6 EETST.ETMSD 2 EETST.ETMR 1 EETST.ETMSE 0 EEPROG 0x00F3 EEPROM Control EEPROG.BULKP 7 Bulk Erase Protection EEPROG..AUTO 5 Automatic shutdown of program/erase operation EEPROG.BYTE 4 Byte and Aligned Word Erase EEPROG.ROW 3 Row or Bulk Erase (when BYTE = 0) EEPROG.ERASE 2 Erase Control EEPROG.EELAT 1 EEPROM Latch Control EEPROG.EEPGM 0 Program and Erase Enable FEELCK 0x00F4 Flash EEPROM Lock Control Register FEELCK.LOCK 0 Lock Register Bit FEEMCR 0x00F5 Flash EEPROM Module Configuration Register FEEMCR.BOOTP 0 Boot Protect FEETST 0x00F6 FEETST FEETST.STRE 7 FEETST.REVTUN 6 FEETST.TMSD 2 FEETST.TMR 1 FEETST.TMSE 0 FEECTL 0x00F7 Flash EEPROM Control Register FEECTL.FEESWAI 4 Flash EEPROM Stop in Wait Control FEECTL.HVEN 3 High-Voltage Enable FEECTL.ERAS 1 Erase Control FEECTL.PGM 0 Program Control MTST0 0x00F8 Mapping Test Register 0 MTST0.MT07 7 MTST0.MT06 6 MTST0.MT05 5 MTST0.MT04 4 MTST0.MT03 3 MTST0.MT02 2 MTST0.MT01 1 MTST0.MT00 0 MTST1 0x00F9 Mapping Test Register 1 MTST1.MT0F 7 MTST1.MT0E 6 MTST1.MT0D 5 MTST1.MT0C 4 MTST1.MT0B 3 MTST1.MT0A 2 MTST1.MT09 1 MTST1.MT08 0 MTST2 0x00FA Mapping Test Register 2 MTST2.MT17 7 MTST2.MT16 6 MTST2.MT15 5 MTST2.MT14 4 MTST2.MT13 3 MTST2.MT12 2 MTST2.MT11 1 MTST2.MT10 0 MTST3 0x00FB Mapping Test Register 3 MTST3.MT1F 7 MTST3.MT1E 6 MTST3.MT1D 5 MTST3.MT1C 4 MTST3.MT1B 3 MTST3.MT1A 2 MTST3.MT19 1 MTST3.MT18 0 PORTK 0x00FC Port K Data Register PORTK.PK7 7 Port K Data Bit 7 PORTK.PK3 3 Port K Data Bit 3 PORTK.PK2 2 Port K Data Bit 2 PORTK.PK1 1 Port K Data Bit 1 PORTK.PK0 0 Port K Data Bit 0 DDRK 0x00FD Port K Data Direction Register DDRK.DDK7 7 Port K Data Direction Bit 7 DDRK.DDK3 3 Port K Data Direction Bit 3 DDRK.DDK2 2 Port K Data Direction Bit 2 DDRK.DDK1 1 Port K Data Direction Bit 1 DDRK.DDK0 0 Port K Data Direction Bit 0 RESERVED00FE 0x00FE RESERVED PPAGE 0x00FF Program Page Index Register PPAGE.PIX2 2 PPAGE.PIX1 1 PPAGE.PIX0 0 C0MCR0 0x0100 msCAN12 Module Control Register 0 C0MCR0.CSWAI 5 CAN Stops in Wait Mode C0MCR0.SYNCH 4 Synchronized Status C0MCR0.TLNKEN 3 Timer Enable C0MCR0.SLPAK 2 SLEEP Mode Acknowledge C0MCR0.SLPRQ 1 SLEEP request C0MCR0.SFTRES 0 SOFT_RESET C0MCR1 0x0101 msCAN12 Module Control Register 1 C0MCR1.LOOPB 2 Loop Back Self Test Mode C0MCR1.WUPM 1 Wake-Up Mode C0MCR1.CLKSRC 0 msCAN12 Clock Source C0BTR0 0x0102 msCAN12 Bus Timing Register 0 C0BTR0.SJW1 7 Synchronization Jump Width 1 C0BTR0.SJW0 6 Synchronization Jump Width 0 C0BTR0.BRP5 5 Baud Rate Prescaler 5 C0BTR0.BRP4 4 Baud Rate Prescaler 4 C0BTR0.BRP3 3 Baud Rate Prescaler 3 C0BTR0.BRP2 2 Baud Rate Prescaler 2 C0BTR0.BRP1 1 Baud Rate Prescaler 1 C0BTR0.BRP0 0 Baud Rate Prescaler 0 C0BTR1 0x0103 msCAN12 Bus Timing Register 1 C0BTR1.SAMP 7 Sampling C0BTR1.TSEG22 6 Time Segment 22 C0BTR1.TSEG21 5 Time Segment 21 C0BTR1.TSEG20 4 Time Segment 20 C0BTR1.TSEG13 3 Time Segment 13 C0BTR1.TSEG12 2 Time Segment 12 C0BTR1.TSEG11 1 Time Segment 11 C0BTR1.TSEG10 0 Time Segment 10 C0RFLG 0x0104 msCAN12 Receiver Flag Register C0RFLG.WUPIF 7 Wake-up Interrupt Flag C0RFLG.RWRNIF 6 Receiver Warning Interrupt Flag C0RFLG.TWRNIF 5 Transmitter Warning Interrupt Flag C0RFLG.RERRIF 4 Receiver Error Passive Interrupt Flag C0RFLG.TERRIF 3 Transmitter Error Passive Interrupt Flag C0RFLG.BOFFIF 2 BUSOFF Interrupt Flag C0RFLG.OVRIF 1 Overrun Interrupt Flag C0RFLG.RXF 0 Receive Buffer Full C0RIER 0x0105 msCAN12 Receiver Interrupt Enable Register C0RIER.WUPIE 7 Wake-up Interrupt Enable C0RIER.RWRNIE 6 Receiver Warning Interrupt Enable C0RIER.TWRNIE 5 Transmitter Warning Interrupt Enable C0RIER.RERRIE 4 Receiver Error Passive Interrupt Enable C0RIER.TERRIE 3 Transmitter Error Passive Interrupt Enable C0RIER.BOFFIE 2 BUSOFF Interrupt Enable C0RIER.OVRIE 1 Overrun Interrupt Enable C0RIER.RXFIE 0 Receiver Full Interrupt Enable C0TFLG 0x0106 msCAN12 Transmitter Flag Register C0TFLG.ABTAK2 6 Abort Acknowledge 2 C0TFLG.ABTAK1 5 Abort Acknowledge 1 C0TFLG.ABTAK0 4 Abort Acknowledge 0 C0TFLG.TXE2 2 Transmitter Buffer Empty 2 C0TFLG.TXE1 1 Transmitter Buffer Empty 1 C0TFLG.TXE0 0 Transmitter Buffer Empty 0 C0TCR 0x0107 msCAN12 Transmitter Control Register C0TCR.ABTRQ2 6 Abort Request 2 C0TCR.ABTRQ1 5 Abort Request 1 C0TCR.ABTRQ0 4 Abort Request 0 C0TCR.TXEIE2 2 Transmitter Empty Interrupt Enable 2 C0TCR.TXEIE1 1 Transmitter Empty Interrupt Enable 1 C0TCR.TXEIE0 0 Transmitter Empty Interrupt Enable 0 C0IDAC 0x0108 msCAN12 Identifier Acceptance Control Register C0IDAC.IDAM1 5 Identifier Acceptance Mode 1 C0IDAC.IDAM0 4 Identifier Acceptance Mode 0 C0IDAC.IDHIT2 2 Identifier Acceptance Hit Indicator 2 C0IDAC.IDHIT1 1 Identifier Acceptance Hit Indicator 1 C0IDAC.IDHIT0 0 Identifier Acceptance Hit Indicator 0 RESERVED0109 0x0109 RESERVED RESERVED010A 0x010A RESERVED RESERVED010B 0x010B RESERVED RESERVED010C 0x010C RESERVED RESERVED010D 0x010D RESERVED C0RXERR 0x010E msCAN12 Receive Error Counter C0RXERR.RXERR7 7 C0RXERR.RXERR6 6 C0RXERR.RXERR5 5 C0RXERR.RXERR4 4 C0RXERR.RXERR3 3 C0RXERR.RXERR2 2 C0RXERR.RXERR1 1 C0RXERR.RXERR0 0 C0TXERR 0x010F msCAN12 Transmit Error Counter C0TXERR.TXERR7 7 C0TXERR.TXERR6 6 C0TXERR.TXERR5 5 C0TXERR.TXERR4 4 C0TXERR.TXERR3 3 C0TXERR.TXERR2 2 C0TXERR.TXERR1 1 C0TXERR.TXERR0 0 C0IDAR0 0x0110 msCAN12 Identifier Acceptance Register 0 C0IDAR0.AC7 7 Acceptance Code Bit 7 C0IDAR0.AC6 6 Acceptance Code Bit 6 C0IDAR0.AC5 5 Acceptance Code Bit 5 C0IDAR0.AC4 4 Acceptance Code Bit 4 C0IDAR0.AC3 3 Acceptance Code Bit 3 C0IDAR0.AC2 2 Acceptance Code Bit 2 C0IDAR0.AC1 1 Acceptance Code Bit 1 C0IDAR0.AC0 0 Acceptance Code Bit 0 C0IDAR1 0x0111 msCAN12 Identifier Acceptance Register 1 C0IDAR1.AC7 7 Acceptance Code Bit 7 C0IDAR1.AC6 6 Acceptance Code Bit 6 C0IDAR1.AC5 5 Acceptance Code Bit 5 C0IDAR1.AC4 4 Acceptance Code Bit 4 C0IDAR1.AC3 3 Acceptance Code Bit 3 C0IDAR1.AC2 2 Acceptance Code Bit 2 C0IDAR1.AC1 1 Acceptance Code Bit 1 C0IDAR1.AC0 0 Acceptance Code Bit 0 C0IDAR2 0x0112 msCAN12 Identifier Acceptance Register 2 C0IDAR2.AC7 7 Acceptance Code Bit 7 C0IDAR2.AC6 6 Acceptance Code Bit 6 C0IDAR2.AC5 5 Acceptance Code Bit 5 C0IDAR2.AC4 4 Acceptance Code Bit 4 C0IDAR2.AC3 3 Acceptance Code Bit 3 C0IDAR2.AC2 2 Acceptance Code Bit 2 C0IDAR2.AC1 1 Acceptance Code Bit 1 C0IDAR2.AC0 0 Acceptance Code Bit 0 C0IDAR3 0x0113 msCAN12 Identifier Acceptance Register 3 C0IDAR3.AC7 7 Acceptance Code Bit 7 C0IDAR3.AC6 6 Acceptance Code Bit 6 C0IDAR3.AC5 5 Acceptance Code Bit 5 C0IDAR3.AC4 4 Acceptance Code Bit 4 C0IDAR3.AC3 3 Acceptance Code Bit 3 C0IDAR3.AC2 2 Acceptance Code Bit 2 C0IDAR3.AC1 1 Acceptance Code Bit 1 C0IDAR3.AC0 0 Acceptance Code Bit 0 C0IDMR0 0x0114 msCAN12 Identifier Mask Register 0 C0IDMR0.AM7 7 Acceptance Mask Bit 7 C0IDMR0.AM6 6 Acceptance Mask Bit 6 C0IDMR0.AM5 5 Acceptance Mask Bit 5 C0IDMR0.AM4 4 Acceptance Mask Bit 4 C0IDMR0.AM3 3 Acceptance Mask Bit 3 C0IDMR0.AM2 2 Acceptance Mask Bit 2 C0IDMR0.AM1 1 Acceptance Mask Bit 1 C0IDMR0.AM0 0 Acceptance Mask Bit 0 C0IDMR1 0x0115 msCAN12 Identifier Mask Register 1 C0IDMR1.AM7 7 Acceptance Mask Bit 7 C0IDMR1.AM6 6 Acceptance Mask Bit 6 C0IDMR1.AM5 5 Acceptance Mask Bit 5 C0IDMR1.AM4 4 Acceptance Mask Bit 4 C0IDMR1.AM3 3 Acceptance Mask Bit 3 C0IDMR1.AM2 2 Acceptance Mask Bit 2 C0IDMR1.AM1 1 Acceptance Mask Bit 1 C0IDMR1.AM0 0 Acceptance Mask Bit 0 C0IDMR2 0x0116 msCAN12 Identifier Mask Register 2 C0IDMR2.AM7 7 Acceptance Mask Bit 7 C0IDMR2.AM6 6 Acceptance Mask Bit 6 C0IDMR2.AM5 5 Acceptance Mask Bit 5 C0IDMR2.AM4 4 Acceptance Mask Bit 4 C0IDMR2.AM3 3 Acceptance Mask Bit 3 C0IDMR2.AM2 2 Acceptance Mask Bit 2 C0IDMR2.AM1 1 Acceptance Mask Bit 1 C0IDMR2.AM0 0 Acceptance Mask Bit 0 C0IDMR3 0x0117 msCAN12 Identifier Mask Register 3 C0IDMR3.AM7 7 Acceptance Mask Bit 7 C0IDMR3.AM6 6 Acceptance Mask Bit 6 C0IDMR3.AM5 5 Acceptance Mask Bit 5 C0IDMR3.AM4 4 Acceptance Mask Bit 4 C0IDMR3.AM3 3 Acceptance Mask Bit 3 C0IDMR3.AM2 2 Acceptance Mask Bit 2 C0IDMR3.AM1 1 Acceptance Mask Bit 1 C0IDMR3.AM0 0 Acceptance Mask Bit 0 C0IDAR4 0x0118 msCAN12 Identifier Acceptance Register 4 C0IDAR4.AC7 7 Acceptance Code Bit 7 C0IDAR4.AC6 6 Acceptance Code Bit 6 C0IDAR4.AC5 5 Acceptance Code Bit 5 C0IDAR4.AC4 4 Acceptance Code Bit 4 C0IDAR4.AC3 3 Acceptance Code Bit 3 C0IDAR4.AC2 2 Acceptance Code Bit 2 C0IDAR4.AC1 1 Acceptance Code Bit 1 C0IDAR4.AC0 0 Acceptance Code Bit 0 C0IDAR5 0x0119 msCAN12 Identifier Acceptance Register 5 C0IDAR5.AC7 7 Acceptance Code Bit 7 C0IDAR5.AC6 6 Acceptance Code Bit 6 C0IDAR5.AC5 5 Acceptance Code Bit 5 C0IDAR5.AC4 4 Acceptance Code Bit 4 C0IDAR5.AC3 3 Acceptance Code Bit 3 C0IDAR5.AC2 2 Acceptance Code Bit 2 C0IDAR5.AC1 1 Acceptance Code Bit 1 C0IDAR5.AC0 0 Acceptance Code Bit 0 C0IDAR6 0x011A msCAN12 Identifier Acceptance Register 6 C0IDAR6.AC7 7 Acceptance Code Bit 7 C0IDAR6.AC6 6 Acceptance Code Bit 6 C0IDAR6.AC5 5 Acceptance Code Bit 5 C0IDAR6.AC4 4 Acceptance Code Bit 4 C0IDAR6.AC3 3 Acceptance Code Bit 3 C0IDAR6.AC2 2 Acceptance Code Bit 2 C0IDAR6.AC1 1 Acceptance Code Bit 1 C0IDAR6.AC0 0 Acceptance Code Bit 0 C0IDAR7 0x011B msCAN12 Identifier Acceptance Register 7 C0IDAR7.AC7 7 Acceptance Code Bit 7 C0IDAR7.AC6 6 Acceptance Code Bit 6 C0IDAR7.AC5 5 Acceptance Code Bit 5 C0IDAR7.AC4 4 Acceptance Code Bit 4 C0IDAR7.AC3 3 Acceptance Code Bit 3 C0IDAR7.AC2 2 Acceptance Code Bit 2 C0IDAR7.AC1 1 Acceptance Code Bit 1 C0IDAR7.AC0 0 Acceptance Code Bit 0 C0IDMR4 0x011C msCAN12 Identifier Mask Register 4 C0IDMR4.AM7 7 Acceptance Mask Bit 7 C0IDMR4.AM6 6 Acceptance Mask Bit 6 C0IDMR4.AM5 5 Acceptance Mask Bit 5 C0IDMR4.AM4 4 Acceptance Mask Bit 4 C0IDMR4.AM3 3 Acceptance Mask Bit 3 C0IDMR4.AM2 2 Acceptance Mask Bit 2 C0IDMR4.AM1 1 Acceptance Mask Bit 1 C0IDMR4.AM0 0 Acceptance Mask Bit 0 C0IDMR5 0x011D msCAN12 Identifier Mask Register 5 C0IDMR5.AM7 7 Acceptance Mask Bit 7 C0IDMR5.AM6 6 Acceptance Mask Bit 6 C0IDMR5.AM5 5 Acceptance Mask Bit 5 C0IDMR5.AM4 4 Acceptance Mask Bit 4 C0IDMR5.AM3 3 Acceptance Mask Bit 3 C0IDMR5.AM2 2 Acceptance Mask Bit 2 C0IDMR5.AM1 1 Acceptance Mask Bit 1 C0IDMR5.AM0 0 Acceptance Mask Bit 0 C0IDMR6 0x011E msCAN12 Identifier Mask Register 6 C0IDMR6.AM7 7 Acceptance Mask Bit 7 C0IDMR6.AM6 6 Acceptance Mask Bit 6 C0IDMR6.AM5 5 Acceptance Mask Bit 5 C0IDMR6.AM4 4 Acceptance Mask Bit 4 C0IDMR6.AM3 3 Acceptance Mask Bit 3 C0IDMR6.AM2 2 Acceptance Mask Bit 2 C0IDMR6.AM1 1 Acceptance Mask Bit 1 C0IDMR6.AM0 0 Acceptance Mask Bit 0 C0IDMR7 0x011F msCAN12 Identifier Mask Register 7 C0IDMR7.AM7 7 Acceptance Mask Bit 7 C0IDMR7.AM6 6 Acceptance Mask Bit 6 C0IDMR7.AM5 5 Acceptance Mask Bit 5 C0IDMR7.AM4 4 Acceptance Mask Bit 4 C0IDMR7.AM3 3 Acceptance Mask Bit 3 C0IDMR7.AM2 2 Acceptance Mask Bit 2 C0IDMR7.AM1 1 Acceptance Mask Bit 1 C0IDMR7.AM0 0 Acceptance Mask Bit 0 RESERVED0120 0x0120 RESERVED RESERVED0121 0x0121 RESERVED RESERVED0122 0x0122 RESERVED RESERVED0123 0x0123 RESERVED RESERVED0124 0x0124 RESERVED RESERVED0125 0x0125 RESERVED RESERVED0126 0x0126 RESERVED RESERVED0127 0x0127 RESERVED RESERVED0128 0x0128 RESERVED RESERVED0129 0x0129 RESERVED RESERVED012A 0x012A RESERVED RESERVED012B 0x012B RESERVED RESERVED012C 0x012C RESERVED RESERVED012D 0x012D RESERVED RESERVED012E 0x012E RESERVED RESERVED012F 0x012F RESERVED RESERVED0130 0x0130 RESERVED RESERVED0131 0x0131 RESERVED RESERVED0132 0x0132 RESERVED RESERVED0133 0x0133 RESERVED RESERVED0134 0x0134 RESERVED RESERVED0135 0x0135 RESERVED RESERVED0136 0x0136 RESERVED RESERVED0137 0x0137 RESERVED RESERVED0138 0x0138 RESERVED RESERVED0139 0x0139 RESERVED RESERVED013A 0x013A RESERVED RESERVED013B 0x013B RESERVED RESERVED013C 0x013C RESERVED PCTLCAN0 0x013D msCAN12 Port CAN Control Register PCTLCAN0.PUPCAN 1 Pull-Up Enable Port CAN PCTLCAN0.RDPCAN 0 Reduced Drive Port CAN PORTCAN0 0x013E msCAN12 Port CAN Data Register PORTCAN0.PCAN7 7 Port CAN Data Bit 7 PORTCAN0.PCAN6 6 Port CAN Data Bit 6 PORTCAN0.PCAN5 5 Port CAN Data Bit 5 PORTCAN0.PCAN4 4 Port CAN Data Bit 4 PORTCAN0.PCAN3 3 Port CAN Data Bit 3 PORTCAN0.PCAN2 2 Port CAN Data Bit 2 PORTCAN0.TxCAN 1 PORTCAN0.RxCAN 0 DDRCAN0 0x013F msCAN12 Port CAN Data Direction Register DDRCAN0.DDCAN7 7 DDRCAN0.DDCAN6 6 DDRCAN0.DDCAN5 5 DDRCAN0.DDCAN4 4 DDRCAN0.DDCAN3 3 DDRCAN0.DDCAN2 2 ATD1CTL2 0x01E2 ATD1 Control Register 2 ATD1CTL2.ADPU 7 ATD Disable ATD1CTL2.AFFC 6 ATD Fast Flag Clear All ATD1CTL2.ASWAI 5 ATD Wait Mode ATD1CTL2.DJM 4 Result Register Data Justification Mode ATD1CTL2.DSGN 3 Signed/Unsigned Result Data Mode ATD1CTL2.ASCIE 1 ATD Sequence Complete Interrupt Enable ATD1CTL2.ASCIF 0 ATD Sequence Complete Interrupt Flag ATD1CTL3 0x01E3 ATD1 Control Register 3 ATD1CTL3.S1C 3 Conversion Sequence Length (Least Significant Bit) ATD1CTL3.FIFO 2 Result Register FIFO Mode ATD1CTL3.FRZ1 1 Background Debug (Freeze) Enable 1 ATD1CTL3.FRZ0 0 Background Debug (Freeze) Enable 0 ATD1CTL4 0x01E4 ATD1 Control Register 4 ATD1CTL4.RES10 7 10 bit Mode ATD1CTL4.SMP1 6 Select Sample Time 1 ATD1CTL4.SMP0 5 Select Sample Time 0 ATD1CTL4.PRS4 4 Select Divide-By Factor for ATD P-Clock Prescaler 4 ATD1CTL4.PRS3 3 Select Divide-By Factor for ATD P-Clock Prescaler 3 ATD1CTL4.PRS2 2 Select Divide-By Factor for ATD P-Clock Prescaler 2 ATD1CTL4.PRS1 1 Select Divide-By Factor for ATD P-Clock Prescaler 1 ATD1CTL4.PRS0 0 Select Divide-By Factor for ATD P-Clock Prescaler 0 ATD1CTL5 0x01E5 ATD1 Control Register 5 ATD1CTL5.S8CM 6 Select 8 Channel Mode ATD1CTL5.SCAN 5 Enable Continuous Channel Scan ATD1CTL5.MULT 4 Enable Multichannel Conversion ATD1CTL5.CD 3 Channel Select for Conversion D ATD1CTL5.CC 2 Channel Select for Conversion C ATD1CTL5.CB 1 Channel Select for Conversion B ATD1CTL5.CA 0 Channel Select for Conversion A ATD1STAT0 0x01E6 ATD1 Status Register ATD1STAT0.SCF 7 Sequence Complete Flag ATD1STAT0.CC2 2 Conversion Counter for Current Sequence of Four or Eight Conversions 2 ATD1STAT0.CC1 1 Conversion Counter for Current Sequence of Four or Eight Conversions 1 ATD1STAT0.CC0 0 Conversion Counter for Current Sequence of Four or Eight Conversions 0 ATD1STAT1 0x01E7 ATD1 Status Register ATD1STAT1.CCF7 7 Conversion Complete Flag 7 ATD1STAT1.CCF6 6 Conversion Complete Flag 6 ATD1STAT1.CCF5 5 Conversion Complete Flag 5 ATD1STAT1.CCF4 4 Conversion Complete Flag 4 ATD1STAT1.CCF3 3 Conversion Complete Flag 3 ATD1STAT1.CCF2 2 Conversion Complete Flag 2 ATD1STAT1.CCF1 1 Conversion Complete Flag 1 ATD1STAT1.CCF0 0 Conversion Complete Flag 0 ATD1TESTH 0x01E8 ATD1 Test Register ATD1TESTH.SAR9 7 SAR Data 9 ATD1TESTH.SAR8 6 SAR Data 8 ATD1TESTH.SAR7 5 SAR Data 7 ATD1TESTH.SAR6 4 SAR Data 6 ATD1TESTH.SAR5 3 SAR Data 5 ATD1TESTH.SAR4 2 SAR Data 4 ATD1TESTH.SAR3 1 SAR Data 3 ATD1TESTH.SAR2 0 SAR Data 2 ATD1TESTL 0x01E9 ATD1 Test Register ATD1TESTL.SAR1 7 SAR Data 1 ATD1TESTL.SAR0 6 SAR Data 0 ATD1TESTL.RST 5 Module Reset Bit ATD1TESTL.TSTOUT 4 Multiplex Output of TST[3:0] (Factory Use) ATD1TESTL.TST3 3 Test Bit 3 ATD1TESTL.TST2 2 Test Bit 2 ATD1TESTL.TST1 1 Test Bit 1 ATD1TESTL.TST0 0 Test Bit 0 RESERVED01EA 0x01EA RESERVED RESERVED01EB 0x01EB RESERVED RESERVED01EC 0x01EC RESERVED RESERVED01ED 0x01ED RESERVED RESERVED01EE 0x01EE RESERVED PORTAD1 0x01EF Port AD1 Data Input Register PORTAD1.PAD17 7 Port AD1 Data Input Bit 7 PORTAD1.PAD16 6 Port AD1 Data Input Bit 6 PORTAD1.PAD15 5 Port AD1 Data Input Bit 5 PORTAD1.PAD14 4 Port AD1 Data Input Bit 4 PORTAD1.PAD13 3 Port AD1 Data Input Bit 3 PORTAD1.PAD12 2 Port AD1 Data Input Bit 2 PORTAD1.PAD11 1 Port AD1 Data Input Bit 1 PORTAD1.PAD10 0 Port AD1 Data Input Bit 0 ADR10H 0x01F0 A/D Conversion Result Register High 0 ADR10L 0x01F1 A/D Conversion Result Register Low 0 ADR11H 0x01F2 A/D Conversion Result Register High 1 ADR11L 0x01F3 A/D Conversion Result Register Low 1 ADR12H 0x01F4 A/D Conversion Result Register High 2 ADR12L 0x01F5 A/D Conversion Result Register Low 2 ADR13H 0x01F6 A/D Conversion Result Register High 3 ADR13L 0x01F7 A/D Conversion Result Register Low 3 ADR14H 0x01F8 A/D Conversion Result Register High 4 ADR14L 0x01F9 A/D Conversion Result Register Low 4 ADR15H 0x01FA A/D Conversion Result Register High 5 ADR15L 0x01FB A/D Conversion Result Register Low 5 ADR16H 0x01FC A/D Conversion Result Register High 6 ADR16L 0x01FD A/D Conversion Result Register Low 6 ADR17H 0x01FE A/D Conversion Result Register High 7 ADR17L 0x01FF A/D Conversion Result Register Low 7 C1MCR0 0x0300 msCAN12 Module Control Register 0 C1MCR0.CSWAI 5 CAN Stops in Wait Mode C1MCR0.SYNCH 4 Synchronized Status C1MCR0.TLNKEN 3 Timer Enable C1MCR0.SLPAK 2 SLEEP Mode Acknowledge C1MCR0.SLPRQ 1 SLEEP request C1MCR0.SFTRES 0 SOFT_RESET C1MCR1 0x0301 msCAN12 Module Control Register 1 C1MCR1.LOOPB 2 Loop Back Self Test Mode C1MCR1.WUPM 1 Wake-Up Mode C1MCR1.CLKSRC 0 msCAN12 Clock Source C1BTR0 0x0302 msCAN12 Bus Timing Register 0 C1BTR0.SJW1 7 Synchronization Jump Width 1 C1BTR0.SJW0 6 Synchronization Jump Width 0 C1BTR0.BRP5 5 Baud Rate Prescaler 5 C1BTR0.BRP4 4 Baud Rate Prescaler 4 C1BTR0.BRP3 3 Baud Rate Prescaler 3 C1BTR0.BRP2 2 Baud Rate Prescaler 2 C1BTR0.BRP1 1 Baud Rate Prescaler 1 C1BTR0.BRP0 0 Baud Rate Prescaler 0 C1BTR1 0x0303 msCAN12 Bus Timing Register 1 C1BTR1.SAMP 7 Sampling C1BTR1.TSEG22 6 Time Segment 22 C1BTR1.TSEG21 5 Time Segment 21 C1BTR1.TSEG20 4 Time Segment 20 C1BTR1.TSEG13 3 Time Segment 13 C1BTR1.TSEG12 2 Time Segment 12 C1BTR1.TSEG11 1 Time Segment 11 C1BTR1.TSEG10 0 Time Segment 10 C1RFLG 0x0304 msCAN12 Receiver Flag Register C1RFLG.WUPIF 7 Wake-up Interrupt Flag C1RFLG.RWRNIF 6 Receiver Warning Interrupt Flag C1RFLG.TWRNIF 5 Transmitter Warning Interrupt Flag C1RFLG.RERRIF 4 Receiver Error Passive Interrupt Flag C1RFLG.TERRIF 3 Transmitter Error Passive Interrupt Flag C1RFLG.BOFFIF 2 BUSOFF Interrupt Flag C1RFLG.OVRIF 1 Overrun Interrupt Flag C1RFLG.RXF 0 Receive Buffer Full C1RIER 0x0305 msCAN12 Receiver Interrupt Enable Register C1RIER.WUPIE 7 Wake-up Interrupt Enable C1RIER.RWRNIE 6 Receiver Warning Interrupt Enable C1RIER.TWRNIE 5 Transmitter Warning Interrupt Enable C1RIER.RERRIE 4 Receiver Error Passive Interrupt Enable C1RIER.TERRIE 3 Transmitter Error Passive Interrupt Enable C1RIER.BOFFIE 2 BUSOFF Interrupt Enable C1RIER.OVRIE 1 Overrun Interrupt Enable C1RIER.RXFIE 0 Receiver Full Interrupt Enable C1TFLG 0x0306 msCAN12 Transmitter Flag Register C1TFLG.ABTAK2 6 Abort Acknowledge 2 C1TFLG.ABTAK1 5 Abort Acknowledge 1 C1TFLG.ABTAK0 4 Abort Acknowledge 0 C1TFLG.TXE2 2 Transmitter Buffer Empty 2 C1TFLG.TXE1 1 Transmitter Buffer Empty 1 C1TFLG.TXE0 0 Transmitter Buffer Empty 0 C1TCR 0x0307 msCAN12 Transmitter Control Register C1TCR.ABTRQ2 6 Abort Request 2 C1TCR.ABTRQ1 5 Abort Request 1 C1TCR.ABTRQ0 4 Abort Request 0 C1TCR.TXEIE2 2 Transmitter Empty Interrupt Enable 2 C1TCR.TXEIE1 1 Transmitter Empty Interrupt Enable 1 C1TCR.TXEIE0 0 Transmitter Empty Interrupt Enable 0 C1IDAC 0x0308 msCAN12 Identifier Acceptance Control Register C1IDAC.IDAM1 5 Identifier Acceptance Mode 1 C1IDAC.IDAM0 4 Identifier Acceptance Mode 0 C1IDAC.IDHIT2 2 Identifier Acceptance Hit Indicator 2 C1IDAC.IDHIT1 1 Identifier Acceptance Hit Indicator 1 C1IDAC.IDHIT0 0 Identifier Acceptance Hit Indicator 0 RESERVED0309 0x0309 RESERVED RESERVED030A 0x030A RESERVED RESERVED030B 0x030B RESERVED RESERVED030C 0x030C RESERVED RESERVED030D 0x030D RESERVED C1RXERR 0x030E msCAN12 Receive Error Counter C1RXERR.RXERR7 7 C1RXERR.RXERR6 6 C1RXERR.RXERR5 5 C1RXERR.RXERR4 4 C1RXERR.RXERR3 3 C1RXERR.RXERR2 2 C1RXERR.RXERR1 1 C1RXERR.RXERR0 0 C1TXERR 0x030F msCAN12 Transmit Error Counter C1TXERR.TXERR7 7 C1TXERR.TXERR6 6 C1TXERR.TXERR5 5 C1TXERR.TXERR4 4 C1TXERR.TXERR3 3 C1TXERR.TXERR2 2 C1TXERR.TXERR1 1 C1TXERR.TXERR0 0 C1IDAR0 0x0310 msCAN12 Identifier Acceptance Register 0 C1IDAR0.AC7 7 Acceptance Code Bit 7 C1IDAR0.AC6 6 Acceptance Code Bit 6 C1IDAR0.AC5 5 Acceptance Code Bit 5 C1IDAR0.AC4 4 Acceptance Code Bit 4 C1IDAR0.AC3 3 Acceptance Code Bit 3 C1IDAR0.AC2 2 Acceptance Code Bit 2 C1IDAR0.AC1 1 Acceptance Code Bit 1 C1IDAR0.AC0 0 Acceptance Code Bit 0 C1IDAR1 0x0311 msCAN12 Identifier Acceptance Register 1 C1IDAR1.AC7 7 Acceptance Code Bit 7 C1IDAR1.AC6 6 Acceptance Code Bit 6 C1IDAR1.AC5 5 Acceptance Code Bit 5 C1IDAR1.AC4 4 Acceptance Code Bit 4 C1IDAR1.AC3 3 Acceptance Code Bit 3 C1IDAR1.AC2 2 Acceptance Code Bit 2 C1IDAR1.AC1 1 Acceptance Code Bit 1 C1IDAR1.AC0 0 Acceptance Code Bit 0 C1IDAR2 0x0312 msCAN12 Identifier Acceptance Register 2 C1IDAR2.AC7 7 Acceptance Code Bit 7 C1IDAR2.AC6 6 Acceptance Code Bit 6 C1IDAR2.AC5 5 Acceptance Code Bit 5 C1IDAR2.AC4 4 Acceptance Code Bit 4 C1IDAR2.AC3 3 Acceptance Code Bit 3 C1IDAR2.AC2 2 Acceptance Code Bit 2 C1IDAR2.AC1 1 Acceptance Code Bit 1 C1IDAR2.AC0 0 Acceptance Code Bit 0 C1IDAR3 0x0313 msCAN12 Identifier Acceptance Register 3 C1IDAR3.AC7 7 Acceptance Code Bit 7 C1IDAR3.AC6 6 Acceptance Code Bit 6 C1IDAR3.AC5 5 Acceptance Code Bit 5 C1IDAR3.AC4 4 Acceptance Code Bit 4 C1IDAR3.AC3 3 Acceptance Code Bit 3 C1IDAR3.AC2 2 Acceptance Code Bit 2 C1IDAR3.AC1 1 Acceptance Code Bit 1 C1IDAR3.AC0 0 Acceptance Code Bit 0 C1IDMR0 0x0314 msCAN12 Identifier Mask Register 0 C1IDMR0.AM7 7 Acceptance Mask Bit 7 C1IDMR0.AM6 6 Acceptance Mask Bit 6 C1IDMR0.AM5 5 Acceptance Mask Bit 5 C1IDMR0.AM4 4 Acceptance Mask Bit 4 C1IDMR0.AM3 3 Acceptance Mask Bit 3 C1IDMR0.AM2 2 Acceptance Mask Bit 2 C1IDMR0.AM1 1 Acceptance Mask Bit 1 C1IDMR0.AM0 0 Acceptance Mask Bit 0 C1IDMR1 0x0315 msCAN12 Identifier Mask Register 1 C1IDMR1.AM7 7 Acceptance Mask Bit 7 C1IDMR1.AM6 6 Acceptance Mask Bit 6 C1IDMR1.AM5 5 Acceptance Mask Bit 5 C1IDMR1.AM4 4 Acceptance Mask Bit 4 C1IDMR1.AM3 3 Acceptance Mask Bit 3 C1IDMR1.AM2 2 Acceptance Mask Bit 2 C1IDMR1.AM1 1 Acceptance Mask Bit 1 C1IDMR1.AM0 0 Acceptance Mask Bit 0 C1IDMR2 0x0316 msCAN12 Identifier Mask Register 2 C1IDMR2.AM7 7 Acceptance Mask Bit 7 C1IDMR2.AM6 6 Acceptance Mask Bit 6 C1IDMR2.AM5 5 Acceptance Mask Bit 5 C1IDMR2.AM4 4 Acceptance Mask Bit 4 C1IDMR2.AM3 3 Acceptance Mask Bit 3 C1IDMR2.AM2 2 Acceptance Mask Bit 2 C1IDMR2.AM1 1 Acceptance Mask Bit 1 C1IDMR2.AM0 0 Acceptance Mask Bit 0 C1IDMR3 0x0317 msCAN12 Identifier Mask Register 3 C1IDMR3.AM7 7 Acceptance Mask Bit 7 C1IDMR3.AM6 6 Acceptance Mask Bit 6 C1IDMR3.AM5 5 Acceptance Mask Bit 5 C1IDMR3.AM4 4 Acceptance Mask Bit 4 C1IDMR3.AM3 3 Acceptance Mask Bit 3 C1IDMR3.AM2 2 Acceptance Mask Bit 2 C1IDMR3.AM1 1 Acceptance Mask Bit 1 C1IDMR3.AM0 0 Acceptance Mask Bit 0 C1IDAR4 0x0318 msCAN12 Identifier Acceptance Register 4 C1IDAR4.AC7 7 Acceptance Code Bit 7 C1IDAR4.AC6 6 Acceptance Code Bit 6 C1IDAR4.AC5 5 Acceptance Code Bit 5 C1IDAR4.AC4 4 Acceptance Code Bit 4 C1IDAR4.AC3 3 Acceptance Code Bit 3 C1IDAR4.AC2 2 Acceptance Code Bit 2 C1IDAR4.AC1 1 Acceptance Code Bit 1 C1IDAR4.AC0 0 Acceptance Code Bit 0 C1IDAR5 0x0319 msCAN12 Identifier Acceptance Register 5 C1IDAR5.AC7 7 Acceptance Code Bit 7 C1IDAR5.AC6 6 Acceptance Code Bit 6 C1IDAR5.AC5 5 Acceptance Code Bit 5 C1IDAR5.AC4 4 Acceptance Code Bit 4 C1IDAR5.AC3 3 Acceptance Code Bit 3 C1IDAR5.AC2 2 Acceptance Code Bit 2 C1IDAR5.AC1 1 Acceptance Code Bit 1 C1IDAR5.AC0 0 Acceptance Code Bit 0 C1IDAR6 0x031A msCAN12 Identifier Acceptance Register 6 C1IDAR6.AC7 7 Acceptance Code Bit 7 C1IDAR6.AC6 6 Acceptance Code Bit 6 C1IDAR6.AC5 5 Acceptance Code Bit 5 C1IDAR6.AC4 4 Acceptance Code Bit 4 C1IDAR6.AC3 3 Acceptance Code Bit 3 C1IDAR6.AC2 2 Acceptance Code Bit 2 C1IDAR6.AC1 1 Acceptance Code Bit 1 C1IDAR6.AC0 0 Acceptance Code Bit 0 C1IDAR7 0x031B msCAN12 Identifier Acceptance Register 7 C1IDAR7.AC7 7 Acceptance Code Bit 7 C1IDAR7.AC6 6 Acceptance Code Bit 6 C1IDAR7.AC5 5 Acceptance Code Bit 5 C1IDAR7.AC4 4 Acceptance Code Bit 4 C1IDAR7.AC3 3 Acceptance Code Bit 3 C1IDAR7.AC2 2 Acceptance Code Bit 2 C1IDAR7.AC1 1 Acceptance Code Bit 1 C1IDAR7.AC0 0 Acceptance Code Bit 0 C1IDMR4 0x031C msCAN12 Identifier Mask Register 4 C1IDMR4.AM7 7 Acceptance Mask Bit 7 C1IDMR4.AM6 6 Acceptance Mask Bit 6 C1IDMR4.AM5 5 Acceptance Mask Bit 5 C1IDMR4.AM4 4 Acceptance Mask Bit 4 C1IDMR4.AM3 3 Acceptance Mask Bit 3 C1IDMR4.AM2 2 Acceptance Mask Bit 2 C1IDMR4.AM1 1 Acceptance Mask Bit 1 C1IDMR4.AM0 0 Acceptance Mask Bit 0 C1IDMR5 0x031D msCAN12 Identifier Mask Register 5 C1IDMR5.AM7 7 Acceptance Mask Bit 7 C1IDMR5.AM6 6 Acceptance Mask Bit 6 C1IDMR5.AM5 5 Acceptance Mask Bit 5 C1IDMR5.AM4 4 Acceptance Mask Bit 4 C1IDMR5.AM3 3 Acceptance Mask Bit 3 C1IDMR5.AM2 2 Acceptance Mask Bit 2 C1IDMR5.AM1 1 Acceptance Mask Bit 1 C1IDMR5.AM0 0 Acceptance Mask Bit 0 C1IDMR6 0x031E msCAN12 Identifier Mask Register 6 C1IDMR6.AM7 7 Acceptance Mask Bit 7 C1IDMR6.AM6 6 Acceptance Mask Bit 6 C1IDMR6.AM5 5 Acceptance Mask Bit 5 C1IDMR6.AM4 4 Acceptance Mask Bit 4 C1IDMR6.AM3 3 Acceptance Mask Bit 3 C1IDMR6.AM2 2 Acceptance Mask Bit 2 C1IDMR6.AM1 1 Acceptance Mask Bit 1 C1IDMR6.AM0 0 Acceptance Mask Bit 0 C1IDMR7 0x031F msCAN12 Identifier Mask Register 7 C1IDMR7.AM7 7 Acceptance Mask Bit 7 C1IDMR7.AM6 6 Acceptance Mask Bit 6 C1IDMR7.AM5 5 Acceptance Mask Bit 5 C1IDMR7.AM4 4 Acceptance Mask Bit 4 C1IDMR7.AM3 3 Acceptance Mask Bit 3 C1IDMR7.AM2 2 Acceptance Mask Bit 2 C1IDMR7.AM1 1 Acceptance Mask Bit 1 C1IDMR7.AM0 0 Acceptance Mask Bit 0 RESERVED0320 0x0320 RESERVED RESERVED0321 0x0321 RESERVED RESERVED0322 0x0322 RESERVED RESERVED0323 0x0323 RESERVED RESERVED0324 0x0324 RESERVED RESERVED0325 0x0325 RESERVED RESERVED0326 0x0326 RESERVED RESERVED0327 0x0327 RESERVED RESERVED0328 0x0328 RESERVED RESERVED0329 0x0329 RESERVED RESERVED032A 0x032A RESERVED RESERVED032B 0x032B RESERVED RESERVED032C 0x032C RESERVED RESERVED032D 0x032D RESERVED RESERVED032E 0x032E RESERVED RESERVED032F 0x032F RESERVED RESERVED0330 0x0330 RESERVED RESERVED0331 0x0331 RESERVED RESERVED0332 0x0332 RESERVED RESERVED0333 0x0333 RESERVED RESERVED0334 0x0334 RESERVED RESERVED0335 0x0335 RESERVED RESERVED0336 0x0336 RESERVED RESERVED0337 0x0337 RESERVED RESERVED0338 0x0338 RESERVED RESERVED0339 0x0339 RESERVED RESERVED033A 0x033A RESERVED RESERVED033B 0x033B RESERVED RESERVED033C 0x033C RESERVED PCTLCAN1 0x033D msCAN12 Port CAN Control Register PCTLCAN1.PUPCAN 1 Pull-Up Enable Port CAN PCTLCAN1.RDPCAN 0 Reduced Drive Port CAN PORTCAN1 0x033E msCAN12 Port CAN Data Register PORTCAN1.PCAN7 7 Port CAN Data Bit 7 PORTCAN1.PCAN6 6 Port CAN Data Bit 6 PORTCAN1.PCAN5 5 Port CAN Data Bit 5 PORTCAN1.PCAN4 4 Port CAN Data Bit 4 PORTCAN1.PCAN3 3 Port CAN Data Bit 3 PORTCAN1.PCAN2 2 Port CAN Data Bit 2 PORTCAN1.TxCAN 1 PORTCAN1.RxCAN 0 DDRCAN1 0x033F msCAN12 Port CAN Data Direction Register DDRCAN1.DDCAN7 7 DDRCAN1.DDCAN6 6 DDRCAN1.DDCAN5 5 DDRCAN1.DDCAN4 4 DDRCAN1.DDCAN3 3 DDRCAN1.DDCAN2 2 .68HC912DT128A ; http://e-www.motorola.com/brdata/PDFDB/docs/MC68HC912DT128A.pdf ; 68HC912DG_DT128A.pdf ; MEMORY MAP area DATA FSR_0 0x0000:0x0140 area DATA RxFG0 0x0140:0x0150 FOREGROUND RECEIVE BUFFER 0 area DATA Tx00 0x0150:0x0160 TRANSMIT BUFFER 00 area DATA Tx01 0x0160:0x0170 TRANSMIT BUFFER 01 area DATA Tx02 0x0170:0x0180 TRANSMIT BUFFER 02 area BSS RESERVED 0x0180:0x01E2 area DATA FSR_1 0x01E2:0x0240 area DATA RxFG2 0x0240:0x0250 FOREGROUND RECEIVE BUFFER 2 area DATA Tx20 0x0250:0x0260 TRANSMIT BUFFER 20 area DATA Tx21 0x0260:0x0270 TRANSMIT BUFFER 21 area DATA Tx22 0x0270:0x0280 TRANSMIT BUFFER 22 area BSS RESERVED 0x0280:0x0300 area DATA FSR_2 0x0300:0x0340 area DATA RxFG1 0x0340:0x0350 FOREGROUND RECEIVE BUFFER 1 area DATA Tx10 0x0350:0x0360 TRANSMIT BUFFER 10 area DATA Tx11 0x0360:0x0370 TRANSMIT BUFFER 11 area DATA Tx12 0x0370:0x0380 TRANSMIT BUFFER 12 area BSS RESERVED 0x0380:0x0800 area DATA EEPROM 0x0800:0x1000 area BSS RESERVED 0x1000:0x2000 area DATA RAM 0x2000:0x4000 area DATA FLASH_EEPROM_1 0x4000:0x8000 16K Fixed Flash EEPROM area DATA FLASH_EEPROM_2 0x8000:0xA000 16K Page Window Eight 16K Flash EEPROM pages area DATA PROT_BOOT_1 0xA000:0xC000 Protected BOOT at odd programing pages area DATA FLASH_EEPROM_3 0xC000:0xE000 16K Fixed Flash EEPROM area DATA PROT_BOOT_2 0xE000:0xFF00 Protected BOOT area DATA USER_VEC 0xFF00:0x10000 ; Interrupt and reset vector assignments interrupt __RESET 0xFFFE Reset interrupt _COPCTL 0xFFFC Clock monitor fail reset interrupt COP_F_R 0xFFFA COP failure reset interrupt UIT 0xFFF8 Unimplemented instruction trap interrupt SWI 0xFFF6 SWI interrupt XIRQ 0xFFF4 XIRQ interrupt INTCR_IRQEN 0xFFF2 IRQ interrupt RTICTL_RTIE 0xFFF0 Real time interrupt interrupt TMSK1_C0I 0xFFEE Timer channel 0 interrupt TMSK1_C1I 0xFFEC Timer channel 1 interrupt TMSK1_C2I 0xFFEA Timer channel 2 interrupt TMSK1_C3I 0xFFE8 Timer channel 3 interrupt TMSK1_C4I 0xFFE6 Timer channel 4 interrupt TMSK1_C5I 0xFFE4 Timer channel 5 interrupt TMSK1_C6I 0xFFE2 Timer channel 6 interrupt TMSK1_C7I 0xFFE0 Timer channel 7 interrupt TMSK2_TOI 0xFFDE Timer overflow interrupt PACTL_PAOVI 0xFFDC Pulse accumulator overflow interrupt PACTL_PAI 0xFFDA Pulse accumulator input edge interrupt SP0CR1_SPIE 0xFFD8 SPI serial transfer complete interrupt _SC0CR2 0xFFD6 SCI 0 interrupt _SC1CR2 0xFFD4 SCI 1 interrupt ATDxCTL2_ASCIE 0xFFD2 ATD0 or ATD1 interrupt C0RIER_WUPIE 0xFFD0 MSCAN 0 wake-up interrupt KWIEJ_KWIEH 0xFFCE Key wake-up J or H interrupt MCCTL_MCZI 0xFFCC Modulus down counter underflow interrupt PBCTL_PBOVI 0xFFCA Pulse Accumulator B Overflow interrupt C0RIER 0xFFC8 MSCAN 0 errors interrupt C0RIER_RXFIE 0xFFC6 MSCAN 0 receive interrupt C0TCR_TXEIE 0xFFC4 MSCAN 0 transmit interrupt PLLCR_LOCKIE_LHIE 0xFFC2 CGM lock and limp home interrupt IBCR_IBIE 0xFFC0 IIC Bus interrupt C1RIER_WUPIE 0xFFBE MSCAN 1 wake-up interrupt C1RIER 0xFFBC MSCAN 1 errors interrupt C1RIER_RXFIE 0xFFBA MSCAN 1 receive interrupt C1TCR_TXEIE 0xFFB8 MSCAN 1 transmit interrupt C2RIER_WUPIE 0xFFB6 MSCAN 2 wake-up interrupt C2RIER 0xFFB4 MSCAN 2 errors interrupt C2RIER_RXFIE 0xFFB2 MSCAN 2 receive interrupt C2TCR_TXEIE 0xFFB0 MSCAN 2 transmit ; INPUT/ OUTPUT PORTS PORTA 0x0000 Port A Data Register PORTA.PA7 7 Port A Data Bit 7 PORTA.PA6 6 Port A Data Bit 6 PORTA.PA5 5 Port A Data Bit 5 PORTA.PA4 4 Port A Data Bit 4 PORTA.PA3 3 Port A Data Bit 3 PORTA.PA2 2 Port A Data Bit 2 PORTA.PA1 1 Port A Data Bit 1 PORTA.PA0 0 Port A Data Bit 0 PORTB 0x0001 Port B Data Register PORTB.PB7 7 Port B Data Bit 7 PORTB.PB6 6 Port B Data Bit 6 PORTB.PB5 5 Port B Data Bit 5 PORTB.PB4 4 Port B Data Bit 4 PORTB.PB3 3 Port B Data Bit 3 PORTB.PB2 2 Port B Data Bit 2 PORTB.PB1 1 Port B Data Bit 1 PORTB.PB0 0 Port B Data Bit 0 DDRA 0x0002 Port A Data Direction Register DDRA.DDA7 7 Port A Data Direction Bit 7 DDRA.DDA6 6 Port A Data Direction Bit 6 DDRA.DDA5 5 Port A Data Direction Bit 5 DDRA.DDA4 4 Port A Data Direction Bit 4 DDRA.DDA3 3 Port A Data Direction Bit 3 DDRA.DDA2 2 Port A Data Direction Bit 2 DDRA.DDA1 1 Port A Data Direction Bit 1 DDRA.DDA0 0 Port A Data Direction Bit 0 DDRB 0x0003 Port B Data Direction Register DDRB.DDB7 7 Port B Data Direction Bit 7 DDRB.DDB6 6 Port B Data Direction Bit 6 DDRB.DDB5 5 Port B Data Direction Bit 5 DDRB.DDB4 4 Port B Data Direction Bit 4 DDRB.DDB3 3 Port B Data Direction Bit 3 DDRB.DDB2 2 Port B Data Direction Bit 2 DDRB.DDB1 1 Port B Data Direction Bit 1 DDRB.DDB0 0 Port B Data Direction Bit 0 RESERVED0004 0x0004 RESERVED RESERVED0005 0x0005 RESERVED RESERVED0006 0x0006 RESERVED RESERVED0007 0x0007 RESERVED PORTE 0x0008 Port E Data Register PORTE.PE7 7 Port E Data Bit 7 PORTE.PE6 6 Port E Data Bit 6 PORTE.PE5 5 Port E Data Bit 5 PORTE.PE4 4 Port E Data Bit 4 PORTE.PE3 3 Port E Data Bit 3 PORTE.PE2 2 Port E Data Bit 2 PORTE.PE1 1 Port E Data Bit 1 PORTE.PE0 0 Port E Data Bit 0 DDRE 0x0009 Port E Data Direction Register DDRE.DDE7 7 Port E Data Direction Bit 7 DDRE.DDE6 6 Port E Data Direction Bit 6 DDRE.DDE5 5 Port E Data Direction Bit 5 DDRE.DDE4 4 Port E Data Direction Bit 4 DDRE.DDE3 3 Port E Data Direction Bit 3 DDRE.DDE2 2 Port E Data Direction Bit 2 PEAR 0x000A Port E Assignment Register PEAR.NDBE 7 No Data Bus Enable PEAR.CGMTE 6 Clock Generator Module Testing Enable PEAR.PIPOE 5 Pipe Status Signal Output Enable PEAR.NECLK 4 No External E Clock PEAR.LSTRE 3 Low Strobe (LSTRB) Enable PEAR.RDWE 2 Read/Write Enable PEAR.CALE 1 Calibration Reference Enable PEAR.DBENE 0 DBE or Inverted E Clock on PE7 MODE 0x000B Mode Register MODE.SMODN 7 Mode Select Special MODE.MODB 6 Mode Select B MODE.MODA 5 Mode Select A MODE.ESTR 4 E Clock Stretch Enable MODE.IVIS 3 Internal Visibility MODE.EBSWAI 2 External Bus Module Stop in Wait Control MODE.EMK 1 Emulate Port K MODE.EME 0 PUCR 0x000C Pull-Up Control Register PUCR.PUPK 7 Pull-Up Port K Enable PUCR.PUPJ 6 Pull-Up or Pull-Down Port J Enable PUCR.PUPH 5 Pull-Up or Pull-Down Port H Enable PUCR.PUPE 4 Pull-Up Port E Enable PUCR.PUPB 1 Pull-Up Port B Enable PUCR.PUPA 0 Pull-Up Port A Enable RDRIV 0x000D Reduced Drive of I/O Lines RDRIV.RDPK 7 Reduced Drive of Port K RDRIV.RDPJ 6 Reduced Drive of Port J RDRIV.RDPH 5 Reduced Drive of Port H RDRIV.RDPE 4 Reduced Drive of Port E RDRIV.RDPB 1 Reduced Drive of Port B RDRIV.RDPA 0 Reduced Drive of Port A RESERVED000E 0x000E RESERVED RESERVED000F 0x000F RESERVED INITRM 0x0010 Initialization of Internal RAM Position Register INITRM.RAM15 7 Internal RAM map position 15 INITRM.RAM14 6 Internal RAM map position 14 INITRM.RAM13 5 Internal RAM map position 13 INITRG 0x0011 Initialization of Internal Register Position Register INITRG.REG15 7 Internal register map position 15 INITRG.REG14 6 Internal register map position 14 INITRG.REG13 5 Internal register map position 13 INITRG.REG12 4 Internal register map position 12 INITRG.REG11 3 Internal register map position 11 INITEE 0x0012 Initialization of Internal EEPROM Position Register INITEE.EE15 7 Internal EEPROM map position 15 INITEE.EE14 6 Internal EEPROM map position 14 INITEE.EE13 5 Internal EEPROM map position 13 INITEE.EE12 4 Internal EEPROM map position 12 INITEE.EEON 0 internal EEPROM On (Enabled) MISC 0x0013 Miscellaneous Mapping Control Register MISC.ROMTST 7 FLASH EEPROM Test mode MISC.NDRF 6 Narrow Data Bus for Register-Following Map Space MISC.RFSTR1 5 Register Following Stretch 1 MISC.RFSTR0 4 Register Following Stretch 0 MISC.EXSTR1 3 External Access Stretch 1 MISC.EXSTR0 2 External Access Stretch 0 MISC.ROMHM 1 FLASH EEPROM only in second Half of Map MISC.ROMON 0 Enable FLASH EEPROM RTICTL 0x0014 Real-Time Interrupt Control Register RTICTL.RTIE 7 Real Time Interrupt Enable RTICTL.RSWAI 6 RTI and COP Stop While in Wait RTICTL.RSBCK 5 RTI and COP Stop While in Background Debug Mode RTICTL.RTBYP 3 Real Time Interrupt Divider Chain Bypass RTICTL.RTR2 2 Real-Time Interrupt Rate Select 2 RTICTL.RTR1 1 Real-Time Interrupt Rate Select 1 RTICTL.RTR0 0 Real-Time Interrupt Rate Select 0 RTIFLG 0x0015 Real Time Interrupt Flag Register RTIFLG.RTIF 7 Real Time Interrupt Flag COPCTL 0x0016 COP Control Register COPCTL.CME 7 Clock Monitor Enable COPCTL.FCME 6 Force Clock Monitor Enable COPCTL.FCMCOP 5 Force Clock Monitor Reset or COP Watchdog Reset COPCTL.WCOP 4 Window COP mode COPCTL.DISR 3 Disable Resets from COP Watchdog and Clock Monitor COPCTL.CR2 2 COP Watchdog Timer Rate select bit 2 COPCTL.CR1 1 COP Watchdog Timer Rate select bit 1 COPCTL.CR0 0 COP Watchdog Timer Rate select bit 0 COPRST 0x0017 Arm/Reset COP Timer Register ITST0 0x0018 Interrupt Test Register 0 ITST0.ITE6 7 ITST0.ITE8 6 ITST0.ITEA 5 ITST0.ITEC 4 ITST0.ITEE 3 ITST0.ITF0 2 ITST0.ITF2 1 ITST0.ITF4 0 ITST1 0x0019 Interrupt Test Register 1 ITST1.ITD6 7 ITST1.ITD8 6 ITST1.ITDA 5 ITST1.ITDC 4 ITST1.ITDE 3 ITST1.ITE0 2 ITST1.ITE2 1 ITST1.ITE4 0 ITST2 0x001A Interrupt Test Register 2 ITST2.ITC6 7 ITST2.ITC8 6 ITST2.ITCA 5 ITST2.ITCC 4 ITST2.ITCE 3 ITST2.ITD0 2 ITST2.ITD2 1 ITST2.ITD4 0 ITST3 0x001B Interrupt Test Register 3 ITST3.ITB6 7 ITST3.ITB8 6 ITST3.ITBA 5 ITST3.ITBC 4 ITST3.ITBE 3 ITST3.ITC0 2 ITST3.ITC2 1 ITST3.ITC4 0 RESERVED001C 0x001C RESERVED RESERVED001D 0x001D RESERVED INTCR 0x001E Interrupt Control Register INTCR.IRQE 7 IRQ Select Edge Sensitive Only INTCR.IRQEN 6 External IRQ Enable INTCR.DLY 5 Enable Oscillator Start-up Delay on Exit from STOP HPRIO 0x001F Highest Priority I Interrupt HPRIO.PSEL6 6 HPRIO.PSEL5 5 HPRIO.PSEL4 4 HPRIO.PSEL3 3 HPRIO.PSEL2 2 HPRIO.PSEL1 1 BRKCT0 0x0020 Breakpoint Control Register 0 BRKCT0.BKEN1 7 Breakpoint Mode Enable 1 BRKCT0.BKEN0 6 Breakpoint Mode Enable 0 BRKCT0.BKPM 5 Break on Program Addresses BRKCT0.BK1ALE 3 Breakpoint 1 Range Control BRKCT0.BK0ALE 2 Breakpoint 0 Range Control BRKCT1 0x0021 Breakpoint Control Register 1 BRKCT1.BKDBE 6 Enable Data Bus BRKCT1.BKMBH 5 Breakpoint Mask High BRKCT1.BKMBL 4 Breakpoint Mask Low BRKCT1.BK1RWE 3 R/W Compare Enable BRKCT1.BK1RW 2 R/W Compare Value BRKCT1.BK0RWE 1 R/W Compare Enable BRKCT1.BK0RW 0 R/W Compare Value BRKAH 0x0022 Breakpoint Address Register, High Byte BRKAL 0x0023 Breakpoint Address Register, Low Byte BRKDH 0x0024 Breakpoint Data Register, High Byte BRKDL 0x0025 Breakpoint Data Register, Low Byte RESERVED0026 0x0026 RESERVED RESERVED0027 0x0027 RESERVED PORTJ 0x0028 Port J Data Register PORTJ.PJ7 7 Port J Data Bit 7 PORTJ.PJ6 6 Port J Data Bit 6 PORTJ.PJ5 5 Port J Data Bit 5 PORTJ.PJ4 4 Port J Data Bit 4 PORTJ.PJ3 3 Port J Data Bit 3 PORTJ.PJ2 2 Port J Data Bit 2 PORTJ.PJ1 1 Port J Data Bit 1 PORTJ.PJ0 0 Port J Data Bit 0 PORTH 0x0029 Port H Data Register PORTH.PH7 7 Port H Data Bit 7 PORTH.PH6 6 Port H Data Bit 6 PORTH.PH5 5 Port H Data Bit 5 PORTH.PH4 4 Port H Data Bit 4 PORTH.PH3 3 Port H Data Bit 3 PORTH.PH2 2 Port H Data Bit 2 PORTH.PH1 1 Port H Data Bit 1 PORTH.PH0 0 Port H Data Bit 0 DDRJ 0x002A Port J Data Direction Register DDRJ.DDRJ7 7 Data Direction Port J Bit 7 DDRJ.DDRJ6 6 Data Direction Port J Bit 6 DDRJ.DDRJ5 5 Data Direction Port J Bit 5 DDRJ.DDRJ4 4 Data Direction Port J Bit 4 DDRJ.DDRJ3 3 Data Direction Port J Bit 3 DDRJ.DDRJ2 2 Data Direction Port J Bit 2 DDRJ.DDRJ1 1 Data Direction Port J Bit 1 DDRJ.DDRJ0 0 Data Direction Port J Bit 0 DDRH 0x002B Port J Data Direction Register DDRH.DDRH7 7 Data Direction Port H Bit 7 DDRH.DDRH6 6 Data Direction Port H Bit 6 DDRH.DDRH5 5 Data Direction Port H Bit 5 DDRH.DDRH4 4 Data Direction Port H Bit 4 DDRH.DDRH3 3 Data Direction Port H Bit 3 DDRH.DDRH2 2 Data Direction Port H Bit 2 DDRH.DDRH1 1 Data Direction Port H Bit 1 DDRH.DDRH0 0 Data Direction Port H Bit 0 KWIEJ 0x002C Key Wake-up Port J Interrupt Enable Register KWIEJ.KWIEJ7 7 Key Wake-up Port J Interrupt Enable 7 KWIEJ.KWIEJ6 6 Key Wake-up Port J Interrupt Enable 6 KWIEJ.KWIEJ5 5 Key Wake-up Port J Interrupt Enable 5 KWIEJ.KWIEJ4 4 Key Wake-up Port J Interrupt Enable 4 KWIEJ.KWIEJ3 3 Key Wake-up Port J Interrupt Enable 3 KWIEJ.KWIEJ2 2 Key Wake-up Port J Interrupt Enable 2 KWIEJ.KWIEJ1 1 Key Wake-up Port J Interrupt Enable 1 KWIEJ.KWIEJ0 0 Key Wake-up Port J Interrupt Enable 0 KWIEH 0x002D Key Wake-up Port H Interrupt Enable Register KWIEH.KWIEH7 7 Key Wake-up Port H Interrupt Enable 7 KWIEH.KWIEH6 6 Key Wake-up Port H Interrupt Enable 6 KWIEH.KWIEH5 5 Key Wake-up Port H Interrupt Enable 5 KWIEH.KWIEH4 4 Key Wake-up Port H Interrupt Enable 4 KWIEH.KWIEH3 3 Key Wake-up Port H Interrupt Enable 3 KWIEH.KWIEH2 2 Key Wake-up Port H Interrupt Enable 2 KWIEH.KWIEH1 1 Key Wake-up Port H Interrupt Enable 1 KWIEH.KWIEH0 0 Key Wake-up Port H Interrupt Enable 0 KWIFJ 0x002E Key Wake-up Port J Flag Register KWIFJ.KWIFJ7 7 Key Wake-up Port J Flag 7 KWIFJ.KWIFJ6 6 Key Wake-up Port J Flag 6 KWIFJ.KWIFJ5 5 Key Wake-up Port J Flag 5 KWIFJ.KWIFJ4 4 Key Wake-up Port J Flag 4 KWIFJ.KWIFJ3 3 Key Wake-up Port J Flag 3 KWIFJ.KWIFJ2 2 Key Wake-up Port J Flag 2 KWIFJ.KWIFJ1 1 Key Wake-up Port J Flag 1 KWIFJ.KWIFJ0 0 Key Wake-up Port J Flag 0 KWIFH 0x002F Key Wake-up Port H Flag Register KWIFH.KWIFH7 7 Key Wake-up Port H Flag 7 KWIFH.KWIFH6 6 Key Wake-up Port H Flag 6 KWIFH.KWIFH5 5 Key Wake-up Port H Flag 5 KWIFH.KWIFH4 4 Key Wake-up Port H Flag 4 KWIFH.KWIFH3 3 Key Wake-up Port H Flag 3 KWIFH.KWIFH2 2 Key Wake-up Port H Flag 2 KWIFH.KWIFH1 1 Key Wake-up Port H Flag 1 KWIFH.KWIFH0 0 Key Wake-up Port H Flag 0 KWPJ 0x0030 Key Wake-up Port J Polarity Register KWPJ.KWPJ7 7 Key Wake-up Port J Polarity Select 7 KWPJ.KWPJ6 6 Key Wake-up Port J Polarity Select 6 KWPJ.KWPJ5 5 Key Wake-up Port J Polarity Select 5 KWPJ.KWPJ4 4 Key Wake-up Port J Polarity Select 4 KWPJ.KWPJ3 3 Key Wake-up Port J Polarity Select 3 KWPJ.KWPJ2 2 Key Wake-up Port J Polarity Select 2 KWPJ.KWPJ1 1 Key Wake-up Port J Polarity Select 1 KWPJ.KWPJ0 0 Key Wake-up Port J Polarity Select 0 KWPH 0x0031 Key Wake-up Port H Polarity Register KWPH.KWPH7 7 Key Wake-up Port H Polarity Select 7 KWPH.KWPH6 6 Key Wake-up Port H Polarity Select 6 KWPH.KWPH5 5 Key Wake-up Port H Polarity Select 5 KWPH.KWPH4 4 Key Wake-up Port H Polarity Select 4 KWPH.KWPH3 3 Key Wake-up Port H Polarity Select 3 KWPH.KWPH2 2 Key Wake-up Port H Polarity Select 2 KWPH.KWPH1 1 Key Wake-up Port H Polarity Select 1 KWPH.KWPH0 0 Key Wake-up Port H Polarity Select 0 RESERVED0032 0x0032 RESERVED RESERVED0033 0x0033 RESERVED RESERVED0034 0x0034 RESERVED RESERVED0035 0x0035 RESERVED RESERVED0036 0x0036 RESERVED RESERVED0037 0x0037 RESERVED SYNR 0x0038 Synthesizer Register SYNR.SYN5 5 SYNR.SYN4 4 SYNR.SYN3 3 SYNR.SYN2 2 SYNR.SYN1 1 SYNR.SYN0 0 REFDV 0x0039 Reference Divider Register REFDV.REFDV2 2 REFDV.REFDV1 1 REFDV.REFDV0 0 CGTFLG 0x003A Clock Generator Test Register CGTFLG.TSTOUT7 7 CGTFLG.TSTOUT6 6 CGTFLG.TSTOUT5 5 CGTFLG.TSTOUT4 4 CGTFLG.TSTOUT3 3 CGTFLG.TSTOUT2 2 CGTFLG.TSTOUT1 1 CGTFLG.TSTOUT0 0 PLLFLG 0x003B PLL Flags PLLFLG.LOCKIF 7 PLL Lock Interrupt Flag PLLFLG.LOCK 6 Locked Phase Lock Loop Circuit PLLFLG.LHIF 1 Limp-Home Interrupt Flag PLLFLG.LHOME 0 Limp-Home Mode Status PLLCR 0x003C PLL Control Register PLLCR.LOCKIE 7 PLL LOCK Interrupt Enable PLLCR.PLLON 6 Phase Lock Loop On PLLCR.AUTO 5 Automatic Bandwidth Control PLLCR.ACQ 4 Not in Acquisition PLLCR.PSTP 2 Pseudo-STOP Enable PLLCR.LHIE 1 Limp-Home Interrupt Enable PLLCR.NOLHM 0 No Limp-Home Mode CLKSEL 0x003D Clock Generator Clock select Register CLKSEL.BCSP 6 Bus Clock Select PLL CLKSEL.BCSS 5 Bus Clock Select Slow CLKSEL.MCS 2 Module Clock Select SLOW 0x003E Slow mode Divider Register SLOW.SLDV5 5 SLOW.SLDV4 4 SLOW.SLDV3 3 SLOW.SLDV2 2 SLOW.SLDV1 1 SLOW.SLDV0 0 CGTCTL 0x003F CGTCTL CGTCTL.OPNLE 7 CGTCTL.TRK 6 CGTCTL.TSTCLKE 5 CGTCTL.TST4 4 CGTCTL.TST3 3 CGTCTL.TST2 2 CGTCTL.TST1 1 CGTCTL.TST0 0 PWCLK 0x0040 PWM Clocks and Concatenate PWCLK.CON23 7 Concatenate PWM Channels 2 and 3 PWCLK.CON01 6 Concatenate PWM Channels 0 and 1 PWCLK.PCKA2 5 Prescaler for Clock A 2 PWCLK.PCKA1 4 Prescaler for Clock A 1 PWCLK.PCKA0 3 Prescaler for Clock A 0 PWCLK.PCKB2 2 Prescaler for Clock B 2 PWCLK.PCKB1 1 Prescaler for Clock B 1 PWCLK.PCKB0 0 Prescaler for Clock B 0 PWPOL 0x0041 PWM Clock Select and Polarity PWPOL.PCLK3 7 PWM Channel 3 Clock Select PWPOL.PCLK2 6 PWM Channel 2 Clock Select PWPOL.PCLK1 5 PWM Channel 1 Clock Select PWPOL.PCLK0 4 PWM Channel 0 Clock Select PWPOL.PPOL3 3 PWM Channel 3 Polarity PWPOL.PPOL2 2 PWM Channel 2 Polarity PWPOL.PPOL1 1 PWM Channel 1 Polarity PWPOL.PPOL0 0 PWM Channel 0 Polarity PWEN 0x0042 PWM Enable PWEN.PWEN3 3 PWM Channel 3 Enable PWEN.PWEN2 2 PWM Channel 2 Enable PWEN.PWEN1 1 PWM Channel 1 Enable PWEN.PWEN0 0 PWM Channel 0 Enable PWPRES 0x0043 PWM Prescale Counter PWSCAL0 0x0044 PWM Scale Register 0 PWSCNT0 0x0045 PWM Scale Counter 0 Value PWSCAL1 0x0046 PWM Scale Register 1 PWSCNT1 0x0047 PWM Scale Counter 1 Value PWCNT0 0x0048 PWM Channel Counter 0 PWCNT1 0x0049 PWM Channel Counter 1 PWCNT2 0x004A PWM Channel Counter 2 PWCNT3 0x004B PWM Channel Counter 3 PWPER0 0x004C PWM Channel Period Register 0 PWPER1 0x004D PWM Channel Period Register 1 PWPER2 0x004E PWM Channel Period Register 2 PWPER3 0x004F PWM Channel Period Register 3 PWDTY0 0x0050 PWM Channel Duty Register 0 PWDTY1 0x0051 PWM Channel Duty Register 1 PWDTY2 0x0052 PWM Channel Duty Register 2 PWDTY3 0x0053 PWM Channel Duty Register 3 PWCTL 0x0054 PWM Control Register PWCTL.PSWAI 4 PWM Halts while in Wait Mode PWCTL.CENTR 3 Center-Aligned Output Mode PWCTL.RDPP 2 Reduced Drive of Port P PWCTL.PUPP 1 Pull-Up Port P Enable PWCTL.PSBCK 0 PWM Stops while in Background Mode PWTST 0x0055 PWM Special Mode Register ("Test") PWTST.DISCR 7 Disable Reset of Channel Counter on Write to Channel Counter PWTST.DISCP 6 Disable Compare Count Period PWTST.DISCAL 5 Disable Load of Scale-Counters on Write to the Associated Scale-Registers PORTP 0x0056 Port P Data Register PORTP.PP7 7 Port P Data Bit 7 PORTP.PP6 6 Port P Data Bit 6 PORTP.PP5 5 Port P Data Bit 5 PORTP.PP4 4 Port P Data Bit 4 PORTP.PP3 3 Port P Data Bit 3 PORTP.PP2 2 Port P Data Bit 2 PORTP.PP1 1 Port P Data Bit 1 PORTP.PP0 0 Port P Data Bit 0 DDRP 0x0057 Port P Data Direction Register DDRP.DDP7 7 Port P Data Direction Bit 7 DDRP.DDP6 6 Port P Data Direction Bit 6 DDRP.DDP5 5 Port P Data Direction Bit 5 DDRP.DDP4 4 Port P Data Direction Bit 4 DDRP.DDP3 3 Port P Data Direction Bit 3 DDRP.DDP2 2 Port P Data Direction Bit 2 DDRP.DDP1 1 Port P Data Direction Bit 1 DDRP.DDP0 0 Port P Data Direction Bit 0 RESERVED0058 0x0058 RESERVED RESERVED0059 0x0059 RESERVED RESERVED005A 0x005A RESERVED RESERVED005B 0x005B RESERVED RESERVED005C 0x005C RESERVED RESERVED005D 0x005D RESERVED RESERVED005E 0x005E RESERVED RESERVED005F 0x005F RESERVED RESERVED0060 0x0060 RESERVED RESERVED0061 0x0061 RESERVED ATD0CTL2 0x0062 ATD0 Control Register 2 ATD0CTL2.ADPU 7 ATD Disable ATD0CTL2.AFFC 6 ATD Fast Flag Clear All ATD0CTL2.ASWAI 5 ATD Wait Mode ATD0CTL2.DJM 4 Result Register Data Justification Mode ATD0CTL2.DSGN 3 Signed/Unsigned Result Data Mode ATD0CTL2.ASCIE 1 ATD Sequence Complete Interrupt Enable ATD0CTL2.ASCIF 0 ATD Sequence Complete Interrupt Flag ATD0CTL3 0x0063 ATD0 Control Register 3 ATD0CTL3.S1C 3 Conversion Sequence Length (Least Significant Bit) ATD0CTL3.FIFO 2 Result Register FIFO Mode ATD0CTL3.FRZ1 1 Background Debug (Freeze) Enable 1 ATD0CTL3.FRZ0 0 Background Debug (Freeze) Enable 0 ATD0CTL4 0x0064 ATD0 Control Register 4 ATD0CTL4.RES10 7 10 bit Mode ATD0CTL4.SMP1 6 Select Sample Time 1 ATD0CTL4.SMP0 5 Select Sample Time 0 ATD0CTL4.PRS4 4 Select Divide-By Factor for ATD P-Clock Prescaler 4 ATD0CTL4.PRS3 3 Select Divide-By Factor for ATD P-Clock Prescaler 3 ATD0CTL4.PRS2 2 Select Divide-By Factor for ATD P-Clock Prescaler 2 ATD0CTL4.PRS1 1 Select Divide-By Factor for ATD P-Clock Prescaler 1 ATD0CTL4.PRS0 0 Select Divide-By Factor for ATD P-Clock Prescaler 0 ATD0CTL5 0x0065 ATD0 Control Register 5 ATD0CTL5.S8CM 6 Select 8 Channel Mode ATD0CTL5.SCAN 5 Enable Continuous Channel Scan ATD0CTL5.MULT 4 Enable Multichannel Conversion ATD0CTL5.CD 3 Channel Select for Conversion D ATD0CTL5.CC 2 Channel Select for Conversion C ATD0CTL5.CB 1 Channel Select for Conversion B ATD0CTL5.CA 0 Channel Select for Conversion A ATD0STAT0 0x0066 ATD0 Status Register ATD0STAT0.SCF 7 Sequence Complete Flag ATD0STAT0.CC2 2 Conversion Counter for Current Sequence of Four or Eight Conversions 2 ATD0STAT0.CC1 1 Conversion Counter for Current Sequence of Four or Eight Conversions 1 ATD0STAT0.CC0 0 Conversion Counter for Current Sequence of Four or Eight Conversions 0 ATD0STAT1 0x0067 ATD0 Status Register ATD0STAT1.CCF7 7 Conversion Complete Flag 7 ATD0STAT1.CCF6 6 Conversion Complete Flag 6 ATD0STAT1.CCF5 5 Conversion Complete Flag 5 ATD0STAT1.CCF4 4 Conversion Complete Flag 4 ATD0STAT1.CCF3 3 Conversion Complete Flag 3 ATD0STAT1.CCF2 2 Conversion Complete Flag 2 ATD0STAT1.CCF1 1 Conversion Complete Flag 1 ATD0STAT1.CCF0 0 Conversion Complete Flag 0 ATD0TESTH 0x0068 ATD0 Test Register ATD0TESTH.SAR9 7 SAR Data 9 ATD0TESTH.SAR8 6 SAR Data 8 ATD0TESTH.SAR7 5 SAR Data 7 ATD0TESTH.SAR6 4 SAR Data 6 ATD0TESTH.SAR5 3 SAR Data 5 ATD0TESTH.SAR4 2 SAR Data 4 ATD0TESTH.SAR3 1 SAR Data 3 ATD0TESTH.SAR2 0 SAR Data 2 ATD0TESTL 0x0069 ATD0 Test Register ATD0TESTL.SAR1 7 SAR Data 1 ATD0TESTL.SAR0 6 SAR Data 0 ATD0TESTL.RST 5 Module Reset Bit ATD0TESTL.TSTOUT 4 Multiplex Output of TST[3:0] (Factory Use) ATD0TESTL.TST3 3 Test Bit 3 ATD0TESTL.TST2 2 Test Bit 2 ATD0TESTL.TST1 1 Test Bit 1 ATD0TESTL.TST0 0 Test Bit 0 RESERVED006A 0x006A RESERVED RESERVED006B 0x006B RESERVED RESERVED006C 0x006C RESERVED RESERVED006D 0x006D RESERVED RESERVED006E 0x006E RESERVED PORTAD0 0x006F Port AD0 Data Input Register PORTAD0.PAD07 7 Port AD0 Data Input Bit 7 PORTAD0.PAD06 6 Port AD0 Data Input Bit 6 PORTAD0.PAD05 5 Port AD0 Data Input Bit 5 PORTAD0.PAD04 4 Port AD0 Data Input Bit 4 PORTAD0.PAD03 3 Port AD0 Data Input Bit 3 PORTAD0.PAD02 2 Port AD0 Data Input Bit 2 PORTAD0.PAD01 1 Port AD0 Data Input Bit 1 PORTAD0.PAD00 0 Port AD0 Data Input Bit 0 ADR00H 0x0070 A/D Conversion Result Register High 0 ADR00L 0x0071 A/D Conversion Result Register Low 0 ADR01H 0x0072 A/D Conversion Result Register High 1 ADR01L 0x0073 A/D Conversion Result Register Low 1 ADR02H 0x0074 A/D Conversion Result Register High 2 ADR02L 0x0075 A/D Conversion Result Register Low 2 ADR03H 0x0076 A/D Conversion Result Register High 3 ADR03L 0x0077 A/D Conversion Result Register Low 3 ADR04H 0x0078 A/D Conversion Result Register High 4 ADR04L 0x0079 A/D Conversion Result Register Low 4 ADR05H 0x007A A/D Conversion Result Register High 5 ADR05L 0x007B A/D Conversion Result Register Low 5 ADR06H 0x007C A/D Conversion Result Register High 6 ADR06L 0x007D A/D Conversion Result Register Low 6 ADR07H 0x007E A/D Conversion Result Register High 7 ADR07L 0x007F A/D Conversion Result Register Low 7 TIOS 0x0080 Timer Input Capture/Output Compare Select TIOS.IOS7 7 Input Capture or Output Compare Channel Configuration 7 TIOS.IOS6 6 Input Capture or Output Compare Channel Configuration 6 TIOS.IOS5 5 Input Capture or Output Compare Channel Configuration 5 TIOS.IOS4 4 Input Capture or Output Compare Channel Configuration 4 TIOS.IOS3 3 Input Capture or Output Compare Channel Configuration 3 TIOS.IOS2 2 Input Capture or Output Compare Channel Configuration 2 TIOS.IOS1 1 Input Capture or Output Compare Channel Configuration 1 TIOS.IOS0 0 Input Capture or Output Compare Channel Configuration 0 CFORC 0x0081 Timer Compare Force Register CFORC.FOC7 7 Force Output Compare Action for Channel 7 CFORC.FOC6 6 Force Output Compare Action for Channel 6 CFORC.FOC5 5 Force Output Compare Action for Channel 5 CFORC.FOC4 4 Force Output Compare Action for Channel 4 CFORC.FOC3 3 Force Output Compare Action for Channel 3 CFORC.FOC2 2 Force Output Compare Action for Channel 2 CFORC.FOC1 1 Force Output Compare Action for Channel 1 CFORC.FOC0 0 Force Output Compare Action for Channel 0 OC7M 0x0082 Output Compare 7 Mask Register OC7M.OC7M7 7 OC7M.OC7M6 6 OC7M.OC7M5 5 OC7M.OC7M4 4 OC7M.OC7M3 3 OC7M.OC7M2 2 OC7M.OC7M1 1 OC7M.OC7M0 0 OC7D 0x0083 Output Compare 7 Data Register OC7D.OC7D7 7 OC7D.OC7D6 6 OC7D.OC7D5 5 OC7D.OC7D4 4 OC7D.OC7D3 3 OC7D.OC7D2 2 OC7D.OC7D1 1 OC7D.OC7D0 0 TCNTH 0x0084 Timer Count Register High TCNTL 0x0085 Timer Count Register Low TSCR 0x0086 Timer System Control Register TSCR.TEN 7 Timer Enable TSCR.TSWAI 6 Timer Module Stops While in Wait TSCR.TSBCK 5 Timer and Modulus Counter Stop While in Background Mode TSCR.TFFCA 4 Timer Fast Flag Clear All RESERVED0087 0x0087 RESERVED TCTL1 0x0088 Timer Control Register 1 TCTL1.OM7 7 Output Mode 7 TCTL1.OL7 6 Output Level 7 TCTL1.OM6 5 Output Mode 6 TCTL1.OL6 4 Output Level 6 TCTL1.OM5 3 Output Mode 5 TCTL1.OL5 2 Output Level 5 TCTL1.OM4 1 Output Mode 4 TCTL1.OL4 0 Output Level 4 TCTL2 0x0089 Timer Control Register 2 TCTL2.OM3 7 Output Mode 3 TCTL2.OL3 6 Output Level 3 TCTL2.OM2 5 Output Mode 2 TCTL2.OL2 4 Output Level 2 TCTL2.OM1 3 Output Mode 1 TCTL2.OL1 2 Output Level 1 TCTL2.OM0 1 Output Mode 0 TCTL2.OL0 0 Output Level 0 TCTL3 0x008A Timer Control Register 3 TCTL3.EDG7B 7 Input Capture Edge Control 7B TCTL3.EDG7A 6 Input Capture Edge Control 7A TCTL3.EDG6B 5 Input Capture Edge Control 6B TCTL3.EDG6A 4 Input Capture Edge Control 6A TCTL3.EDG5B 3 Input Capture Edge Control 5B TCTL3.EDG5A 2 Input Capture Edge Control 5A TCTL3.EDG4B 1 Input Capture Edge Control 4B TCTL3.EDG4A 0 Input Capture Edge Control 4A TCTL4 0x008B Timer Control Register 4 TCTL4.EDG3B 7 Input Capture Edge Control 3B TCTL4.EDG3A 6 Input Capture Edge Control 3A TCTL4.EDG2B 5 Input Capture Edge Control 2B TCTL4.EDG2A 4 Input Capture Edge Control 2A TCTL4.EDG1B 3 Input Capture Edge Control 1B TCTL4.EDG1A 2 Input Capture Edge Control 1A TCTL4.EDG0B 1 Input Capture Edge Control 0B TCTL4.EDG0A 0 Input Capture Edge Control 0A TMSK1 0x008C Timer Interrupt Mask 1 TMSK1.C7I 7 Input Capture/Output Compare 7 Interrupt Enable TMSK1.C6I 6 Input Capture/Output Compare 6 Interrupt Enable TMSK1.C5I 5 Input Capture/Output Compare 5 Interrupt Enable TMSK1.C4I 4 Input Capture/Output Compare 4 Interrupt Enable TMSK1.C3I 3 Input Capture/Output Compare 3 Interrupt Enable TMSK1.C2I 2 Input Capture/Output Compare 2 Interrupt Enable TMSK1.C1I 1 Input Capture/Output Compare 1 Interrupt Enable TMSK1.C0I 0 Input Capture/Output Compare 0 Interrupt Enable TMSK2 0x008D Timer Interrupt Mask 2 TMSK2.TOI 7 Timer Overflow Interrupt Enable TMSK2.PUPT 5 Timer Port Pull-Up Resistor Enable TMSK2.RDPT 4 Timer Port Drive Reduction TMSK2.TCRE 3 Timer Counter Reset Enable TMSK2.PR2 2 Timer Prescaler Select 2 TMSK2.PR1 1 Timer Prescaler Select 1 TMSK2.PR0 0 Timer Prescaler Select 0 TFLG1 0x008E Main Timer Interrupt Flag 1 TFLG1.C7F 7 Input Capture/Output Compare Channel 7 Flag TFLG1.C6F 6 Input Capture/Output Compare Channel 6 Flag TFLG1.C5F 5 Input Capture/Output Compare Channel 5 Flag TFLG1.C4F 4 Input Capture/Output Compare Channel 4 Flag TFLG1.C3F 3 Input Capture/Output Compare Channel 3 Flag TFLG1.C2F 2 Input Capture/Output Compare Channel 2 Flag TFLG1.C1F 1 Input Capture/Output Compare Channel 1 Flag TFLG1.C0F 0 Input Capture/Output Compare Channel 0 Flag TFLG2 0x008F Main Timer Interrupt Flag 2 TFLG2.TOF 7 Timer Overflow Flag TC0H 0x0090 Timer Input Capture/Output Compare Register 0 High TC0L 0x0091 Timer Input Capture/Output Compare Register 0 Low TC1H 0x0092 Timer Input Capture/Output Compare Register 1 High TC1L 0x0093 Timer Input Capture/Output Compare Register 1 Low TC2H 0x0094 Timer Input Capture/Output Compare Register 2 High TC2L 0x0095 Timer Input Capture/Output Compare Register 2 Low TC3H 0x0096 Timer Input Capture/Output Compare Register 3 High TC3L 0x0097 Timer Input Capture/Output Compare Register 3 Low TC4H 0x0098 Timer Input Capture/Output Compare Register 4 High TC4L 0x0099 Timer Input Capture/Output Compare Register 4 Low TC5H 0x009A Timer Input Capture/Output Compare Register 5 High TC5L 0x009B Timer Input Capture/Output Compare Register 5 Low TC6H 0x009C Timer Input Capture/Output Compare Register 6 High TC6L 0x009D Timer Input Capture/Output Compare Register 6 Low TC7H 0x009E Timer Input Capture/Output Compare Register 7 High TC7L 0x009F Timer Input Capture/Output Compare Register 7 Low PACTL 0x00A0 16-Bit Pulse Accumulator A Control Register PACTL.PAEN 6 Pulse Accumulator A System Enable PACTL.PAMOD 5 Pulse Accumulator Mode PACTL.PEDGE 4 Pulse Accumulator Edge Control PACTL.CLK1 3 Clock Select Bit 1 PACTL.CLK0 2 Clock Select Bit 0 PACTL.PAOVI 1 Pulse Accumulator A Overflow Interrupt enable PACTL.PAI 0 Pulse Accumulator Input Interrupt enable PAFLG 0x00A1 Pulse Accumulator A Flag Register PAFLG.PAOVF 1 Pulse Accumulator A Overflow Flag PAFLG.PAIF 0 Pulse Accumulator Input edge Flag PACN3 0x00A2 Pulse Accumulators Count Register 3 PACN2 0x00A3 Pulse Accumulators Count Register 2 PACN1 0x00A4 Pulse Accumulators Count Register 1 PACN0 0x00A5 Pulse Accumulators Count Register 0 MCCTL 0x00A6 16-Bit Modulus Down-Counter Control Register MCCTL.MCZI 7 Modulus Counter Underflow Interrupt Enable MCCTL.MODMC 6 Modulus Mode Enable MCCTL.RDMCL 5 Read Modulus Down-Counter Load MCCTL.ICLAT 4 Input Capture Force Latch Action MCCTL.FLMC 3 Force Load Register into the Modulus Counter Count Register MCCTL.MCEN 2 Modulus Down-Counter Enable MCCTL.MCPR1 1 Modulus Counter Prescaler select 1 MCCTL.MCPR0 0 Modulus Counter Prescaler select 0 MCFLG 0x00A7 16-Bit Modulus Down-Counter FLAG Register MCFLG.MCZF 7 Modulus Counter Underflow Interrupt Flag MCFLG.POLF3 3 First Input Capture Polarity Status 3 MCFLG.POLF2 2 First Input Capture Polarity Status 2 MCFLG.POLF1 1 First Input Capture Polarity Status 1 MCFLG.POLF0 0 First Input Capture Polarity Status 0 ICPACR 0x00A8 Input Control Pulse Accumulators Control Register ICPACR.PA3EN 3 8-Bit Pulse Accumulator 3 Enable ICPACR.PA2EN 2 8-Bit Pulse Accumulator 2 Enable ICPACR.PA1EN 1 8-Bit Pulse Accumulator 1 Enable ICPACR.PA0EN 0 8-Bit Pulse Accumulator 0 Enable DLYCT 0x00A9 Delay Counter Control Register DLYCT.DLY1 1 Delay Counter Select 1 DLYCT.DLY0 0 Delay Counter Select 0 ICOVW 0x00AA Input Control Overwrite Register ICOVW.NOVW7 7 No Input Capture Overwrite 7 ICOVW.NOVW6 6 No Input Capture Overwrite 6 ICOVW.NOVW5 5 No Input Capture Overwrite 5 ICOVW.NOVW4 4 No Input Capture Overwrite 4 ICOVW.NOVW3 3 No Input Capture Overwrite 3 ICOVW.NOVW2 2 No Input Capture Overwrite 2 ICOVW.NOVW1 1 No Input Capture Overwrite 1 ICOVW.NOVW0 0 No Input Capture Overwrite 0 ICSYS 0x00AB Input Control System Control Register ICSYS.SH37 7 Share Input action of Input Capture Channels 3 and 7 ICSYS.SH26 6 Share Input action of Input Capture Channels 2 and 6 ICSYS.SH15 5 Share Input action of Input Capture Channels 1 and 5 ICSYS.SH04 4 Share Input action of Input Capture Channels 0 and 4 ICSYS.TFMOD 3 Timer Flag-setting Mode ICSYS.PACMX 2 8-Bit Pulse Accumulators Maximum Count ICSYS.BUFEN 1 IC Buffer Enable ICSYS.LATQ 0 Input Control Latch or Queue Mode Enable RESERVED00AC 0x00AC RESERVED TIMTST 0x00AD Timer Test Register TIMTST.TCBYP 1 Main Timer Divider Chain Bypass PORTT 0x00AE Port T Data Register PORTT.PT7 7 Port T Data Bit 7 PORTT.PT6 6 Port T Data Bit 6 PORTT.PT5 5 Port T Data Bit 5 PORTT.PT4 4 Port T Data Bit 4 PORTT.PT3 3 Port T Data Bit 3 PORTT.PT2 2 Port T Data Bit 2 PORTT.PT1 1 Port T Data Bit 1 PORTT.PT0 0 Port T Data Bit 0 DDRT 0x00AF Port T Data Direction Register DDRT.DDT7 7 Port T Data Direction Bit 7 DDRT.DDT6 6 Port T Data Direction Bit 6 DDRT.DDT5 5 Port T Data Direction Bit 5 DDRT.DDT4 4 Port T Data Direction Bit 4 DDRT.DDT3 3 Port T Data Direction Bit 3 DDRT.DDT2 2 Port T Data Direction Bit 2 DDRT.DDT1 1 Port T Data Direction Bit 1 DDRT.DDT0 0 Port T Data Direction Bit 0 PBCTL 0x00B0 16-Bit Pulse Accumulator B Control Register PBCTL.PBEN 6 Pulse Accumulator B System Enable PBCTL.PBOVI 1 Pulse Accumulator B Overflow Interrupt enable PBFLG 0x00B1 Pulse Accumulator B Flag Register PBFLG.PBOVF 1 Pulse Accumulator B Overflow Flag PA3H 0x00B2 8-Bit Pulse Accumulators Holding Register 3 PA2H 0x00B3 8-Bit Pulse Accumulators Holding Register 2 PA1H 0x00B4 8-Bit Pulse Accumulators Holding Register 1 PA0H 0x00B5 8-Bit Pulse Accumulators Holding Register 0 MCCNTH 0x00B6 Modulus Down-Counter Count Register High MCCNTL 0x00B7 Modulus Down-Counter Count Register Low TC0HH 0x00B8 Timer Input Capture Holding Register 0 High TC0HL 0x00B9 Timer Input Capture Holding Register 0 Low TC1HH 0x00BA Timer Input Capture Holding Register 1 High TC1HL 0x00BB Timer Input Capture Holding Register 1 Low TC2HH 0x00BC Timer Input Capture Holding Register 2 High TC2HL 0x00BD Timer Input Capture Holding Register 2 Low TC3HH 0x00BE Timer Input Capture Holding Register 3 High TC3HL 0x00BF Timer Input Capture Holding Register 3 Low SC0BDH 0x00C0 SCI Baud Rate Control Register High SC0BDH.BTST 7 Reserved for test function SC0BDH.BSPL 6 Reserved for test function SC0BDH.BRLD 5 Reserved for test function SC0BDH.SBR12 4 SC0BDH.SBR11 3 SC0BDH.SBR10 2 SC0BDH.SBR9 1 SC0BDH.SBR8 0 SC0BDL 0x00C1 SCI Baud Rate Control Register Low SC0BDL.SBR7 7 SC0BDL.SBR6 6 SC0BDL.SBR5 5 SC0BDL.SBR4 4 SC0BDL.SBR3 3 SC0BDL.SBR2 2 SC0BDL.SBR1 1 SC0BDL.SBR0 0 SC0CR1 0x00C2 SCI Control Register 1 SC0CR1.LOOPS 7 SCI LOOP Mode/Single Wire Mode Enable SC0CR1.WOMS 6 Wired-Or Mode for Serial Pins SC0CR1.RSRC 5 Receiver Source SC0CR1.M 4 Mode (select character format) SC0CR1.WAKE 3 Wake-up by Address Mark/Idle SC0CR1.ILT 2 Idle Line Type SC0CR1.PE 1 Parity Enable SC0CR1.PT 0 Parity Type SC0CR2 0x00C3 SCI Control Register 2 SC0CR2.TIE 7 Transmit Interrupt Enable SC0CR2.TCIE 6 Transmit Complete Interrupt Enable SC0CR2.RIE 5 Receiver Interrupt Enable SC0CR2.ILIE 4 Idle Line Interrupt Enable SC0CR2.TE 3 Transmitter Enable SC0CR2.RE 2 Receiver Enable SC0CR2.RWU 1 Receiver Wake-Up Control SC0CR2.SBK 0 Send Break SC0SR1 0x00C4 SCI Status Register 1 SC0SR1.TDRE 7 Transmit Data Register Empty Flag SC0SR1.TC 6 Transmit Complete Flag SC0SR1.RDRF 5 Receive Data Register Full Flag SC0SR1.IDLE 4 Idle Line Detected Flag SC0SR1.OR 3 Overrun Error Flag SC0SR1.NF 2 Noise Error Flag SC0SR1.FE 1 Framing Error Flag SC0SR1.PF 0 Parity Error Flag SC0SR2 0x00C5 SCI Status Register 2 SC0SR2.RAF 0 Receiver Active Flag SC0DRH 0x00C6 SCI Data Register High SC0DRH.R8 7 Receive Bit 8 SC0DRH.T8 6 Transmit Bit 8 SC0DRL 0x00C7 SCI Data Register Low SC0DRL.R7_T7 7 Receive/Transmit Data Bit 7 SC0DRL.R6_T6 6 Receive/Transmit Data Bit 6 SC0DRL.R5_T5 5 Receive/Transmit Data Bit 5 SC0DRL.R4_T4 4 Receive/Transmit Data Bit 4 SC0DRL.R3_T3 3 Receive/Transmit Data Bit 3 SC0DRL.R2_T2 2 Receive/Transmit Data Bit 2 SC0DRL.R1_T1 1 Receive/Transmit Data Bit 1 SC0DRL.R0_T0 0 Receive/Transmit Data Bit 0 SC1BDH 0x00C8 SCI Baud Rate Control Register High SC1BDH.BTST 7 Reserved for test function SC1BDH.BSPL 6 Reserved for test function SC1BDH.BRLD 5 Reserved for test function SC1BDH.SBR12 4 SC1BDH.SBR11 3 SC1BDH.SBR10 2 SC1BDH.SBR9 1 SC1BDH.SBR8 0 SC1BDL 0x00C9 SCI Baud Rate Control Register Low SC1BDL.SBR7 7 SC1BDL.SBR6 6 SC1BDL.SBR5 5 SC1BDL.SBR4 4 SC1BDL.SBR3 3 SC1BDL.SBR2 2 SC1BDL.SBR1 1 SC1BDL.SBR0 0 SC1CR1 0x00CA SCI Control Register 1 SC1CR1.LOOPS 7 SCI LOOP Mode/Single Wire Mode Enable SC1CR1.WOMS 6 Wired-Or Mode for Serial Pins SC1CR1.RSRC 5 Receiver Source SC1CR1.M 4 Mode (select character format) SC1CR1.WAKE 3 Wake-up by Address Mark/Idle SC1CR1.ILT 2 Idle Line Type SC1CR1.PE 1 Parity Enable SC1CR1.PT 0 Parity Type SC1CR2 0x00CB SCI Control Register 2 SC1CR2.TIE 7 Transmit Interrupt Enable SC1CR2.TCIE 6 Transmit Complete Interrupt Enable SC1CR2.RIE 5 Receiver Interrupt Enable SC1CR2.ILIE 4 Idle Line Interrupt Enable SC1CR2.TE 3 Transmitter Enable SC1CR2.RE 2 Receiver Enable SC1CR2.RWU 1 Receiver Wake-Up Control SC1CR2.SBK 0 Send Break SC1SR1 0x00CC SCI Status Register 1 SC1SR1.TDRE 7 Transmit Data Register Empty Flag SC1SR1.TC 6 Transmit Complete Flag SC1SR1.RDRF 5 Receive Data Register Full Flag SC1SR1.IDLE 4 Idle Line Detected Flag SC1SR1.OR 3 Overrun Error Flag SC1SR1.NF 2 Noise Error Flag SC1SR1.FE 1 Framing Error Flag SC1SR1.PF 0 Parity Error Flag SC1SR2 0x00CD SCI Status Register 2 SC1SR2.RAF 0 Receiver Active Flag SC1DRH 0x00CE SCI Data Register High SC1DRH.R8 7 Receive Bit 8 SC1DRH.T8 6 Transmit Bit 8 SC1DRL 0x00CF SCI Data Register Low SC1DRL.R7_T7 7 Receive/Transmit Data Bit 7 SC1DRL.R6_T6 6 Receive/Transmit Data Bit 6 SC1DRL.R5_T5 5 Receive/Transmit Data Bit 5 SC1DRL.R4_T4 4 Receive/Transmit Data Bit 4 SC1DRL.R3_T3 3 Receive/Transmit Data Bit 3 SC1DRL.R2_T2 2 Receive/Transmit Data Bit 2 SC1DRL.R1_T1 1 Receive/Transmit Data Bit 1 SC1DRL.R0_T0 0 Receive/Transmit Data Bit 0 SP0CR1 0x00D0 SPI Control Register 1 SP0CR1.SPIE 7 SPI Interrupt Enable SP0CR1.SPE 6 SPI System Enable SP0CR1.SWOM 5 Port S Wired-OR Mode SP0CR1.MSTR 4 SPI Master/Slave Mode Select SP0CR1.CPOL 3 SPI Clock Polarity SP0CR1.CPHA 2 Clock Phase SP0CR1.SSOE 1 Slave Select Output Enable SP0CR1.LSBF 0 SPI LSB First enable SP0CR2 0x00D1 SPI Control Register 2 SP0CR2.PUPS 3 Pull-Up Port S Enable SP0CR2.RDPS 2 Reduce Drive of Port S SP0CR2.SSWAI 1 Serial Interface Stop in WAIT mode SP0CR2.SPC0 0 Serial Pin Control 0 SP0BR 0x00D2 SPI Baud Rate Register SP0BR.SPR2 2 SPI Clock (SCK) Rate Select Bit 2 SP0BR.SPR1 1 SPI Clock (SCK) Rate Select Bit 1 SP0BR.SPR0 0 SPI Clock (SCK) Rate Select Bit 0 SP0SR 0x00D3 SPI Status Register SP0SR.SPIF 7 SPI Interrupt Request SP0SR.WCOL 6 Write Collision Status Flag SP0SR.MODF 4 SPI Mode Error Interrupt Status Flag RESERVED00D4 0x00D4 RESERVED SP0DR 0x00D5 SPI Data Register PORTS 0x00D6 Port S Data Register PORTS.PS7 7 Port S Data Bit 7 PORTS.PS6 6 Port S Data Bit 6 PORTS.PS5 5 Port S Data Bit 5 PORTS.PS4 4 Port S Data Bit 4 PORTS.PS3 3 Port S Data Bit 3 PORTS.PS2 2 Port S Data Bit 2 PORTS.PS1 1 Port S Data Bit 1 PORTS.PS0 0 Port S Data Bit 0 DDRS 0x00D7 Port S Data Direction Register DDRS.DDS7 7 Port S Data Direction Bit 7 DDRS.DDS6 6 Port S Data Direction Bit 6 DDRS.DDS5 5 Port S Data Direction Bit 5 DDRS.DDS4 4 Port S Data Direction Bit 4 DDRS.DDS3 3 Port S Data Direction Bit 3 DDRS.DDS2 2 Port S Data Direction Bit 2 DDRS.DDS1 1 Port S Data Direction Bit 1 DDRS.DDS0 0 Port S Data Direction Bit 0 RESERVED00D8 0x00D8 RESERVED RESERVED00D9 0x00D9 RESERVED RESERVED00DA 0x00DA RESERVED RESERVED00DB 0x00DB RESERVED RESERVED00DC 0x00DC RESERVED RESERVED00DD 0x00DD RESERVED RESERVED00DE 0x00DE RESERVED RESERVED00DF 0x00DF RESERVED IBAD 0x00E0 Bus Address Register IBAD.ADR7 7 Slave Address 7 IBAD.ADR6 6 Slave Address 6 IBAD.ADR5 5 Slave Address 5 IBAD.ADR4 4 Slave Address 4 IBAD.ADR3 3 Slave Address 3 IBAD.ADR2 2 Slave Address 2 IBAD.ADR1 1 Slave Address 1 IBFD 0x00E1 IIC Bus Frequency Divider Register IBFD.IBC5 5 IIC Bus Clock Rate 5 IBFD.IBC4 4 IIC Bus Clock Rate 4 IBFD.IBC3 3 IIC Bus Clock Rate 3 IBFD.IBC2 2 IIC Bus Clock Rate 2 IBFD.IBC1 1 IIC Bus Clock Rate 1 IBFD.IBC0 0 IIC Bus Clock Rate 0 IBCR 0x00E2 IIC Bus Control Register IBCR.IBEN 7 IIC Bus Enable IBCR.IBIE 6 IIC Bus Interrupt Enable IBCR.MS_SL 5 Master/Slave mode select bit IBCR.Tx_Rx 4 Transmit/Receive mode select bit IBCR.TXAK 3 Transmit Acknowledge enable IBCR.RSTA 2 Repeat Start IBCR.IBSWAI 0 IIC Stop in WAIT mode IBSR 0x00E3 IIC Bus Status Register IBSR.TCF 7 Data transferring bit IBSR.IAAS 6 Addressed as a slave bit IBSR.IBB 5 IIC Bus busy bit IBSR.IBAL 4 Arbitration Lost IBSR.SRW 2 Slave Read/Write IBSR.IBIF 1 IIC Bus Interrupt Flag IBSR.RXAK 0 Received Acknowledge IBDR 0x00E4 IIC Bus Data I/O Register IBDR.D7 7 IBDR.D6 6 IBDR.D5 5 IBDR.D4 4 IBDR.D3 3 IBDR.D2 2 IBDR.D1 1 IBDR.D0 0 IBPURD 0x00E5 Pull-Up and Reduced Drive for Port IB IBPURD.RDPIB 4 Reduced Drive of Port IB IBPURD.PUPIB 0 Pull-Up Port IB Enable PORTIB 0x00E6 Port Data IB Register PORTIB.PIB7 7 Port Data IB Register bit 7 PORTIB.PIB6 6 Port Data IB Register bit 6 PORTIB.PIB5 5 Port Data IB Register bit 5 PORTIB.PIB4 4 Port Data IB Register bit 4 PORTIB.PIB3 3 Port Data IB Register bit 3 PORTIB.PIB2 2 Port Data IB Register bit 2 PORTIB.PIB1 1 Port Data IB Register bit 1 PORTIB.PIB0 0 Port Data IB Register bit 0 DDRIB 0x00E7 Data Direction for Port IB Register DDRIB.DDRIB7 7 Port IB Data direction 7 DDRIB.DDRIB6 6 Port IB Data direction 6 DDRIB.DDRIB5 5 Port IB Data direction 5 DDRIB.DDRIB4 4 Port IB Data direction 4 DDRIB.DDRIB3 3 Port IB Data direction 3 DDRIB.DDRIB2 2 Port IB Data direction 2 DDRIB.DDRIB1 1 DDRIB.DDRIB0 0 RESERVED00E8 0x00E8 RESERVED RESERVED00E9 0x00E9 RESERVED RESERVED00EA 0x00EA RESERVED RESERVED00EB 0x00EB RESERVED RESERVED00EC 0x00EC RESERVED RESERVED00ED 0x00ED RESERVED EEDIVH 0x00EE EEPROM Modulus Divider High EEDIVH.EEDIV9 1 Prescaler divider 9 EEDIVH.EEDIV8 0 Prescaler divider 8 EEDIVL 0x00EF EEPROM Modulus Divider Low EEDIVL.EEDIV7 7 Prescaler divider 7 EEDIVL.EEDIV6 6 Prescaler divider 6 EEDIVL.EEDIV5 5 Prescaler divider 5 EEDIVL.EEDIV4 4 Prescaler divider 4 EEDIVL.EEDIV3 3 Prescaler divider 3 EEDIVL.EEDIV2 2 Prescaler divider 2 EEDIVL.EEDIV1 1 Prescaler divider 1 EEDIVL.EEDIV0 0 Prescaler divider 0 EEMCR 0x00F0 EEPROM Module Configuration EEMCR.NOBDML 7 Background Debug Mode Lockout Disable EEMCR.NOSHW 6 SHADOW Byte Disable EEMCR.EESWAI 2 EEPROM Stops in Wait Mode EEMCR.PROTLCK 1 Block Protect Write Lock EEMCR.EERC 0 EEPROM Charge Pump Clock EEPROT 0x00F1 EEPROM Block Protect EEPROT.SHPROT 7 SHADOW Byte Protection EEPROT.BPROT5 5 EEPROM Block Protection 5 EEPROT.BPROT4 4 EEPROM Block Protection 4 EEPROT.BPROT3 3 EEPROM Block Protection 3 EEPROT.BPROT2 2 EEPROM Block Protection 2 EEPROT.BPROT1 1 EEPROM Block Protection 1 EEPROT.BPROT0 0 EEPROM Block Protection 0 EETST 0x00F2 EEPROM Test EETST.EREVTN 6 EETST.ETMSD 2 EETST.ETMR 1 EETST.ETMSE 0 EEPROG 0x00F3 EEPROM Control EEPROG.BULKP 7 Bulk Erase Protection EEPROG..AUTO 5 Automatic shutdown of program/erase operation EEPROG.BYTE 4 Byte and Aligned Word Erase EEPROG.ROW 3 Row or Bulk Erase (when BYTE = 0) EEPROG.ERASE 2 Erase Control EEPROG.EELAT 1 EEPROM Latch Control EEPROG.EEPGM 0 Program and Erase Enable FEELCK 0x00F4 Flash EEPROM Lock Control Register FEELCK.LOCK 0 Lock Register Bit FEEMCR 0x00F5 Flash EEPROM Module Configuration Register FEEMCR.BOOTP 0 Boot Protect FEETST 0x00F6 FEETST FEETST.STRE 7 FEETST.REVTUN 6 FEETST.TMSD 2 FEETST.TMR 1 FEETST.TMSE 0 FEECTL 0x00F7 Flash EEPROM Control Register FEECTL.FEESWAI 4 Flash EEPROM Stop in Wait Control FEECTL.HVEN 3 High-Voltage Enable FEECTL.ERAS 1 Erase Control FEECTL.PGM 0 Program Control MTST0 0x00F8 Mapping Test Register 0 MTST0.MT07 7 MTST0.MT06 6 MTST0.MT05 5 MTST0.MT04 4 MTST0.MT03 3 MTST0.MT02 2 MTST0.MT01 1 MTST0.MT00 0 MTST1 0x00F9 Mapping Test Register 1 MTST1.MT0F 7 MTST1.MT0E 6 MTST1.MT0D 5 MTST1.MT0C 4 MTST1.MT0B 3 MTST1.MT0A 2 MTST1.MT09 1 MTST1.MT08 0 MTST2 0x00FA Mapping Test Register 2 MTST2.MT17 7 MTST2.MT16 6 MTST2.MT15 5 MTST2.MT14 4 MTST2.MT13 3 MTST2.MT12 2 MTST2.MT11 1 MTST2.MT10 0 MTST3 0x00FB Mapping Test Register 3 MTST3.MT1F 7 MTST3.MT1E 6 MTST3.MT1D 5 MTST3.MT1C 4 MTST3.MT1B 3 MTST3.MT1A 2 MTST3.MT19 1 MTST3.MT18 0 PORTK 0x00FC Port K Data Register PORTK.PK7 7 Port K Data Bit 7 PORTK.PK3 3 Port K Data Bit 3 PORTK.PK2 2 Port K Data Bit 2 PORTK.PK1 1 Port K Data Bit 1 PORTK.PK0 0 Port K Data Bit 0 DDRK 0x00FD Port K Data Direction Register DDRK.DDK7 7 Port K Data Direction Bit 7 DDRK.DDK3 3 Port K Data Direction Bit 3 DDRK.DDK2 2 Port K Data Direction Bit 2 DDRK.DDK1 1 Port K Data Direction Bit 1 DDRK.DDK0 0 Port K Data Direction Bit 0 RESERVED00FE 0x00FE RESERVED PPAGE 0x00FF Program Page Index Register PPAGE.PIX2 2 PPAGE.PIX1 1 PPAGE.PIX0 0 C0MCR0 0x0100 msCAN12 Module Control Register 0 C0MCR0.CSWAI 5 CAN Stops in Wait Mode C0MCR0.SYNCH 4 Synchronized Status C0MCR0.TLNKEN 3 Timer Enable C0MCR0.SLPAK 2 SLEEP Mode Acknowledge C0MCR0.SLPRQ 1 SLEEP request C0MCR0.SFTRES 0 SOFT_RESET C0MCR1 0x0101 msCAN12 Module Control Register 1 C0MCR1.LOOPB 2 Loop Back Self Test Mode C0MCR1.WUPM 1 Wake-Up Mode C0MCR1.CLKSRC 0 msCAN12 Clock Source C0BTR0 0x0102 msCAN12 Bus Timing Register 0 C0BTR0.SJW1 7 Synchronization Jump Width 1 C0BTR0.SJW0 6 Synchronization Jump Width 0 C0BTR0.BRP5 5 Baud Rate Prescaler 5 C0BTR0.BRP4 4 Baud Rate Prescaler 4 C0BTR0.BRP3 3 Baud Rate Prescaler 3 C0BTR0.BRP2 2 Baud Rate Prescaler 2 C0BTR0.BRP1 1 Baud Rate Prescaler 1 C0BTR0.BRP0 0 Baud Rate Prescaler 0 C0BTR1 0x0103 msCAN12 Bus Timing Register 1 C0BTR1.SAMP 7 Sampling C0BTR1.TSEG22 6 Time Segment 22 C0BTR1.TSEG21 5 Time Segment 21 C0BTR1.TSEG20 4 Time Segment 20 C0BTR1.TSEG13 3 Time Segment 13 C0BTR1.TSEG12 2 Time Segment 12 C0BTR1.TSEG11 1 Time Segment 11 C0BTR1.TSEG10 0 Time Segment 10 C0RFLG 0x0104 msCAN12 Receiver Flag Register C0RFLG.WUPIF 7 Wake-up Interrupt Flag C0RFLG.RWRNIF 6 Receiver Warning Interrupt Flag C0RFLG.TWRNIF 5 Transmitter Warning Interrupt Flag C0RFLG.RERRIF 4 Receiver Error Passive Interrupt Flag C0RFLG.TERRIF 3 Transmitter Error Passive Interrupt Flag C0RFLG.BOFFIF 2 BUSOFF Interrupt Flag C0RFLG.OVRIF 1 Overrun Interrupt Flag C0RFLG.RXF 0 Receive Buffer Full C0RIER 0x0105 msCAN12 Receiver Interrupt Enable Register C0RIER.WUPIE 7 Wake-up Interrupt Enable C0RIER.RWRNIE 6 Receiver Warning Interrupt Enable C0RIER.TWRNIE 5 Transmitter Warning Interrupt Enable C0RIER.RERRIE 4 Receiver Error Passive Interrupt Enable C0RIER.TERRIE 3 Transmitter Error Passive Interrupt Enable C0RIER.BOFFIE 2 BUSOFF Interrupt Enable C0RIER.OVRIE 1 Overrun Interrupt Enable C0RIER.RXFIE 0 Receiver Full Interrupt Enable C0TFLG 0x0106 msCAN12 Transmitter Flag Register C0TFLG.ABTAK2 6 Abort Acknowledge 2 C0TFLG.ABTAK1 5 Abort Acknowledge 1 C0TFLG.ABTAK0 4 Abort Acknowledge 0 C0TFLG.TXE2 2 Transmitter Buffer Empty 2 C0TFLG.TXE1 1 Transmitter Buffer Empty 1 C0TFLG.TXE0 0 Transmitter Buffer Empty 0 C0TCR 0x0107 msCAN12 Transmitter Control Register C0TCR.ABTRQ2 6 Abort Request 2 C0TCR.ABTRQ1 5 Abort Request 1 C0TCR.ABTRQ0 4 Abort Request 0 C0TCR.TXEIE2 2 Transmitter Empty Interrupt Enable 2 C0TCR.TXEIE1 1 Transmitter Empty Interrupt Enable 1 C0TCR.TXEIE0 0 Transmitter Empty Interrupt Enable 0 C0IDAC 0x0108 msCAN12 Identifier Acceptance Control Register C0IDAC.IDAM1 5 Identifier Acceptance Mode 1 C0IDAC.IDAM0 4 Identifier Acceptance Mode 0 C0IDAC.IDHIT2 2 Identifier Acceptance Hit Indicator 2 C0IDAC.IDHIT1 1 Identifier Acceptance Hit Indicator 1 C0IDAC.IDHIT0 0 Identifier Acceptance Hit Indicator 0 RESERVED0109 0x0109 RESERVED RESERVED010A 0x010A RESERVED RESERVED010B 0x010B RESERVED RESERVED010C 0x010C RESERVED RESERVED010D 0x010D RESERVED C0RXERR 0x010E msCAN12 Receive Error Counter C0RXERR.RXERR7 7 C0RXERR.RXERR6 6 C0RXERR.RXERR5 5 C0RXERR.RXERR4 4 C0RXERR.RXERR3 3 C0RXERR.RXERR2 2 C0RXERR.RXERR1 1 C0RXERR.RXERR0 0 C0TXERR 0x010F msCAN12 Transmit Error Counter C0TXERR.TXERR7 7 C0TXERR.TXERR6 6 C0TXERR.TXERR5 5 C0TXERR.TXERR4 4 C0TXERR.TXERR3 3 C0TXERR.TXERR2 2 C0TXERR.TXERR1 1 C0TXERR.TXERR0 0 C0IDAR0 0x0110 msCAN12 Identifier Acceptance Register 0 C0IDAR0.AC7 7 Acceptance Code Bit 7 C0IDAR0.AC6 6 Acceptance Code Bit 6 C0IDAR0.AC5 5 Acceptance Code Bit 5 C0IDAR0.AC4 4 Acceptance Code Bit 4 C0IDAR0.AC3 3 Acceptance Code Bit 3 C0IDAR0.AC2 2 Acceptance Code Bit 2 C0IDAR0.AC1 1 Acceptance Code Bit 1 C0IDAR0.AC0 0 Acceptance Code Bit 0 C0IDAR1 0x0111 msCAN12 Identifier Acceptance Register 1 C0IDAR1.AC7 7 Acceptance Code Bit 7 C0IDAR1.AC6 6 Acceptance Code Bit 6 C0IDAR1.AC5 5 Acceptance Code Bit 5 C0IDAR1.AC4 4 Acceptance Code Bit 4 C0IDAR1.AC3 3 Acceptance Code Bit 3 C0IDAR1.AC2 2 Acceptance Code Bit 2 C0IDAR1.AC1 1 Acceptance Code Bit 1 C0IDAR1.AC0 0 Acceptance Code Bit 0 C0IDAR2 0x0112 msCAN12 Identifier Acceptance Register 2 C0IDAR2.AC7 7 Acceptance Code Bit 7 C0IDAR2.AC6 6 Acceptance Code Bit 6 C0IDAR2.AC5 5 Acceptance Code Bit 5 C0IDAR2.AC4 4 Acceptance Code Bit 4 C0IDAR2.AC3 3 Acceptance Code Bit 3 C0IDAR2.AC2 2 Acceptance Code Bit 2 C0IDAR2.AC1 1 Acceptance Code Bit 1 C0IDAR2.AC0 0 Acceptance Code Bit 0 C0IDAR3 0x0113 msCAN12 Identifier Acceptance Register 3 C0IDAR3.AC7 7 Acceptance Code Bit 7 C0IDAR3.AC6 6 Acceptance Code Bit 6 C0IDAR3.AC5 5 Acceptance Code Bit 5 C0IDAR3.AC4 4 Acceptance Code Bit 4 C0IDAR3.AC3 3 Acceptance Code Bit 3 C0IDAR3.AC2 2 Acceptance Code Bit 2 C0IDAR3.AC1 1 Acceptance Code Bit 1 C0IDAR3.AC0 0 Acceptance Code Bit 0 C0IDMR0 0x0114 msCAN12 Identifier Mask Register 0 C0IDMR0.AM7 7 Acceptance Mask Bit 7 C0IDMR0.AM6 6 Acceptance Mask Bit 6 C0IDMR0.AM5 5 Acceptance Mask Bit 5 C0IDMR0.AM4 4 Acceptance Mask Bit 4 C0IDMR0.AM3 3 Acceptance Mask Bit 3 C0IDMR0.AM2 2 Acceptance Mask Bit 2 C0IDMR0.AM1 1 Acceptance Mask Bit 1 C0IDMR0.AM0 0 Acceptance Mask Bit 0 C0IDMR1 0x0115 msCAN12 Identifier Mask Register 1 C0IDMR1.AM7 7 Acceptance Mask Bit 7 C0IDMR1.AM6 6 Acceptance Mask Bit 6 C0IDMR1.AM5 5 Acceptance Mask Bit 5 C0IDMR1.AM4 4 Acceptance Mask Bit 4 C0IDMR1.AM3 3 Acceptance Mask Bit 3 C0IDMR1.AM2 2 Acceptance Mask Bit 2 C0IDMR1.AM1 1 Acceptance Mask Bit 1 C0IDMR1.AM0 0 Acceptance Mask Bit 0 C0IDMR2 0x0116 msCAN12 Identifier Mask Register 2 C0IDMR2.AM7 7 Acceptance Mask Bit 7 C0IDMR2.AM6 6 Acceptance Mask Bit 6 C0IDMR2.AM5 5 Acceptance Mask Bit 5 C0IDMR2.AM4 4 Acceptance Mask Bit 4 C0IDMR2.AM3 3 Acceptance Mask Bit 3 C0IDMR2.AM2 2 Acceptance Mask Bit 2 C0IDMR2.AM1 1 Acceptance Mask Bit 1 C0IDMR2.AM0 0 Acceptance Mask Bit 0 C0IDMR3 0x0117 msCAN12 Identifier Mask Register 3 C0IDMR3.AM7 7 Acceptance Mask Bit 7 C0IDMR3.AM6 6 Acceptance Mask Bit 6 C0IDMR3.AM5 5 Acceptance Mask Bit 5 C0IDMR3.AM4 4 Acceptance Mask Bit 4 C0IDMR3.AM3 3 Acceptance Mask Bit 3 C0IDMR3.AM2 2 Acceptance Mask Bit 2 C0IDMR3.AM1 1 Acceptance Mask Bit 1 C0IDMR3.AM0 0 Acceptance Mask Bit 0 C0IDAR4 0x0118 msCAN12 Identifier Acceptance Register 4 C0IDAR4.AC7 7 Acceptance Code Bit 7 C0IDAR4.AC6 6 Acceptance Code Bit 6 C0IDAR4.AC5 5 Acceptance Code Bit 5 C0IDAR4.AC4 4 Acceptance Code Bit 4 C0IDAR4.AC3 3 Acceptance Code Bit 3 C0IDAR4.AC2 2 Acceptance Code Bit 2 C0IDAR4.AC1 1 Acceptance Code Bit 1 C0IDAR4.AC0 0 Acceptance Code Bit 0 C0IDAR5 0x0119 msCAN12 Identifier Acceptance Register 5 C0IDAR5.AC7 7 Acceptance Code Bit 7 C0IDAR5.AC6 6 Acceptance Code Bit 6 C0IDAR5.AC5 5 Acceptance Code Bit 5 C0IDAR5.AC4 4 Acceptance Code Bit 4 C0IDAR5.AC3 3 Acceptance Code Bit 3 C0IDAR5.AC2 2 Acceptance Code Bit 2 C0IDAR5.AC1 1 Acceptance Code Bit 1 C0IDAR5.AC0 0 Acceptance Code Bit 0 C0IDAR6 0x011A msCAN12 Identifier Acceptance Register 6 C0IDAR6.AC7 7 Acceptance Code Bit 7 C0IDAR6.AC6 6 Acceptance Code Bit 6 C0IDAR6.AC5 5 Acceptance Code Bit 5 C0IDAR6.AC4 4 Acceptance Code Bit 4 C0IDAR6.AC3 3 Acceptance Code Bit 3 C0IDAR6.AC2 2 Acceptance Code Bit 2 C0IDAR6.AC1 1 Acceptance Code Bit 1 C0IDAR6.AC0 0 Acceptance Code Bit 0 C0IDAR7 0x011B msCAN12 Identifier Acceptance Register 7 C0IDAR7.AC7 7 Acceptance Code Bit 7 C0IDAR7.AC6 6 Acceptance Code Bit 6 C0IDAR7.AC5 5 Acceptance Code Bit 5 C0IDAR7.AC4 4 Acceptance Code Bit 4 C0IDAR7.AC3 3 Acceptance Code Bit 3 C0IDAR7.AC2 2 Acceptance Code Bit 2 C0IDAR7.AC1 1 Acceptance Code Bit 1 C0IDAR7.AC0 0 Acceptance Code Bit 0 C0IDMR4 0x011C msCAN12 Identifier Mask Register 4 C0IDMR4.AM7 7 Acceptance Mask Bit 7 C0IDMR4.AM6 6 Acceptance Mask Bit 6 C0IDMR4.AM5 5 Acceptance Mask Bit 5 C0IDMR4.AM4 4 Acceptance Mask Bit 4 C0IDMR4.AM3 3 Acceptance Mask Bit 3 C0IDMR4.AM2 2 Acceptance Mask Bit 2 C0IDMR4.AM1 1 Acceptance Mask Bit 1 C0IDMR4.AM0 0 Acceptance Mask Bit 0 C0IDMR5 0x011D msCAN12 Identifier Mask Register 5 C0IDMR5.AM7 7 Acceptance Mask Bit 7 C0IDMR5.AM6 6 Acceptance Mask Bit 6 C0IDMR5.AM5 5 Acceptance Mask Bit 5 C0IDMR5.AM4 4 Acceptance Mask Bit 4 C0IDMR5.AM3 3 Acceptance Mask Bit 3 C0IDMR5.AM2 2 Acceptance Mask Bit 2 C0IDMR5.AM1 1 Acceptance Mask Bit 1 C0IDMR5.AM0 0 Acceptance Mask Bit 0 C0IDMR6 0x011E msCAN12 Identifier Mask Register 6 C0IDMR6.AM7 7 Acceptance Mask Bit 7 C0IDMR6.AM6 6 Acceptance Mask Bit 6 C0IDMR6.AM5 5 Acceptance Mask Bit 5 C0IDMR6.AM4 4 Acceptance Mask Bit 4 C0IDMR6.AM3 3 Acceptance Mask Bit 3 C0IDMR6.AM2 2 Acceptance Mask Bit 2 C0IDMR6.AM1 1 Acceptance Mask Bit 1 C0IDMR6.AM0 0 Acceptance Mask Bit 0 C0IDMR7 0x011F msCAN12 Identifier Mask Register 7 C0IDMR7.AM7 7 Acceptance Mask Bit 7 C0IDMR7.AM6 6 Acceptance Mask Bit 6 C0IDMR7.AM5 5 Acceptance Mask Bit 5 C0IDMR7.AM4 4 Acceptance Mask Bit 4 C0IDMR7.AM3 3 Acceptance Mask Bit 3 C0IDMR7.AM2 2 Acceptance Mask Bit 2 C0IDMR7.AM1 1 Acceptance Mask Bit 1 C0IDMR7.AM0 0 Acceptance Mask Bit 0 RESERVED0120 0x0120 RESERVED RESERVED0121 0x0121 RESERVED RESERVED0122 0x0122 RESERVED RESERVED0123 0x0123 RESERVED RESERVED0124 0x0124 RESERVED RESERVED0125 0x0125 RESERVED RESERVED0126 0x0126 RESERVED RESERVED0127 0x0127 RESERVED RESERVED0128 0x0128 RESERVED RESERVED0129 0x0129 RESERVED RESERVED012A 0x012A RESERVED RESERVED012B 0x012B RESERVED RESERVED012C 0x012C RESERVED RESERVED012D 0x012D RESERVED RESERVED012E 0x012E RESERVED RESERVED012F 0x012F RESERVED RESERVED0130 0x0130 RESERVED RESERVED0131 0x0131 RESERVED RESERVED0132 0x0132 RESERVED RESERVED0133 0x0133 RESERVED RESERVED0134 0x0134 RESERVED RESERVED0135 0x0135 RESERVED RESERVED0136 0x0136 RESERVED RESERVED0137 0x0137 RESERVED RESERVED0138 0x0138 RESERVED RESERVED0139 0x0139 RESERVED RESERVED013A 0x013A RESERVED RESERVED013B 0x013B RESERVED RESERVED013C 0x013C RESERVED PCTLCAN0 0x013D msCAN12 Port CAN Control Register PCTLCAN0.PUPCAN 1 Pull-Up Enable Port CAN PCTLCAN0.RDPCAN 0 Reduced Drive Port CAN PORTCAN0 0x013E msCAN12 Port CAN Data Register PORTCAN0.PCAN7 7 Port CAN Data Bit 7 PORTCAN0.PCAN6 6 Port CAN Data Bit 6 PORTCAN0.PCAN5 5 Port CAN Data Bit 5 PORTCAN0.PCAN4 4 Port CAN Data Bit 4 PORTCAN0.PCAN3 3 Port CAN Data Bit 3 PORTCAN0.PCAN2 2 Port CAN Data Bit 2 PORTCAN0.TxCAN 1 PORTCAN0.RxCAN 0 DDRCAN0 0x013F msCAN12 Port CAN Data Direction Register DDRCAN0.DDCAN7 7 DDRCAN0.DDCAN6 6 DDRCAN0.DDCAN5 5 DDRCAN0.DDCAN4 4 DDRCAN0.DDCAN3 3 DDRCAN0.DDCAN2 2 ATD1CTL2 0x01E2 ATD1 Control Register 2 ATD1CTL2.ADPU 7 ATD Disable ATD1CTL2.AFFC 6 ATD Fast Flag Clear All ATD1CTL2.ASWAI 5 ATD Wait Mode ATD1CTL2.DJM 4 Result Register Data Justification Mode ATD1CTL2.DSGN 3 Signed/Unsigned Result Data Mode ATD1CTL2.ASCIE 1 ATD Sequence Complete Interrupt Enable ATD1CTL2.ASCIF 0 ATD Sequence Complete Interrupt Flag ATD1CTL3 0x01E3 ATD1 Control Register 3 ATD1CTL3.S1C 3 Conversion Sequence Length (Least Significant Bit) ATD1CTL3.FIFO 2 Result Register FIFO Mode ATD1CTL3.FRZ1 1 Background Debug (Freeze) Enable 1 ATD1CTL3.FRZ0 0 Background Debug (Freeze) Enable 0 ATD1CTL4 0x01E4 ATD1 Control Register 4 ATD1CTL4.RES10 7 10 bit Mode ATD1CTL4.SMP1 6 Select Sample Time 1 ATD1CTL4.SMP0 5 Select Sample Time 0 ATD1CTL4.PRS4 4 Select Divide-By Factor for ATD P-Clock Prescaler 4 ATD1CTL4.PRS3 3 Select Divide-By Factor for ATD P-Clock Prescaler 3 ATD1CTL4.PRS2 2 Select Divide-By Factor for ATD P-Clock Prescaler 2 ATD1CTL4.PRS1 1 Select Divide-By Factor for ATD P-Clock Prescaler 1 ATD1CTL4.PRS0 0 Select Divide-By Factor for ATD P-Clock Prescaler 0 ATD1CTL5 0x01E5 ATD1 Control Register 5 ATD1CTL5.S8CM 6 Select 8 Channel Mode ATD1CTL5.SCAN 5 Enable Continuous Channel Scan ATD1CTL5.MULT 4 Enable Multichannel Conversion ATD1CTL5.CD 3 Channel Select for Conversion D ATD1CTL5.CC 2 Channel Select for Conversion C ATD1CTL5.CB 1 Channel Select for Conversion B ATD1CTL5.CA 0 Channel Select for Conversion A ATD1STAT0 0x01E6 ATD1 Status Register ATD1STAT0.SCF 7 Sequence Complete Flag ATD1STAT0.CC2 2 Conversion Counter for Current Sequence of Four or Eight Conversions 2 ATD1STAT0.CC1 1 Conversion Counter for Current Sequence of Four or Eight Conversions 1 ATD1STAT0.CC0 0 Conversion Counter for Current Sequence of Four or Eight Conversions 0 ATD1STAT1 0x01E7 ATD1 Status Register ATD1STAT1.CCF7 7 Conversion Complete Flag 7 ATD1STAT1.CCF6 6 Conversion Complete Flag 6 ATD1STAT1.CCF5 5 Conversion Complete Flag 5 ATD1STAT1.CCF4 4 Conversion Complete Flag 4 ATD1STAT1.CCF3 3 Conversion Complete Flag 3 ATD1STAT1.CCF2 2 Conversion Complete Flag 2 ATD1STAT1.CCF1 1 Conversion Complete Flag 1 ATD1STAT1.CCF0 0 Conversion Complete Flag 0 ATD1TESTH 0x01E8 ATD1 Test Register ATD1TESTH.SAR9 7 SAR Data 9 ATD1TESTH.SAR8 6 SAR Data 8 ATD1TESTH.SAR7 5 SAR Data 7 ATD1TESTH.SAR6 4 SAR Data 6 ATD1TESTH.SAR5 3 SAR Data 5 ATD1TESTH.SAR4 2 SAR Data 4 ATD1TESTH.SAR3 1 SAR Data 3 ATD1TESTH.SAR2 0 SAR Data 2 ATD1TESTL 0x01E9 ATD1 Test Register ATD1TESTL.SAR1 7 SAR Data 1 ATD1TESTL.SAR0 6 SAR Data 0 ATD1TESTL.RST 5 Module Reset Bit ATD1TESTL.TSTOUT 4 Multiplex Output of TST[3:0] (Factory Use) ATD1TESTL.TST3 3 Test Bit 3 ATD1TESTL.TST2 2 Test Bit 2 ATD1TESTL.TST1 1 Test Bit 1 ATD1TESTL.TST0 0 Test Bit 0 RESERVED01EA 0x01EA RESERVED RESERVED01EB 0x01EB RESERVED RESERVED01EC 0x01EC RESERVED RESERVED01ED 0x01ED RESERVED RESERVED01EE 0x01EE RESERVED PORTAD1 0x01EF Port AD1 Data Input Register PORTAD1.PAD17 7 Port AD1 Data Input Bit 7 PORTAD1.PAD16 6 Port AD1 Data Input Bit 6 PORTAD1.PAD15 5 Port AD1 Data Input Bit 5 PORTAD1.PAD14 4 Port AD1 Data Input Bit 4 PORTAD1.PAD13 3 Port AD1 Data Input Bit 3 PORTAD1.PAD12 2 Port AD1 Data Input Bit 2 PORTAD1.PAD11 1 Port AD1 Data Input Bit 1 PORTAD1.PAD10 0 Port AD1 Data Input Bit 0 ADR10H 0x01F0 A/D Conversion Result Register High 0 ADR10L 0x01F1 A/D Conversion Result Register Low 0 ADR11H 0x01F2 A/D Conversion Result Register High 1 ADR11L 0x01F3 A/D Conversion Result Register Low 1 ADR12H 0x01F4 A/D Conversion Result Register High 2 ADR12L 0x01F5 A/D Conversion Result Register Low 2 ADR13H 0x01F6 A/D Conversion Result Register High 3 ADR13L 0x01F7 A/D Conversion Result Register Low 3 ADR14H 0x01F8 A/D Conversion Result Register High 4 ADR14L 0x01F9 A/D Conversion Result Register Low 4 ADR15H 0x01FA A/D Conversion Result Register High 5 ADR15L 0x01FB A/D Conversion Result Register Low 5 ADR16H 0x01FC A/D Conversion Result Register High 6 ADR16L 0x01FD A/D Conversion Result Register Low 6 ADR17H 0x01FE A/D Conversion Result Register High 7 ADR17L 0x01FF A/D Conversion Result Register Low 7 C2MCR0 0x0200 msCAN12 Module Control Register 0 C2MCR0.CSWAI 5 CAN Stops in Wait Mode C2MCR0.SYNCH 4 Synchronized Status C2MCR0.TLNKEN 3 Timer Enable C2MCR0.SLPAK 2 SLEEP Mode Acknowledge C2MCR0.SLPRQ 1 SLEEP request C2MCR0.SFTRES 0 SOFT_RESET C2MCR1 0x0201 msCAN12 Module Control Register 1 C2MCR1.LOOPB 2 Loop Back Self Test Mode C2MCR1.WUPM 1 Wake-Up Mode C2MCR1.CLKSRC 0 msCAN12 Clock Source C2BTR0 0x0202 msCAN12 Bus Timing Register 0 C2BTR0.SJW1 7 Synchronization Jump Width 1 C2BTR0.SJW0 6 Synchronization Jump Width 0 C2BTR0.BRP5 5 Baud Rate Prescaler 5 C2BTR0.BRP4 4 Baud Rate Prescaler 4 C2BTR0.BRP3 3 Baud Rate Prescaler 3 C2BTR0.BRP2 2 Baud Rate Prescaler 2 C2BTR0.BRP1 1 Baud Rate Prescaler 1 C2BTR0.BRP0 0 Baud Rate Prescaler 0 C2BTR1 0x0203 msCAN12 Bus Timing Register 1 C2BTR1.SAMP 7 Sampling C2BTR1.TSEG22 6 Time Segment 22 C2BTR1.TSEG21 5 Time Segment 21 C2BTR1.TSEG20 4 Time Segment 20 C2BTR1.TSEG13 3 Time Segment 13 C2BTR1.TSEG12 2 Time Segment 12 C2BTR1.TSEG11 1 Time Segment 11 C2BTR1.TSEG10 0 Time Segment 10 C2RFLG 0x0204 msCAN12 Receiver Flag Register C2RFLG.WUPIF 7 Wake-up Interrupt Flag C2RFLG.RWRNIF 6 Receiver Warning Interrupt Flag C2RFLG.TWRNIF 5 Transmitter Warning Interrupt Flag C2RFLG.RERRIF 4 Receiver Error Passive Interrupt Flag C2RFLG.TERRIF 3 Transmitter Error Passive Interrupt Flag C2RFLG.BOFFIF 2 BUSOFF Interrupt Flag C2RFLG.OVRIF 1 Overrun Interrupt Flag C2RFLG.RXF 0 Receive Buffer Full C2RIER 0x0205 msCAN12 Receiver Interrupt Enable Register C2RIER.WUPIE 7 Wake-up Interrupt Enable C2RIER.RWRNIE 6 Receiver Warning Interrupt Enable C2RIER.TWRNIE 5 Transmitter Warning Interrupt Enable C2RIER.RERRIE 4 Receiver Error Passive Interrupt Enable C2RIER.TERRIE 3 Transmitter Error Passive Interrupt Enable C2RIER.BOFFIE 2 BUSOFF Interrupt Enable C2RIER.OVRIE 1 Overrun Interrupt Enable C2RIER.RXFIE 0 Receiver Full Interrupt Enable C2TFLG 0x0206 msCAN12 Transmitter Flag Register C2TFLG.ABTAK2 6 Abort Acknowledge 2 C2TFLG.ABTAK1 5 Abort Acknowledge 1 C2TFLG.ABTAK0 4 Abort Acknowledge 0 C2TFLG.TXE2 2 Transmitter Buffer Empty 2 C2TFLG.TXE1 1 Transmitter Buffer Empty 1 C2TFLG.TXE0 0 Transmitter Buffer Empty 0 C2TCR 0x0207 msCAN12 Transmitter Control Register C2TCR.ABTRQ2 6 Abort Request 2 C2TCR.ABTRQ1 5 Abort Request 1 C2TCR.ABTRQ0 4 Abort Request 0 C2TCR.TXEIE2 2 Transmitter Empty Interrupt Enable 2 C2TCR.TXEIE1 1 Transmitter Empty Interrupt Enable 1 C2TCR.TXEIE0 0 Transmitter Empty Interrupt Enable 0 C2IDAC 0x0208 msCAN12 Identifier Acceptance Control Register C2IDAC.IDAM1 5 Identifier Acceptance Mode 1 C2IDAC.IDAM0 4 Identifier Acceptance Mode 0 C2IDAC.IDHIT2 2 Identifier Acceptance Hit Indicator 2 C2IDAC.IDHIT1 1 Identifier Acceptance Hit Indicator 1 C2IDAC.IDHIT0 0 Identifier Acceptance Hit Indicator 0 RESERVED0209 0x0209 RESERVED RESERVED020A 0x020A RESERVED RESERVED020B 0x020B RESERVED RESERVED020C 0x020C RESERVED RESERVED020D 0x020D RESERVED C2RXERR 0x020E msCAN12 Receive Error Counter C2RXERR.RXERR7 7 C2RXERR.RXERR6 6 C2RXERR.RXERR5 5 C2RXERR.RXERR4 4 C2RXERR.RXERR3 3 C2RXERR.RXERR2 2 C2RXERR.RXERR1 1 C2RXERR.RXERR0 0 C2TXERR 0x020F msCAN12 Transmit Error Counter C2TXERR.TXERR7 7 C2TXERR.TXERR6 6 C2TXERR.TXERR5 5 C2TXERR.TXERR4 4 C2TXERR.TXERR3 3 C2TXERR.TXERR2 2 C2TXERR.TXERR1 1 C2TXERR.TXERR0 0 C2IDAR0 0x0210 msCAN12 Identifier Acceptance Register 0 C2IDAR0.AC7 7 Acceptance Code Bit 7 C2IDAR0.AC6 6 Acceptance Code Bit 6 C2IDAR0.AC5 5 Acceptance Code Bit 5 C2IDAR0.AC4 4 Acceptance Code Bit 4 C2IDAR0.AC3 3 Acceptance Code Bit 3 C2IDAR0.AC2 2 Acceptance Code Bit 2 C2IDAR0.AC1 1 Acceptance Code Bit 1 C2IDAR0.AC0 0 Acceptance Code Bit 0 C2IDAR1 0x0211 msCAN12 Identifier Acceptance Register 1 C2IDAR1.AC7 7 Acceptance Code Bit 7 C2IDAR1.AC6 6 Acceptance Code Bit 6 C2IDAR1.AC5 5 Acceptance Code Bit 5 C2IDAR1.AC4 4 Acceptance Code Bit 4 C2IDAR1.AC3 3 Acceptance Code Bit 3 C2IDAR1.AC2 2 Acceptance Code Bit 2 C2IDAR1.AC1 1 Acceptance Code Bit 1 C2IDAR1.AC0 0 Acceptance Code Bit 0 C2IDAR2 0x0212 msCAN12 Identifier Acceptance Register 2 C2IDAR2.AC7 7 Acceptance Code Bit 7 C2IDAR2.AC6 6 Acceptance Code Bit 6 C2IDAR2.AC5 5 Acceptance Code Bit 5 C2IDAR2.AC4 4 Acceptance Code Bit 4 C2IDAR2.AC3 3 Acceptance Code Bit 3 C2IDAR2.AC2 2 Acceptance Code Bit 2 C2IDAR2.AC1 1 Acceptance Code Bit 1 C2IDAR2.AC0 0 Acceptance Code Bit 0 C2IDAR3 0x0213 msCAN12 Identifier Acceptance Register 3 C2IDAR3.AC7 7 Acceptance Code Bit 7 C2IDAR3.AC6 6 Acceptance Code Bit 6 C2IDAR3.AC5 5 Acceptance Code Bit 5 C2IDAR3.AC4 4 Acceptance Code Bit 4 C2IDAR3.AC3 3 Acceptance Code Bit 3 C2IDAR3.AC2 2 Acceptance Code Bit 2 C2IDAR3.AC1 1 Acceptance Code Bit 1 C2IDAR3.AC0 0 Acceptance Code Bit 0 C2IDMR0 0x0214 msCAN12 Identifier Mask Register 0 C2IDMR0.AM7 7 Acceptance Mask Bit 7 C2IDMR0.AM6 6 Acceptance Mask Bit 6 C2IDMR0.AM5 5 Acceptance Mask Bit 5 C2IDMR0.AM4 4 Acceptance Mask Bit 4 C2IDMR0.AM3 3 Acceptance Mask Bit 3 C2IDMR0.AM2 2 Acceptance Mask Bit 2 C2IDMR0.AM1 1 Acceptance Mask Bit 1 C2IDMR0.AM0 0 Acceptance Mask Bit 0 C2IDMR1 0x0215 msCAN12 Identifier Mask Register 1 C2IDMR1.AM7 7 Acceptance Mask Bit 7 C2IDMR1.AM6 6 Acceptance Mask Bit 6 C2IDMR1.AM5 5 Acceptance Mask Bit 5 C2IDMR1.AM4 4 Acceptance Mask Bit 4 C2IDMR1.AM3 3 Acceptance Mask Bit 3 C2IDMR1.AM2 2 Acceptance Mask Bit 2 C2IDMR1.AM1 1 Acceptance Mask Bit 1 C2IDMR1.AM0 0 Acceptance Mask Bit 0 C2IDMR2 0x0216 msCAN12 Identifier Mask Register 2 C2IDMR2.AM7 7 Acceptance Mask Bit 7 C2IDMR2.AM6 6 Acceptance Mask Bit 6 C2IDMR2.AM5 5 Acceptance Mask Bit 5 C2IDMR2.AM4 4 Acceptance Mask Bit 4 C2IDMR2.AM3 3 Acceptance Mask Bit 3 C2IDMR2.AM2 2 Acceptance Mask Bit 2 C2IDMR2.AM1 1 Acceptance Mask Bit 1 C2IDMR2.AM0 0 Acceptance Mask Bit 0 C2IDMR3 0x0217 msCAN12 Identifier Mask Register 3 C2IDMR3.AM7 7 Acceptance Mask Bit 7 C2IDMR3.AM6 6 Acceptance Mask Bit 6 C2IDMR3.AM5 5 Acceptance Mask Bit 5 C2IDMR3.AM4 4 Acceptance Mask Bit 4 C2IDMR3.AM3 3 Acceptance Mask Bit 3 C2IDMR3.AM2 2 Acceptance Mask Bit 2 C2IDMR3.AM1 1 Acceptance Mask Bit 1 C2IDMR3.AM0 0 Acceptance Mask Bit 0 C2IDAR4 0x0218 msCAN12 Identifier Acceptance Register 4 C2IDAR4.AC7 7 Acceptance Code Bit 7 C2IDAR4.AC6 6 Acceptance Code Bit 6 C2IDAR4.AC5 5 Acceptance Code Bit 5 C2IDAR4.AC4 4 Acceptance Code Bit 4 C2IDAR4.AC3 3 Acceptance Code Bit 3 C2IDAR4.AC2 2 Acceptance Code Bit 2 C2IDAR4.AC1 1 Acceptance Code Bit 1 C2IDAR4.AC0 0 Acceptance Code Bit 0 C2IDAR5 0x0219 msCAN12 Identifier Acceptance Register 5 C2IDAR5.AC7 7 Acceptance Code Bit 7 C2IDAR5.AC6 6 Acceptance Code Bit 6 C2IDAR5.AC5 5 Acceptance Code Bit 5 C2IDAR5.AC4 4 Acceptance Code Bit 4 C2IDAR5.AC3 3 Acceptance Code Bit 3 C2IDAR5.AC2 2 Acceptance Code Bit 2 C2IDAR5.AC1 1 Acceptance Code Bit 1 C2IDAR5.AC0 0 Acceptance Code Bit 0 C2IDAR6 0x021A msCAN12 Identifier Acceptance Register 6 C2IDAR6.AC7 7 Acceptance Code Bit 7 C2IDAR6.AC6 6 Acceptance Code Bit 6 C2IDAR6.AC5 5 Acceptance Code Bit 5 C2IDAR6.AC4 4 Acceptance Code Bit 4 C2IDAR6.AC3 3 Acceptance Code Bit 3 C2IDAR6.AC2 2 Acceptance Code Bit 2 C2IDAR6.AC1 1 Acceptance Code Bit 1 C2IDAR6.AC0 0 Acceptance Code Bit 0 C2IDAR7 0x021B msCAN12 Identifier Acceptance Register 7 C2IDAR7.AC7 7 Acceptance Code Bit 7 C2IDAR7.AC6 6 Acceptance Code Bit 6 C2IDAR7.AC5 5 Acceptance Code Bit 5 C2IDAR7.AC4 4 Acceptance Code Bit 4 C2IDAR7.AC3 3 Acceptance Code Bit 3 C2IDAR7.AC2 2 Acceptance Code Bit 2 C2IDAR7.AC1 1 Acceptance Code Bit 1 C2IDAR7.AC0 0 Acceptance Code Bit 0 C2IDMR4 0x021C msCAN12 Identifier Mask Register 4 C2IDMR4.AM7 7 Acceptance Mask Bit 7 C2IDMR4.AM6 6 Acceptance Mask Bit 6 C2IDMR4.AM5 5 Acceptance Mask Bit 5 C2IDMR4.AM4 4 Acceptance Mask Bit 4 C2IDMR4.AM3 3 Acceptance Mask Bit 3 C2IDMR4.AM2 2 Acceptance Mask Bit 2 C2IDMR4.AM1 1 Acceptance Mask Bit 1 C2IDMR4.AM0 0 Acceptance Mask Bit 0 C2IDMR5 0x021D msCAN12 Identifier Mask Register 5 C2IDMR5.AM7 7 Acceptance Mask Bit 7 C2IDMR5.AM6 6 Acceptance Mask Bit 6 C2IDMR5.AM5 5 Acceptance Mask Bit 5 C2IDMR5.AM4 4 Acceptance Mask Bit 4 C2IDMR5.AM3 3 Acceptance Mask Bit 3 C2IDMR5.AM2 2 Acceptance Mask Bit 2 C2IDMR5.AM1 1 Acceptance Mask Bit 1 C2IDMR5.AM0 0 Acceptance Mask Bit 0 C2IDMR6 0x021E msCAN12 Identifier Mask Register 6 C2IDMR6.AM7 7 Acceptance Mask Bit 7 C2IDMR6.AM6 6 Acceptance Mask Bit 6 C2IDMR6.AM5 5 Acceptance Mask Bit 5 C2IDMR6.AM4 4 Acceptance Mask Bit 4 C2IDMR6.AM3 3 Acceptance Mask Bit 3 C2IDMR6.AM2 2 Acceptance Mask Bit 2 C2IDMR6.AM1 1 Acceptance Mask Bit 1 C2IDMR6.AM0 0 Acceptance Mask Bit 0 C2IDMR7 0x021F msCAN12 Identifier Mask Register 7 C2IDMR7.AM7 7 Acceptance Mask Bit 7 C2IDMR7.AM6 6 Acceptance Mask Bit 6 C2IDMR7.AM5 5 Acceptance Mask Bit 5 C2IDMR7.AM4 4 Acceptance Mask Bit 4 C2IDMR7.AM3 3 Acceptance Mask Bit 3 C2IDMR7.AM2 2 Acceptance Mask Bit 2 C2IDMR7.AM1 1 Acceptance Mask Bit 1 C2IDMR7.AM0 0 Acceptance Mask Bit 0 RESERVED0220 0x0220 RESERVED RESERVED0221 0x0221 RESERVED RESERVED0222 0x0222 RESERVED RESERVED0223 0x0223 RESERVED RESERVED0224 0x0224 RESERVED RESERVED0225 0x0225 RESERVED RESERVED0226 0x0226 RESERVED RESERVED0227 0x0227 RESERVED RESERVED0228 0x0228 RESERVED RESERVED0229 0x0229 RESERVED RESERVED022A 0x022A RESERVED RESERVED022B 0x022B RESERVED RESERVED022C 0x022C RESERVED RESERVED022D 0x022D RESERVED RESERVED022E 0x022E RESERVED RESERVED022F 0x022F RESERVED RESERVED0230 0x0230 RESERVED RESERVED0231 0x0231 RESERVED RESERVED0232 0x0232 RESERVED RESERVED0233 0x0233 RESERVED RESERVED0234 0x0234 RESERVED RESERVED0235 0x0235 RESERVED RESERVED0236 0x0236 RESERVED RESERVED0237 0x0237 RESERVED RESERVED0238 0x0238 RESERVED RESERVED0239 0x0239 RESERVED RESERVED023A 0x023A RESERVED RESERVED023B 0x023B RESERVED RESERVED023C 0x023C RESERVED PCTLCAN2 0x023D msCAN12 Port CAN Control Register PCTLCAN2.PUPCAN 1 Pull-Up Enable Port CAN PCTLCAN2.RDPCAN 0 Reduced Drive Port CAN PORTCAN2 0x023E msCAN12 Port CAN Data Register PORTCAN2.PCAN7 7 Port CAN Data Bit 7 PORTCAN2.PCAN6 6 Port CAN Data Bit 6 PORTCAN2.PCAN5 5 Port CAN Data Bit 5 PORTCAN2.PCAN4 4 Port CAN Data Bit 4 PORTCAN2.PCAN3 3 Port CAN Data Bit 3 PORTCAN2.PCAN2 2 Port CAN Data Bit 2 PORTCAN2.TxCAN 1 PORTCAN2.RxCAN 0 DDRCAN2 0x023F msCAN12 Port CAN Data Direction Register DDRCAN2.DDCAN7 7 DDRCAN2.DDCAN6 6 DDRCAN2.DDCAN5 5 DDRCAN2.DDCAN4 4 DDRCAN2.DDCAN3 3 DDRCAN2.DDCAN2 2 C1MCR0 0x0300 msCAN12 Module Control Register 0 C1MCR0.CSWAI 5 CAN Stops in Wait Mode C1MCR0.SYNCH 4 Synchronized Status C1MCR0.TLNKEN 3 Timer Enable C1MCR0.SLPAK 2 SLEEP Mode Acknowledge C1MCR0.SLPRQ 1 SLEEP request C1MCR0.SFTRES 0 SOFT_RESET C1MCR1 0x0301 msCAN12 Module Control Register 1 C1MCR1.LOOPB 2 Loop Back Self Test Mode C1MCR1.WUPM 1 Wake-Up Mode C1MCR1.CLKSRC 0 msCAN12 Clock Source C1BTR0 0x0302 msCAN12 Bus Timing Register 0 C1BTR0.SJW1 7 Synchronization Jump Width 1 C1BTR0.SJW0 6 Synchronization Jump Width 0 C1BTR0.BRP5 5 Baud Rate Prescaler 5 C1BTR0.BRP4 4 Baud Rate Prescaler 4 C1BTR0.BRP3 3 Baud Rate Prescaler 3 C1BTR0.BRP2 2 Baud Rate Prescaler 2 C1BTR0.BRP1 1 Baud Rate Prescaler 1 C1BTR0.BRP0 0 Baud Rate Prescaler 0 C1BTR1 0x0303 msCAN12 Bus Timing Register 1 C1BTR1.SAMP 7 Sampling C1BTR1.TSEG22 6 Time Segment 22 C1BTR1.TSEG21 5 Time Segment 21 C1BTR1.TSEG20 4 Time Segment 20 C1BTR1.TSEG13 3 Time Segment 13 C1BTR1.TSEG12 2 Time Segment 12 C1BTR1.TSEG11 1 Time Segment 11 C1BTR1.TSEG10 0 Time Segment 10 C1RFLG 0x0304 msCAN12 Receiver Flag Register C1RFLG.WUPIF 7 Wake-up Interrupt Flag C1RFLG.RWRNIF 6 Receiver Warning Interrupt Flag C1RFLG.TWRNIF 5 Transmitter Warning Interrupt Flag C1RFLG.RERRIF 4 Receiver Error Passive Interrupt Flag C1RFLG.TERRIF 3 Transmitter Error Passive Interrupt Flag C1RFLG.BOFFIF 2 BUSOFF Interrupt Flag C1RFLG.OVRIF 1 Overrun Interrupt Flag C1RFLG.RXF 0 Receive Buffer Full C1RIER 0x0305 msCAN12 Receiver Interrupt Enable Register C1RIER.WUPIE 7 Wake-up Interrupt Enable C1RIER.RWRNIE 6 Receiver Warning Interrupt Enable C1RIER.TWRNIE 5 Transmitter Warning Interrupt Enable C1RIER.RERRIE 4 Receiver Error Passive Interrupt Enable C1RIER.TERRIE 3 Transmitter Error Passive Interrupt Enable C1RIER.BOFFIE 2 BUSOFF Interrupt Enable C1RIER.OVRIE 1 Overrun Interrupt Enable C1RIER.RXFIE 0 Receiver Full Interrupt Enable C1TFLG 0x0306 msCAN12 Transmitter Flag Register C1TFLG.ABTAK2 6 Abort Acknowledge 2 C1TFLG.ABTAK1 5 Abort Acknowledge 1 C1TFLG.ABTAK0 4 Abort Acknowledge 0 C1TFLG.TXE2 2 Transmitter Buffer Empty 2 C1TFLG.TXE1 1 Transmitter Buffer Empty 1 C1TFLG.TXE0 0 Transmitter Buffer Empty 0 C1TCR 0x0307 msCAN12 Transmitter Control Register C1TCR.ABTRQ2 6 Abort Request 2 C1TCR.ABTRQ1 5 Abort Request 1 C1TCR.ABTRQ0 4 Abort Request 0 C1TCR.TXEIE2 2 Transmitter Empty Interrupt Enable 2 C1TCR.TXEIE1 1 Transmitter Empty Interrupt Enable 1 C1TCR.TXEIE0 0 Transmitter Empty Interrupt Enable 0 C1IDAC 0x0308 msCAN12 Identifier Acceptance Control Register C1IDAC.IDAM1 5 Identifier Acceptance Mode 1 C1IDAC.IDAM0 4 Identifier Acceptance Mode 0 C1IDAC.IDHIT2 2 Identifier Acceptance Hit Indicator 2 C1IDAC.IDHIT1 1 Identifier Acceptance Hit Indicator 1 C1IDAC.IDHIT0 0 Identifier Acceptance Hit Indicator 0 RESERVED0309 0x0309 RESERVED RESERVED030A 0x030A RESERVED RESERVED030B 0x030B RESERVED RESERVED030C 0x030C RESERVED RESERVED030D 0x030D RESERVED C1RXERR 0x030E msCAN12 Receive Error Counter C1RXERR.RXERR7 7 C1RXERR.RXERR6 6 C1RXERR.RXERR5 5 C1RXERR.RXERR4 4 C1RXERR.RXERR3 3 C1RXERR.RXERR2 2 C1RXERR.RXERR1 1 C1RXERR.RXERR0 0 C1TXERR 0x030F msCAN12 Transmit Error Counter C1TXERR.TXERR7 7 C1TXERR.TXERR6 6 C1TXERR.TXERR5 5 C1TXERR.TXERR4 4 C1TXERR.TXERR3 3 C1TXERR.TXERR2 2 C1TXERR.TXERR1 1 C1TXERR.TXERR0 0 C1IDAR0 0x0310 msCAN12 Identifier Acceptance Register 0 C1IDAR0.AC7 7 Acceptance Code Bit 7 C1IDAR0.AC6 6 Acceptance Code Bit 6 C1IDAR0.AC5 5 Acceptance Code Bit 5 C1IDAR0.AC4 4 Acceptance Code Bit 4 C1IDAR0.AC3 3 Acceptance Code Bit 3 C1IDAR0.AC2 2 Acceptance Code Bit 2 C1IDAR0.AC1 1 Acceptance Code Bit 1 C1IDAR0.AC0 0 Acceptance Code Bit 0 C1IDAR1 0x0311 msCAN12 Identifier Acceptance Register 1 C1IDAR1.AC7 7 Acceptance Code Bit 7 C1IDAR1.AC6 6 Acceptance Code Bit 6 C1IDAR1.AC5 5 Acceptance Code Bit 5 C1IDAR1.AC4 4 Acceptance Code Bit 4 C1IDAR1.AC3 3 Acceptance Code Bit 3 C1IDAR1.AC2 2 Acceptance Code Bit 2 C1IDAR1.AC1 1 Acceptance Code Bit 1 C1IDAR1.AC0 0 Acceptance Code Bit 0 C1IDAR2 0x0312 msCAN12 Identifier Acceptance Register 2 C1IDAR2.AC7 7 Acceptance Code Bit 7 C1IDAR2.AC6 6 Acceptance Code Bit 6 C1IDAR2.AC5 5 Acceptance Code Bit 5 C1IDAR2.AC4 4 Acceptance Code Bit 4 C1IDAR2.AC3 3 Acceptance Code Bit 3 C1IDAR2.AC2 2 Acceptance Code Bit 2 C1IDAR2.AC1 1 Acceptance Code Bit 1 C1IDAR2.AC0 0 Acceptance Code Bit 0 C1IDAR3 0x0313 msCAN12 Identifier Acceptance Register 3 C1IDAR3.AC7 7 Acceptance Code Bit 7 C1IDAR3.AC6 6 Acceptance Code Bit 6 C1IDAR3.AC5 5 Acceptance Code Bit 5 C1IDAR3.AC4 4 Acceptance Code Bit 4 C1IDAR3.AC3 3 Acceptance Code Bit 3 C1IDAR3.AC2 2 Acceptance Code Bit 2 C1IDAR3.AC1 1 Acceptance Code Bit 1 C1IDAR3.AC0 0 Acceptance Code Bit 0 C1IDMR0 0x0314 msCAN12 Identifier Mask Register 0 C1IDMR0.AM7 7 Acceptance Mask Bit 7 C1IDMR0.AM6 6 Acceptance Mask Bit 6 C1IDMR0.AM5 5 Acceptance Mask Bit 5 C1IDMR0.AM4 4 Acceptance Mask Bit 4 C1IDMR0.AM3 3 Acceptance Mask Bit 3 C1IDMR0.AM2 2 Acceptance Mask Bit 2 C1IDMR0.AM1 1 Acceptance Mask Bit 1 C1IDMR0.AM0 0 Acceptance Mask Bit 0 C1IDMR1 0x0315 msCAN12 Identifier Mask Register 1 C1IDMR1.AM7 7 Acceptance Mask Bit 7 C1IDMR1.AM6 6 Acceptance Mask Bit 6 C1IDMR1.AM5 5 Acceptance Mask Bit 5 C1IDMR1.AM4 4 Acceptance Mask Bit 4 C1IDMR1.AM3 3 Acceptance Mask Bit 3 C1IDMR1.AM2 2 Acceptance Mask Bit 2 C1IDMR1.AM1 1 Acceptance Mask Bit 1 C1IDMR1.AM0 0 Acceptance Mask Bit 0 C1IDMR2 0x0316 msCAN12 Identifier Mask Register 2 C1IDMR2.AM7 7 Acceptance Mask Bit 7 C1IDMR2.AM6 6 Acceptance Mask Bit 6 C1IDMR2.AM5 5 Acceptance Mask Bit 5 C1IDMR2.AM4 4 Acceptance Mask Bit 4 C1IDMR2.AM3 3 Acceptance Mask Bit 3 C1IDMR2.AM2 2 Acceptance Mask Bit 2 C1IDMR2.AM1 1 Acceptance Mask Bit 1 C1IDMR2.AM0 0 Acceptance Mask Bit 0 C1IDMR3 0x0317 msCAN12 Identifier Mask Register 3 C1IDMR3.AM7 7 Acceptance Mask Bit 7 C1IDMR3.AM6 6 Acceptance Mask Bit 6 C1IDMR3.AM5 5 Acceptance Mask Bit 5 C1IDMR3.AM4 4 Acceptance Mask Bit 4 C1IDMR3.AM3 3 Acceptance Mask Bit 3 C1IDMR3.AM2 2 Acceptance Mask Bit 2 C1IDMR3.AM1 1 Acceptance Mask Bit 1 C1IDMR3.AM0 0 Acceptance Mask Bit 0 C1IDAR4 0x0318 msCAN12 Identifier Acceptance Register 4 C1IDAR4.AC7 7 Acceptance Code Bit 7 C1IDAR4.AC6 6 Acceptance Code Bit 6 C1IDAR4.AC5 5 Acceptance Code Bit 5 C1IDAR4.AC4 4 Acceptance Code Bit 4 C1IDAR4.AC3 3 Acceptance Code Bit 3 C1IDAR4.AC2 2 Acceptance Code Bit 2 C1IDAR4.AC1 1 Acceptance Code Bit 1 C1IDAR4.AC0 0 Acceptance Code Bit 0 C1IDAR5 0x0319 msCAN12 Identifier Acceptance Register 5 C1IDAR5.AC7 7 Acceptance Code Bit 7 C1IDAR5.AC6 6 Acceptance Code Bit 6 C1IDAR5.AC5 5 Acceptance Code Bit 5 C1IDAR5.AC4 4 Acceptance Code Bit 4 C1IDAR5.AC3 3 Acceptance Code Bit 3 C1IDAR5.AC2 2 Acceptance Code Bit 2 C1IDAR5.AC1 1 Acceptance Code Bit 1 C1IDAR5.AC0 0 Acceptance Code Bit 0 C1IDAR6 0x031A msCAN12 Identifier Acceptance Register 6 C1IDAR6.AC7 7 Acceptance Code Bit 7 C1IDAR6.AC6 6 Acceptance Code Bit 6 C1IDAR6.AC5 5 Acceptance Code Bit 5 C1IDAR6.AC4 4 Acceptance Code Bit 4 C1IDAR6.AC3 3 Acceptance Code Bit 3 C1IDAR6.AC2 2 Acceptance Code Bit 2 C1IDAR6.AC1 1 Acceptance Code Bit 1 C1IDAR6.AC0 0 Acceptance Code Bit 0 C1IDAR7 0x031B msCAN12 Identifier Acceptance Register 7 C1IDAR7.AC7 7 Acceptance Code Bit 7 C1IDAR7.AC6 6 Acceptance Code Bit 6 C1IDAR7.AC5 5 Acceptance Code Bit 5 C1IDAR7.AC4 4 Acceptance Code Bit 4 C1IDAR7.AC3 3 Acceptance Code Bit 3 C1IDAR7.AC2 2 Acceptance Code Bit 2 C1IDAR7.AC1 1 Acceptance Code Bit 1 C1IDAR7.AC0 0 Acceptance Code Bit 0 C1IDMR4 0x031C msCAN12 Identifier Mask Register 4 C1IDMR4.AM7 7 Acceptance Mask Bit 7 C1IDMR4.AM6 6 Acceptance Mask Bit 6 C1IDMR4.AM5 5 Acceptance Mask Bit 5 C1IDMR4.AM4 4 Acceptance Mask Bit 4 C1IDMR4.AM3 3 Acceptance Mask Bit 3 C1IDMR4.AM2 2 Acceptance Mask Bit 2 C1IDMR4.AM1 1 Acceptance Mask Bit 1 C1IDMR4.AM0 0 Acceptance Mask Bit 0 C1IDMR5 0x031D msCAN12 Identifier Mask Register 5 C1IDMR5.AM7 7 Acceptance Mask Bit 7 C1IDMR5.AM6 6 Acceptance Mask Bit 6 C1IDMR5.AM5 5 Acceptance Mask Bit 5 C1IDMR5.AM4 4 Acceptance Mask Bit 4 C1IDMR5.AM3 3 Acceptance Mask Bit 3 C1IDMR5.AM2 2 Acceptance Mask Bit 2 C1IDMR5.AM1 1 Acceptance Mask Bit 1 C1IDMR5.AM0 0 Acceptance Mask Bit 0 C1IDMR6 0x031E msCAN12 Identifier Mask Register 6 C1IDMR6.AM7 7 Acceptance Mask Bit 7 C1IDMR6.AM6 6 Acceptance Mask Bit 6 C1IDMR6.AM5 5 Acceptance Mask Bit 5 C1IDMR6.AM4 4 Acceptance Mask Bit 4 C1IDMR6.AM3 3 Acceptance Mask Bit 3 C1IDMR6.AM2 2 Acceptance Mask Bit 2 C1IDMR6.AM1 1 Acceptance Mask Bit 1 C1IDMR6.AM0 0 Acceptance Mask Bit 0 C1IDMR7 0x031F msCAN12 Identifier Mask Register 7 C1IDMR7.AM7 7 Acceptance Mask Bit 7 C1IDMR7.AM6 6 Acceptance Mask Bit 6 C1IDMR7.AM5 5 Acceptance Mask Bit 5 C1IDMR7.AM4 4 Acceptance Mask Bit 4 C1IDMR7.AM3 3 Acceptance Mask Bit 3 C1IDMR7.AM2 2 Acceptance Mask Bit 2 C1IDMR7.AM1 1 Acceptance Mask Bit 1 C1IDMR7.AM0 0 Acceptance Mask Bit 0 RESERVED0320 0x0320 RESERVED RESERVED0321 0x0321 RESERVED RESERVED0322 0x0322 RESERVED RESERVED0323 0x0323 RESERVED RESERVED0324 0x0324 RESERVED RESERVED0325 0x0325 RESERVED RESERVED0326 0x0326 RESERVED RESERVED0327 0x0327 RESERVED RESERVED0328 0x0328 RESERVED RESERVED0329 0x0329 RESERVED RESERVED032A 0x032A RESERVED RESERVED032B 0x032B RESERVED RESERVED032C 0x032C RESERVED RESERVED032D 0x032D RESERVED RESERVED032E 0x032E RESERVED RESERVED032F 0x032F RESERVED RESERVED0330 0x0330 RESERVED RESERVED0331 0x0331 RESERVED RESERVED0332 0x0332 RESERVED RESERVED0333 0x0333 RESERVED RESERVED0334 0x0334 RESERVED RESERVED0335 0x0335 RESERVED RESERVED0336 0x0336 RESERVED RESERVED0337 0x0337 RESERVED RESERVED0338 0x0338 RESERVED RESERVED0339 0x0339 RESERVED RESERVED033A 0x033A RESERVED RESERVED033B 0x033B RESERVED RESERVED033C 0x033C RESERVED PCTLCAN1 0x033D msCAN12 Port CAN Control Register PCTLCAN1.PUPCAN 1 Pull-Up Enable Port CAN PCTLCAN1.RDPCAN 0 Reduced Drive Port CAN PORTCAN1 0x033E msCAN12 Port CAN Data Register PORTCAN1.PCAN7 7 Port CAN Data Bit 7 PORTCAN1.PCAN6 6 Port CAN Data Bit 6 PORTCAN1.PCAN5 5 Port CAN Data Bit 5 PORTCAN1.PCAN4 4 Port CAN Data Bit 4 PORTCAN1.PCAN3 3 Port CAN Data Bit 3 PORTCAN1.PCAN2 2 Port CAN Data Bit 2 PORTCAN1.TxCAN 1 PORTCAN1.RxCAN 0 DDRCAN1 0x033F msCAN12 Port CAN Data Direction Register DDRCAN1.DDCAN7 7 DDRCAN1.DDCAN6 6 DDRCAN1.DDCAN5 5 DDRCAN1.DDCAN4 4 DDRCAN1.DDCAN3 3 DDRCAN1.DDCAN2 2 .68HC912DT128C ; MEMORY MAP area DATA FSR_0 0x0000:0x0140 area DATA RxFG0 0x0140:0x0150 FOREGROUND RECEIVE BUFFER 0 area DATA Tx00 0x0150:0x0160 TRANSMIT BUFFER 00 area DATA Tx01 0x0160:0x0170 TRANSMIT BUFFER 01 area DATA Tx02 0x0170:0x0180 TRANSMIT BUFFER 02 area BSS RESERVED 0x0180:0x01E2 area DATA FSR_1 0x01E2:0x0240 area DATA RxFG2 0x0240:0x0250 FOREGROUND RECEIVE BUFFER 2 area DATA Tx20 0x0250:0x0260 TRANSMIT BUFFER 20 area DATA Tx21 0x0260:0x0270 TRANSMIT BUFFER 21 area DATA Tx22 0x0270:0x0280 TRANSMIT BUFFER 22 area BSS RESERVED 0x0280:0x0300 area DATA FSR_2 0x0300:0x0340 area DATA RxFG1 0x0340:0x0350 FOREGROUND RECEIVE BUFFER 1 area DATA Tx10 0x0350:0x0360 TRANSMIT BUFFER 10 area DATA Tx11 0x0360:0x0370 TRANSMIT BUFFER 11 area DATA Tx12 0x0370:0x0380 TRANSMIT BUFFER 12 area BSS RESERVED 0x0380:0x0800 area DATA EEPROM 0x0800:0x1000 area BSS RESERVED 0x1000:0x2000 area DATA RAM 0x2000:0x4000 area DATA FLASH_EEPROM_1 0x4000:0x8000 16K Fixed Flash EEPROM area DATA FLASH_EEPROM_2 0x8000:0xA000 16K Page Window Eight 16K Flash EEPROM pages area DATA PROT_BOOT_1 0xA000:0xC000 Protected BOOT at odd programing pages area DATA FLASH_EEPROM_3 0xC000:0xE000 16K Fixed Flash EEPROM area DATA PROT_BOOT_2 0xE000:0xFF00 Protected BOOT area DATA USER_VEC 0xFF00:0x10000 ; Interrupt and reset vector assignments interrupt __RESET 0xFFFE Reset interrupt _COPCTL 0xFFFC Clock monitor fail reset interrupt COP_F_R 0xFFFA COP failure reset interrupt UIT 0xFFF8 Unimplemented instruction trap interrupt SWI 0xFFF6 SWI interrupt XIRQ 0xFFF4 XIRQ interrupt INTCR_IRQEN 0xFFF2 IRQ interrupt RTICTL_RTIE 0xFFF0 Real time interrupt interrupt TMSK1_C0I 0xFFEE Timer channel 0 interrupt TMSK1_C1I 0xFFEC Timer channel 1 interrupt TMSK1_C2I 0xFFEA Timer channel 2 interrupt TMSK1_C3I 0xFFE8 Timer channel 3 interrupt TMSK1_C4I 0xFFE6 Timer channel 4 interrupt TMSK1_C5I 0xFFE4 Timer channel 5 interrupt TMSK1_C6I 0xFFE2 Timer channel 6 interrupt TMSK1_C7I 0xFFE0 Timer channel 7 interrupt TMSK2_TOI 0xFFDE Timer overflow interrupt PACTL_PAOVI 0xFFDC Pulse accumulator overflow interrupt PACTL_PAI 0xFFDA Pulse accumulator input edge interrupt SP0CR1_SPIE 0xFFD8 SPI serial transfer complete interrupt _SC0CR2 0xFFD6 SCI 0 interrupt _SC1CR2 0xFFD4 SCI 1 interrupt ATDxCTL2_ASCIE 0xFFD2 ATD0 or ATD1 interrupt C0RIER_WUPIE 0xFFD0 MSCAN 0 wake-up interrupt KWIEJ_KWIEH 0xFFCE Key wake-up J or H interrupt MCCTL_MCZI 0xFFCC Modulus down counter underflow interrupt PBCTL_PBOVI 0xFFCA Pulse Accumulator B Overflow interrupt C0RIER 0xFFC8 MSCAN 0 errors interrupt C0RIER_RXFIE 0xFFC6 MSCAN 0 receive interrupt C0TCR_TXEIE 0xFFC4 MSCAN 0 transmit interrupt PLLCR_LOCKIE_LHIE 0xFFC2 CGM lock and limp home interrupt IBCR_IBIE 0xFFC0 IIC Bus interrupt C1RIER_WUPIE 0xFFBE MSCAN 1 wake-up interrupt C1RIER 0xFFBC MSCAN 1 errors interrupt C1RIER_RXFIE 0xFFBA MSCAN 1 receive interrupt C1TCR_TXEIE 0xFFB8 MSCAN 1 transmit interrupt C2RIER_WUPIE 0xFFB6 MSCAN 2 wake-up interrupt C2RIER 0xFFB4 MSCAN 2 errors interrupt C2RIER_RXFIE 0xFFB2 MSCAN 2 receive interrupt C2TCR_TXEIE 0xFFB0 MSCAN 2 transmit ; INPUT/ OUTPUT PORTS PORTA 0x0000 Port A Data Register PORTA.PA7 7 Port A Data Bit 7 PORTA.PA6 6 Port A Data Bit 6 PORTA.PA5 5 Port A Data Bit 5 PORTA.PA4 4 Port A Data Bit 4 PORTA.PA3 3 Port A Data Bit 3 PORTA.PA2 2 Port A Data Bit 2 PORTA.PA1 1 Port A Data Bit 1 PORTA.PA0 0 Port A Data Bit 0 PORTB 0x0001 Port B Data Register PORTB.PB7 7 Port B Data Bit 7 PORTB.PB6 6 Port B Data Bit 6 PORTB.PB5 5 Port B Data Bit 5 PORTB.PB4 4 Port B Data Bit 4 PORTB.PB3 3 Port B Data Bit 3 PORTB.PB2 2 Port B Data Bit 2 PORTB.PB1 1 Port B Data Bit 1 PORTB.PB0 0 Port B Data Bit 0 DDRA 0x0002 Port A Data Direction Register DDRA.DDA7 7 Port A Data Direction Bit 7 DDRA.DDA6 6 Port A Data Direction Bit 6 DDRA.DDA5 5 Port A Data Direction Bit 5 DDRA.DDA4 4 Port A Data Direction Bit 4 DDRA.DDA3 3 Port A Data Direction Bit 3 DDRA.DDA2 2 Port A Data Direction Bit 2 DDRA.DDA1 1 Port A Data Direction Bit 1 DDRA.DDA0 0 Port A Data Direction Bit 0 DDRB 0x0003 Port B Data Direction Register DDRB.DDB7 7 Port B Data Direction Bit 7 DDRB.DDB6 6 Port B Data Direction Bit 6 DDRB.DDB5 5 Port B Data Direction Bit 5 DDRB.DDB4 4 Port B Data Direction Bit 4 DDRB.DDB3 3 Port B Data Direction Bit 3 DDRB.DDB2 2 Port B Data Direction Bit 2 DDRB.DDB1 1 Port B Data Direction Bit 1 DDRB.DDB0 0 Port B Data Direction Bit 0 RESERVED0004 0x0004 RESERVED RESERVED0005 0x0005 RESERVED RESERVED0006 0x0006 RESERVED RESERVED0007 0x0007 RESERVED PORTE 0x0008 Port E Data Register PORTE.PE7 7 Port E Data Bit 7 PORTE.PE6 6 Port E Data Bit 6 PORTE.PE5 5 Port E Data Bit 5 PORTE.PE4 4 Port E Data Bit 4 PORTE.PE3 3 Port E Data Bit 3 PORTE.PE2 2 Port E Data Bit 2 PORTE.PE1 1 Port E Data Bit 1 PORTE.PE0 0 Port E Data Bit 0 DDRE 0x0009 Port E Data Direction Register DDRE.DDE7 7 Port E Data Direction Bit 7 DDRE.DDE6 6 Port E Data Direction Bit 6 DDRE.DDE5 5 Port E Data Direction Bit 5 DDRE.DDE4 4 Port E Data Direction Bit 4 DDRE.DDE3 3 Port E Data Direction Bit 3 DDRE.DDE2 2 Port E Data Direction Bit 2 PEAR 0x000A Port E Assignment Register PEAR.NDBE 7 No Data Bus Enable PEAR.CGMTE 6 Clock Generator Module Testing Enable PEAR.PIPOE 5 Pipe Status Signal Output Enable PEAR.NECLK 4 No External E Clock PEAR.LSTRE 3 Low Strobe (LSTRB) Enable PEAR.RDWE 2 Read/Write Enable PEAR.CALE 1 Calibration Reference Enable PEAR.DBENE 0 DBE or Inverted E Clock on PE7 MODE 0x000B Mode Register MODE.SMODN 7 Mode Select Special MODE.MODB 6 Mode Select B MODE.MODA 5 Mode Select A MODE.ESTR 4 E Clock Stretch Enable MODE.IVIS 3 Internal Visibility MODE.EBSWAI 2 External Bus Module Stop in Wait Control MODE.EMK 1 Emulate Port K MODE.EME 0 PUCR 0x000C Pull-Up Control Register PUCR.PUPK 7 Pull-Up Port K Enable PUCR.PUPJ 6 Pull-Up or Pull-Down Port J Enable PUCR.PUPH 5 Pull-Up or Pull-Down Port H Enable PUCR.PUPE 4 Pull-Up Port E Enable PUCR.PUPB 1 Pull-Up Port B Enable PUCR.PUPA 0 Pull-Up Port A Enable RDRIV 0x000D Reduced Drive of I/O Lines RDRIV.RDPK 7 Reduced Drive of Port K RDRIV.RDPJ 6 Reduced Drive of Port J RDRIV.RDPH 5 Reduced Drive of Port H RDRIV.RDPE 4 Reduced Drive of Port E RDRIV.RDPB 1 Reduced Drive of Port B RDRIV.RDPA 0 Reduced Drive of Port A RESERVED000E 0x000E RESERVED RESERVED000F 0x000F RESERVED INITRM 0x0010 Initialization of Internal RAM Position Register INITRM.RAM15 7 Internal RAM map position 15 INITRM.RAM14 6 Internal RAM map position 14 INITRM.RAM13 5 Internal RAM map position 13 INITRG 0x0011 Initialization of Internal Register Position Register INITRG.REG15 7 Internal register map position 15 INITRG.REG14 6 Internal register map position 14 INITRG.REG13 5 Internal register map position 13 INITRG.REG12 4 Internal register map position 12 INITRG.REG11 3 Internal register map position 11 INITEE 0x0012 Initialization of Internal EEPROM Position Register INITEE.EE15 7 Internal EEPROM map position 15 INITEE.EE14 6 Internal EEPROM map position 14 INITEE.EE13 5 Internal EEPROM map position 13 INITEE.EE12 4 Internal EEPROM map position 12 INITEE.EEON 0 internal EEPROM On (Enabled) MISC 0x0013 Miscellaneous Mapping Control Register MISC.ROMTST 7 FLASH EEPROM Test mode MISC.NDRF 6 Narrow Data Bus for Register-Following Map Space MISC.RFSTR1 5 Register Following Stretch 1 MISC.RFSTR0 4 Register Following Stretch 0 MISC.EXSTR1 3 External Access Stretch 1 MISC.EXSTR0 2 External Access Stretch 0 MISC.ROMHM 1 FLASH EEPROM only in second Half of Map MISC.ROMON 0 Enable FLASH EEPROM RTICTL 0x0014 Real-Time Interrupt Control Register RTICTL.RTIE 7 Real Time Interrupt Enable RTICTL.RSWAI 6 RTI and COP Stop While in Wait RTICTL.RSBCK 5 RTI and COP Stop While in Background Debug Mode RTICTL.RTBYP 3 Real Time Interrupt Divider Chain Bypass RTICTL.RTR2 2 Real-Time Interrupt Rate Select 2 RTICTL.RTR1 1 Real-Time Interrupt Rate Select 1 RTICTL.RTR0 0 Real-Time Interrupt Rate Select 0 RTIFLG 0x0015 Real Time Interrupt Flag Register RTIFLG.RTIF 7 Real Time Interrupt Flag COPCTL 0x0016 COP Control Register COPCTL.CME 7 Clock Monitor Enable COPCTL.FCME 6 Force Clock Monitor Enable COPCTL.FCMCOP 5 Force Clock Monitor Reset or COP Watchdog Reset COPCTL.WCOP 4 Window COP mode COPCTL.DISR 3 Disable Resets from COP Watchdog and Clock Monitor COPCTL.CR2 2 COP Watchdog Timer Rate select bit 2 COPCTL.CR1 1 COP Watchdog Timer Rate select bit 1 COPCTL.CR0 0 COP Watchdog Timer Rate select bit 0 COPRST 0x0017 Arm/Reset COP Timer Register ITST0 0x0018 Interrupt Test Register 0 ITST0.ITE6 7 ITST0.ITE8 6 ITST0.ITEA 5 ITST0.ITEC 4 ITST0.ITEE 3 ITST0.ITF0 2 ITST0.ITF2 1 ITST0.ITF4 0 ITST1 0x0019 Interrupt Test Register 1 ITST1.ITD6 7 ITST1.ITD8 6 ITST1.ITDA 5 ITST1.ITDC 4 ITST1.ITDE 3 ITST1.ITE0 2 ITST1.ITE2 1 ITST1.ITE4 0 ITST2 0x001A Interrupt Test Register 2 ITST2.ITC6 7 ITST2.ITC8 6 ITST2.ITCA 5 ITST2.ITCC 4 ITST2.ITCE 3 ITST2.ITD0 2 ITST2.ITD2 1 ITST2.ITD4 0 ITST3 0x001B Interrupt Test Register 3 ITST3.ITB6 7 ITST3.ITB8 6 ITST3.ITBA 5 ITST3.ITBC 4 ITST3.ITBE 3 ITST3.ITC0 2 ITST3.ITC2 1 ITST3.ITC4 0 RESERVED001C 0x001C RESERVED RESERVED001D 0x001D RESERVED INTCR 0x001E Interrupt Control Register INTCR.IRQE 7 IRQ Select Edge Sensitive Only INTCR.IRQEN 6 External IRQ Enable INTCR.DLY 5 Enable Oscillator Start-up Delay on Exit from STOP HPRIO 0x001F Highest Priority I Interrupt HPRIO.PSEL6 6 HPRIO.PSEL5 5 HPRIO.PSEL4 4 HPRIO.PSEL3 3 HPRIO.PSEL2 2 HPRIO.PSEL1 1 BRKCT0 0x0020 Breakpoint Control Register 0 BRKCT0.BKEN1 7 Breakpoint Mode Enable 1 BRKCT0.BKEN0 6 Breakpoint Mode Enable 0 BRKCT0.BKPM 5 Break on Program Addresses BRKCT0.BK1ALE 3 Breakpoint 1 Range Control BRKCT0.BK0ALE 2 Breakpoint 0 Range Control BRKCT1 0x0021 Breakpoint Control Register 1 BRKCT1.BKDBE 6 Enable Data Bus BRKCT1.BKMBH 5 Breakpoint Mask High BRKCT1.BKMBL 4 Breakpoint Mask Low BRKCT1.BK1RWE 3 R/W Compare Enable BRKCT1.BK1RW 2 R/W Compare Value BRKCT1.BK0RWE 1 R/W Compare Enable BRKCT1.BK0RW 0 R/W Compare Value BRKAH 0x0022 Breakpoint Address Register, High Byte BRKAL 0x0023 Breakpoint Address Register, Low Byte BRKDH 0x0024 Breakpoint Data Register, High Byte BRKDL 0x0025 Breakpoint Data Register, Low Byte RESERVED0026 0x0026 RESERVED RESERVED0027 0x0027 RESERVED PORTJ 0x0028 Port J Data Register PORTJ.PJ7 7 Port J Data Bit 7 PORTJ.PJ6 6 Port J Data Bit 6 PORTJ.PJ5 5 Port J Data Bit 5 PORTJ.PJ4 4 Port J Data Bit 4 PORTJ.PJ3 3 Port J Data Bit 3 PORTJ.PJ2 2 Port J Data Bit 2 PORTJ.PJ1 1 Port J Data Bit 1 PORTJ.PJ0 0 Port J Data Bit 0 PORTH 0x0029 Port H Data Register PORTH.PH7 7 Port H Data Bit 7 PORTH.PH6 6 Port H Data Bit 6 PORTH.PH5 5 Port H Data Bit 5 PORTH.PH4 4 Port H Data Bit 4 PORTH.PH3 3 Port H Data Bit 3 PORTH.PH2 2 Port H Data Bit 2 PORTH.PH1 1 Port H Data Bit 1 PORTH.PH0 0 Port H Data Bit 0 DDRJ 0x002A Port J Data Direction Register DDRJ.DDRJ7 7 Data Direction Port J Bit 7 DDRJ.DDRJ6 6 Data Direction Port J Bit 6 DDRJ.DDRJ5 5 Data Direction Port J Bit 5 DDRJ.DDRJ4 4 Data Direction Port J Bit 4 DDRJ.DDRJ3 3 Data Direction Port J Bit 3 DDRJ.DDRJ2 2 Data Direction Port J Bit 2 DDRJ.DDRJ1 1 Data Direction Port J Bit 1 DDRJ.DDRJ0 0 Data Direction Port J Bit 0 DDRH 0x002B Port J Data Direction Register DDRH.DDRH7 7 Data Direction Port H Bit 7 DDRH.DDRH6 6 Data Direction Port H Bit 6 DDRH.DDRH5 5 Data Direction Port H Bit 5 DDRH.DDRH4 4 Data Direction Port H Bit 4 DDRH.DDRH3 3 Data Direction Port H Bit 3 DDRH.DDRH2 2 Data Direction Port H Bit 2 DDRH.DDRH1 1 Data Direction Port H Bit 1 DDRH.DDRH0 0 Data Direction Port H Bit 0 KWIEJ 0x002C Key Wake-up Port J Interrupt Enable Register KWIEJ.KWIEJ7 7 Key Wake-up Port J Interrupt Enable 7 KWIEJ.KWIEJ6 6 Key Wake-up Port J Interrupt Enable 6 KWIEJ.KWIEJ5 5 Key Wake-up Port J Interrupt Enable 5 KWIEJ.KWIEJ4 4 Key Wake-up Port J Interrupt Enable 4 KWIEJ.KWIEJ3 3 Key Wake-up Port J Interrupt Enable 3 KWIEJ.KWIEJ2 2 Key Wake-up Port J Interrupt Enable 2 KWIEJ.KWIEJ1 1 Key Wake-up Port J Interrupt Enable 1 KWIEJ.KWIEJ0 0 Key Wake-up Port J Interrupt Enable 0 KWIEH 0x002D Key Wake-up Port H Interrupt Enable Register KWIEH.KWIEH7 7 Key Wake-up Port H Interrupt Enable 7 KWIEH.KWIEH6 6 Key Wake-up Port H Interrupt Enable 6 KWIEH.KWIEH5 5 Key Wake-up Port H Interrupt Enable 5 KWIEH.KWIEH4 4 Key Wake-up Port H Interrupt Enable 4 KWIEH.KWIEH3 3 Key Wake-up Port H Interrupt Enable 3 KWIEH.KWIEH2 2 Key Wake-up Port H Interrupt Enable 2 KWIEH.KWIEH1 1 Key Wake-up Port H Interrupt Enable 1 KWIEH.KWIEH0 0 Key Wake-up Port H Interrupt Enable 0 KWIFJ 0x002E Key Wake-up Port J Flag Register KWIFJ.KWIFJ7 7 Key Wake-up Port J Flag 7 KWIFJ.KWIFJ6 6 Key Wake-up Port J Flag 6 KWIFJ.KWIFJ5 5 Key Wake-up Port J Flag 5 KWIFJ.KWIFJ4 4 Key Wake-up Port J Flag 4 KWIFJ.KWIFJ3 3 Key Wake-up Port J Flag 3 KWIFJ.KWIFJ2 2 Key Wake-up Port J Flag 2 KWIFJ.KWIFJ1 1 Key Wake-up Port J Flag 1 KWIFJ.KWIFJ0 0 Key Wake-up Port J Flag 0 KWIFH 0x002F Key Wake-up Port H Flag Register KWIFH.KWIFH7 7 Key Wake-up Port H Flag 7 KWIFH.KWIFH6 6 Key Wake-up Port H Flag 6 KWIFH.KWIFH5 5 Key Wake-up Port H Flag 5 KWIFH.KWIFH4 4 Key Wake-up Port H Flag 4 KWIFH.KWIFH3 3 Key Wake-up Port H Flag 3 KWIFH.KWIFH2 2 Key Wake-up Port H Flag 2 KWIFH.KWIFH1 1 Key Wake-up Port H Flag 1 KWIFH.KWIFH0 0 Key Wake-up Port H Flag 0 KWPJ 0x0030 Key Wake-up Port J Polarity Register KWPJ.KWPJ7 7 Key Wake-up Port J Polarity Select 7 KWPJ.KWPJ6 6 Key Wake-up Port J Polarity Select 6 KWPJ.KWPJ5 5 Key Wake-up Port J Polarity Select 5 KWPJ.KWPJ4 4 Key Wake-up Port J Polarity Select 4 KWPJ.KWPJ3 3 Key Wake-up Port J Polarity Select 3 KWPJ.KWPJ2 2 Key Wake-up Port J Polarity Select 2 KWPJ.KWPJ1 1 Key Wake-up Port J Polarity Select 1 KWPJ.KWPJ0 0 Key Wake-up Port J Polarity Select 0 KWPH 0x0031 Key Wake-up Port H Polarity Register KWPH.KWPH7 7 Key Wake-up Port H Polarity Select 7 KWPH.KWPH6 6 Key Wake-up Port H Polarity Select 6 KWPH.KWPH5 5 Key Wake-up Port H Polarity Select 5 KWPH.KWPH4 4 Key Wake-up Port H Polarity Select 4 KWPH.KWPH3 3 Key Wake-up Port H Polarity Select 3 KWPH.KWPH2 2 Key Wake-up Port H Polarity Select 2 KWPH.KWPH1 1 Key Wake-up Port H Polarity Select 1 KWPH.KWPH0 0 Key Wake-up Port H Polarity Select 0 RESERVED0032 0x0032 RESERVED RESERVED0033 0x0033 RESERVED RESERVED0034 0x0034 RESERVED RESERVED0035 0x0035 RESERVED RESERVED0036 0x0036 RESERVED RESERVED0037 0x0037 RESERVED SYNR 0x0038 Synthesizer Register SYNR.SYN5 5 SYNR.SYN4 4 SYNR.SYN3 3 SYNR.SYN2 2 SYNR.SYN1 1 SYNR.SYN0 0 REFDV 0x0039 Reference Divider Register REFDV.REFDV2 2 REFDV.REFDV1 1 REFDV.REFDV0 0 CGTFLG 0x003A Clock Generator Test Register CGTFLG.TSTOUT7 7 CGTFLG.TSTOUT6 6 CGTFLG.TSTOUT5 5 CGTFLG.TSTOUT4 4 CGTFLG.TSTOUT3 3 CGTFLG.TSTOUT2 2 CGTFLG.TSTOUT1 1 CGTFLG.TSTOUT0 0 PLLFLG 0x003B PLL Flags PLLFLG.LOCKIF 7 PLL Lock Interrupt Flag PLLFLG.LOCK 6 Locked Phase Lock Loop Circuit PLLFLG.LHIF 1 Limp-Home Interrupt Flag PLLFLG.LHOME 0 Limp-Home Mode Status PLLCR 0x003C PLL Control Register PLLCR.LOCKIE 7 PLL LOCK Interrupt Enable PLLCR.PLLON 6 Phase Lock Loop On PLLCR.AUTO 5 Automatic Bandwidth Control PLLCR.ACQ 4 Not in Acquisition PLLCR.PSTP 2 Pseudo-STOP Enable PLLCR.LHIE 1 Limp-Home Interrupt Enable PLLCR.NOLHM 0 No Limp-Home Mode CLKSEL 0x003D Clock Generator Clock select Register CLKSEL.BCSP 6 Bus Clock Select PLL CLKSEL.BCSS 5 Bus Clock Select Slow CLKSEL.MCS 2 Module Clock Select SLOW 0x003E Slow mode Divider Register SLOW.SLDV5 5 SLOW.SLDV4 4 SLOW.SLDV3 3 SLOW.SLDV2 2 SLOW.SLDV1 1 SLOW.SLDV0 0 CGTCTL 0x003F CGTCTL CGTCTL.OPNLE 7 CGTCTL.TRK 6 CGTCTL.TSTCLKE 5 CGTCTL.TST4 4 CGTCTL.TST3 3 CGTCTL.TST2 2 CGTCTL.TST1 1 CGTCTL.TST0 0 PWCLK 0x0040 PWM Clocks and Concatenate PWCLK.CON23 7 Concatenate PWM Channels 2 and 3 PWCLK.CON01 6 Concatenate PWM Channels 0 and 1 PWCLK.PCKA2 5 Prescaler for Clock A 2 PWCLK.PCKA1 4 Prescaler for Clock A 1 PWCLK.PCKA0 3 Prescaler for Clock A 0 PWCLK.PCKB2 2 Prescaler for Clock B 2 PWCLK.PCKB1 1 Prescaler for Clock B 1 PWCLK.PCKB0 0 Prescaler for Clock B 0 PWPOL 0x0041 PWM Clock Select and Polarity PWPOL.PCLK3 7 PWM Channel 3 Clock Select PWPOL.PCLK2 6 PWM Channel 2 Clock Select PWPOL.PCLK1 5 PWM Channel 1 Clock Select PWPOL.PCLK0 4 PWM Channel 0 Clock Select PWPOL.PPOL3 3 PWM Channel 3 Polarity PWPOL.PPOL2 2 PWM Channel 2 Polarity PWPOL.PPOL1 1 PWM Channel 1 Polarity PWPOL.PPOL0 0 PWM Channel 0 Polarity PWEN 0x0042 PWM Enable PWEN.PWEN3 3 PWM Channel 3 Enable PWEN.PWEN2 2 PWM Channel 2 Enable PWEN.PWEN1 1 PWM Channel 1 Enable PWEN.PWEN0 0 PWM Channel 0 Enable PWPRES 0x0043 PWM Prescale Counter PWSCAL0 0x0044 PWM Scale Register 0 PWSCNT0 0x0045 PWM Scale Counter 0 Value PWSCAL1 0x0046 PWM Scale Register 1 PWSCNT1 0x0047 PWM Scale Counter 1 Value PWCNT0 0x0048 PWM Channel Counter 0 PWCNT1 0x0049 PWM Channel Counter 1 PWCNT2 0x004A PWM Channel Counter 2 PWCNT3 0x004B PWM Channel Counter 3 PWPER0 0x004C PWM Channel Period Register 0 PWPER1 0x004D PWM Channel Period Register 1 PWPER2 0x004E PWM Channel Period Register 2 PWPER3 0x004F PWM Channel Period Register 3 PWDTY0 0x0050 PWM Channel Duty Register 0 PWDTY1 0x0051 PWM Channel Duty Register 1 PWDTY2 0x0052 PWM Channel Duty Register 2 PWDTY3 0x0053 PWM Channel Duty Register 3 PWCTL 0x0054 PWM Control Register PWCTL.PSWAI 4 PWM Halts while in Wait Mode PWCTL.CENTR 3 Center-Aligned Output Mode PWCTL.RDPP 2 Reduced Drive of Port P PWCTL.PUPP 1 Pull-Up Port P Enable PWCTL.PSBCK 0 PWM Stops while in Background Mode PWTST 0x0055 PWM Special Mode Register ("Test") PWTST.DISCR 7 Disable Reset of Channel Counter on Write to Channel Counter PWTST.DISCP 6 Disable Compare Count Period PWTST.DISCAL 5 Disable Load of Scale-Counters on Write to the Associated Scale-Registers PORTP 0x0056 Port P Data Register PORTP.PP7 7 Port P Data Bit 7 PORTP.PP6 6 Port P Data Bit 6 PORTP.PP5 5 Port P Data Bit 5 PORTP.PP4 4 Port P Data Bit 4 PORTP.PP3 3 Port P Data Bit 3 PORTP.PP2 2 Port P Data Bit 2 PORTP.PP1 1 Port P Data Bit 1 PORTP.PP0 0 Port P Data Bit 0 DDRP 0x0057 Port P Data Direction Register DDRP.DDP7 7 Port P Data Direction Bit 7 DDRP.DDP6 6 Port P Data Direction Bit 6 DDRP.DDP5 5 Port P Data Direction Bit 5 DDRP.DDP4 4 Port P Data Direction Bit 4 DDRP.DDP3 3 Port P Data Direction Bit 3 DDRP.DDP2 2 Port P Data Direction Bit 2 DDRP.DDP1 1 Port P Data Direction Bit 1 DDRP.DDP0 0 Port P Data Direction Bit 0 RESERVED0058 0x0058 RESERVED RESERVED0059 0x0059 RESERVED RESERVED005A 0x005A RESERVED RESERVED005B 0x005B RESERVED RESERVED005C 0x005C RESERVED RESERVED005D 0x005D RESERVED RESERVED005E 0x005E RESERVED RESERVED005F 0x005F RESERVED RESERVED0060 0x0060 RESERVED RESERVED0061 0x0061 RESERVED ATD0CTL2 0x0062 ATD0 Control Register 2 ATD0CTL2.ADPU 7 ATD Disable ATD0CTL2.AFFC 6 ATD Fast Flag Clear All ATD0CTL2.ASWAI 5 ATD Wait Mode ATD0CTL2.DJM 4 Result Register Data Justification Mode ATD0CTL2.DSGN 3 Signed/Unsigned Result Data Mode ATD0CTL2.ASCIE 1 ATD Sequence Complete Interrupt Enable ATD0CTL2.ASCIF 0 ATD Sequence Complete Interrupt Flag ATD0CTL3 0x0063 ATD0 Control Register 3 ATD0CTL3.S1C 3 Conversion Sequence Length (Least Significant Bit) ATD0CTL3.FIFO 2 Result Register FIFO Mode ATD0CTL3.FRZ1 1 Background Debug (Freeze) Enable 1 ATD0CTL3.FRZ0 0 Background Debug (Freeze) Enable 0 ATD0CTL4 0x0064 ATD0 Control Register 4 ATD0CTL4.RES10 7 10 bit Mode ATD0CTL4.SMP1 6 Select Sample Time 1 ATD0CTL4.SMP0 5 Select Sample Time 0 ATD0CTL4.PRS4 4 Select Divide-By Factor for ATD P-Clock Prescaler 4 ATD0CTL4.PRS3 3 Select Divide-By Factor for ATD P-Clock Prescaler 3 ATD0CTL4.PRS2 2 Select Divide-By Factor for ATD P-Clock Prescaler 2 ATD0CTL4.PRS1 1 Select Divide-By Factor for ATD P-Clock Prescaler 1 ATD0CTL4.PRS0 0 Select Divide-By Factor for ATD P-Clock Prescaler 0 ATD0CTL5 0x0065 ATD0 Control Register 5 ATD0CTL5.S8CM 6 Select 8 Channel Mode ATD0CTL5.SCAN 5 Enable Continuous Channel Scan ATD0CTL5.MULT 4 Enable Multichannel Conversion ATD0CTL5.CD 3 Channel Select for Conversion D ATD0CTL5.CC 2 Channel Select for Conversion C ATD0CTL5.CB 1 Channel Select for Conversion B ATD0CTL5.CA 0 Channel Select for Conversion A ATD0STAT0 0x0066 ATD0 Status Register ATD0STAT0.SCF 7 Sequence Complete Flag ATD0STAT0.CC2 2 Conversion Counter for Current Sequence of Four or Eight Conversions 2 ATD0STAT0.CC1 1 Conversion Counter for Current Sequence of Four or Eight Conversions 1 ATD0STAT0.CC0 0 Conversion Counter for Current Sequence of Four or Eight Conversions 0 ATD0STAT1 0x0067 ATD0 Status Register ATD0STAT1.CCF7 7 Conversion Complete Flag 7 ATD0STAT1.CCF6 6 Conversion Complete Flag 6 ATD0STAT1.CCF5 5 Conversion Complete Flag 5 ATD0STAT1.CCF4 4 Conversion Complete Flag 4 ATD0STAT1.CCF3 3 Conversion Complete Flag 3 ATD0STAT1.CCF2 2 Conversion Complete Flag 2 ATD0STAT1.CCF1 1 Conversion Complete Flag 1 ATD0STAT1.CCF0 0 Conversion Complete Flag 0 ATD0TESTH 0x0068 ATD0 Test Register ATD0TESTH.SAR9 7 SAR Data 9 ATD0TESTH.SAR8 6 SAR Data 8 ATD0TESTH.SAR7 5 SAR Data 7 ATD0TESTH.SAR6 4 SAR Data 6 ATD0TESTH.SAR5 3 SAR Data 5 ATD0TESTH.SAR4 2 SAR Data 4 ATD0TESTH.SAR3 1 SAR Data 3 ATD0TESTH.SAR2 0 SAR Data 2 ATD0TESTL 0x0069 ATD0 Test Register ATD0TESTL.SAR1 7 SAR Data 1 ATD0TESTL.SAR0 6 SAR Data 0 ATD0TESTL.RST 5 Module Reset Bit ATD0TESTL.TSTOUT 4 Multiplex Output of TST[3:0] (Factory Use) ATD0TESTL.TST3 3 Test Bit 3 ATD0TESTL.TST2 2 Test Bit 2 ATD0TESTL.TST1 1 Test Bit 1 ATD0TESTL.TST0 0 Test Bit 0 RESERVED006A 0x006A RESERVED RESERVED006B 0x006B RESERVED RESERVED006C 0x006C RESERVED RESERVED006D 0x006D RESERVED RESERVED006E 0x006E RESERVED PORTAD0 0x006F Port AD0 Data Input Register PORTAD0.PAD07 7 Port AD0 Data Input Bit 7 PORTAD0.PAD06 6 Port AD0 Data Input Bit 6 PORTAD0.PAD05 5 Port AD0 Data Input Bit 5 PORTAD0.PAD04 4 Port AD0 Data Input Bit 4 PORTAD0.PAD03 3 Port AD0 Data Input Bit 3 PORTAD0.PAD02 2 Port AD0 Data Input Bit 2 PORTAD0.PAD01 1 Port AD0 Data Input Bit 1 PORTAD0.PAD00 0 Port AD0 Data Input Bit 0 ADR00H 0x0070 A/D Conversion Result Register High 0 ADR00L 0x0071 A/D Conversion Result Register Low 0 ADR01H 0x0072 A/D Conversion Result Register High 1 ADR01L 0x0073 A/D Conversion Result Register Low 1 ADR02H 0x0074 A/D Conversion Result Register High 2 ADR02L 0x0075 A/D Conversion Result Register Low 2 ADR03H 0x0076 A/D Conversion Result Register High 3 ADR03L 0x0077 A/D Conversion Result Register Low 3 ADR04H 0x0078 A/D Conversion Result Register High 4 ADR04L 0x0079 A/D Conversion Result Register Low 4 ADR05H 0x007A A/D Conversion Result Register High 5 ADR05L 0x007B A/D Conversion Result Register Low 5 ADR06H 0x007C A/D Conversion Result Register High 6 ADR06L 0x007D A/D Conversion Result Register Low 6 ADR07H 0x007E A/D Conversion Result Register High 7 ADR07L 0x007F A/D Conversion Result Register Low 7 TIOS 0x0080 Timer Input Capture/Output Compare Select TIOS.IOS7 7 Input Capture or Output Compare Channel Configuration 7 TIOS.IOS6 6 Input Capture or Output Compare Channel Configuration 6 TIOS.IOS5 5 Input Capture or Output Compare Channel Configuration 5 TIOS.IOS4 4 Input Capture or Output Compare Channel Configuration 4 TIOS.IOS3 3 Input Capture or Output Compare Channel Configuration 3 TIOS.IOS2 2 Input Capture or Output Compare Channel Configuration 2 TIOS.IOS1 1 Input Capture or Output Compare Channel Configuration 1 TIOS.IOS0 0 Input Capture or Output Compare Channel Configuration 0 CFORC 0x0081 Timer Compare Force Register CFORC.FOC7 7 Force Output Compare Action for Channel 7 CFORC.FOC6 6 Force Output Compare Action for Channel 6 CFORC.FOC5 5 Force Output Compare Action for Channel 5 CFORC.FOC4 4 Force Output Compare Action for Channel 4 CFORC.FOC3 3 Force Output Compare Action for Channel 3 CFORC.FOC2 2 Force Output Compare Action for Channel 2 CFORC.FOC1 1 Force Output Compare Action for Channel 1 CFORC.FOC0 0 Force Output Compare Action for Channel 0 OC7M 0x0082 Output Compare 7 Mask Register OC7M.OC7M7 7 OC7M.OC7M6 6 OC7M.OC7M5 5 OC7M.OC7M4 4 OC7M.OC7M3 3 OC7M.OC7M2 2 OC7M.OC7M1 1 OC7M.OC7M0 0 OC7D 0x0083 Output Compare 7 Data Register OC7D.OC7D7 7 OC7D.OC7D6 6 OC7D.OC7D5 5 OC7D.OC7D4 4 OC7D.OC7D3 3 OC7D.OC7D2 2 OC7D.OC7D1 1 OC7D.OC7D0 0 TCNTH 0x0084 Timer Count Register High TCNTL 0x0085 Timer Count Register Low TSCR 0x0086 Timer System Control Register TSCR.TEN 7 Timer Enable TSCR.TSWAI 6 Timer Module Stops While in Wait TSCR.TSBCK 5 Timer and Modulus Counter Stop While in Background Mode TSCR.TFFCA 4 Timer Fast Flag Clear All RESERVED0087 0x0087 RESERVED TCTL1 0x0088 Timer Control Register 1 TCTL1.OM7 7 Output Mode 7 TCTL1.OL7 6 Output Level 7 TCTL1.OM6 5 Output Mode 6 TCTL1.OL6 4 Output Level 6 TCTL1.OM5 3 Output Mode 5 TCTL1.OL5 2 Output Level 5 TCTL1.OM4 1 Output Mode 4 TCTL1.OL4 0 Output Level 4 TCTL2 0x0089 Timer Control Register 2 TCTL2.OM3 7 Output Mode 3 TCTL2.OL3 6 Output Level 3 TCTL2.OM2 5 Output Mode 2 TCTL2.OL2 4 Output Level 2 TCTL2.OM1 3 Output Mode 1 TCTL2.OL1 2 Output Level 1 TCTL2.OM0 1 Output Mode 0 TCTL2.OL0 0 Output Level 0 TCTL3 0x008A Timer Control Register 3 TCTL3.EDG7B 7 Input Capture Edge Control 7B TCTL3.EDG7A 6 Input Capture Edge Control 7A TCTL3.EDG6B 5 Input Capture Edge Control 6B TCTL3.EDG6A 4 Input Capture Edge Control 6A TCTL3.EDG5B 3 Input Capture Edge Control 5B TCTL3.EDG5A 2 Input Capture Edge Control 5A TCTL3.EDG4B 1 Input Capture Edge Control 4B TCTL3.EDG4A 0 Input Capture Edge Control 4A TCTL4 0x008B Timer Control Register 4 TCTL4.EDG3B 7 Input Capture Edge Control 3B TCTL4.EDG3A 6 Input Capture Edge Control 3A TCTL4.EDG2B 5 Input Capture Edge Control 2B TCTL4.EDG2A 4 Input Capture Edge Control 2A TCTL4.EDG1B 3 Input Capture Edge Control 1B TCTL4.EDG1A 2 Input Capture Edge Control 1A TCTL4.EDG0B 1 Input Capture Edge Control 0B TCTL4.EDG0A 0 Input Capture Edge Control 0A TMSK1 0x008C Timer Interrupt Mask 1 TMSK1.C7I 7 Input Capture/Output Compare 7 Interrupt Enable TMSK1.C6I 6 Input Capture/Output Compare 6 Interrupt Enable TMSK1.C5I 5 Input Capture/Output Compare 5 Interrupt Enable TMSK1.C4I 4 Input Capture/Output Compare 4 Interrupt Enable TMSK1.C3I 3 Input Capture/Output Compare 3 Interrupt Enable TMSK1.C2I 2 Input Capture/Output Compare 2 Interrupt Enable TMSK1.C1I 1 Input Capture/Output Compare 1 Interrupt Enable TMSK1.C0I 0 Input Capture/Output Compare 0 Interrupt Enable TMSK2 0x008D Timer Interrupt Mask 2 TMSK2.TOI 7 Timer Overflow Interrupt Enable TMSK2.PUPT 5 Timer Port Pull-Up Resistor Enable TMSK2.RDPT 4 Timer Port Drive Reduction TMSK2.TCRE 3 Timer Counter Reset Enable TMSK2.PR2 2 Timer Prescaler Select 2 TMSK2.PR1 1 Timer Prescaler Select 1 TMSK2.PR0 0 Timer Prescaler Select 0 TFLG1 0x008E Main Timer Interrupt Flag 1 TFLG1.C7F 7 Input Capture/Output Compare Channel 7 Flag TFLG1.C6F 6 Input Capture/Output Compare Channel 6 Flag TFLG1.C5F 5 Input Capture/Output Compare Channel 5 Flag TFLG1.C4F 4 Input Capture/Output Compare Channel 4 Flag TFLG1.C3F 3 Input Capture/Output Compare Channel 3 Flag TFLG1.C2F 2 Input Capture/Output Compare Channel 2 Flag TFLG1.C1F 1 Input Capture/Output Compare Channel 1 Flag TFLG1.C0F 0 Input Capture/Output Compare Channel 0 Flag TFLG2 0x008F Main Timer Interrupt Flag 2 TFLG2.TOF 7 Timer Overflow Flag TC0H 0x0090 Timer Input Capture/Output Compare Register 0 High TC0L 0x0091 Timer Input Capture/Output Compare Register 0 Low TC1H 0x0092 Timer Input Capture/Output Compare Register 1 High TC1L 0x0093 Timer Input Capture/Output Compare Register 1 Low TC2H 0x0094 Timer Input Capture/Output Compare Register 2 High TC2L 0x0095 Timer Input Capture/Output Compare Register 2 Low TC3H 0x0096 Timer Input Capture/Output Compare Register 3 High TC3L 0x0097 Timer Input Capture/Output Compare Register 3 Low TC4H 0x0098 Timer Input Capture/Output Compare Register 4 High TC4L 0x0099 Timer Input Capture/Output Compare Register 4 Low TC5H 0x009A Timer Input Capture/Output Compare Register 5 High TC5L 0x009B Timer Input Capture/Output Compare Register 5 Low TC6H 0x009C Timer Input Capture/Output Compare Register 6 High TC6L 0x009D Timer Input Capture/Output Compare Register 6 Low TC7H 0x009E Timer Input Capture/Output Compare Register 7 High TC7L 0x009F Timer Input Capture/Output Compare Register 7 Low PACTL 0x00A0 16-Bit Pulse Accumulator A Control Register PACTL.PAEN 6 Pulse Accumulator A System Enable PACTL.PAMOD 5 Pulse Accumulator Mode PACTL.PEDGE 4 Pulse Accumulator Edge Control PACTL.CLK1 3 Clock Select Bit 1 PACTL.CLK0 2 Clock Select Bit 0 PACTL.PAOVI 1 Pulse Accumulator A Overflow Interrupt enable PACTL.PAI 0 Pulse Accumulator Input Interrupt enable PAFLG 0x00A1 Pulse Accumulator A Flag Register PAFLG.PAOVF 1 Pulse Accumulator A Overflow Flag PAFLG.PAIF 0 Pulse Accumulator Input edge Flag PACN3 0x00A2 Pulse Accumulators Count Register 3 PACN2 0x00A3 Pulse Accumulators Count Register 2 PACN1 0x00A4 Pulse Accumulators Count Register 1 PACN0 0x00A5 Pulse Accumulators Count Register 0 MCCTL 0x00A6 16-Bit Modulus Down-Counter Control Register MCCTL.MCZI 7 Modulus Counter Underflow Interrupt Enable MCCTL.MODMC 6 Modulus Mode Enable MCCTL.RDMCL 5 Read Modulus Down-Counter Load MCCTL.ICLAT 4 Input Capture Force Latch Action MCCTL.FLMC 3 Force Load Register into the Modulus Counter Count Register MCCTL.MCEN 2 Modulus Down-Counter Enable MCCTL.MCPR1 1 Modulus Counter Prescaler select 1 MCCTL.MCPR0 0 Modulus Counter Prescaler select 0 MCFLG 0x00A7 16-Bit Modulus Down-Counter FLAG Register MCFLG.MCZF 7 Modulus Counter Underflow Interrupt Flag MCFLG.POLF3 3 First Input Capture Polarity Status 3 MCFLG.POLF2 2 First Input Capture Polarity Status 2 MCFLG.POLF1 1 First Input Capture Polarity Status 1 MCFLG.POLF0 0 First Input Capture Polarity Status 0 ICPACR 0x00A8 Input Control Pulse Accumulators Control Register ICPACR.PA3EN 3 8-Bit Pulse Accumulator 3 Enable ICPACR.PA2EN 2 8-Bit Pulse Accumulator 2 Enable ICPACR.PA1EN 1 8-Bit Pulse Accumulator 1 Enable ICPACR.PA0EN 0 8-Bit Pulse Accumulator 0 Enable DLYCT 0x00A9 Delay Counter Control Register DLYCT.DLY1 1 Delay Counter Select 1 DLYCT.DLY0 0 Delay Counter Select 0 ICOVW 0x00AA Input Control Overwrite Register ICOVW.NOVW7 7 No Input Capture Overwrite 7 ICOVW.NOVW6 6 No Input Capture Overwrite 6 ICOVW.NOVW5 5 No Input Capture Overwrite 5 ICOVW.NOVW4 4 No Input Capture Overwrite 4 ICOVW.NOVW3 3 No Input Capture Overwrite 3 ICOVW.NOVW2 2 No Input Capture Overwrite 2 ICOVW.NOVW1 1 No Input Capture Overwrite 1 ICOVW.NOVW0 0 No Input Capture Overwrite 0 ICSYS 0x00AB Input Control System Control Register ICSYS.SH37 7 Share Input action of Input Capture Channels 3 and 7 ICSYS.SH26 6 Share Input action of Input Capture Channels 2 and 6 ICSYS.SH15 5 Share Input action of Input Capture Channels 1 and 5 ICSYS.SH04 4 Share Input action of Input Capture Channels 0 and 4 ICSYS.TFMOD 3 Timer Flag-setting Mode ICSYS.PACMX 2 8-Bit Pulse Accumulators Maximum Count ICSYS.BUFEN 1 IC Buffer Enable ICSYS.LATQ 0 Input Control Latch or Queue Mode Enable RESERVED00AC 0x00AC RESERVED TIMTST 0x00AD Timer Test Register TIMTST.TCBYP 1 Main Timer Divider Chain Bypass PORTT 0x00AE Port T Data Register PORTT.PT7 7 Port T Data Bit 7 PORTT.PT6 6 Port T Data Bit 6 PORTT.PT5 5 Port T Data Bit 5 PORTT.PT4 4 Port T Data Bit 4 PORTT.PT3 3 Port T Data Bit 3 PORTT.PT2 2 Port T Data Bit 2 PORTT.PT1 1 Port T Data Bit 1 PORTT.PT0 0 Port T Data Bit 0 DDRT 0x00AF Port T Data Direction Register DDRT.DDT7 7 Port T Data Direction Bit 7 DDRT.DDT6 6 Port T Data Direction Bit 6 DDRT.DDT5 5 Port T Data Direction Bit 5 DDRT.DDT4 4 Port T Data Direction Bit 4 DDRT.DDT3 3 Port T Data Direction Bit 3 DDRT.DDT2 2 Port T Data Direction Bit 2 DDRT.DDT1 1 Port T Data Direction Bit 1 DDRT.DDT0 0 Port T Data Direction Bit 0 PBCTL 0x00B0 16-Bit Pulse Accumulator B Control Register PBCTL.PBEN 6 Pulse Accumulator B System Enable PBCTL.PBOVI 1 Pulse Accumulator B Overflow Interrupt enable PBFLG 0x00B1 Pulse Accumulator B Flag Register PBFLG.PBOVF 1 Pulse Accumulator B Overflow Flag PA3H 0x00B2 8-Bit Pulse Accumulators Holding Register 3 PA2H 0x00B3 8-Bit Pulse Accumulators Holding Register 2 PA1H 0x00B4 8-Bit Pulse Accumulators Holding Register 1 PA0H 0x00B5 8-Bit Pulse Accumulators Holding Register 0 MCCNTH 0x00B6 Modulus Down-Counter Count Register High MCCNTL 0x00B7 Modulus Down-Counter Count Register Low TC0HH 0x00B8 Timer Input Capture Holding Register 0 High TC0HL 0x00B9 Timer Input Capture Holding Register 0 Low TC1HH 0x00BA Timer Input Capture Holding Register 1 High TC1HL 0x00BB Timer Input Capture Holding Register 1 Low TC2HH 0x00BC Timer Input Capture Holding Register 2 High TC2HL 0x00BD Timer Input Capture Holding Register 2 Low TC3HH 0x00BE Timer Input Capture Holding Register 3 High TC3HL 0x00BF Timer Input Capture Holding Register 3 Low SC0BDH 0x00C0 SCI Baud Rate Control Register High SC0BDH.BTST 7 Reserved for test function SC0BDH.BSPL 6 Reserved for test function SC0BDH.BRLD 5 Reserved for test function SC0BDH.SBR12 4 SC0BDH.SBR11 3 SC0BDH.SBR10 2 SC0BDH.SBR9 1 SC0BDH.SBR8 0 SC0BDL 0x00C1 SCI Baud Rate Control Register Low SC0BDL.SBR7 7 SC0BDL.SBR6 6 SC0BDL.SBR5 5 SC0BDL.SBR4 4 SC0BDL.SBR3 3 SC0BDL.SBR2 2 SC0BDL.SBR1 1 SC0BDL.SBR0 0 SC0CR1 0x00C2 SCI Control Register 1 SC0CR1.LOOPS 7 SCI LOOP Mode/Single Wire Mode Enable SC0CR1.WOMS 6 Wired-Or Mode for Serial Pins SC0CR1.RSRC 5 Receiver Source SC0CR1.M 4 Mode (select character format) SC0CR1.WAKE 3 Wake-up by Address Mark/Idle SC0CR1.ILT 2 Idle Line Type SC0CR1.PE 1 Parity Enable SC0CR1.PT 0 Parity Type SC0CR2 0x00C3 SCI Control Register 2 SC0CR2.TIE 7 Transmit Interrupt Enable SC0CR2.TCIE 6 Transmit Complete Interrupt Enable SC0CR2.RIE 5 Receiver Interrupt Enable SC0CR2.ILIE 4 Idle Line Interrupt Enable SC0CR2.TE 3 Transmitter Enable SC0CR2.RE 2 Receiver Enable SC0CR2.RWU 1 Receiver Wake-Up Control SC0CR2.SBK 0 Send Break SC0SR1 0x00C4 SCI Status Register 1 SC0SR1.TDRE 7 Transmit Data Register Empty Flag SC0SR1.TC 6 Transmit Complete Flag SC0SR1.RDRF 5 Receive Data Register Full Flag SC0SR1.IDLE 4 Idle Line Detected Flag SC0SR1.OR 3 Overrun Error Flag SC0SR1.NF 2 Noise Error Flag SC0SR1.FE 1 Framing Error Flag SC0SR1.PF 0 Parity Error Flag SC0SR2 0x00C5 SCI Status Register 2 SC0SR2.RAF 0 Receiver Active Flag SC0DRH 0x00C6 SCI Data Register High SC0DRH.R8 7 Receive Bit 8 SC0DRH.T8 6 Transmit Bit 8 SC0DRL 0x00C7 SCI Data Register Low SC0DRL.R7_T7 7 Receive/Transmit Data Bit 7 SC0DRL.R6_T6 6 Receive/Transmit Data Bit 6 SC0DRL.R5_T5 5 Receive/Transmit Data Bit 5 SC0DRL.R4_T4 4 Receive/Transmit Data Bit 4 SC0DRL.R3_T3 3 Receive/Transmit Data Bit 3 SC0DRL.R2_T2 2 Receive/Transmit Data Bit 2 SC0DRL.R1_T1 1 Receive/Transmit Data Bit 1 SC0DRL.R0_T0 0 Receive/Transmit Data Bit 0 SC1BDH 0x00C8 SCI Baud Rate Control Register High SC1BDH.BTST 7 Reserved for test function SC1BDH.BSPL 6 Reserved for test function SC1BDH.BRLD 5 Reserved for test function SC1BDH.SBR12 4 SC1BDH.SBR11 3 SC1BDH.SBR10 2 SC1BDH.SBR9 1 SC1BDH.SBR8 0 SC1BDL 0x00C9 SCI Baud Rate Control Register Low SC1BDL.SBR7 7 SC1BDL.SBR6 6 SC1BDL.SBR5 5 SC1BDL.SBR4 4 SC1BDL.SBR3 3 SC1BDL.SBR2 2 SC1BDL.SBR1 1 SC1BDL.SBR0 0 SC1CR1 0x00CA SCI Control Register 1 SC1CR1.LOOPS 7 SCI LOOP Mode/Single Wire Mode Enable SC1CR1.WOMS 6 Wired-Or Mode for Serial Pins SC1CR1.RSRC 5 Receiver Source SC1CR1.M 4 Mode (select character format) SC1CR1.WAKE 3 Wake-up by Address Mark/Idle SC1CR1.ILT 2 Idle Line Type SC1CR1.PE 1 Parity Enable SC1CR1.PT 0 Parity Type SC1CR2 0x00CB SCI Control Register 2 SC1CR2.TIE 7 Transmit Interrupt Enable SC1CR2.TCIE 6 Transmit Complete Interrupt Enable SC1CR2.RIE 5 Receiver Interrupt Enable SC1CR2.ILIE 4 Idle Line Interrupt Enable SC1CR2.TE 3 Transmitter Enable SC1CR2.RE 2 Receiver Enable SC1CR2.RWU 1 Receiver Wake-Up Control SC1CR2.SBK 0 Send Break SC1SR1 0x00CC SCI Status Register 1 SC1SR1.TDRE 7 Transmit Data Register Empty Flag SC1SR1.TC 6 Transmit Complete Flag SC1SR1.RDRF 5 Receive Data Register Full Flag SC1SR1.IDLE 4 Idle Line Detected Flag SC1SR1.OR 3 Overrun Error Flag SC1SR1.NF 2 Noise Error Flag SC1SR1.FE 1 Framing Error Flag SC1SR1.PF 0 Parity Error Flag SC1SR2 0x00CD SCI Status Register 2 SC1SR2.RAF 0 Receiver Active Flag SC1DRH 0x00CE SCI Data Register High SC1DRH.R8 7 Receive Bit 8 SC1DRH.T8 6 Transmit Bit 8 SC1DRL 0x00CF SCI Data Register Low SC1DRL.R7_T7 7 Receive/Transmit Data Bit 7 SC1DRL.R6_T6 6 Receive/Transmit Data Bit 6 SC1DRL.R5_T5 5 Receive/Transmit Data Bit 5 SC1DRL.R4_T4 4 Receive/Transmit Data Bit 4 SC1DRL.R3_T3 3 Receive/Transmit Data Bit 3 SC1DRL.R2_T2 2 Receive/Transmit Data Bit 2 SC1DRL.R1_T1 1 Receive/Transmit Data Bit 1 SC1DRL.R0_T0 0 Receive/Transmit Data Bit 0 SP0CR1 0x00D0 SPI Control Register 1 SP0CR1.SPIE 7 SPI Interrupt Enable SP0CR1.SPE 6 SPI System Enable SP0CR1.SWOM 5 Port S Wired-OR Mode SP0CR1.MSTR 4 SPI Master/Slave Mode Select SP0CR1.CPOL 3 SPI Clock Polarity SP0CR1.CPHA 2 Clock Phase SP0CR1.SSOE 1 Slave Select Output Enable SP0CR1.LSBF 0 SPI LSB First enable SP0CR2 0x00D1 SPI Control Register 2 SP0CR2.PUPS 3 Pull-Up Port S Enable SP0CR2.RDPS 2 Reduce Drive of Port S SP0CR2.SSWAI 1 Serial Interface Stop in WAIT mode SP0CR2.SPC0 0 Serial Pin Control 0 SP0BR 0x00D2 SPI Baud Rate Register SP0BR.SPR2 2 SPI Clock (SCK) Rate Select Bit 2 SP0BR.SPR1 1 SPI Clock (SCK) Rate Select Bit 1 SP0BR.SPR0 0 SPI Clock (SCK) Rate Select Bit 0 SP0SR 0x00D3 SPI Status Register SP0SR.SPIF 7 SPI Interrupt Request SP0SR.WCOL 6 Write Collision Status Flag SP0SR.MODF 4 SPI Mode Error Interrupt Status Flag RESERVED00D4 0x00D4 RESERVED SP0DR 0x00D5 SPI Data Register PORTS 0x00D6 Port S Data Register PORTS.PS7 7 Port S Data Bit 7 PORTS.PS6 6 Port S Data Bit 6 PORTS.PS5 5 Port S Data Bit 5 PORTS.PS4 4 Port S Data Bit 4 PORTS.PS3 3 Port S Data Bit 3 PORTS.PS2 2 Port S Data Bit 2 PORTS.PS1 1 Port S Data Bit 1 PORTS.PS0 0 Port S Data Bit 0 DDRS 0x00D7 Port S Data Direction Register DDRS.DDS7 7 Port S Data Direction Bit 7 DDRS.DDS6 6 Port S Data Direction Bit 6 DDRS.DDS5 5 Port S Data Direction Bit 5 DDRS.DDS4 4 Port S Data Direction Bit 4 DDRS.DDS3 3 Port S Data Direction Bit 3 DDRS.DDS2 2 Port S Data Direction Bit 2 DDRS.DDS1 1 Port S Data Direction Bit 1 DDRS.DDS0 0 Port S Data Direction Bit 0 RESERVED00D8 0x00D8 RESERVED RESERVED00D9 0x00D9 RESERVED RESERVED00DA 0x00DA RESERVED RESERVED00DB 0x00DB RESERVED RESERVED00DC 0x00DC RESERVED RESERVED00DD 0x00DD RESERVED RESERVED00DE 0x00DE RESERVED RESERVED00DF 0x00DF RESERVED IBAD 0x00E0 Bus Address Register IBAD.ADR7 7 Slave Address 7 IBAD.ADR6 6 Slave Address 6 IBAD.ADR5 5 Slave Address 5 IBAD.ADR4 4 Slave Address 4 IBAD.ADR3 3 Slave Address 3 IBAD.ADR2 2 Slave Address 2 IBAD.ADR1 1 Slave Address 1 IBFD 0x00E1 IIC Bus Frequency Divider Register IBFD.IBC5 5 IIC Bus Clock Rate 5 IBFD.IBC4 4 IIC Bus Clock Rate 4 IBFD.IBC3 3 IIC Bus Clock Rate 3 IBFD.IBC2 2 IIC Bus Clock Rate 2 IBFD.IBC1 1 IIC Bus Clock Rate 1 IBFD.IBC0 0 IIC Bus Clock Rate 0 IBCR 0x00E2 IIC Bus Control Register IBCR.IBEN 7 IIC Bus Enable IBCR.IBIE 6 IIC Bus Interrupt Enable IBCR.MS_SL 5 Master/Slave mode select bit IBCR.Tx_Rx 4 Transmit/Receive mode select bit IBCR.TXAK 3 Transmit Acknowledge enable IBCR.RSTA 2 Repeat Start IBCR.IBSWAI 0 IIC Stop in WAIT mode IBSR 0x00E3 IIC Bus Status Register IBSR.TCF 7 Data transferring bit IBSR.IAAS 6 Addressed as a slave bit IBSR.IBB 5 IIC Bus busy bit IBSR.IBAL 4 Arbitration Lost IBSR.SRW 2 Slave Read/Write IBSR.IBIF 1 IIC Bus Interrupt Flag IBSR.RXAK 0 Received Acknowledge IBDR 0x00E4 IIC Bus Data I/O Register IBDR.D7 7 IBDR.D6 6 IBDR.D5 5 IBDR.D4 4 IBDR.D3 3 IBDR.D2 2 IBDR.D1 1 IBDR.D0 0 IBPURD 0x00E5 Pull-Up and Reduced Drive for Port IB IBPURD.RDPIB 4 Reduced Drive of Port IB IBPURD.PUPIB 0 Pull-Up Port IB Enable PORTIB 0x00E6 Port Data IB Register PORTIB.PIB7 7 Port Data IB Register bit 7 PORTIB.PIB6 6 Port Data IB Register bit 6 PORTIB.PIB5 5 Port Data IB Register bit 5 PORTIB.PIB4 4 Port Data IB Register bit 4 PORTIB.PIB3 3 Port Data IB Register bit 3 PORTIB.PIB2 2 Port Data IB Register bit 2 PORTIB.PIB1 1 Port Data IB Register bit 1 PORTIB.PIB0 0 Port Data IB Register bit 0 DDRIB 0x00E7 Data Direction for Port IB Register DDRIB.DDRIB7 7 Port IB Data direction 7 DDRIB.DDRIB6 6 Port IB Data direction 6 DDRIB.DDRIB5 5 Port IB Data direction 5 DDRIB.DDRIB4 4 Port IB Data direction 4 DDRIB.DDRIB3 3 Port IB Data direction 3 DDRIB.DDRIB2 2 Port IB Data direction 2 DDRIB.DDRIB1 1 DDRIB.DDRIB0 0 RESERVED00E8 0x00E8 RESERVED RESERVED00E9 0x00E9 RESERVED RESERVED00EA 0x00EA RESERVED RESERVED00EB 0x00EB RESERVED RESERVED00EC 0x00EC RESERVED RESERVED00ED 0x00ED RESERVED EEDIVH 0x00EE EEPROM Modulus Divider High EEDIVH.EEDIV9 1 Prescaler divider 9 EEDIVH.EEDIV8 0 Prescaler divider 8 EEDIVL 0x00EF EEPROM Modulus Divider Low EEDIVL.EEDIV7 7 Prescaler divider 7 EEDIVL.EEDIV6 6 Prescaler divider 6 EEDIVL.EEDIV5 5 Prescaler divider 5 EEDIVL.EEDIV4 4 Prescaler divider 4 EEDIVL.EEDIV3 3 Prescaler divider 3 EEDIVL.EEDIV2 2 Prescaler divider 2 EEDIVL.EEDIV1 1 Prescaler divider 1 EEDIVL.EEDIV0 0 Prescaler divider 0 EEMCR 0x00F0 EEPROM Module Configuration EEMCR.NOBDML 7 Background Debug Mode Lockout Disable EEMCR.NOSHW 6 SHADOW Byte Disable EEMCR.EESWAI 2 EEPROM Stops in Wait Mode EEMCR.PROTLCK 1 Block Protect Write Lock EEMCR.EERC 0 EEPROM Charge Pump Clock EEPROT 0x00F1 EEPROM Block Protect EEPROT.SHPROT 7 SHADOW Byte Protection EEPROT.BPROT5 5 EEPROM Block Protection 5 EEPROT.BPROT4 4 EEPROM Block Protection 4 EEPROT.BPROT3 3 EEPROM Block Protection 3 EEPROT.BPROT2 2 EEPROM Block Protection 2 EEPROT.BPROT1 1 EEPROM Block Protection 1 EEPROT.BPROT0 0 EEPROM Block Protection 0 EETST 0x00F2 EEPROM Test EETST.EREVTN 6 EETST.ETMSD 2 EETST.ETMR 1 EETST.ETMSE 0 EEPROG 0x00F3 EEPROM Control EEPROG.BULKP 7 Bulk Erase Protection EEPROG..AUTO 5 Automatic shutdown of program/erase operation EEPROG.BYTE 4 Byte and Aligned Word Erase EEPROG.ROW 3 Row or Bulk Erase (when BYTE = 0) EEPROG.ERASE 2 Erase Control EEPROG.EELAT 1 EEPROM Latch Control EEPROG.EEPGM 0 Program and Erase Enable FEELCK 0x00F4 Flash EEPROM Lock Control Register FEELCK.LOCK 0 Lock Register Bit FEEMCR 0x00F5 Flash EEPROM Module Configuration Register FEEMCR.BOOTP 0 Boot Protect FEETST 0x00F6 FEETST FEETST.STRE 7 FEETST.REVTUN 6 FEETST.TMSD 2 FEETST.TMR 1 FEETST.TMSE 0 FEECTL 0x00F7 Flash EEPROM Control Register FEECTL.FEESWAI 4 Flash EEPROM Stop in Wait Control FEECTL.HVEN 3 High-Voltage Enable FEECTL.ERAS 1 Erase Control FEECTL.PGM 0 Program Control MTST0 0x00F8 Mapping Test Register 0 MTST0.MT07 7 MTST0.MT06 6 MTST0.MT05 5 MTST0.MT04 4 MTST0.MT03 3 MTST0.MT02 2 MTST0.MT01 1 MTST0.MT00 0 MTST1 0x00F9 Mapping Test Register 1 MTST1.MT0F 7 MTST1.MT0E 6 MTST1.MT0D 5 MTST1.MT0C 4 MTST1.MT0B 3 MTST1.MT0A 2 MTST1.MT09 1 MTST1.MT08 0 MTST2 0x00FA Mapping Test Register 2 MTST2.MT17 7 MTST2.MT16 6 MTST2.MT15 5 MTST2.MT14 4 MTST2.MT13 3 MTST2.MT12 2 MTST2.MT11 1 MTST2.MT10 0 MTST3 0x00FB Mapping Test Register 3 MTST3.MT1F 7 MTST3.MT1E 6 MTST3.MT1D 5 MTST3.MT1C 4 MTST3.MT1B 3 MTST3.MT1A 2 MTST3.MT19 1 MTST3.MT18 0 PORTK 0x00FC Port K Data Register PORTK.PK7 7 Port K Data Bit 7 PORTK.PK3 3 Port K Data Bit 3 PORTK.PK2 2 Port K Data Bit 2 PORTK.PK1 1 Port K Data Bit 1 PORTK.PK0 0 Port K Data Bit 0 DDRK 0x00FD Port K Data Direction Register DDRK.DDK7 7 Port K Data Direction Bit 7 DDRK.DDK3 3 Port K Data Direction Bit 3 DDRK.DDK2 2 Port K Data Direction Bit 2 DDRK.DDK1 1 Port K Data Direction Bit 1 DDRK.DDK0 0 Port K Data Direction Bit 0 RESERVED00FE 0x00FE RESERVED PPAGE 0x00FF Program Page Index Register PPAGE.PIX2 2 PPAGE.PIX1 1 PPAGE.PIX0 0 C0MCR0 0x0100 msCAN12 Module Control Register 0 C0MCR0.CSWAI 5 CAN Stops in Wait Mode C0MCR0.SYNCH 4 Synchronized Status C0MCR0.TLNKEN 3 Timer Enable C0MCR0.SLPAK 2 SLEEP Mode Acknowledge C0MCR0.SLPRQ 1 SLEEP request C0MCR0.SFTRES 0 SOFT_RESET C0MCR1 0x0101 msCAN12 Module Control Register 1 C0MCR1.LOOPB 2 Loop Back Self Test Mode C0MCR1.WUPM 1 Wake-Up Mode C0MCR1.CLKSRC 0 msCAN12 Clock Source C0BTR0 0x0102 msCAN12 Bus Timing Register 0 C0BTR0.SJW1 7 Synchronization Jump Width 1 C0BTR0.SJW0 6 Synchronization Jump Width 0 C0BTR0.BRP5 5 Baud Rate Prescaler 5 C0BTR0.BRP4 4 Baud Rate Prescaler 4 C0BTR0.BRP3 3 Baud Rate Prescaler 3 C0BTR0.BRP2 2 Baud Rate Prescaler 2 C0BTR0.BRP1 1 Baud Rate Prescaler 1 C0BTR0.BRP0 0 Baud Rate Prescaler 0 C0BTR1 0x0103 msCAN12 Bus Timing Register 1 C0BTR1.SAMP 7 Sampling C0BTR1.TSEG22 6 Time Segment 22 C0BTR1.TSEG21 5 Time Segment 21 C0BTR1.TSEG20 4 Time Segment 20 C0BTR1.TSEG13 3 Time Segment 13 C0BTR1.TSEG12 2 Time Segment 12 C0BTR1.TSEG11 1 Time Segment 11 C0BTR1.TSEG10 0 Time Segment 10 C0RFLG 0x0104 msCAN12 Receiver Flag Register C0RFLG.WUPIF 7 Wake-up Interrupt Flag C0RFLG.RWRNIF 6 Receiver Warning Interrupt Flag C0RFLG.TWRNIF 5 Transmitter Warning Interrupt Flag C0RFLG.RERRIF 4 Receiver Error Passive Interrupt Flag C0RFLG.TERRIF 3 Transmitter Error Passive Interrupt Flag C0RFLG.BOFFIF 2 BUSOFF Interrupt Flag C0RFLG.OVRIF 1 Overrun Interrupt Flag C0RFLG.RXF 0 Receive Buffer Full C0RIER 0x0105 msCAN12 Receiver Interrupt Enable Register C0RIER.WUPIE 7 Wake-up Interrupt Enable C0RIER.RWRNIE 6 Receiver Warning Interrupt Enable C0RIER.TWRNIE 5 Transmitter Warning Interrupt Enable C0RIER.RERRIE 4 Receiver Error Passive Interrupt Enable C0RIER.TERRIE 3 Transmitter Error Passive Interrupt Enable C0RIER.BOFFIE 2 BUSOFF Interrupt Enable C0RIER.OVRIE 1 Overrun Interrupt Enable C0RIER.RXFIE 0 Receiver Full Interrupt Enable C0TFLG 0x0106 msCAN12 Transmitter Flag Register C0TFLG.ABTAK2 6 Abort Acknowledge 2 C0TFLG.ABTAK1 5 Abort Acknowledge 1 C0TFLG.ABTAK0 4 Abort Acknowledge 0 C0TFLG.TXE2 2 Transmitter Buffer Empty 2 C0TFLG.TXE1 1 Transmitter Buffer Empty 1 C0TFLG.TXE0 0 Transmitter Buffer Empty 0 C0TCR 0x0107 msCAN12 Transmitter Control Register C0TCR.ABTRQ2 6 Abort Request 2 C0TCR.ABTRQ1 5 Abort Request 1 C0TCR.ABTRQ0 4 Abort Request 0 C0TCR.TXEIE2 2 Transmitter Empty Interrupt Enable 2 C0TCR.TXEIE1 1 Transmitter Empty Interrupt Enable 1 C0TCR.TXEIE0 0 Transmitter Empty Interrupt Enable 0 C0IDAC 0x0108 msCAN12 Identifier Acceptance Control Register C0IDAC.IDAM1 5 Identifier Acceptance Mode 1 C0IDAC.IDAM0 4 Identifier Acceptance Mode 0 C0IDAC.IDHIT2 2 Identifier Acceptance Hit Indicator 2 C0IDAC.IDHIT1 1 Identifier Acceptance Hit Indicator 1 C0IDAC.IDHIT0 0 Identifier Acceptance Hit Indicator 0 RESERVED0109 0x0109 RESERVED RESERVED010A 0x010A RESERVED RESERVED010B 0x010B RESERVED RESERVED010C 0x010C RESERVED RESERVED010D 0x010D RESERVED C0RXERR 0x010E msCAN12 Receive Error Counter C0RXERR.RXERR7 7 C0RXERR.RXERR6 6 C0RXERR.RXERR5 5 C0RXERR.RXERR4 4 C0RXERR.RXERR3 3 C0RXERR.RXERR2 2 C0RXERR.RXERR1 1 C0RXERR.RXERR0 0 C0TXERR 0x010F msCAN12 Transmit Error Counter C0TXERR.TXERR7 7 C0TXERR.TXERR6 6 C0TXERR.TXERR5 5 C0TXERR.TXERR4 4 C0TXERR.TXERR3 3 C0TXERR.TXERR2 2 C0TXERR.TXERR1 1 C0TXERR.TXERR0 0 C0IDAR0 0x0110 msCAN12 Identifier Acceptance Register 0 C0IDAR0.AC7 7 Acceptance Code Bit 7 C0IDAR0.AC6 6 Acceptance Code Bit 6 C0IDAR0.AC5 5 Acceptance Code Bit 5 C0IDAR0.AC4 4 Acceptance Code Bit 4 C0IDAR0.AC3 3 Acceptance Code Bit 3 C0IDAR0.AC2 2 Acceptance Code Bit 2 C0IDAR0.AC1 1 Acceptance Code Bit 1 C0IDAR0.AC0 0 Acceptance Code Bit 0 C0IDAR1 0x0111 msCAN12 Identifier Acceptance Register 1 C0IDAR1.AC7 7 Acceptance Code Bit 7 C0IDAR1.AC6 6 Acceptance Code Bit 6 C0IDAR1.AC5 5 Acceptance Code Bit 5 C0IDAR1.AC4 4 Acceptance Code Bit 4 C0IDAR1.AC3 3 Acceptance Code Bit 3 C0IDAR1.AC2 2 Acceptance Code Bit 2 C0IDAR1.AC1 1 Acceptance Code Bit 1 C0IDAR1.AC0 0 Acceptance Code Bit 0 C0IDAR2 0x0112 msCAN12 Identifier Acceptance Register 2 C0IDAR2.AC7 7 Acceptance Code Bit 7 C0IDAR2.AC6 6 Acceptance Code Bit 6 C0IDAR2.AC5 5 Acceptance Code Bit 5 C0IDAR2.AC4 4 Acceptance Code Bit 4 C0IDAR2.AC3 3 Acceptance Code Bit 3 C0IDAR2.AC2 2 Acceptance Code Bit 2 C0IDAR2.AC1 1 Acceptance Code Bit 1 C0IDAR2.AC0 0 Acceptance Code Bit 0 C0IDAR3 0x0113 msCAN12 Identifier Acceptance Register 3 C0IDAR3.AC7 7 Acceptance Code Bit 7 C0IDAR3.AC6 6 Acceptance Code Bit 6 C0IDAR3.AC5 5 Acceptance Code Bit 5 C0IDAR3.AC4 4 Acceptance Code Bit 4 C0IDAR3.AC3 3 Acceptance Code Bit 3 C0IDAR3.AC2 2 Acceptance Code Bit 2 C0IDAR3.AC1 1 Acceptance Code Bit 1 C0IDAR3.AC0 0 Acceptance Code Bit 0 C0IDMR0 0x0114 msCAN12 Identifier Mask Register 0 C0IDMR0.AM7 7 Acceptance Mask Bit 7 C0IDMR0.AM6 6 Acceptance Mask Bit 6 C0IDMR0.AM5 5 Acceptance Mask Bit 5 C0IDMR0.AM4 4 Acceptance Mask Bit 4 C0IDMR0.AM3 3 Acceptance Mask Bit 3 C0IDMR0.AM2 2 Acceptance Mask Bit 2 C0IDMR0.AM1 1 Acceptance Mask Bit 1 C0IDMR0.AM0 0 Acceptance Mask Bit 0 C0IDMR1 0x0115 msCAN12 Identifier Mask Register 1 C0IDMR1.AM7 7 Acceptance Mask Bit 7 C0IDMR1.AM6 6 Acceptance Mask Bit 6 C0IDMR1.AM5 5 Acceptance Mask Bit 5 C0IDMR1.AM4 4 Acceptance Mask Bit 4 C0IDMR1.AM3 3 Acceptance Mask Bit 3 C0IDMR1.AM2 2 Acceptance Mask Bit 2 C0IDMR1.AM1 1 Acceptance Mask Bit 1 C0IDMR1.AM0 0 Acceptance Mask Bit 0 C0IDMR2 0x0116 msCAN12 Identifier Mask Register 2 C0IDMR2.AM7 7 Acceptance Mask Bit 7 C0IDMR2.AM6 6 Acceptance Mask Bit 6 C0IDMR2.AM5 5 Acceptance Mask Bit 5 C0IDMR2.AM4 4 Acceptance Mask Bit 4 C0IDMR2.AM3 3 Acceptance Mask Bit 3 C0IDMR2.AM2 2 Acceptance Mask Bit 2 C0IDMR2.AM1 1 Acceptance Mask Bit 1 C0IDMR2.AM0 0 Acceptance Mask Bit 0 C0IDMR3 0x0117 msCAN12 Identifier Mask Register 3 C0IDMR3.AM7 7 Acceptance Mask Bit 7 C0IDMR3.AM6 6 Acceptance Mask Bit 6 C0IDMR3.AM5 5 Acceptance Mask Bit 5 C0IDMR3.AM4 4 Acceptance Mask Bit 4 C0IDMR3.AM3 3 Acceptance Mask Bit 3 C0IDMR3.AM2 2 Acceptance Mask Bit 2 C0IDMR3.AM1 1 Acceptance Mask Bit 1 C0IDMR3.AM0 0 Acceptance Mask Bit 0 C0IDAR4 0x0118 msCAN12 Identifier Acceptance Register 4 C0IDAR4.AC7 7 Acceptance Code Bit 7 C0IDAR4.AC6 6 Acceptance Code Bit 6 C0IDAR4.AC5 5 Acceptance Code Bit 5 C0IDAR4.AC4 4 Acceptance Code Bit 4 C0IDAR4.AC3 3 Acceptance Code Bit 3 C0IDAR4.AC2 2 Acceptance Code Bit 2 C0IDAR4.AC1 1 Acceptance Code Bit 1 C0IDAR4.AC0 0 Acceptance Code Bit 0 C0IDAR5 0x0119 msCAN12 Identifier Acceptance Register 5 C0IDAR5.AC7 7 Acceptance Code Bit 7 C0IDAR5.AC6 6 Acceptance Code Bit 6 C0IDAR5.AC5 5 Acceptance Code Bit 5 C0IDAR5.AC4 4 Acceptance Code Bit 4 C0IDAR5.AC3 3 Acceptance Code Bit 3 C0IDAR5.AC2 2 Acceptance Code Bit 2 C0IDAR5.AC1 1 Acceptance Code Bit 1 C0IDAR5.AC0 0 Acceptance Code Bit 0 C0IDAR6 0x011A msCAN12 Identifier Acceptance Register 6 C0IDAR6.AC7 7 Acceptance Code Bit 7 C0IDAR6.AC6 6 Acceptance Code Bit 6 C0IDAR6.AC5 5 Acceptance Code Bit 5 C0IDAR6.AC4 4 Acceptance Code Bit 4 C0IDAR6.AC3 3 Acceptance Code Bit 3 C0IDAR6.AC2 2 Acceptance Code Bit 2 C0IDAR6.AC1 1 Acceptance Code Bit 1 C0IDAR6.AC0 0 Acceptance Code Bit 0 C0IDAR7 0x011B msCAN12 Identifier Acceptance Register 7 C0IDAR7.AC7 7 Acceptance Code Bit 7 C0IDAR7.AC6 6 Acceptance Code Bit 6 C0IDAR7.AC5 5 Acceptance Code Bit 5 C0IDAR7.AC4 4 Acceptance Code Bit 4 C0IDAR7.AC3 3 Acceptance Code Bit 3 C0IDAR7.AC2 2 Acceptance Code Bit 2 C0IDAR7.AC1 1 Acceptance Code Bit 1 C0IDAR7.AC0 0 Acceptance Code Bit 0 C0IDMR4 0x011C msCAN12 Identifier Mask Register 4 C0IDMR4.AM7 7 Acceptance Mask Bit 7 C0IDMR4.AM6 6 Acceptance Mask Bit 6 C0IDMR4.AM5 5 Acceptance Mask Bit 5 C0IDMR4.AM4 4 Acceptance Mask Bit 4 C0IDMR4.AM3 3 Acceptance Mask Bit 3 C0IDMR4.AM2 2 Acceptance Mask Bit 2 C0IDMR4.AM1 1 Acceptance Mask Bit 1 C0IDMR4.AM0 0 Acceptance Mask Bit 0 C0IDMR5 0x011D msCAN12 Identifier Mask Register 5 C0IDMR5.AM7 7 Acceptance Mask Bit 7 C0IDMR5.AM6 6 Acceptance Mask Bit 6 C0IDMR5.AM5 5 Acceptance Mask Bit 5 C0IDMR5.AM4 4 Acceptance Mask Bit 4 C0IDMR5.AM3 3 Acceptance Mask Bit 3 C0IDMR5.AM2 2 Acceptance Mask Bit 2 C0IDMR5.AM1 1 Acceptance Mask Bit 1 C0IDMR5.AM0 0 Acceptance Mask Bit 0 C0IDMR6 0x011E msCAN12 Identifier Mask Register 6 C0IDMR6.AM7 7 Acceptance Mask Bit 7 C0IDMR6.AM6 6 Acceptance Mask Bit 6 C0IDMR6.AM5 5 Acceptance Mask Bit 5 C0IDMR6.AM4 4 Acceptance Mask Bit 4 C0IDMR6.AM3 3 Acceptance Mask Bit 3 C0IDMR6.AM2 2 Acceptance Mask Bit 2 C0IDMR6.AM1 1 Acceptance Mask Bit 1 C0IDMR6.AM0 0 Acceptance Mask Bit 0 C0IDMR7 0x011F msCAN12 Identifier Mask Register 7 C0IDMR7.AM7 7 Acceptance Mask Bit 7 C0IDMR7.AM6 6 Acceptance Mask Bit 6 C0IDMR7.AM5 5 Acceptance Mask Bit 5 C0IDMR7.AM4 4 Acceptance Mask Bit 4 C0IDMR7.AM3 3 Acceptance Mask Bit 3 C0IDMR7.AM2 2 Acceptance Mask Bit 2 C0IDMR7.AM1 1 Acceptance Mask Bit 1 C0IDMR7.AM0 0 Acceptance Mask Bit 0 RESERVED0120 0x0120 RESERVED RESERVED0121 0x0121 RESERVED RESERVED0122 0x0122 RESERVED RESERVED0123 0x0123 RESERVED RESERVED0124 0x0124 RESERVED RESERVED0125 0x0125 RESERVED RESERVED0126 0x0126 RESERVED RESERVED0127 0x0127 RESERVED RESERVED0128 0x0128 RESERVED RESERVED0129 0x0129 RESERVED RESERVED012A 0x012A RESERVED RESERVED012B 0x012B RESERVED RESERVED012C 0x012C RESERVED RESERVED012D 0x012D RESERVED RESERVED012E 0x012E RESERVED RESERVED012F 0x012F RESERVED RESERVED0130 0x0130 RESERVED RESERVED0131 0x0131 RESERVED RESERVED0132 0x0132 RESERVED RESERVED0133 0x0133 RESERVED RESERVED0134 0x0134 RESERVED RESERVED0135 0x0135 RESERVED RESERVED0136 0x0136 RESERVED RESERVED0137 0x0137 RESERVED RESERVED0138 0x0138 RESERVED RESERVED0139 0x0139 RESERVED RESERVED013A 0x013A RESERVED RESERVED013B 0x013B RESERVED RESERVED013C 0x013C RESERVED PCTLCAN0 0x013D msCAN12 Port CAN Control Register PCTLCAN0.PUPCAN 1 Pull-Up Enable Port CAN PCTLCAN0.RDPCAN 0 Reduced Drive Port CAN PORTCAN0 0x013E msCAN12 Port CAN Data Register PORTCAN0.PCAN7 7 Port CAN Data Bit 7 PORTCAN0.PCAN6 6 Port CAN Data Bit 6 PORTCAN0.PCAN5 5 Port CAN Data Bit 5 PORTCAN0.PCAN4 4 Port CAN Data Bit 4 PORTCAN0.PCAN3 3 Port CAN Data Bit 3 PORTCAN0.PCAN2 2 Port CAN Data Bit 2 PORTCAN0.TxCAN 1 PORTCAN0.RxCAN 0 DDRCAN0 0x013F msCAN12 Port CAN Data Direction Register DDRCAN0.DDCAN7 7 DDRCAN0.DDCAN6 6 DDRCAN0.DDCAN5 5 DDRCAN0.DDCAN4 4 DDRCAN0.DDCAN3 3 DDRCAN0.DDCAN2 2 ATD1CTL2 0x01E2 ATD1 Control Register 2 ATD1CTL2.ADPU 7 ATD Disable ATD1CTL2.AFFC 6 ATD Fast Flag Clear All ATD1CTL2.ASWAI 5 ATD Wait Mode ATD1CTL2.DJM 4 Result Register Data Justification Mode ATD1CTL2.DSGN 3 Signed/Unsigned Result Data Mode ATD1CTL2.ASCIE 1 ATD Sequence Complete Interrupt Enable ATD1CTL2.ASCIF 0 ATD Sequence Complete Interrupt Flag ATD1CTL3 0x01E3 ATD1 Control Register 3 ATD1CTL3.S1C 3 Conversion Sequence Length (Least Significant Bit) ATD1CTL3.FIFO 2 Result Register FIFO Mode ATD1CTL3.FRZ1 1 Background Debug (Freeze) Enable 1 ATD1CTL3.FRZ0 0 Background Debug (Freeze) Enable 0 ATD1CTL4 0x01E4 ATD1 Control Register 4 ATD1CTL4.RES10 7 10 bit Mode ATD1CTL4.SMP1 6 Select Sample Time 1 ATD1CTL4.SMP0 5 Select Sample Time 0 ATD1CTL4.PRS4 4 Select Divide-By Factor for ATD P-Clock Prescaler 4 ATD1CTL4.PRS3 3 Select Divide-By Factor for ATD P-Clock Prescaler 3 ATD1CTL4.PRS2 2 Select Divide-By Factor for ATD P-Clock Prescaler 2 ATD1CTL4.PRS1 1 Select Divide-By Factor for ATD P-Clock Prescaler 1 ATD1CTL4.PRS0 0 Select Divide-By Factor for ATD P-Clock Prescaler 0 ATD1CTL5 0x01E5 ATD1 Control Register 5 ATD1CTL5.S8CM 6 Select 8 Channel Mode ATD1CTL5.SCAN 5 Enable Continuous Channel Scan ATD1CTL5.MULT 4 Enable Multichannel Conversion ATD1CTL5.CD 3 Channel Select for Conversion D ATD1CTL5.CC 2 Channel Select for Conversion C ATD1CTL5.CB 1 Channel Select for Conversion B ATD1CTL5.CA 0 Channel Select for Conversion A ATD1STAT0 0x01E6 ATD1 Status Register ATD1STAT0.SCF 7 Sequence Complete Flag ATD1STAT0.CC2 2 Conversion Counter for Current Sequence of Four or Eight Conversions 2 ATD1STAT0.CC1 1 Conversion Counter for Current Sequence of Four or Eight Conversions 1 ATD1STAT0.CC0 0 Conversion Counter for Current Sequence of Four or Eight Conversions 0 ATD1STAT1 0x01E7 ATD1 Status Register ATD1STAT1.CCF7 7 Conversion Complete Flag 7 ATD1STAT1.CCF6 6 Conversion Complete Flag 6 ATD1STAT1.CCF5 5 Conversion Complete Flag 5 ATD1STAT1.CCF4 4 Conversion Complete Flag 4 ATD1STAT1.CCF3 3 Conversion Complete Flag 3 ATD1STAT1.CCF2 2 Conversion Complete Flag 2 ATD1STAT1.CCF1 1 Conversion Complete Flag 1 ATD1STAT1.CCF0 0 Conversion Complete Flag 0 ATD1TESTH 0x01E8 ATD1 Test Register ATD1TESTH.SAR9 7 SAR Data 9 ATD1TESTH.SAR8 6 SAR Data 8 ATD1TESTH.SAR7 5 SAR Data 7 ATD1TESTH.SAR6 4 SAR Data 6 ATD1TESTH.SAR5 3 SAR Data 5 ATD1TESTH.SAR4 2 SAR Data 4 ATD1TESTH.SAR3 1 SAR Data 3 ATD1TESTH.SAR2 0 SAR Data 2 ATD1TESTL 0x01E9 ATD1 Test Register ATD1TESTL.SAR1 7 SAR Data 1 ATD1TESTL.SAR0 6 SAR Data 0 ATD1TESTL.RST 5 Module Reset Bit ATD1TESTL.TSTOUT 4 Multiplex Output of TST[3:0] (Factory Use) ATD1TESTL.TST3 3 Test Bit 3 ATD1TESTL.TST2 2 Test Bit 2 ATD1TESTL.TST1 1 Test Bit 1 ATD1TESTL.TST0 0 Test Bit 0 RESERVED01EA 0x01EA RESERVED RESERVED01EB 0x01EB RESERVED RESERVED01EC 0x01EC RESERVED RESERVED01ED 0x01ED RESERVED RESERVED01EE 0x01EE RESERVED PORTAD1 0x01EF Port AD1 Data Input Register PORTAD1.PAD17 7 Port AD1 Data Input Bit 7 PORTAD1.PAD16 6 Port AD1 Data Input Bit 6 PORTAD1.PAD15 5 Port AD1 Data Input Bit 5 PORTAD1.PAD14 4 Port AD1 Data Input Bit 4 PORTAD1.PAD13 3 Port AD1 Data Input Bit 3 PORTAD1.PAD12 2 Port AD1 Data Input Bit 2 PORTAD1.PAD11 1 Port AD1 Data Input Bit 1 PORTAD1.PAD10 0 Port AD1 Data Input Bit 0 ADR10H 0x01F0 A/D Conversion Result Register High 0 ADR10L 0x01F1 A/D Conversion Result Register Low 0 ADR11H 0x01F2 A/D Conversion Result Register High 1 ADR11L 0x01F3 A/D Conversion Result Register Low 1 ADR12H 0x01F4 A/D Conversion Result Register High 2 ADR12L 0x01F5 A/D Conversion Result Register Low 2 ADR13H 0x01F6 A/D Conversion Result Register High 3 ADR13L 0x01F7 A/D Conversion Result Register Low 3 ADR14H 0x01F8 A/D Conversion Result Register High 4 ADR14L 0x01F9 A/D Conversion Result Register Low 4 ADR15H 0x01FA A/D Conversion Result Register High 5 ADR15L 0x01FB A/D Conversion Result Register Low 5 ADR16H 0x01FC A/D Conversion Result Register High 6 ADR16L 0x01FD A/D Conversion Result Register Low 6 ADR17H 0x01FE A/D Conversion Result Register High 7 ADR17L 0x01FF A/D Conversion Result Register Low 7 C2MCR0 0x0200 msCAN12 Module Control Register 0 C2MCR0.CSWAI 5 CAN Stops in Wait Mode C2MCR0.SYNCH 4 Synchronized Status C2MCR0.TLNKEN 3 Timer Enable C2MCR0.SLPAK 2 SLEEP Mode Acknowledge C2MCR0.SLPRQ 1 SLEEP request C2MCR0.SFTRES 0 SOFT_RESET C2MCR1 0x0201 msCAN12 Module Control Register 1 C2MCR1.LOOPB 2 Loop Back Self Test Mode C2MCR1.WUPM 1 Wake-Up Mode C2MCR1.CLKSRC 0 msCAN12 Clock Source C2BTR0 0x0202 msCAN12 Bus Timing Register 0 C2BTR0.SJW1 7 Synchronization Jump Width 1 C2BTR0.SJW0 6 Synchronization Jump Width 0 C2BTR0.BRP5 5 Baud Rate Prescaler 5 C2BTR0.BRP4 4 Baud Rate Prescaler 4 C2BTR0.BRP3 3 Baud Rate Prescaler 3 C2BTR0.BRP2 2 Baud Rate Prescaler 2 C2BTR0.BRP1 1 Baud Rate Prescaler 1 C2BTR0.BRP0 0 Baud Rate Prescaler 0 C2BTR1 0x0203 msCAN12 Bus Timing Register 1 C2BTR1.SAMP 7 Sampling C2BTR1.TSEG22 6 Time Segment 22 C2BTR1.TSEG21 5 Time Segment 21 C2BTR1.TSEG20 4 Time Segment 20 C2BTR1.TSEG13 3 Time Segment 13 C2BTR1.TSEG12 2 Time Segment 12 C2BTR1.TSEG11 1 Time Segment 11 C2BTR1.TSEG10 0 Time Segment 10 C2RFLG 0x0204 msCAN12 Receiver Flag Register C2RFLG.WUPIF 7 Wake-up Interrupt Flag C2RFLG.RWRNIF 6 Receiver Warning Interrupt Flag C2RFLG.TWRNIF 5 Transmitter Warning Interrupt Flag C2RFLG.RERRIF 4 Receiver Error Passive Interrupt Flag C2RFLG.TERRIF 3 Transmitter Error Passive Interrupt Flag C2RFLG.BOFFIF 2 BUSOFF Interrupt Flag C2RFLG.OVRIF 1 Overrun Interrupt Flag C2RFLG.RXF 0 Receive Buffer Full C2RIER 0x0205 msCAN12 Receiver Interrupt Enable Register C2RIER.WUPIE 7 Wake-up Interrupt Enable C2RIER.RWRNIE 6 Receiver Warning Interrupt Enable C2RIER.TWRNIE 5 Transmitter Warning Interrupt Enable C2RIER.RERRIE 4 Receiver Error Passive Interrupt Enable C2RIER.TERRIE 3 Transmitter Error Passive Interrupt Enable C2RIER.BOFFIE 2 BUSOFF Interrupt Enable C2RIER.OVRIE 1 Overrun Interrupt Enable C2RIER.RXFIE 0 Receiver Full Interrupt Enable C2TFLG 0x0206 msCAN12 Transmitter Flag Register C2TFLG.ABTAK2 6 Abort Acknowledge 2 C2TFLG.ABTAK1 5 Abort Acknowledge 1 C2TFLG.ABTAK0 4 Abort Acknowledge 0 C2TFLG.TXE2 2 Transmitter Buffer Empty 2 C2TFLG.TXE1 1 Transmitter Buffer Empty 1 C2TFLG.TXE0 0 Transmitter Buffer Empty 0 C2TCR 0x0207 msCAN12 Transmitter Control Register C2TCR.ABTRQ2 6 Abort Request 2 C2TCR.ABTRQ1 5 Abort Request 1 C2TCR.ABTRQ0 4 Abort Request 0 C2TCR.TXEIE2 2 Transmitter Empty Interrupt Enable 2 C2TCR.TXEIE1 1 Transmitter Empty Interrupt Enable 1 C2TCR.TXEIE0 0 Transmitter Empty Interrupt Enable 0 C2IDAC 0x0208 msCAN12 Identifier Acceptance Control Register C2IDAC.IDAM1 5 Identifier Acceptance Mode 1 C2IDAC.IDAM0 4 Identifier Acceptance Mode 0 C2IDAC.IDHIT2 2 Identifier Acceptance Hit Indicator 2 C2IDAC.IDHIT1 1 Identifier Acceptance Hit Indicator 1 C2IDAC.IDHIT0 0 Identifier Acceptance Hit Indicator 0 RESERVED0209 0x0209 RESERVED RESERVED020A 0x020A RESERVED RESERVED020B 0x020B RESERVED RESERVED020C 0x020C RESERVED RESERVED020D 0x020D RESERVED C2RXERR 0x020E msCAN12 Receive Error Counter C2RXERR.RXERR7 7 C2RXERR.RXERR6 6 C2RXERR.RXERR5 5 C2RXERR.RXERR4 4 C2RXERR.RXERR3 3 C2RXERR.RXERR2 2 C2RXERR.RXERR1 1 C2RXERR.RXERR0 0 C2TXERR 0x020F msCAN12 Transmit Error Counter C2TXERR.TXERR7 7 C2TXERR.TXERR6 6 C2TXERR.TXERR5 5 C2TXERR.TXERR4 4 C2TXERR.TXERR3 3 C2TXERR.TXERR2 2 C2TXERR.TXERR1 1 C2TXERR.TXERR0 0 C2IDAR0 0x0210 msCAN12 Identifier Acceptance Register 0 C2IDAR0.AC7 7 Acceptance Code Bit 7 C2IDAR0.AC6 6 Acceptance Code Bit 6 C2IDAR0.AC5 5 Acceptance Code Bit 5 C2IDAR0.AC4 4 Acceptance Code Bit 4 C2IDAR0.AC3 3 Acceptance Code Bit 3 C2IDAR0.AC2 2 Acceptance Code Bit 2 C2IDAR0.AC1 1 Acceptance Code Bit 1 C2IDAR0.AC0 0 Acceptance Code Bit 0 C2IDAR1 0x0211 msCAN12 Identifier Acceptance Register 1 C2IDAR1.AC7 7 Acceptance Code Bit 7 C2IDAR1.AC6 6 Acceptance Code Bit 6 C2IDAR1.AC5 5 Acceptance Code Bit 5 C2IDAR1.AC4 4 Acceptance Code Bit 4 C2IDAR1.AC3 3 Acceptance Code Bit 3 C2IDAR1.AC2 2 Acceptance Code Bit 2 C2IDAR1.AC1 1 Acceptance Code Bit 1 C2IDAR1.AC0 0 Acceptance Code Bit 0 C2IDAR2 0x0212 msCAN12 Identifier Acceptance Register 2 C2IDAR2.AC7 7 Acceptance Code Bit 7 C2IDAR2.AC6 6 Acceptance Code Bit 6 C2IDAR2.AC5 5 Acceptance Code Bit 5 C2IDAR2.AC4 4 Acceptance Code Bit 4 C2IDAR2.AC3 3 Acceptance Code Bit 3 C2IDAR2.AC2 2 Acceptance Code Bit 2 C2IDAR2.AC1 1 Acceptance Code Bit 1 C2IDAR2.AC0 0 Acceptance Code Bit 0 C2IDAR3 0x0213 msCAN12 Identifier Acceptance Register 3 C2IDAR3.AC7 7 Acceptance Code Bit 7 C2IDAR3.AC6 6 Acceptance Code Bit 6 C2IDAR3.AC5 5 Acceptance Code Bit 5 C2IDAR3.AC4 4 Acceptance Code Bit 4 C2IDAR3.AC3 3 Acceptance Code Bit 3 C2IDAR3.AC2 2 Acceptance Code Bit 2 C2IDAR3.AC1 1 Acceptance Code Bit 1 C2IDAR3.AC0 0 Acceptance Code Bit 0 C2IDMR0 0x0214 msCAN12 Identifier Mask Register 0 C2IDMR0.AM7 7 Acceptance Mask Bit 7 C2IDMR0.AM6 6 Acceptance Mask Bit 6 C2IDMR0.AM5 5 Acceptance Mask Bit 5 C2IDMR0.AM4 4 Acceptance Mask Bit 4 C2IDMR0.AM3 3 Acceptance Mask Bit 3 C2IDMR0.AM2 2 Acceptance Mask Bit 2 C2IDMR0.AM1 1 Acceptance Mask Bit 1 C2IDMR0.AM0 0 Acceptance Mask Bit 0 C2IDMR1 0x0215 msCAN12 Identifier Mask Register 1 C2IDMR1.AM7 7 Acceptance Mask Bit 7 C2IDMR1.AM6 6 Acceptance Mask Bit 6 C2IDMR1.AM5 5 Acceptance Mask Bit 5 C2IDMR1.AM4 4 Acceptance Mask Bit 4 C2IDMR1.AM3 3 Acceptance Mask Bit 3 C2IDMR1.AM2 2 Acceptance Mask Bit 2 C2IDMR1.AM1 1 Acceptance Mask Bit 1 C2IDMR1.AM0 0 Acceptance Mask Bit 0 C2IDMR2 0x0216 msCAN12 Identifier Mask Register 2 C2IDMR2.AM7 7 Acceptance Mask Bit 7 C2IDMR2.AM6 6 Acceptance Mask Bit 6 C2IDMR2.AM5 5 Acceptance Mask Bit 5 C2IDMR2.AM4 4 Acceptance Mask Bit 4 C2IDMR2.AM3 3 Acceptance Mask Bit 3 C2IDMR2.AM2 2 Acceptance Mask Bit 2 C2IDMR2.AM1 1 Acceptance Mask Bit 1 C2IDMR2.AM0 0 Acceptance Mask Bit 0 C2IDMR3 0x0217 msCAN12 Identifier Mask Register 3 C2IDMR3.AM7 7 Acceptance Mask Bit 7 C2IDMR3.AM6 6 Acceptance Mask Bit 6 C2IDMR3.AM5 5 Acceptance Mask Bit 5 C2IDMR3.AM4 4 Acceptance Mask Bit 4 C2IDMR3.AM3 3 Acceptance Mask Bit 3 C2IDMR3.AM2 2 Acceptance Mask Bit 2 C2IDMR3.AM1 1 Acceptance Mask Bit 1 C2IDMR3.AM0 0 Acceptance Mask Bit 0 C2IDAR4 0x0218 msCAN12 Identifier Acceptance Register 4 C2IDAR4.AC7 7 Acceptance Code Bit 7 C2IDAR4.AC6 6 Acceptance Code Bit 6 C2IDAR4.AC5 5 Acceptance Code Bit 5 C2IDAR4.AC4 4 Acceptance Code Bit 4 C2IDAR4.AC3 3 Acceptance Code Bit 3 C2IDAR4.AC2 2 Acceptance Code Bit 2 C2IDAR4.AC1 1 Acceptance Code Bit 1 C2IDAR4.AC0 0 Acceptance Code Bit 0 C2IDAR5 0x0219 msCAN12 Identifier Acceptance Register 5 C2IDAR5.AC7 7 Acceptance Code Bit 7 C2IDAR5.AC6 6 Acceptance Code Bit 6 C2IDAR5.AC5 5 Acceptance Code Bit 5 C2IDAR5.AC4 4 Acceptance Code Bit 4 C2IDAR5.AC3 3 Acceptance Code Bit 3 C2IDAR5.AC2 2 Acceptance Code Bit 2 C2IDAR5.AC1 1 Acceptance Code Bit 1 C2IDAR5.AC0 0 Acceptance Code Bit 0 C2IDAR6 0x021A msCAN12 Identifier Acceptance Register 6 C2IDAR6.AC7 7 Acceptance Code Bit 7 C2IDAR6.AC6 6 Acceptance Code Bit 6 C2IDAR6.AC5 5 Acceptance Code Bit 5 C2IDAR6.AC4 4 Acceptance Code Bit 4 C2IDAR6.AC3 3 Acceptance Code Bit 3 C2IDAR6.AC2 2 Acceptance Code Bit 2 C2IDAR6.AC1 1 Acceptance Code Bit 1 C2IDAR6.AC0 0 Acceptance Code Bit 0 C2IDAR7 0x021B msCAN12 Identifier Acceptance Register 7 C2IDAR7.AC7 7 Acceptance Code Bit 7 C2IDAR7.AC6 6 Acceptance Code Bit 6 C2IDAR7.AC5 5 Acceptance Code Bit 5 C2IDAR7.AC4 4 Acceptance Code Bit 4 C2IDAR7.AC3 3 Acceptance Code Bit 3 C2IDAR7.AC2 2 Acceptance Code Bit 2 C2IDAR7.AC1 1 Acceptance Code Bit 1 C2IDAR7.AC0 0 Acceptance Code Bit 0 C2IDMR4 0x021C msCAN12 Identifier Mask Register 4 C2IDMR4.AM7 7 Acceptance Mask Bit 7 C2IDMR4.AM6 6 Acceptance Mask Bit 6 C2IDMR4.AM5 5 Acceptance Mask Bit 5 C2IDMR4.AM4 4 Acceptance Mask Bit 4 C2IDMR4.AM3 3 Acceptance Mask Bit 3 C2IDMR4.AM2 2 Acceptance Mask Bit 2 C2IDMR4.AM1 1 Acceptance Mask Bit 1 C2IDMR4.AM0 0 Acceptance Mask Bit 0 C2IDMR5 0x021D msCAN12 Identifier Mask Register 5 C2IDMR5.AM7 7 Acceptance Mask Bit 7 C2IDMR5.AM6 6 Acceptance Mask Bit 6 C2IDMR5.AM5 5 Acceptance Mask Bit 5 C2IDMR5.AM4 4 Acceptance Mask Bit 4 C2IDMR5.AM3 3 Acceptance Mask Bit 3 C2IDMR5.AM2 2 Acceptance Mask Bit 2 C2IDMR5.AM1 1 Acceptance Mask Bit 1 C2IDMR5.AM0 0 Acceptance Mask Bit 0 C2IDMR6 0x021E msCAN12 Identifier Mask Register 6 C2IDMR6.AM7 7 Acceptance Mask Bit 7 C2IDMR6.AM6 6 Acceptance Mask Bit 6 C2IDMR6.AM5 5 Acceptance Mask Bit 5 C2IDMR6.AM4 4 Acceptance Mask Bit 4 C2IDMR6.AM3 3 Acceptance Mask Bit 3 C2IDMR6.AM2 2 Acceptance Mask Bit 2 C2IDMR6.AM1 1 Acceptance Mask Bit 1 C2IDMR6.AM0 0 Acceptance Mask Bit 0 C2IDMR7 0x021F msCAN12 Identifier Mask Register 7 C2IDMR7.AM7 7 Acceptance Mask Bit 7 C2IDMR7.AM6 6 Acceptance Mask Bit 6 C2IDMR7.AM5 5 Acceptance Mask Bit 5 C2IDMR7.AM4 4 Acceptance Mask Bit 4 C2IDMR7.AM3 3 Acceptance Mask Bit 3 C2IDMR7.AM2 2 Acceptance Mask Bit 2 C2IDMR7.AM1 1 Acceptance Mask Bit 1 C2IDMR7.AM0 0 Acceptance Mask Bit 0 RESERVED0220 0x0220 RESERVED RESERVED0221 0x0221 RESERVED RESERVED0222 0x0222 RESERVED RESERVED0223 0x0223 RESERVED RESERVED0224 0x0224 RESERVED RESERVED0225 0x0225 RESERVED RESERVED0226 0x0226 RESERVED RESERVED0227 0x0227 RESERVED RESERVED0228 0x0228 RESERVED RESERVED0229 0x0229 RESERVED RESERVED022A 0x022A RESERVED RESERVED022B 0x022B RESERVED RESERVED022C 0x022C RESERVED RESERVED022D 0x022D RESERVED RESERVED022E 0x022E RESERVED RESERVED022F 0x022F RESERVED RESERVED0230 0x0230 RESERVED RESERVED0231 0x0231 RESERVED RESERVED0232 0x0232 RESERVED RESERVED0233 0x0233 RESERVED RESERVED0234 0x0234 RESERVED RESERVED0235 0x0235 RESERVED RESERVED0236 0x0236 RESERVED RESERVED0237 0x0237 RESERVED RESERVED0238 0x0238 RESERVED RESERVED0239 0x0239 RESERVED RESERVED023A 0x023A RESERVED RESERVED023B 0x023B RESERVED RESERVED023C 0x023C RESERVED PCTLCAN2 0x023D msCAN12 Port CAN Control Register PCTLCAN2.PUPCAN 1 Pull-Up Enable Port CAN PCTLCAN2.RDPCAN 0 Reduced Drive Port CAN PORTCAN2 0x023E msCAN12 Port CAN Data Register PORTCAN2.PCAN7 7 Port CAN Data Bit 7 PORTCAN2.PCAN6 6 Port CAN Data Bit 6 PORTCAN2.PCAN5 5 Port CAN Data Bit 5 PORTCAN2.PCAN4 4 Port CAN Data Bit 4 PORTCAN2.PCAN3 3 Port CAN Data Bit 3 PORTCAN2.PCAN2 2 Port CAN Data Bit 2 PORTCAN2.TxCAN 1 PORTCAN2.RxCAN 0 DDRCAN2 0x023F msCAN12 Port CAN Data Direction Register DDRCAN2.DDCAN7 7 DDRCAN2.DDCAN6 6 DDRCAN2.DDCAN5 5 DDRCAN2.DDCAN4 4 DDRCAN2.DDCAN3 3 DDRCAN2.DDCAN2 2 C1MCR0 0x0300 msCAN12 Module Control Register 0 C1MCR0.CSWAI 5 CAN Stops in Wait Mode C1MCR0.SYNCH 4 Synchronized Status C1MCR0.TLNKEN 3 Timer Enable C1MCR0.SLPAK 2 SLEEP Mode Acknowledge C1MCR0.SLPRQ 1 SLEEP request C1MCR0.SFTRES 0 SOFT_RESET C1MCR1 0x0301 msCAN12 Module Control Register 1 C1MCR1.LOOPB 2 Loop Back Self Test Mode C1MCR1.WUPM 1 Wake-Up Mode C1MCR1.CLKSRC 0 msCAN12 Clock Source C1BTR0 0x0302 msCAN12 Bus Timing Register 0 C1BTR0.SJW1 7 Synchronization Jump Width 1 C1BTR0.SJW0 6 Synchronization Jump Width 0 C1BTR0.BRP5 5 Baud Rate Prescaler 5 C1BTR0.BRP4 4 Baud Rate Prescaler 4 C1BTR0.BRP3 3 Baud Rate Prescaler 3 C1BTR0.BRP2 2 Baud Rate Prescaler 2 C1BTR0.BRP1 1 Baud Rate Prescaler 1 C1BTR0.BRP0 0 Baud Rate Prescaler 0 C1BTR1 0x0303 msCAN12 Bus Timing Register 1 C1BTR1.SAMP 7 Sampling C1BTR1.TSEG22 6 Time Segment 22 C1BTR1.TSEG21 5 Time Segment 21 C1BTR1.TSEG20 4 Time Segment 20 C1BTR1.TSEG13 3 Time Segment 13 C1BTR1.TSEG12 2 Time Segment 12 C1BTR1.TSEG11 1 Time Segment 11 C1BTR1.TSEG10 0 Time Segment 10 C1RFLG 0x0304 msCAN12 Receiver Flag Register C1RFLG.WUPIF 7 Wake-up Interrupt Flag C1RFLG.RWRNIF 6 Receiver Warning Interrupt Flag C1RFLG.TWRNIF 5 Transmitter Warning Interrupt Flag C1RFLG.RERRIF 4 Receiver Error Passive Interrupt Flag C1RFLG.TERRIF 3 Transmitter Error Passive Interrupt Flag C1RFLG.BOFFIF 2 BUSOFF Interrupt Flag C1RFLG.OVRIF 1 Overrun Interrupt Flag C1RFLG.RXF 0 Receive Buffer Full C1RIER 0x0305 msCAN12 Receiver Interrupt Enable Register C1RIER.WUPIE 7 Wake-up Interrupt Enable C1RIER.RWRNIE 6 Receiver Warning Interrupt Enable C1RIER.TWRNIE 5 Transmitter Warning Interrupt Enable C1RIER.RERRIE 4 Receiver Error Passive Interrupt Enable C1RIER.TERRIE 3 Transmitter Error Passive Interrupt Enable C1RIER.BOFFIE 2 BUSOFF Interrupt Enable C1RIER.OVRIE 1 Overrun Interrupt Enable C1RIER.RXFIE 0 Receiver Full Interrupt Enable C1TFLG 0x0306 msCAN12 Transmitter Flag Register C1TFLG.ABTAK2 6 Abort Acknowledge 2 C1TFLG.ABTAK1 5 Abort Acknowledge 1 C1TFLG.ABTAK0 4 Abort Acknowledge 0 C1TFLG.TXE2 2 Transmitter Buffer Empty 2 C1TFLG.TXE1 1 Transmitter Buffer Empty 1 C1TFLG.TXE0 0 Transmitter Buffer Empty 0 C1TCR 0x0307 msCAN12 Transmitter Control Register C1TCR.ABTRQ2 6 Abort Request 2 C1TCR.ABTRQ1 5 Abort Request 1 C1TCR.ABTRQ0 4 Abort Request 0 C1TCR.TXEIE2 2 Transmitter Empty Interrupt Enable 2 C1TCR.TXEIE1 1 Transmitter Empty Interrupt Enable 1 C1TCR.TXEIE0 0 Transmitter Empty Interrupt Enable 0 C1IDAC 0x0308 msCAN12 Identifier Acceptance Control Register C1IDAC.IDAM1 5 Identifier Acceptance Mode 1 C1IDAC.IDAM0 4 Identifier Acceptance Mode 0 C1IDAC.IDHIT2 2 Identifier Acceptance Hit Indicator 2 C1IDAC.IDHIT1 1 Identifier Acceptance Hit Indicator 1 C1IDAC.IDHIT0 0 Identifier Acceptance Hit Indicator 0 RESERVED0309 0x0309 RESERVED RESERVED030A 0x030A RESERVED RESERVED030B 0x030B RESERVED RESERVED030C 0x030C RESERVED RESERVED030D 0x030D RESERVED C1RXERR 0x030E msCAN12 Receive Error Counter C1RXERR.RXERR7 7 C1RXERR.RXERR6 6 C1RXERR.RXERR5 5 C1RXERR.RXERR4 4 C1RXERR.RXERR3 3 C1RXERR.RXERR2 2 C1RXERR.RXERR1 1 C1RXERR.RXERR0 0 C1TXERR 0x030F msCAN12 Transmit Error Counter C1TXERR.TXERR7 7 C1TXERR.TXERR6 6 C1TXERR.TXERR5 5 C1TXERR.TXERR4 4 C1TXERR.TXERR3 3 C1TXERR.TXERR2 2 C1TXERR.TXERR1 1 C1TXERR.TXERR0 0 C1IDAR0 0x0310 msCAN12 Identifier Acceptance Register 0 C1IDAR0.AC7 7 Acceptance Code Bit 7 C1IDAR0.AC6 6 Acceptance Code Bit 6 C1IDAR0.AC5 5 Acceptance Code Bit 5 C1IDAR0.AC4 4 Acceptance Code Bit 4 C1IDAR0.AC3 3 Acceptance Code Bit 3 C1IDAR0.AC2 2 Acceptance Code Bit 2 C1IDAR0.AC1 1 Acceptance Code Bit 1 C1IDAR0.AC0 0 Acceptance Code Bit 0 C1IDAR1 0x0311 msCAN12 Identifier Acceptance Register 1 C1IDAR1.AC7 7 Acceptance Code Bit 7 C1IDAR1.AC6 6 Acceptance Code Bit 6 C1IDAR1.AC5 5 Acceptance Code Bit 5 C1IDAR1.AC4 4 Acceptance Code Bit 4 C1IDAR1.AC3 3 Acceptance Code Bit 3 C1IDAR1.AC2 2 Acceptance Code Bit 2 C1IDAR1.AC1 1 Acceptance Code Bit 1 C1IDAR1.AC0 0 Acceptance Code Bit 0 C1IDAR2 0x0312 msCAN12 Identifier Acceptance Register 2 C1IDAR2.AC7 7 Acceptance Code Bit 7 C1IDAR2.AC6 6 Acceptance Code Bit 6 C1IDAR2.AC5 5 Acceptance Code Bit 5 C1IDAR2.AC4 4 Acceptance Code Bit 4 C1IDAR2.AC3 3 Acceptance Code Bit 3 C1IDAR2.AC2 2 Acceptance Code Bit 2 C1IDAR2.AC1 1 Acceptance Code Bit 1 C1IDAR2.AC0 0 Acceptance Code Bit 0 C1IDAR3 0x0313 msCAN12 Identifier Acceptance Register 3 C1IDAR3.AC7 7 Acceptance Code Bit 7 C1IDAR3.AC6 6 Acceptance Code Bit 6 C1IDAR3.AC5 5 Acceptance Code Bit 5 C1IDAR3.AC4 4 Acceptance Code Bit 4 C1IDAR3.AC3 3 Acceptance Code Bit 3 C1IDAR3.AC2 2 Acceptance Code Bit 2 C1IDAR3.AC1 1 Acceptance Code Bit 1 C1IDAR3.AC0 0 Acceptance Code Bit 0 C1IDMR0 0x0314 msCAN12 Identifier Mask Register 0 C1IDMR0.AM7 7 Acceptance Mask Bit 7 C1IDMR0.AM6 6 Acceptance Mask Bit 6 C1IDMR0.AM5 5 Acceptance Mask Bit 5 C1IDMR0.AM4 4 Acceptance Mask Bit 4 C1IDMR0.AM3 3 Acceptance Mask Bit 3 C1IDMR0.AM2 2 Acceptance Mask Bit 2 C1IDMR0.AM1 1 Acceptance Mask Bit 1 C1IDMR0.AM0 0 Acceptance Mask Bit 0 C1IDMR1 0x0315 msCAN12 Identifier Mask Register 1 C1IDMR1.AM7 7 Acceptance Mask Bit 7 C1IDMR1.AM6 6 Acceptance Mask Bit 6 C1IDMR1.AM5 5 Acceptance Mask Bit 5 C1IDMR1.AM4 4 Acceptance Mask Bit 4 C1IDMR1.AM3 3 Acceptance Mask Bit 3 C1IDMR1.AM2 2 Acceptance Mask Bit 2 C1IDMR1.AM1 1 Acceptance Mask Bit 1 C1IDMR1.AM0 0 Acceptance Mask Bit 0 C1IDMR2 0x0316 msCAN12 Identifier Mask Register 2 C1IDMR2.AM7 7 Acceptance Mask Bit 7 C1IDMR2.AM6 6 Acceptance Mask Bit 6 C1IDMR2.AM5 5 Acceptance Mask Bit 5 C1IDMR2.AM4 4 Acceptance Mask Bit 4 C1IDMR2.AM3 3 Acceptance Mask Bit 3 C1IDMR2.AM2 2 Acceptance Mask Bit 2 C1IDMR2.AM1 1 Acceptance Mask Bit 1 C1IDMR2.AM0 0 Acceptance Mask Bit 0 C1IDMR3 0x0317 msCAN12 Identifier Mask Register 3 C1IDMR3.AM7 7 Acceptance Mask Bit 7 C1IDMR3.AM6 6 Acceptance Mask Bit 6 C1IDMR3.AM5 5 Acceptance Mask Bit 5 C1IDMR3.AM4 4 Acceptance Mask Bit 4 C1IDMR3.AM3 3 Acceptance Mask Bit 3 C1IDMR3.AM2 2 Acceptance Mask Bit 2 C1IDMR3.AM1 1 Acceptance Mask Bit 1 C1IDMR3.AM0 0 Acceptance Mask Bit 0 C1IDAR4 0x0318 msCAN12 Identifier Acceptance Register 4 C1IDAR4.AC7 7 Acceptance Code Bit 7 C1IDAR4.AC6 6 Acceptance Code Bit 6 C1IDAR4.AC5 5 Acceptance Code Bit 5 C1IDAR4.AC4 4 Acceptance Code Bit 4 C1IDAR4.AC3 3 Acceptance Code Bit 3 C1IDAR4.AC2 2 Acceptance Code Bit 2 C1IDAR4.AC1 1 Acceptance Code Bit 1 C1IDAR4.AC0 0 Acceptance Code Bit 0 C1IDAR5 0x0319 msCAN12 Identifier Acceptance Register 5 C1IDAR5.AC7 7 Acceptance Code Bit 7 C1IDAR5.AC6 6 Acceptance Code Bit 6 C1IDAR5.AC5 5 Acceptance Code Bit 5 C1IDAR5.AC4 4 Acceptance Code Bit 4 C1IDAR5.AC3 3 Acceptance Code Bit 3 C1IDAR5.AC2 2 Acceptance Code Bit 2 C1IDAR5.AC1 1 Acceptance Code Bit 1 C1IDAR5.AC0 0 Acceptance Code Bit 0 C1IDAR6 0x031A msCAN12 Identifier Acceptance Register 6 C1IDAR6.AC7 7 Acceptance Code Bit 7 C1IDAR6.AC6 6 Acceptance Code Bit 6 C1IDAR6.AC5 5 Acceptance Code Bit 5 C1IDAR6.AC4 4 Acceptance Code Bit 4 C1IDAR6.AC3 3 Acceptance Code Bit 3 C1IDAR6.AC2 2 Acceptance Code Bit 2 C1IDAR6.AC1 1 Acceptance Code Bit 1 C1IDAR6.AC0 0 Acceptance Code Bit 0 C1IDAR7 0x031B msCAN12 Identifier Acceptance Register 7 C1IDAR7.AC7 7 Acceptance Code Bit 7 C1IDAR7.AC6 6 Acceptance Code Bit 6 C1IDAR7.AC5 5 Acceptance Code Bit 5 C1IDAR7.AC4 4 Acceptance Code Bit 4 C1IDAR7.AC3 3 Acceptance Code Bit 3 C1IDAR7.AC2 2 Acceptance Code Bit 2 C1IDAR7.AC1 1 Acceptance Code Bit 1 C1IDAR7.AC0 0 Acceptance Code Bit 0 C1IDMR4 0x031C msCAN12 Identifier Mask Register 4 C1IDMR4.AM7 7 Acceptance Mask Bit 7 C1IDMR4.AM6 6 Acceptance Mask Bit 6 C1IDMR4.AM5 5 Acceptance Mask Bit 5 C1IDMR4.AM4 4 Acceptance Mask Bit 4 C1IDMR4.AM3 3 Acceptance Mask Bit 3 C1IDMR4.AM2 2 Acceptance Mask Bit 2 C1IDMR4.AM1 1 Acceptance Mask Bit 1 C1IDMR4.AM0 0 Acceptance Mask Bit 0 C1IDMR5 0x031D msCAN12 Identifier Mask Register 5 C1IDMR5.AM7 7 Acceptance Mask Bit 7 C1IDMR5.AM6 6 Acceptance Mask Bit 6 C1IDMR5.AM5 5 Acceptance Mask Bit 5 C1IDMR5.AM4 4 Acceptance Mask Bit 4 C1IDMR5.AM3 3 Acceptance Mask Bit 3 C1IDMR5.AM2 2 Acceptance Mask Bit 2 C1IDMR5.AM1 1 Acceptance Mask Bit 1 C1IDMR5.AM0 0 Acceptance Mask Bit 0 C1IDMR6 0x031E msCAN12 Identifier Mask Register 6 C1IDMR6.AM7 7 Acceptance Mask Bit 7 C1IDMR6.AM6 6 Acceptance Mask Bit 6 C1IDMR6.AM5 5 Acceptance Mask Bit 5 C1IDMR6.AM4 4 Acceptance Mask Bit 4 C1IDMR6.AM3 3 Acceptance Mask Bit 3 C1IDMR6.AM2 2 Acceptance Mask Bit 2 C1IDMR6.AM1 1 Acceptance Mask Bit 1 C1IDMR6.AM0 0 Acceptance Mask Bit 0 C1IDMR7 0x031F msCAN12 Identifier Mask Register 7 C1IDMR7.AM7 7 Acceptance Mask Bit 7 C1IDMR7.AM6 6 Acceptance Mask Bit 6 C1IDMR7.AM5 5 Acceptance Mask Bit 5 C1IDMR7.AM4 4 Acceptance Mask Bit 4 C1IDMR7.AM3 3 Acceptance Mask Bit 3 C1IDMR7.AM2 2 Acceptance Mask Bit 2 C1IDMR7.AM1 1 Acceptance Mask Bit 1 C1IDMR7.AM0 0 Acceptance Mask Bit 0 RESERVED0320 0x0320 RESERVED RESERVED0321 0x0321 RESERVED RESERVED0322 0x0322 RESERVED RESERVED0323 0x0323 RESERVED RESERVED0324 0x0324 RESERVED RESERVED0325 0x0325 RESERVED RESERVED0326 0x0326 RESERVED RESERVED0327 0x0327 RESERVED RESERVED0328 0x0328 RESERVED RESERVED0329 0x0329 RESERVED RESERVED032A 0x032A RESERVED RESERVED032B 0x032B RESERVED RESERVED032C 0x032C RESERVED RESERVED032D 0x032D RESERVED RESERVED032E 0x032E RESERVED RESERVED032F 0x032F RESERVED RESERVED0330 0x0330 RESERVED RESERVED0331 0x0331 RESERVED RESERVED0332 0x0332 RESERVED RESERVED0333 0x0333 RESERVED RESERVED0334 0x0334 RESERVED RESERVED0335 0x0335 RESERVED RESERVED0336 0x0336 RESERVED RESERVED0337 0x0337 RESERVED RESERVED0338 0x0338 RESERVED RESERVED0339 0x0339 RESERVED RESERVED033A 0x033A RESERVED RESERVED033B 0x033B RESERVED RESERVED033C 0x033C RESERVED PCTLCAN1 0x033D msCAN12 Port CAN Control Register PCTLCAN1.PUPCAN 1 Pull-Up Enable Port CAN PCTLCAN1.RDPCAN 0 Reduced Drive Port CAN PORTCAN1 0x033E msCAN12 Port CAN Data Register PORTCAN1.PCAN7 7 Port CAN Data Bit 7 PORTCAN1.PCAN6 6 Port CAN Data Bit 6 PORTCAN1.PCAN5 5 Port CAN Data Bit 5 PORTCAN1.PCAN4 4 Port CAN Data Bit 4 PORTCAN1.PCAN3 3 Port CAN Data Bit 3 PORTCAN1.PCAN2 2 Port CAN Data Bit 2 PORTCAN1.TxCAN 1 PORTCAN1.RxCAN 0 DDRCAN1 0x033F msCAN12 Port CAN Data Direction Register DDRCAN1.DDCAN7 7 DDRCAN1.DDCAN6 6 DDRCAN1.DDCAN5 5 DDRCAN1.DDCAN4 4 DDRCAN1.DDCAN3 3 DDRCAN1.DDCAN2 2 .68HC912DT128P ; MEMORY MAP area DATA FSR_0 0x0000:0x0140 area DATA RxFG0 0x0140:0x0150 FOREGROUND RECEIVE BUFFER 0 area DATA Tx00 0x0150:0x0160 TRANSMIT BUFFER 00 area DATA Tx01 0x0160:0x0170 TRANSMIT BUFFER 01 area DATA Tx02 0x0170:0x0180 TRANSMIT BUFFER 02 area BSS RESERVED 0x0180:0x01E2 area DATA FSR_1 0x01E2:0x0240 area DATA RxFG2 0x0240:0x0250 FOREGROUND RECEIVE BUFFER 2 area DATA Tx20 0x0250:0x0260 TRANSMIT BUFFER 20 area DATA Tx21 0x0260:0x0270 TRANSMIT BUFFER 21 area DATA Tx22 0x0270:0x0280 TRANSMIT BUFFER 22 area BSS RESERVED 0x0280:0x0300 area DATA FSR_2 0x0300:0x0340 area DATA RxFG1 0x0340:0x0350 FOREGROUND RECEIVE BUFFER 1 area DATA Tx10 0x0350:0x0360 TRANSMIT BUFFER 10 area DATA Tx11 0x0360:0x0370 TRANSMIT BUFFER 11 area DATA Tx12 0x0370:0x0380 TRANSMIT BUFFER 12 area BSS RESERVED 0x0380:0x0800 area DATA EEPROM 0x0800:0x1000 area BSS RESERVED 0x1000:0x2000 area DATA RAM 0x2000:0x4000 area DATA FLASH_EEPROM_1 0x4000:0x8000 16K Fixed Flash EEPROM area DATA FLASH_EEPROM_2 0x8000:0xA000 16K Page Window Eight 16K Flash EEPROM pages area DATA PROT_BOOT_1 0xA000:0xC000 Protected BOOT at odd programing pages area DATA FLASH_EEPROM_3 0xC000:0xE000 16K Fixed Flash EEPROM area DATA PROT_BOOT_2 0xE000:0xFF00 Protected BOOT area DATA USER_VEC 0xFF00:0x10000 ; Interrupt and reset vector assignments interrupt __RESET 0xFFFE Reset interrupt _COPCTL 0xFFFC Clock monitor fail reset interrupt COP_F_R 0xFFFA COP failure reset interrupt UIT 0xFFF8 Unimplemented instruction trap interrupt SWI 0xFFF6 SWI interrupt XIRQ 0xFFF4 XIRQ interrupt INTCR_IRQEN 0xFFF2 IRQ interrupt RTICTL_RTIE 0xFFF0 Real time interrupt interrupt TMSK1_C0I 0xFFEE Timer channel 0 interrupt TMSK1_C1I 0xFFEC Timer channel 1 interrupt TMSK1_C2I 0xFFEA Timer channel 2 interrupt TMSK1_C3I 0xFFE8 Timer channel 3 interrupt TMSK1_C4I 0xFFE6 Timer channel 4 interrupt TMSK1_C5I 0xFFE4 Timer channel 5 interrupt TMSK1_C6I 0xFFE2 Timer channel 6 interrupt TMSK1_C7I 0xFFE0 Timer channel 7 interrupt TMSK2_TOI 0xFFDE Timer overflow interrupt PACTL_PAOVI 0xFFDC Pulse accumulator overflow interrupt PACTL_PAI 0xFFDA Pulse accumulator input edge interrupt SP0CR1_SPIE 0xFFD8 SPI serial transfer complete interrupt _SC0CR2 0xFFD6 SCI 0 interrupt _SC1CR2 0xFFD4 SCI 1 interrupt ATDxCTL2_ASCIE 0xFFD2 ATD0 or ATD1 interrupt C0RIER_WUPIE 0xFFD0 MSCAN 0 wake-up interrupt KWIEJ_KWIEH 0xFFCE Key wake-up J or H interrupt MCCTL_MCZI 0xFFCC Modulus down counter underflow interrupt PBCTL_PBOVI 0xFFCA Pulse Accumulator B Overflow interrupt C0RIER 0xFFC8 MSCAN 0 errors interrupt C0RIER_RXFIE 0xFFC6 MSCAN 0 receive interrupt C0TCR_TXEIE 0xFFC4 MSCAN 0 transmit interrupt PLLCR_LOCKIE_LHIE 0xFFC2 CGM lock and limp home interrupt IBCR_IBIE 0xFFC0 IIC Bus interrupt C1RIER_WUPIE 0xFFBE MSCAN 1 wake-up interrupt C1RIER 0xFFBC MSCAN 1 errors interrupt C1RIER_RXFIE 0xFFBA MSCAN 1 receive interrupt C1TCR_TXEIE 0xFFB8 MSCAN 1 transmit interrupt C2RIER_WUPIE 0xFFB6 MSCAN 2 wake-up interrupt C2RIER 0xFFB4 MSCAN 2 errors interrupt C2RIER_RXFIE 0xFFB2 MSCAN 2 receive interrupt C2TCR_TXEIE 0xFFB0 MSCAN 2 transmit ; INPUT/ OUTPUT PORTS PORTA 0x0000 Port A Data Register PORTA.PA7 7 Port A Data Bit 7 PORTA.PA6 6 Port A Data Bit 6 PORTA.PA5 5 Port A Data Bit 5 PORTA.PA4 4 Port A Data Bit 4 PORTA.PA3 3 Port A Data Bit 3 PORTA.PA2 2 Port A Data Bit 2 PORTA.PA1 1 Port A Data Bit 1 PORTA.PA0 0 Port A Data Bit 0 PORTB 0x0001 Port B Data Register PORTB.PB7 7 Port B Data Bit 7 PORTB.PB6 6 Port B Data Bit 6 PORTB.PB5 5 Port B Data Bit 5 PORTB.PB4 4 Port B Data Bit 4 PORTB.PB3 3 Port B Data Bit 3 PORTB.PB2 2 Port B Data Bit 2 PORTB.PB1 1 Port B Data Bit 1 PORTB.PB0 0 Port B Data Bit 0 DDRA 0x0002 Port A Data Direction Register DDRA.DDA7 7 Port A Data Direction Bit 7 DDRA.DDA6 6 Port A Data Direction Bit 6 DDRA.DDA5 5 Port A Data Direction Bit 5 DDRA.DDA4 4 Port A Data Direction Bit 4 DDRA.DDA3 3 Port A Data Direction Bit 3 DDRA.DDA2 2 Port A Data Direction Bit 2 DDRA.DDA1 1 Port A Data Direction Bit 1 DDRA.DDA0 0 Port A Data Direction Bit 0 DDRB 0x0003 Port B Data Direction Register DDRB.DDB7 7 Port B Data Direction Bit 7 DDRB.DDB6 6 Port B Data Direction Bit 6 DDRB.DDB5 5 Port B Data Direction Bit 5 DDRB.DDB4 4 Port B Data Direction Bit 4 DDRB.DDB3 3 Port B Data Direction Bit 3 DDRB.DDB2 2 Port B Data Direction Bit 2 DDRB.DDB1 1 Port B Data Direction Bit 1 DDRB.DDB0 0 Port B Data Direction Bit 0 RESERVED0004 0x0004 RESERVED RESERVED0005 0x0005 RESERVED RESERVED0006 0x0006 RESERVED RESERVED0007 0x0007 RESERVED PORTE 0x0008 Port E Data Register PORTE.PE7 7 Port E Data Bit 7 PORTE.PE6 6 Port E Data Bit 6 PORTE.PE5 5 Port E Data Bit 5 PORTE.PE4 4 Port E Data Bit 4 PORTE.PE3 3 Port E Data Bit 3 PORTE.PE2 2 Port E Data Bit 2 PORTE.PE1 1 Port E Data Bit 1 PORTE.PE0 0 Port E Data Bit 0 DDRE 0x0009 Port E Data Direction Register DDRE.DDE7 7 Port E Data Direction Bit 7 DDRE.DDE6 6 Port E Data Direction Bit 6 DDRE.DDE5 5 Port E Data Direction Bit 5 DDRE.DDE4 4 Port E Data Direction Bit 4 DDRE.DDE3 3 Port E Data Direction Bit 3 DDRE.DDE2 2 Port E Data Direction Bit 2 PEAR 0x000A Port E Assignment Register PEAR.NDBE 7 No Data Bus Enable PEAR.CGMTE 6 Clock Generator Module Testing Enable PEAR.PIPOE 5 Pipe Status Signal Output Enable PEAR.NECLK 4 No External E Clock PEAR.LSTRE 3 Low Strobe (LSTRB) Enable PEAR.RDWE 2 Read/Write Enable PEAR.CALE 1 Calibration Reference Enable PEAR.DBENE 0 DBE or Inverted E Clock on PE7 MODE 0x000B Mode Register MODE.SMODN 7 Mode Select Special MODE.MODB 6 Mode Select B MODE.MODA 5 Mode Select A MODE.ESTR 4 E Clock Stretch Enable MODE.IVIS 3 Internal Visibility MODE.EBSWAI 2 External Bus Module Stop in Wait Control MODE.EMK 1 Emulate Port K MODE.EME 0 PUCR 0x000C Pull-Up Control Register PUCR.PUPK 7 Pull-Up Port K Enable PUCR.PUPJ 6 Pull-Up or Pull-Down Port J Enable PUCR.PUPH 5 Pull-Up or Pull-Down Port H Enable PUCR.PUPE 4 Pull-Up Port E Enable PUCR.PUPB 1 Pull-Up Port B Enable PUCR.PUPA 0 Pull-Up Port A Enable RDRIV 0x000D Reduced Drive of I/O Lines RDRIV.RDPK 7 Reduced Drive of Port K RDRIV.RDPJ 6 Reduced Drive of Port J RDRIV.RDPH 5 Reduced Drive of Port H RDRIV.RDPE 4 Reduced Drive of Port E RDRIV.RDPB 1 Reduced Drive of Port B RDRIV.RDPA 0 Reduced Drive of Port A RESERVED000E 0x000E RESERVED RESERVED000F 0x000F RESERVED INITRM 0x0010 Initialization of Internal RAM Position Register INITRM.RAM15 7 Internal RAM map position 15 INITRM.RAM14 6 Internal RAM map position 14 INITRM.RAM13 5 Internal RAM map position 13 INITRG 0x0011 Initialization of Internal Register Position Register INITRG.REG15 7 Internal register map position 15 INITRG.REG14 6 Internal register map position 14 INITRG.REG13 5 Internal register map position 13 INITRG.REG12 4 Internal register map position 12 INITRG.REG11 3 Internal register map position 11 INITEE 0x0012 Initialization of Internal EEPROM Position Register INITEE.EE15 7 Internal EEPROM map position 15 INITEE.EE14 6 Internal EEPROM map position 14 INITEE.EE13 5 Internal EEPROM map position 13 INITEE.EE12 4 Internal EEPROM map position 12 INITEE.EEON 0 internal EEPROM On (Enabled) MISC 0x0013 Miscellaneous Mapping Control Register MISC.ROMTST 7 FLASH EEPROM Test mode MISC.NDRF 6 Narrow Data Bus for Register-Following Map Space MISC.RFSTR1 5 Register Following Stretch 1 MISC.RFSTR0 4 Register Following Stretch 0 MISC.EXSTR1 3 External Access Stretch 1 MISC.EXSTR0 2 External Access Stretch 0 MISC.ROMHM 1 FLASH EEPROM only in second Half of Map MISC.ROMON 0 Enable FLASH EEPROM RTICTL 0x0014 Real-Time Interrupt Control Register RTICTL.RTIE 7 Real Time Interrupt Enable RTICTL.RSWAI 6 RTI and COP Stop While in Wait RTICTL.RSBCK 5 RTI and COP Stop While in Background Debug Mode RTICTL.RTBYP 3 Real Time Interrupt Divider Chain Bypass RTICTL.RTR2 2 Real-Time Interrupt Rate Select 2 RTICTL.RTR1 1 Real-Time Interrupt Rate Select 1 RTICTL.RTR0 0 Real-Time Interrupt Rate Select 0 RTIFLG 0x0015 Real Time Interrupt Flag Register RTIFLG.RTIF 7 Real Time Interrupt Flag COPCTL 0x0016 COP Control Register COPCTL.CME 7 Clock Monitor Enable COPCTL.FCME 6 Force Clock Monitor Enable COPCTL.FCMCOP 5 Force Clock Monitor Reset or COP Watchdog Reset COPCTL.WCOP 4 Window COP mode COPCTL.DISR 3 Disable Resets from COP Watchdog and Clock Monitor COPCTL.CR2 2 COP Watchdog Timer Rate select bit 2 COPCTL.CR1 1 COP Watchdog Timer Rate select bit 1 COPCTL.CR0 0 COP Watchdog Timer Rate select bit 0 COPRST 0x0017 Arm/Reset COP Timer Register ITST0 0x0018 Interrupt Test Register 0 ITST0.ITE6 7 ITST0.ITE8 6 ITST0.ITEA 5 ITST0.ITEC 4 ITST0.ITEE 3 ITST0.ITF0 2 ITST0.ITF2 1 ITST0.ITF4 0 ITST1 0x0019 Interrupt Test Register 1 ITST1.ITD6 7 ITST1.ITD8 6 ITST1.ITDA 5 ITST1.ITDC 4 ITST1.ITDE 3 ITST1.ITE0 2 ITST1.ITE2 1 ITST1.ITE4 0 ITST2 0x001A Interrupt Test Register 2 ITST2.ITC6 7 ITST2.ITC8 6 ITST2.ITCA 5 ITST2.ITCC 4 ITST2.ITCE 3 ITST2.ITD0 2 ITST2.ITD2 1 ITST2.ITD4 0 ITST3 0x001B Interrupt Test Register 3 ITST3.ITB6 7 ITST3.ITB8 6 ITST3.ITBA 5 ITST3.ITBC 4 ITST3.ITBE 3 ITST3.ITC0 2 ITST3.ITC2 1 ITST3.ITC4 0 RESERVED001C 0x001C RESERVED RESERVED001D 0x001D RESERVED INTCR 0x001E Interrupt Control Register INTCR.IRQE 7 IRQ Select Edge Sensitive Only INTCR.IRQEN 6 External IRQ Enable INTCR.DLY 5 Enable Oscillator Start-up Delay on Exit from STOP HPRIO 0x001F Highest Priority I Interrupt HPRIO.PSEL6 6 HPRIO.PSEL5 5 HPRIO.PSEL4 4 HPRIO.PSEL3 3 HPRIO.PSEL2 2 HPRIO.PSEL1 1 BRKCT0 0x0020 Breakpoint Control Register 0 BRKCT0.BKEN1 7 Breakpoint Mode Enable 1 BRKCT0.BKEN0 6 Breakpoint Mode Enable 0 BRKCT0.BKPM 5 Break on Program Addresses BRKCT0.BK1ALE 3 Breakpoint 1 Range Control BRKCT0.BK0ALE 2 Breakpoint 0 Range Control BRKCT1 0x0021 Breakpoint Control Register 1 BRKCT1.BKDBE 6 Enable Data Bus BRKCT1.BKMBH 5 Breakpoint Mask High BRKCT1.BKMBL 4 Breakpoint Mask Low BRKCT1.BK1RWE 3 R/W Compare Enable BRKCT1.BK1RW 2 R/W Compare Value BRKCT1.BK0RWE 1 R/W Compare Enable BRKCT1.BK0RW 0 R/W Compare Value BRKAH 0x0022 Breakpoint Address Register, High Byte BRKAL 0x0023 Breakpoint Address Register, Low Byte BRKDH 0x0024 Breakpoint Data Register, High Byte BRKDL 0x0025 Breakpoint Data Register, Low Byte RESERVED0026 0x0026 RESERVED RESERVED0027 0x0027 RESERVED PORTJ 0x0028 Port J Data Register PORTJ.PJ7 7 Port J Data Bit 7 PORTJ.PJ6 6 Port J Data Bit 6 PORTJ.PJ5 5 Port J Data Bit 5 PORTJ.PJ4 4 Port J Data Bit 4 PORTJ.PJ3 3 Port J Data Bit 3 PORTJ.PJ2 2 Port J Data Bit 2 PORTJ.PJ1 1 Port J Data Bit 1 PORTJ.PJ0 0 Port J Data Bit 0 PORTH 0x0029 Port H Data Register PORTH.PH7 7 Port H Data Bit 7 PORTH.PH6 6 Port H Data Bit 6 PORTH.PH5 5 Port H Data Bit 5 PORTH.PH4 4 Port H Data Bit 4 PORTH.PH3 3 Port H Data Bit 3 PORTH.PH2 2 Port H Data Bit 2 PORTH.PH1 1 Port H Data Bit 1 PORTH.PH0 0 Port H Data Bit 0 DDRJ 0x002A Port J Data Direction Register DDRJ.DDRJ7 7 Data Direction Port J Bit 7 DDRJ.DDRJ6 6 Data Direction Port J Bit 6 DDRJ.DDRJ5 5 Data Direction Port J Bit 5 DDRJ.DDRJ4 4 Data Direction Port J Bit 4 DDRJ.DDRJ3 3 Data Direction Port J Bit 3 DDRJ.DDRJ2 2 Data Direction Port J Bit 2 DDRJ.DDRJ1 1 Data Direction Port J Bit 1 DDRJ.DDRJ0 0 Data Direction Port J Bit 0 DDRH 0x002B Port J Data Direction Register DDRH.DDRH7 7 Data Direction Port H Bit 7 DDRH.DDRH6 6 Data Direction Port H Bit 6 DDRH.DDRH5 5 Data Direction Port H Bit 5 DDRH.DDRH4 4 Data Direction Port H Bit 4 DDRH.DDRH3 3 Data Direction Port H Bit 3 DDRH.DDRH2 2 Data Direction Port H Bit 2 DDRH.DDRH1 1 Data Direction Port H Bit 1 DDRH.DDRH0 0 Data Direction Port H Bit 0 KWIEJ 0x002C Key Wake-up Port J Interrupt Enable Register KWIEJ.KWIEJ7 7 Key Wake-up Port J Interrupt Enable 7 KWIEJ.KWIEJ6 6 Key Wake-up Port J Interrupt Enable 6 KWIEJ.KWIEJ5 5 Key Wake-up Port J Interrupt Enable 5 KWIEJ.KWIEJ4 4 Key Wake-up Port J Interrupt Enable 4 KWIEJ.KWIEJ3 3 Key Wake-up Port J Interrupt Enable 3 KWIEJ.KWIEJ2 2 Key Wake-up Port J Interrupt Enable 2 KWIEJ.KWIEJ1 1 Key Wake-up Port J Interrupt Enable 1 KWIEJ.KWIEJ0 0 Key Wake-up Port J Interrupt Enable 0 KWIEH 0x002D Key Wake-up Port H Interrupt Enable Register KWIEH.KWIEH7 7 Key Wake-up Port H Interrupt Enable 7 KWIEH.KWIEH6 6 Key Wake-up Port H Interrupt Enable 6 KWIEH.KWIEH5 5 Key Wake-up Port H Interrupt Enable 5 KWIEH.KWIEH4 4 Key Wake-up Port H Interrupt Enable 4 KWIEH.KWIEH3 3 Key Wake-up Port H Interrupt Enable 3 KWIEH.KWIEH2 2 Key Wake-up Port H Interrupt Enable 2 KWIEH.KWIEH1 1 Key Wake-up Port H Interrupt Enable 1 KWIEH.KWIEH0 0 Key Wake-up Port H Interrupt Enable 0 KWIFJ 0x002E Key Wake-up Port J Flag Register KWIFJ.KWIFJ7 7 Key Wake-up Port J Flag 7 KWIFJ.KWIFJ6 6 Key Wake-up Port J Flag 6 KWIFJ.KWIFJ5 5 Key Wake-up Port J Flag 5 KWIFJ.KWIFJ4 4 Key Wake-up Port J Flag 4 KWIFJ.KWIFJ3 3 Key Wake-up Port J Flag 3 KWIFJ.KWIFJ2 2 Key Wake-up Port J Flag 2 KWIFJ.KWIFJ1 1 Key Wake-up Port J Flag 1 KWIFJ.KWIFJ0 0 Key Wake-up Port J Flag 0 KWIFH 0x002F Key Wake-up Port H Flag Register KWIFH.KWIFH7 7 Key Wake-up Port H Flag 7 KWIFH.KWIFH6 6 Key Wake-up Port H Flag 6 KWIFH.KWIFH5 5 Key Wake-up Port H Flag 5 KWIFH.KWIFH4 4 Key Wake-up Port H Flag 4 KWIFH.KWIFH3 3 Key Wake-up Port H Flag 3 KWIFH.KWIFH2 2 Key Wake-up Port H Flag 2 KWIFH.KWIFH1 1 Key Wake-up Port H Flag 1 KWIFH.KWIFH0 0 Key Wake-up Port H Flag 0 KWPJ 0x0030 Key Wake-up Port J Polarity Register KWPJ.KWPJ7 7 Key Wake-up Port J Polarity Select 7 KWPJ.KWPJ6 6 Key Wake-up Port J Polarity Select 6 KWPJ.KWPJ5 5 Key Wake-up Port J Polarity Select 5 KWPJ.KWPJ4 4 Key Wake-up Port J Polarity Select 4 KWPJ.KWPJ3 3 Key Wake-up Port J Polarity Select 3 KWPJ.KWPJ2 2 Key Wake-up Port J Polarity Select 2 KWPJ.KWPJ1 1 Key Wake-up Port J Polarity Select 1 KWPJ.KWPJ0 0 Key Wake-up Port J Polarity Select 0 KWPH 0x0031 Key Wake-up Port H Polarity Register KWPH.KWPH7 7 Key Wake-up Port H Polarity Select 7 KWPH.KWPH6 6 Key Wake-up Port H Polarity Select 6 KWPH.KWPH5 5 Key Wake-up Port H Polarity Select 5 KWPH.KWPH4 4 Key Wake-up Port H Polarity Select 4 KWPH.KWPH3 3 Key Wake-up Port H Polarity Select 3 KWPH.KWPH2 2 Key Wake-up Port H Polarity Select 2 KWPH.KWPH1 1 Key Wake-up Port H Polarity Select 1 KWPH.KWPH0 0 Key Wake-up Port H Polarity Select 0 RESERVED0032 0x0032 RESERVED RESERVED0033 0x0033 RESERVED RESERVED0034 0x0034 RESERVED RESERVED0035 0x0035 RESERVED RESERVED0036 0x0036 RESERVED RESERVED0037 0x0037 RESERVED SYNR 0x0038 Synthesizer Register SYNR.SYN5 5 SYNR.SYN4 4 SYNR.SYN3 3 SYNR.SYN2 2 SYNR.SYN1 1 SYNR.SYN0 0 REFDV 0x0039 Reference Divider Register REFDV.REFDV2 2 REFDV.REFDV1 1 REFDV.REFDV0 0 CGTFLG 0x003A Clock Generator Test Register CGTFLG.TSTOUT7 7 CGTFLG.TSTOUT6 6 CGTFLG.TSTOUT5 5 CGTFLG.TSTOUT4 4 CGTFLG.TSTOUT3 3 CGTFLG.TSTOUT2 2 CGTFLG.TSTOUT1 1 CGTFLG.TSTOUT0 0 PLLFLG 0x003B PLL Flags PLLFLG.LOCKIF 7 PLL Lock Interrupt Flag PLLFLG.LOCK 6 Locked Phase Lock Loop Circuit PLLFLG.LHIF 1 Limp-Home Interrupt Flag PLLFLG.LHOME 0 Limp-Home Mode Status PLLCR 0x003C PLL Control Register PLLCR.LOCKIE 7 PLL LOCK Interrupt Enable PLLCR.PLLON 6 Phase Lock Loop On PLLCR.AUTO 5 Automatic Bandwidth Control PLLCR.ACQ 4 Not in Acquisition PLLCR.PSTP 2 Pseudo-STOP Enable PLLCR.LHIE 1 Limp-Home Interrupt Enable PLLCR.NOLHM 0 No Limp-Home Mode CLKSEL 0x003D Clock Generator Clock select Register CLKSEL.BCSP 6 Bus Clock Select PLL CLKSEL.BCSS 5 Bus Clock Select Slow CLKSEL.MCS 2 Module Clock Select SLOW 0x003E Slow mode Divider Register SLOW.SLDV5 5 SLOW.SLDV4 4 SLOW.SLDV3 3 SLOW.SLDV2 2 SLOW.SLDV1 1 SLOW.SLDV0 0 CGTCTL 0x003F CGTCTL CGTCTL.OPNLE 7 CGTCTL.TRK 6 CGTCTL.TSTCLKE 5 CGTCTL.TST4 4 CGTCTL.TST3 3 CGTCTL.TST2 2 CGTCTL.TST1 1 CGTCTL.TST0 0 PWCLK 0x0040 PWM Clocks and Concatenate PWCLK.CON23 7 Concatenate PWM Channels 2 and 3 PWCLK.CON01 6 Concatenate PWM Channels 0 and 1 PWCLK.PCKA2 5 Prescaler for Clock A 2 PWCLK.PCKA1 4 Prescaler for Clock A 1 PWCLK.PCKA0 3 Prescaler for Clock A 0 PWCLK.PCKB2 2 Prescaler for Clock B 2 PWCLK.PCKB1 1 Prescaler for Clock B 1 PWCLK.PCKB0 0 Prescaler for Clock B 0 PWPOL 0x0041 PWM Clock Select and Polarity PWPOL.PCLK3 7 PWM Channel 3 Clock Select PWPOL.PCLK2 6 PWM Channel 2 Clock Select PWPOL.PCLK1 5 PWM Channel 1 Clock Select PWPOL.PCLK0 4 PWM Channel 0 Clock Select PWPOL.PPOL3 3 PWM Channel 3 Polarity PWPOL.PPOL2 2 PWM Channel 2 Polarity PWPOL.PPOL1 1 PWM Channel 1 Polarity PWPOL.PPOL0 0 PWM Channel 0 Polarity PWEN 0x0042 PWM Enable PWEN.PWEN3 3 PWM Channel 3 Enable PWEN.PWEN2 2 PWM Channel 2 Enable PWEN.PWEN1 1 PWM Channel 1 Enable PWEN.PWEN0 0 PWM Channel 0 Enable PWPRES 0x0043 PWM Prescale Counter PWSCAL0 0x0044 PWM Scale Register 0 PWSCNT0 0x0045 PWM Scale Counter 0 Value PWSCAL1 0x0046 PWM Scale Register 1 PWSCNT1 0x0047 PWM Scale Counter 1 Value PWCNT0 0x0048 PWM Channel Counter 0 PWCNT1 0x0049 PWM Channel Counter 1 PWCNT2 0x004A PWM Channel Counter 2 PWCNT3 0x004B PWM Channel Counter 3 PWPER0 0x004C PWM Channel Period Register 0 PWPER1 0x004D PWM Channel Period Register 1 PWPER2 0x004E PWM Channel Period Register 2 PWPER3 0x004F PWM Channel Period Register 3 PWDTY0 0x0050 PWM Channel Duty Register 0 PWDTY1 0x0051 PWM Channel Duty Register 1 PWDTY2 0x0052 PWM Channel Duty Register 2 PWDTY3 0x0053 PWM Channel Duty Register 3 PWCTL 0x0054 PWM Control Register PWCTL.PSWAI 4 PWM Halts while in Wait Mode PWCTL.CENTR 3 Center-Aligned Output Mode PWCTL.RDPP 2 Reduced Drive of Port P PWCTL.PUPP 1 Pull-Up Port P Enable PWCTL.PSBCK 0 PWM Stops while in Background Mode PWTST 0x0055 PWM Special Mode Register ("Test") PWTST.DISCR 7 Disable Reset of Channel Counter on Write to Channel Counter PWTST.DISCP 6 Disable Compare Count Period PWTST.DISCAL 5 Disable Load of Scale-Counters on Write to the Associated Scale-Registers PORTP 0x0056 Port P Data Register PORTP.PP7 7 Port P Data Bit 7 PORTP.PP6 6 Port P Data Bit 6 PORTP.PP5 5 Port P Data Bit 5 PORTP.PP4 4 Port P Data Bit 4 PORTP.PP3 3 Port P Data Bit 3 PORTP.PP2 2 Port P Data Bit 2 PORTP.PP1 1 Port P Data Bit 1 PORTP.PP0 0 Port P Data Bit 0 DDRP 0x0057 Port P Data Direction Register DDRP.DDP7 7 Port P Data Direction Bit 7 DDRP.DDP6 6 Port P Data Direction Bit 6 DDRP.DDP5 5 Port P Data Direction Bit 5 DDRP.DDP4 4 Port P Data Direction Bit 4 DDRP.DDP3 3 Port P Data Direction Bit 3 DDRP.DDP2 2 Port P Data Direction Bit 2 DDRP.DDP1 1 Port P Data Direction Bit 1 DDRP.DDP0 0 Port P Data Direction Bit 0 RESERVED0058 0x0058 RESERVED RESERVED0059 0x0059 RESERVED RESERVED005A 0x005A RESERVED RESERVED005B 0x005B RESERVED RESERVED005C 0x005C RESERVED RESERVED005D 0x005D RESERVED RESERVED005E 0x005E RESERVED RESERVED005F 0x005F RESERVED RESERVED0060 0x0060 RESERVED RESERVED0061 0x0061 RESERVED ATD0CTL2 0x0062 ATD0 Control Register 2 ATD0CTL2.ADPU 7 ATD Disable ATD0CTL2.AFFC 6 ATD Fast Flag Clear All ATD0CTL2.ASWAI 5 ATD Wait Mode ATD0CTL2.DJM 4 Result Register Data Justification Mode ATD0CTL2.DSGN 3 Signed/Unsigned Result Data Mode ATD0CTL2.ASCIE 1 ATD Sequence Complete Interrupt Enable ATD0CTL2.ASCIF 0 ATD Sequence Complete Interrupt Flag ATD0CTL3 0x0063 ATD0 Control Register 3 ATD0CTL3.S1C 3 Conversion Sequence Length (Least Significant Bit) ATD0CTL3.FIFO 2 Result Register FIFO Mode ATD0CTL3.FRZ1 1 Background Debug (Freeze) Enable 1 ATD0CTL3.FRZ0 0 Background Debug (Freeze) Enable 0 ATD0CTL4 0x0064 ATD0 Control Register 4 ATD0CTL4.RES10 7 10 bit Mode ATD0CTL4.SMP1 6 Select Sample Time 1 ATD0CTL4.SMP0 5 Select Sample Time 0 ATD0CTL4.PRS4 4 Select Divide-By Factor for ATD P-Clock Prescaler 4 ATD0CTL4.PRS3 3 Select Divide-By Factor for ATD P-Clock Prescaler 3 ATD0CTL4.PRS2 2 Select Divide-By Factor for ATD P-Clock Prescaler 2 ATD0CTL4.PRS1 1 Select Divide-By Factor for ATD P-Clock Prescaler 1 ATD0CTL4.PRS0 0 Select Divide-By Factor for ATD P-Clock Prescaler 0 ATD0CTL5 0x0065 ATD0 Control Register 5 ATD0CTL5.S8CM 6 Select 8 Channel Mode ATD0CTL5.SCAN 5 Enable Continuous Channel Scan ATD0CTL5.MULT 4 Enable Multichannel Conversion ATD0CTL5.CD 3 Channel Select for Conversion D ATD0CTL5.CC 2 Channel Select for Conversion C ATD0CTL5.CB 1 Channel Select for Conversion B ATD0CTL5.CA 0 Channel Select for Conversion A ATD0STAT0 0x0066 ATD0 Status Register ATD0STAT0.SCF 7 Sequence Complete Flag ATD0STAT0.CC2 2 Conversion Counter for Current Sequence of Four or Eight Conversions 2 ATD0STAT0.CC1 1 Conversion Counter for Current Sequence of Four or Eight Conversions 1 ATD0STAT0.CC0 0 Conversion Counter for Current Sequence of Four or Eight Conversions 0 ATD0STAT1 0x0067 ATD0 Status Register ATD0STAT1.CCF7 7 Conversion Complete Flag 7 ATD0STAT1.CCF6 6 Conversion Complete Flag 6 ATD0STAT1.CCF5 5 Conversion Complete Flag 5 ATD0STAT1.CCF4 4 Conversion Complete Flag 4 ATD0STAT1.CCF3 3 Conversion Complete Flag 3 ATD0STAT1.CCF2 2 Conversion Complete Flag 2 ATD0STAT1.CCF1 1 Conversion Complete Flag 1 ATD0STAT1.CCF0 0 Conversion Complete Flag 0 ATD0TESTH 0x0068 ATD0 Test Register ATD0TESTH.SAR9 7 SAR Data 9 ATD0TESTH.SAR8 6 SAR Data 8 ATD0TESTH.SAR7 5 SAR Data 7 ATD0TESTH.SAR6 4 SAR Data 6 ATD0TESTH.SAR5 3 SAR Data 5 ATD0TESTH.SAR4 2 SAR Data 4 ATD0TESTH.SAR3 1 SAR Data 3 ATD0TESTH.SAR2 0 SAR Data 2 ATD0TESTL 0x0069 ATD0 Test Register ATD0TESTL.SAR1 7 SAR Data 1 ATD0TESTL.SAR0 6 SAR Data 0 ATD0TESTL.RST 5 Module Reset Bit ATD0TESTL.TSTOUT 4 Multiplex Output of TST[3:0] (Factory Use) ATD0TESTL.TST3 3 Test Bit 3 ATD0TESTL.TST2 2 Test Bit 2 ATD0TESTL.TST1 1 Test Bit 1 ATD0TESTL.TST0 0 Test Bit 0 RESERVED006A 0x006A RESERVED RESERVED006B 0x006B RESERVED RESERVED006C 0x006C RESERVED RESERVED006D 0x006D RESERVED RESERVED006E 0x006E RESERVED PORTAD0 0x006F Port AD0 Data Input Register PORTAD0.PAD07 7 Port AD0 Data Input Bit 7 PORTAD0.PAD06 6 Port AD0 Data Input Bit 6 PORTAD0.PAD05 5 Port AD0 Data Input Bit 5 PORTAD0.PAD04 4 Port AD0 Data Input Bit 4 PORTAD0.PAD03 3 Port AD0 Data Input Bit 3 PORTAD0.PAD02 2 Port AD0 Data Input Bit 2 PORTAD0.PAD01 1 Port AD0 Data Input Bit 1 PORTAD0.PAD00 0 Port AD0 Data Input Bit 0 ADR00H 0x0070 A/D Conversion Result Register High 0 ADR00L 0x0071 A/D Conversion Result Register Low 0 ADR01H 0x0072 A/D Conversion Result Register High 1 ADR01L 0x0073 A/D Conversion Result Register Low 1 ADR02H 0x0074 A/D Conversion Result Register High 2 ADR02L 0x0075 A/D Conversion Result Register Low 2 ADR03H 0x0076 A/D Conversion Result Register High 3 ADR03L 0x0077 A/D Conversion Result Register Low 3 ADR04H 0x0078 A/D Conversion Result Register High 4 ADR04L 0x0079 A/D Conversion Result Register Low 4 ADR05H 0x007A A/D Conversion Result Register High 5 ADR05L 0x007B A/D Conversion Result Register Low 5 ADR06H 0x007C A/D Conversion Result Register High 6 ADR06L 0x007D A/D Conversion Result Register Low 6 ADR07H 0x007E A/D Conversion Result Register High 7 ADR07L 0x007F A/D Conversion Result Register Low 7 TIOS 0x0080 Timer Input Capture/Output Compare Select TIOS.IOS7 7 Input Capture or Output Compare Channel Configuration 7 TIOS.IOS6 6 Input Capture or Output Compare Channel Configuration 6 TIOS.IOS5 5 Input Capture or Output Compare Channel Configuration 5 TIOS.IOS4 4 Input Capture or Output Compare Channel Configuration 4 TIOS.IOS3 3 Input Capture or Output Compare Channel Configuration 3 TIOS.IOS2 2 Input Capture or Output Compare Channel Configuration 2 TIOS.IOS1 1 Input Capture or Output Compare Channel Configuration 1 TIOS.IOS0 0 Input Capture or Output Compare Channel Configuration 0 CFORC 0x0081 Timer Compare Force Register CFORC.FOC7 7 Force Output Compare Action for Channel 7 CFORC.FOC6 6 Force Output Compare Action for Channel 6 CFORC.FOC5 5 Force Output Compare Action for Channel 5 CFORC.FOC4 4 Force Output Compare Action for Channel 4 CFORC.FOC3 3 Force Output Compare Action for Channel 3 CFORC.FOC2 2 Force Output Compare Action for Channel 2 CFORC.FOC1 1 Force Output Compare Action for Channel 1 CFORC.FOC0 0 Force Output Compare Action for Channel 0 OC7M 0x0082 Output Compare 7 Mask Register OC7M.OC7M7 7 OC7M.OC7M6 6 OC7M.OC7M5 5 OC7M.OC7M4 4 OC7M.OC7M3 3 OC7M.OC7M2 2 OC7M.OC7M1 1 OC7M.OC7M0 0 OC7D 0x0083 Output Compare 7 Data Register OC7D.OC7D7 7 OC7D.OC7D6 6 OC7D.OC7D5 5 OC7D.OC7D4 4 OC7D.OC7D3 3 OC7D.OC7D2 2 OC7D.OC7D1 1 OC7D.OC7D0 0 TCNTH 0x0084 Timer Count Register High TCNTL 0x0085 Timer Count Register Low TSCR 0x0086 Timer System Control Register TSCR.TEN 7 Timer Enable TSCR.TSWAI 6 Timer Module Stops While in Wait TSCR.TSBCK 5 Timer and Modulus Counter Stop While in Background Mode TSCR.TFFCA 4 Timer Fast Flag Clear All RESERVED0087 0x0087 RESERVED TCTL1 0x0088 Timer Control Register 1 TCTL1.OM7 7 Output Mode 7 TCTL1.OL7 6 Output Level 7 TCTL1.OM6 5 Output Mode 6 TCTL1.OL6 4 Output Level 6 TCTL1.OM5 3 Output Mode 5 TCTL1.OL5 2 Output Level 5 TCTL1.OM4 1 Output Mode 4 TCTL1.OL4 0 Output Level 4 TCTL2 0x0089 Timer Control Register 2 TCTL2.OM3 7 Output Mode 3 TCTL2.OL3 6 Output Level 3 TCTL2.OM2 5 Output Mode 2 TCTL2.OL2 4 Output Level 2 TCTL2.OM1 3 Output Mode 1 TCTL2.OL1 2 Output Level 1 TCTL2.OM0 1 Output Mode 0 TCTL2.OL0 0 Output Level 0 TCTL3 0x008A Timer Control Register 3 TCTL3.EDG7B 7 Input Capture Edge Control 7B TCTL3.EDG7A 6 Input Capture Edge Control 7A TCTL3.EDG6B 5 Input Capture Edge Control 6B TCTL3.EDG6A 4 Input Capture Edge Control 6A TCTL3.EDG5B 3 Input Capture Edge Control 5B TCTL3.EDG5A 2 Input Capture Edge Control 5A TCTL3.EDG4B 1 Input Capture Edge Control 4B TCTL3.EDG4A 0 Input Capture Edge Control 4A TCTL4 0x008B Timer Control Register 4 TCTL4.EDG3B 7 Input Capture Edge Control 3B TCTL4.EDG3A 6 Input Capture Edge Control 3A TCTL4.EDG2B 5 Input Capture Edge Control 2B TCTL4.EDG2A 4 Input Capture Edge Control 2A TCTL4.EDG1B 3 Input Capture Edge Control 1B TCTL4.EDG1A 2 Input Capture Edge Control 1A TCTL4.EDG0B 1 Input Capture Edge Control 0B TCTL4.EDG0A 0 Input Capture Edge Control 0A TMSK1 0x008C Timer Interrupt Mask 1 TMSK1.C7I 7 Input Capture/Output Compare 7 Interrupt Enable TMSK1.C6I 6 Input Capture/Output Compare 6 Interrupt Enable TMSK1.C5I 5 Input Capture/Output Compare 5 Interrupt Enable TMSK1.C4I 4 Input Capture/Output Compare 4 Interrupt Enable TMSK1.C3I 3 Input Capture/Output Compare 3 Interrupt Enable TMSK1.C2I 2 Input Capture/Output Compare 2 Interrupt Enable TMSK1.C1I 1 Input Capture/Output Compare 1 Interrupt Enable TMSK1.C0I 0 Input Capture/Output Compare 0 Interrupt Enable TMSK2 0x008D Timer Interrupt Mask 2 TMSK2.TOI 7 Timer Overflow Interrupt Enable TMSK2.PUPT 5 Timer Port Pull-Up Resistor Enable TMSK2.RDPT 4 Timer Port Drive Reduction TMSK2.TCRE 3 Timer Counter Reset Enable TMSK2.PR2 2 Timer Prescaler Select 2 TMSK2.PR1 1 Timer Prescaler Select 1 TMSK2.PR0 0 Timer Prescaler Select 0 TFLG1 0x008E Main Timer Interrupt Flag 1 TFLG1.C7F 7 Input Capture/Output Compare Channel 7 Flag TFLG1.C6F 6 Input Capture/Output Compare Channel 6 Flag TFLG1.C5F 5 Input Capture/Output Compare Channel 5 Flag TFLG1.C4F 4 Input Capture/Output Compare Channel 4 Flag TFLG1.C3F 3 Input Capture/Output Compare Channel 3 Flag TFLG1.C2F 2 Input Capture/Output Compare Channel 2 Flag TFLG1.C1F 1 Input Capture/Output Compare Channel 1 Flag TFLG1.C0F 0 Input Capture/Output Compare Channel 0 Flag TFLG2 0x008F Main Timer Interrupt Flag 2 TFLG2.TOF 7 Timer Overflow Flag TC0H 0x0090 Timer Input Capture/Output Compare Register 0 High TC0L 0x0091 Timer Input Capture/Output Compare Register 0 Low TC1H 0x0092 Timer Input Capture/Output Compare Register 1 High TC1L 0x0093 Timer Input Capture/Output Compare Register 1 Low TC2H 0x0094 Timer Input Capture/Output Compare Register 2 High TC2L 0x0095 Timer Input Capture/Output Compare Register 2 Low TC3H 0x0096 Timer Input Capture/Output Compare Register 3 High TC3L 0x0097 Timer Input Capture/Output Compare Register 3 Low TC4H 0x0098 Timer Input Capture/Output Compare Register 4 High TC4L 0x0099 Timer Input Capture/Output Compare Register 4 Low TC5H 0x009A Timer Input Capture/Output Compare Register 5 High TC5L 0x009B Timer Input Capture/Output Compare Register 5 Low TC6H 0x009C Timer Input Capture/Output Compare Register 6 High TC6L 0x009D Timer Input Capture/Output Compare Register 6 Low TC7H 0x009E Timer Input Capture/Output Compare Register 7 High TC7L 0x009F Timer Input Capture/Output Compare Register 7 Low PACTL 0x00A0 16-Bit Pulse Accumulator A Control Register PACTL.PAEN 6 Pulse Accumulator A System Enable PACTL.PAMOD 5 Pulse Accumulator Mode PACTL.PEDGE 4 Pulse Accumulator Edge Control PACTL.CLK1 3 Clock Select Bit 1 PACTL.CLK0 2 Clock Select Bit 0 PACTL.PAOVI 1 Pulse Accumulator A Overflow Interrupt enable PACTL.PAI 0 Pulse Accumulator Input Interrupt enable PAFLG 0x00A1 Pulse Accumulator A Flag Register PAFLG.PAOVF 1 Pulse Accumulator A Overflow Flag PAFLG.PAIF 0 Pulse Accumulator Input edge Flag PACN3 0x00A2 Pulse Accumulators Count Register 3 PACN2 0x00A3 Pulse Accumulators Count Register 2 PACN1 0x00A4 Pulse Accumulators Count Register 1 PACN0 0x00A5 Pulse Accumulators Count Register 0 MCCTL 0x00A6 16-Bit Modulus Down-Counter Control Register MCCTL.MCZI 7 Modulus Counter Underflow Interrupt Enable MCCTL.MODMC 6 Modulus Mode Enable MCCTL.RDMCL 5 Read Modulus Down-Counter Load MCCTL.ICLAT 4 Input Capture Force Latch Action MCCTL.FLMC 3 Force Load Register into the Modulus Counter Count Register MCCTL.MCEN 2 Modulus Down-Counter Enable MCCTL.MCPR1 1 Modulus Counter Prescaler select 1 MCCTL.MCPR0 0 Modulus Counter Prescaler select 0 MCFLG 0x00A7 16-Bit Modulus Down-Counter FLAG Register MCFLG.MCZF 7 Modulus Counter Underflow Interrupt Flag MCFLG.POLF3 3 First Input Capture Polarity Status 3 MCFLG.POLF2 2 First Input Capture Polarity Status 2 MCFLG.POLF1 1 First Input Capture Polarity Status 1 MCFLG.POLF0 0 First Input Capture Polarity Status 0 ICPACR 0x00A8 Input Control Pulse Accumulators Control Register ICPACR.PA3EN 3 8-Bit Pulse Accumulator 3 Enable ICPACR.PA2EN 2 8-Bit Pulse Accumulator 2 Enable ICPACR.PA1EN 1 8-Bit Pulse Accumulator 1 Enable ICPACR.PA0EN 0 8-Bit Pulse Accumulator 0 Enable DLYCT 0x00A9 Delay Counter Control Register DLYCT.DLY1 1 Delay Counter Select 1 DLYCT.DLY0 0 Delay Counter Select 0 ICOVW 0x00AA Input Control Overwrite Register ICOVW.NOVW7 7 No Input Capture Overwrite 7 ICOVW.NOVW6 6 No Input Capture Overwrite 6 ICOVW.NOVW5 5 No Input Capture Overwrite 5 ICOVW.NOVW4 4 No Input Capture Overwrite 4 ICOVW.NOVW3 3 No Input Capture Overwrite 3 ICOVW.NOVW2 2 No Input Capture Overwrite 2 ICOVW.NOVW1 1 No Input Capture Overwrite 1 ICOVW.NOVW0 0 No Input Capture Overwrite 0 ICSYS 0x00AB Input Control System Control Register ICSYS.SH37 7 Share Input action of Input Capture Channels 3 and 7 ICSYS.SH26 6 Share Input action of Input Capture Channels 2 and 6 ICSYS.SH15 5 Share Input action of Input Capture Channels 1 and 5 ICSYS.SH04 4 Share Input action of Input Capture Channels 0 and 4 ICSYS.TFMOD 3 Timer Flag-setting Mode ICSYS.PACMX 2 8-Bit Pulse Accumulators Maximum Count ICSYS.BUFEN 1 IC Buffer Enable ICSYS.LATQ 0 Input Control Latch or Queue Mode Enable RESERVED00AC 0x00AC RESERVED TIMTST 0x00AD Timer Test Register TIMTST.TCBYP 1 Main Timer Divider Chain Bypass PORTT 0x00AE Port T Data Register PORTT.PT7 7 Port T Data Bit 7 PORTT.PT6 6 Port T Data Bit 6 PORTT.PT5 5 Port T Data Bit 5 PORTT.PT4 4 Port T Data Bit 4 PORTT.PT3 3 Port T Data Bit 3 PORTT.PT2 2 Port T Data Bit 2 PORTT.PT1 1 Port T Data Bit 1 PORTT.PT0 0 Port T Data Bit 0 DDRT 0x00AF Port T Data Direction Register DDRT.DDT7 7 Port T Data Direction Bit 7 DDRT.DDT6 6 Port T Data Direction Bit 6 DDRT.DDT5 5 Port T Data Direction Bit 5 DDRT.DDT4 4 Port T Data Direction Bit 4 DDRT.DDT3 3 Port T Data Direction Bit 3 DDRT.DDT2 2 Port T Data Direction Bit 2 DDRT.DDT1 1 Port T Data Direction Bit 1 DDRT.DDT0 0 Port T Data Direction Bit 0 PBCTL 0x00B0 16-Bit Pulse Accumulator B Control Register PBCTL.PBEN 6 Pulse Accumulator B System Enable PBCTL.PBOVI 1 Pulse Accumulator B Overflow Interrupt enable PBFLG 0x00B1 Pulse Accumulator B Flag Register PBFLG.PBOVF 1 Pulse Accumulator B Overflow Flag PA3H 0x00B2 8-Bit Pulse Accumulators Holding Register 3 PA2H 0x00B3 8-Bit Pulse Accumulators Holding Register 2 PA1H 0x00B4 8-Bit Pulse Accumulators Holding Register 1 PA0H 0x00B5 8-Bit Pulse Accumulators Holding Register 0 MCCNTH 0x00B6 Modulus Down-Counter Count Register High MCCNTL 0x00B7 Modulus Down-Counter Count Register Low TC0HH 0x00B8 Timer Input Capture Holding Register 0 High TC0HL 0x00B9 Timer Input Capture Holding Register 0 Low TC1HH 0x00BA Timer Input Capture Holding Register 1 High TC1HL 0x00BB Timer Input Capture Holding Register 1 Low TC2HH 0x00BC Timer Input Capture Holding Register 2 High TC2HL 0x00BD Timer Input Capture Holding Register 2 Low TC3HH 0x00BE Timer Input Capture Holding Register 3 High TC3HL 0x00BF Timer Input Capture Holding Register 3 Low SC0BDH 0x00C0 SCI Baud Rate Control Register High SC0BDH.BTST 7 Reserved for test function SC0BDH.BSPL 6 Reserved for test function SC0BDH.BRLD 5 Reserved for test function SC0BDH.SBR12 4 SC0BDH.SBR11 3 SC0BDH.SBR10 2 SC0BDH.SBR9 1 SC0BDH.SBR8 0 SC0BDL 0x00C1 SCI Baud Rate Control Register Low SC0BDL.SBR7 7 SC0BDL.SBR6 6 SC0BDL.SBR5 5 SC0BDL.SBR4 4 SC0BDL.SBR3 3 SC0BDL.SBR2 2 SC0BDL.SBR1 1 SC0BDL.SBR0 0 SC0CR1 0x00C2 SCI Control Register 1 SC0CR1.LOOPS 7 SCI LOOP Mode/Single Wire Mode Enable SC0CR1.WOMS 6 Wired-Or Mode for Serial Pins SC0CR1.RSRC 5 Receiver Source SC0CR1.M 4 Mode (select character format) SC0CR1.WAKE 3 Wake-up by Address Mark/Idle SC0CR1.ILT 2 Idle Line Type SC0CR1.PE 1 Parity Enable SC0CR1.PT 0 Parity Type SC0CR2 0x00C3 SCI Control Register 2 SC0CR2.TIE 7 Transmit Interrupt Enable SC0CR2.TCIE 6 Transmit Complete Interrupt Enable SC0CR2.RIE 5 Receiver Interrupt Enable SC0CR2.ILIE 4 Idle Line Interrupt Enable SC0CR2.TE 3 Transmitter Enable SC0CR2.RE 2 Receiver Enable SC0CR2.RWU 1 Receiver Wake-Up Control SC0CR2.SBK 0 Send Break SC0SR1 0x00C4 SCI Status Register 1 SC0SR1.TDRE 7 Transmit Data Register Empty Flag SC0SR1.TC 6 Transmit Complete Flag SC0SR1.RDRF 5 Receive Data Register Full Flag SC0SR1.IDLE 4 Idle Line Detected Flag SC0SR1.OR 3 Overrun Error Flag SC0SR1.NF 2 Noise Error Flag SC0SR1.FE 1 Framing Error Flag SC0SR1.PF 0 Parity Error Flag SC0SR2 0x00C5 SCI Status Register 2 SC0SR2.RAF 0 Receiver Active Flag SC0DRH 0x00C6 SCI Data Register High SC0DRH.R8 7 Receive Bit 8 SC0DRH.T8 6 Transmit Bit 8 SC0DRL 0x00C7 SCI Data Register Low SC0DRL.R7_T7 7 Receive/Transmit Data Bit 7 SC0DRL.R6_T6 6 Receive/Transmit Data Bit 6 SC0DRL.R5_T5 5 Receive/Transmit Data Bit 5 SC0DRL.R4_T4 4 Receive/Transmit Data Bit 4 SC0DRL.R3_T3 3 Receive/Transmit Data Bit 3 SC0DRL.R2_T2 2 Receive/Transmit Data Bit 2 SC0DRL.R1_T1 1 Receive/Transmit Data Bit 1 SC0DRL.R0_T0 0 Receive/Transmit Data Bit 0 SC1BDH 0x00C8 SCI Baud Rate Control Register High SC1BDH.BTST 7 Reserved for test function SC1BDH.BSPL 6 Reserved for test function SC1BDH.BRLD 5 Reserved for test function SC1BDH.SBR12 4 SC1BDH.SBR11 3 SC1BDH.SBR10 2 SC1BDH.SBR9 1 SC1BDH.SBR8 0 SC1BDL 0x00C9 SCI Baud Rate Control Register Low SC1BDL.SBR7 7 SC1BDL.SBR6 6 SC1BDL.SBR5 5 SC1BDL.SBR4 4 SC1BDL.SBR3 3 SC1BDL.SBR2 2 SC1BDL.SBR1 1 SC1BDL.SBR0 0 SC1CR1 0x00CA SCI Control Register 1 SC1CR1.LOOPS 7 SCI LOOP Mode/Single Wire Mode Enable SC1CR1.WOMS 6 Wired-Or Mode for Serial Pins SC1CR1.RSRC 5 Receiver Source SC1CR1.M 4 Mode (select character format) SC1CR1.WAKE 3 Wake-up by Address Mark/Idle SC1CR1.ILT 2 Idle Line Type SC1CR1.PE 1 Parity Enable SC1CR1.PT 0 Parity Type SC1CR2 0x00CB SCI Control Register 2 SC1CR2.TIE 7 Transmit Interrupt Enable SC1CR2.TCIE 6 Transmit Complete Interrupt Enable SC1CR2.RIE 5 Receiver Interrupt Enable SC1CR2.ILIE 4 Idle Line Interrupt Enable SC1CR2.TE 3 Transmitter Enable SC1CR2.RE 2 Receiver Enable SC1CR2.RWU 1 Receiver Wake-Up Control SC1CR2.SBK 0 Send Break SC1SR1 0x00CC SCI Status Register 1 SC1SR1.TDRE 7 Transmit Data Register Empty Flag SC1SR1.TC 6 Transmit Complete Flag SC1SR1.RDRF 5 Receive Data Register Full Flag SC1SR1.IDLE 4 Idle Line Detected Flag SC1SR1.OR 3 Overrun Error Flag SC1SR1.NF 2 Noise Error Flag SC1SR1.FE 1 Framing Error Flag SC1SR1.PF 0 Parity Error Flag SC1SR2 0x00CD SCI Status Register 2 SC1SR2.RAF 0 Receiver Active Flag SC1DRH 0x00CE SCI Data Register High SC1DRH.R8 7 Receive Bit 8 SC1DRH.T8 6 Transmit Bit 8 SC1DRL 0x00CF SCI Data Register Low SC1DRL.R7_T7 7 Receive/Transmit Data Bit 7 SC1DRL.R6_T6 6 Receive/Transmit Data Bit 6 SC1DRL.R5_T5 5 Receive/Transmit Data Bit 5 SC1DRL.R4_T4 4 Receive/Transmit Data Bit 4 SC1DRL.R3_T3 3 Receive/Transmit Data Bit 3 SC1DRL.R2_T2 2 Receive/Transmit Data Bit 2 SC1DRL.R1_T1 1 Receive/Transmit Data Bit 1 SC1DRL.R0_T0 0 Receive/Transmit Data Bit 0 SP0CR1 0x00D0 SPI Control Register 1 SP0CR1.SPIE 7 SPI Interrupt Enable SP0CR1.SPE 6 SPI System Enable SP0CR1.SWOM 5 Port S Wired-OR Mode SP0CR1.MSTR 4 SPI Master/Slave Mode Select SP0CR1.CPOL 3 SPI Clock Polarity SP0CR1.CPHA 2 Clock Phase SP0CR1.SSOE 1 Slave Select Output Enable SP0CR1.LSBF 0 SPI LSB First enable SP0CR2 0x00D1 SPI Control Register 2 SP0CR2.PUPS 3 Pull-Up Port S Enable SP0CR2.RDPS 2 Reduce Drive of Port S SP0CR2.SSWAI 1 Serial Interface Stop in WAIT mode SP0CR2.SPC0 0 Serial Pin Control 0 SP0BR 0x00D2 SPI Baud Rate Register SP0BR.SPR2 2 SPI Clock (SCK) Rate Select Bit 2 SP0BR.SPR1 1 SPI Clock (SCK) Rate Select Bit 1 SP0BR.SPR0 0 SPI Clock (SCK) Rate Select Bit 0 SP0SR 0x00D3 SPI Status Register SP0SR.SPIF 7 SPI Interrupt Request SP0SR.WCOL 6 Write Collision Status Flag SP0SR.MODF 4 SPI Mode Error Interrupt Status Flag RESERVED00D4 0x00D4 RESERVED SP0DR 0x00D5 SPI Data Register PORTS 0x00D6 Port S Data Register PORTS.PS7 7 Port S Data Bit 7 PORTS.PS6 6 Port S Data Bit 6 PORTS.PS5 5 Port S Data Bit 5 PORTS.PS4 4 Port S Data Bit 4 PORTS.PS3 3 Port S Data Bit 3 PORTS.PS2 2 Port S Data Bit 2 PORTS.PS1 1 Port S Data Bit 1 PORTS.PS0 0 Port S Data Bit 0 DDRS 0x00D7 Port S Data Direction Register DDRS.DDS7 7 Port S Data Direction Bit 7 DDRS.DDS6 6 Port S Data Direction Bit 6 DDRS.DDS5 5 Port S Data Direction Bit 5 DDRS.DDS4 4 Port S Data Direction Bit 4 DDRS.DDS3 3 Port S Data Direction Bit 3 DDRS.DDS2 2 Port S Data Direction Bit 2 DDRS.DDS1 1 Port S Data Direction Bit 1 DDRS.DDS0 0 Port S Data Direction Bit 0 RESERVED00D8 0x00D8 RESERVED RESERVED00D9 0x00D9 RESERVED RESERVED00DA 0x00DA RESERVED RESERVED00DB 0x00DB RESERVED RESERVED00DC 0x00DC RESERVED RESERVED00DD 0x00DD RESERVED RESERVED00DE 0x00DE RESERVED RESERVED00DF 0x00DF RESERVED IBAD 0x00E0 Bus Address Register IBAD.ADR7 7 Slave Address 7 IBAD.ADR6 6 Slave Address 6 IBAD.ADR5 5 Slave Address 5 IBAD.ADR4 4 Slave Address 4 IBAD.ADR3 3 Slave Address 3 IBAD.ADR2 2 Slave Address 2 IBAD.ADR1 1 Slave Address 1 IBFD 0x00E1 IIC Bus Frequency Divider Register IBFD.IBC5 5 IIC Bus Clock Rate 5 IBFD.IBC4 4 IIC Bus Clock Rate 4 IBFD.IBC3 3 IIC Bus Clock Rate 3 IBFD.IBC2 2 IIC Bus Clock Rate 2 IBFD.IBC1 1 IIC Bus Clock Rate 1 IBFD.IBC0 0 IIC Bus Clock Rate 0 IBCR 0x00E2 IIC Bus Control Register IBCR.IBEN 7 IIC Bus Enable IBCR.IBIE 6 IIC Bus Interrupt Enable IBCR.MS_SL 5 Master/Slave mode select bit IBCR.Tx_Rx 4 Transmit/Receive mode select bit IBCR.TXAK 3 Transmit Acknowledge enable IBCR.RSTA 2 Repeat Start IBCR.IBSWAI 0 IIC Stop in WAIT mode IBSR 0x00E3 IIC Bus Status Register IBSR.TCF 7 Data transferring bit IBSR.IAAS 6 Addressed as a slave bit IBSR.IBB 5 IIC Bus busy bit IBSR.IBAL 4 Arbitration Lost IBSR.SRW 2 Slave Read/Write IBSR.IBIF 1 IIC Bus Interrupt Flag IBSR.RXAK 0 Received Acknowledge IBDR 0x00E4 IIC Bus Data I/O Register IBDR.D7 7 IBDR.D6 6 IBDR.D5 5 IBDR.D4 4 IBDR.D3 3 IBDR.D2 2 IBDR.D1 1 IBDR.D0 0 IBPURD 0x00E5 Pull-Up and Reduced Drive for Port IB IBPURD.RDPIB 4 Reduced Drive of Port IB IBPURD.PUPIB 0 Pull-Up Port IB Enable PORTIB 0x00E6 Port Data IB Register PORTIB.PIB7 7 Port Data IB Register bit 7 PORTIB.PIB6 6 Port Data IB Register bit 6 PORTIB.PIB5 5 Port Data IB Register bit 5 PORTIB.PIB4 4 Port Data IB Register bit 4 PORTIB.PIB3 3 Port Data IB Register bit 3 PORTIB.PIB2 2 Port Data IB Register bit 2 PORTIB.PIB1 1 Port Data IB Register bit 1 PORTIB.PIB0 0 Port Data IB Register bit 0 DDRIB 0x00E7 Data Direction for Port IB Register DDRIB.DDRIB7 7 Port IB Data direction 7 DDRIB.DDRIB6 6 Port IB Data direction 6 DDRIB.DDRIB5 5 Port IB Data direction 5 DDRIB.DDRIB4 4 Port IB Data direction 4 DDRIB.DDRIB3 3 Port IB Data direction 3 DDRIB.DDRIB2 2 Port IB Data direction 2 DDRIB.DDRIB1 1 DDRIB.DDRIB0 0 RESERVED00E8 0x00E8 RESERVED RESERVED00E9 0x00E9 RESERVED RESERVED00EA 0x00EA RESERVED RESERVED00EB 0x00EB RESERVED RESERVED00EC 0x00EC RESERVED RESERVED00ED 0x00ED RESERVED EEDIVH 0x00EE EEPROM Modulus Divider High EEDIVH.EEDIV9 1 Prescaler divider 9 EEDIVH.EEDIV8 0 Prescaler divider 8 EEDIVL 0x00EF EEPROM Modulus Divider Low EEDIVL.EEDIV7 7 Prescaler divider 7 EEDIVL.EEDIV6 6 Prescaler divider 6 EEDIVL.EEDIV5 5 Prescaler divider 5 EEDIVL.EEDIV4 4 Prescaler divider 4 EEDIVL.EEDIV3 3 Prescaler divider 3 EEDIVL.EEDIV2 2 Prescaler divider 2 EEDIVL.EEDIV1 1 Prescaler divider 1 EEDIVL.EEDIV0 0 Prescaler divider 0 EEMCR 0x00F0 EEPROM Module Configuration EEMCR.NOBDML 7 Background Debug Mode Lockout Disable EEMCR.NOSHW 6 SHADOW Byte Disable EEMCR.EESWAI 2 EEPROM Stops in Wait Mode EEMCR.PROTLCK 1 Block Protect Write Lock EEMCR.EERC 0 EEPROM Charge Pump Clock EEPROT 0x00F1 EEPROM Block Protect EEPROT.SHPROT 7 SHADOW Byte Protection EEPROT.BPROT5 5 EEPROM Block Protection 5 EEPROT.BPROT4 4 EEPROM Block Protection 4 EEPROT.BPROT3 3 EEPROM Block Protection 3 EEPROT.BPROT2 2 EEPROM Block Protection 2 EEPROT.BPROT1 1 EEPROM Block Protection 1 EEPROT.BPROT0 0 EEPROM Block Protection 0 EETST 0x00F2 EEPROM Test EETST.EREVTN 6 EETST.ETMSD 2 EETST.ETMR 1 EETST.ETMSE 0 EEPROG 0x00F3 EEPROM Control EEPROG.BULKP 7 Bulk Erase Protection EEPROG..AUTO 5 Automatic shutdown of program/erase operation EEPROG.BYTE 4 Byte and Aligned Word Erase EEPROG.ROW 3 Row or Bulk Erase (when BYTE = 0) EEPROG.ERASE 2 Erase Control EEPROG.EELAT 1 EEPROM Latch Control EEPROG.EEPGM 0 Program and Erase Enable FEELCK 0x00F4 Flash EEPROM Lock Control Register FEELCK.LOCK 0 Lock Register Bit FEEMCR 0x00F5 Flash EEPROM Module Configuration Register FEEMCR.BOOTP 0 Boot Protect FEETST 0x00F6 FEETST FEETST.STRE 7 FEETST.REVTUN 6 FEETST.TMSD 2 FEETST.TMR 1 FEETST.TMSE 0 FEECTL 0x00F7 Flash EEPROM Control Register FEECTL.FEESWAI 4 Flash EEPROM Stop in Wait Control FEECTL.HVEN 3 High-Voltage Enable FEECTL.ERAS 1 Erase Control FEECTL.PGM 0 Program Control MTST0 0x00F8 Mapping Test Register 0 MTST0.MT07 7 MTST0.MT06 6 MTST0.MT05 5 MTST0.MT04 4 MTST0.MT03 3 MTST0.MT02 2 MTST0.MT01 1 MTST0.MT00 0 MTST1 0x00F9 Mapping Test Register 1 MTST1.MT0F 7 MTST1.MT0E 6 MTST1.MT0D 5 MTST1.MT0C 4 MTST1.MT0B 3 MTST1.MT0A 2 MTST1.MT09 1 MTST1.MT08 0 MTST2 0x00FA Mapping Test Register 2 MTST2.MT17 7 MTST2.MT16 6 MTST2.MT15 5 MTST2.MT14 4 MTST2.MT13 3 MTST2.MT12 2 MTST2.MT11 1 MTST2.MT10 0 MTST3 0x00FB Mapping Test Register 3 MTST3.MT1F 7 MTST3.MT1E 6 MTST3.MT1D 5 MTST3.MT1C 4 MTST3.MT1B 3 MTST3.MT1A 2 MTST3.MT19 1 MTST3.MT18 0 PORTK 0x00FC Port K Data Register PORTK.PK7 7 Port K Data Bit 7 PORTK.PK3 3 Port K Data Bit 3 PORTK.PK2 2 Port K Data Bit 2 PORTK.PK1 1 Port K Data Bit 1 PORTK.PK0 0 Port K Data Bit 0 DDRK 0x00FD Port K Data Direction Register DDRK.DDK7 7 Port K Data Direction Bit 7 DDRK.DDK3 3 Port K Data Direction Bit 3 DDRK.DDK2 2 Port K Data Direction Bit 2 DDRK.DDK1 1 Port K Data Direction Bit 1 DDRK.DDK0 0 Port K Data Direction Bit 0 RESERVED00FE 0x00FE RESERVED PPAGE 0x00FF Program Page Index Register PPAGE.PIX2 2 PPAGE.PIX1 1 PPAGE.PIX0 0 C0MCR0 0x0100 msCAN12 Module Control Register 0 C0MCR0.CSWAI 5 CAN Stops in Wait Mode C0MCR0.SYNCH 4 Synchronized Status C0MCR0.TLNKEN 3 Timer Enable C0MCR0.SLPAK 2 SLEEP Mode Acknowledge C0MCR0.SLPRQ 1 SLEEP request C0MCR0.SFTRES 0 SOFT_RESET C0MCR1 0x0101 msCAN12 Module Control Register 1 C0MCR1.LOOPB 2 Loop Back Self Test Mode C0MCR1.WUPM 1 Wake-Up Mode C0MCR1.CLKSRC 0 msCAN12 Clock Source C0BTR0 0x0102 msCAN12 Bus Timing Register 0 C0BTR0.SJW1 7 Synchronization Jump Width 1 C0BTR0.SJW0 6 Synchronization Jump Width 0 C0BTR0.BRP5 5 Baud Rate Prescaler 5 C0BTR0.BRP4 4 Baud Rate Prescaler 4 C0BTR0.BRP3 3 Baud Rate Prescaler 3 C0BTR0.BRP2 2 Baud Rate Prescaler 2 C0BTR0.BRP1 1 Baud Rate Prescaler 1 C0BTR0.BRP0 0 Baud Rate Prescaler 0 C0BTR1 0x0103 msCAN12 Bus Timing Register 1 C0BTR1.SAMP 7 Sampling C0BTR1.TSEG22 6 Time Segment 22 C0BTR1.TSEG21 5 Time Segment 21 C0BTR1.TSEG20 4 Time Segment 20 C0BTR1.TSEG13 3 Time Segment 13 C0BTR1.TSEG12 2 Time Segment 12 C0BTR1.TSEG11 1 Time Segment 11 C0BTR1.TSEG10 0 Time Segment 10 C0RFLG 0x0104 msCAN12 Receiver Flag Register C0RFLG.WUPIF 7 Wake-up Interrupt Flag C0RFLG.RWRNIF 6 Receiver Warning Interrupt Flag C0RFLG.TWRNIF 5 Transmitter Warning Interrupt Flag C0RFLG.RERRIF 4 Receiver Error Passive Interrupt Flag C0RFLG.TERRIF 3 Transmitter Error Passive Interrupt Flag C0RFLG.BOFFIF 2 BUSOFF Interrupt Flag C0RFLG.OVRIF 1 Overrun Interrupt Flag C0RFLG.RXF 0 Receive Buffer Full C0RIER 0x0105 msCAN12 Receiver Interrupt Enable Register C0RIER.WUPIE 7 Wake-up Interrupt Enable C0RIER.RWRNIE 6 Receiver Warning Interrupt Enable C0RIER.TWRNIE 5 Transmitter Warning Interrupt Enable C0RIER.RERRIE 4 Receiver Error Passive Interrupt Enable C0RIER.TERRIE 3 Transmitter Error Passive Interrupt Enable C0RIER.BOFFIE 2 BUSOFF Interrupt Enable C0RIER.OVRIE 1 Overrun Interrupt Enable C0RIER.RXFIE 0 Receiver Full Interrupt Enable C0TFLG 0x0106 msCAN12 Transmitter Flag Register C0TFLG.ABTAK2 6 Abort Acknowledge 2 C0TFLG.ABTAK1 5 Abort Acknowledge 1 C0TFLG.ABTAK0 4 Abort Acknowledge 0 C0TFLG.TXE2 2 Transmitter Buffer Empty 2 C0TFLG.TXE1 1 Transmitter Buffer Empty 1 C0TFLG.TXE0 0 Transmitter Buffer Empty 0 C0TCR 0x0107 msCAN12 Transmitter Control Register C0TCR.ABTRQ2 6 Abort Request 2 C0TCR.ABTRQ1 5 Abort Request 1 C0TCR.ABTRQ0 4 Abort Request 0 C0TCR.TXEIE2 2 Transmitter Empty Interrupt Enable 2 C0TCR.TXEIE1 1 Transmitter Empty Interrupt Enable 1 C0TCR.TXEIE0 0 Transmitter Empty Interrupt Enable 0 C0IDAC 0x0108 msCAN12 Identifier Acceptance Control Register C0IDAC.IDAM1 5 Identifier Acceptance Mode 1 C0IDAC.IDAM0 4 Identifier Acceptance Mode 0 C0IDAC.IDHIT2 2 Identifier Acceptance Hit Indicator 2 C0IDAC.IDHIT1 1 Identifier Acceptance Hit Indicator 1 C0IDAC.IDHIT0 0 Identifier Acceptance Hit Indicator 0 RESERVED0109 0x0109 RESERVED RESERVED010A 0x010A RESERVED RESERVED010B 0x010B RESERVED RESERVED010C 0x010C RESERVED RESERVED010D 0x010D RESERVED C0RXERR 0x010E msCAN12 Receive Error Counter C0RXERR.RXERR7 7 C0RXERR.RXERR6 6 C0RXERR.RXERR5 5 C0RXERR.RXERR4 4 C0RXERR.RXERR3 3 C0RXERR.RXERR2 2 C0RXERR.RXERR1 1 C0RXERR.RXERR0 0 C0TXERR 0x010F msCAN12 Transmit Error Counter C0TXERR.TXERR7 7 C0TXERR.TXERR6 6 C0TXERR.TXERR5 5 C0TXERR.TXERR4 4 C0TXERR.TXERR3 3 C0TXERR.TXERR2 2 C0TXERR.TXERR1 1 C0TXERR.TXERR0 0 C0IDAR0 0x0110 msCAN12 Identifier Acceptance Register 0 C0IDAR0.AC7 7 Acceptance Code Bit 7 C0IDAR0.AC6 6 Acceptance Code Bit 6 C0IDAR0.AC5 5 Acceptance Code Bit 5 C0IDAR0.AC4 4 Acceptance Code Bit 4 C0IDAR0.AC3 3 Acceptance Code Bit 3 C0IDAR0.AC2 2 Acceptance Code Bit 2 C0IDAR0.AC1 1 Acceptance Code Bit 1 C0IDAR0.AC0 0 Acceptance Code Bit 0 C0IDAR1 0x0111 msCAN12 Identifier Acceptance Register 1 C0IDAR1.AC7 7 Acceptance Code Bit 7 C0IDAR1.AC6 6 Acceptance Code Bit 6 C0IDAR1.AC5 5 Acceptance Code Bit 5 C0IDAR1.AC4 4 Acceptance Code Bit 4 C0IDAR1.AC3 3 Acceptance Code Bit 3 C0IDAR1.AC2 2 Acceptance Code Bit 2 C0IDAR1.AC1 1 Acceptance Code Bit 1 C0IDAR1.AC0 0 Acceptance Code Bit 0 C0IDAR2 0x0112 msCAN12 Identifier Acceptance Register 2 C0IDAR2.AC7 7 Acceptance Code Bit 7 C0IDAR2.AC6 6 Acceptance Code Bit 6 C0IDAR2.AC5 5 Acceptance Code Bit 5 C0IDAR2.AC4 4 Acceptance Code Bit 4 C0IDAR2.AC3 3 Acceptance Code Bit 3 C0IDAR2.AC2 2 Acceptance Code Bit 2 C0IDAR2.AC1 1 Acceptance Code Bit 1 C0IDAR2.AC0 0 Acceptance Code Bit 0 C0IDAR3 0x0113 msCAN12 Identifier Acceptance Register 3 C0IDAR3.AC7 7 Acceptance Code Bit 7 C0IDAR3.AC6 6 Acceptance Code Bit 6 C0IDAR3.AC5 5 Acceptance Code Bit 5 C0IDAR3.AC4 4 Acceptance Code Bit 4 C0IDAR3.AC3 3 Acceptance Code Bit 3 C0IDAR3.AC2 2 Acceptance Code Bit 2 C0IDAR3.AC1 1 Acceptance Code Bit 1 C0IDAR3.AC0 0 Acceptance Code Bit 0 C0IDMR0 0x0114 msCAN12 Identifier Mask Register 0 C0IDMR0.AM7 7 Acceptance Mask Bit 7 C0IDMR0.AM6 6 Acceptance Mask Bit 6 C0IDMR0.AM5 5 Acceptance Mask Bit 5 C0IDMR0.AM4 4 Acceptance Mask Bit 4 C0IDMR0.AM3 3 Acceptance Mask Bit 3 C0IDMR0.AM2 2 Acceptance Mask Bit 2 C0IDMR0.AM1 1 Acceptance Mask Bit 1 C0IDMR0.AM0 0 Acceptance Mask Bit 0 C0IDMR1 0x0115 msCAN12 Identifier Mask Register 1 C0IDMR1.AM7 7 Acceptance Mask Bit 7 C0IDMR1.AM6 6 Acceptance Mask Bit 6 C0IDMR1.AM5 5 Acceptance Mask Bit 5 C0IDMR1.AM4 4 Acceptance Mask Bit 4 C0IDMR1.AM3 3 Acceptance Mask Bit 3 C0IDMR1.AM2 2 Acceptance Mask Bit 2 C0IDMR1.AM1 1 Acceptance Mask Bit 1 C0IDMR1.AM0 0 Acceptance Mask Bit 0 C0IDMR2 0x0116 msCAN12 Identifier Mask Register 2 C0IDMR2.AM7 7 Acceptance Mask Bit 7 C0IDMR2.AM6 6 Acceptance Mask Bit 6 C0IDMR2.AM5 5 Acceptance Mask Bit 5 C0IDMR2.AM4 4 Acceptance Mask Bit 4 C0IDMR2.AM3 3 Acceptance Mask Bit 3 C0IDMR2.AM2 2 Acceptance Mask Bit 2 C0IDMR2.AM1 1 Acceptance Mask Bit 1 C0IDMR2.AM0 0 Acceptance Mask Bit 0 C0IDMR3 0x0117 msCAN12 Identifier Mask Register 3 C0IDMR3.AM7 7 Acceptance Mask Bit 7 C0IDMR3.AM6 6 Acceptance Mask Bit 6 C0IDMR3.AM5 5 Acceptance Mask Bit 5 C0IDMR3.AM4 4 Acceptance Mask Bit 4 C0IDMR3.AM3 3 Acceptance Mask Bit 3 C0IDMR3.AM2 2 Acceptance Mask Bit 2 C0IDMR3.AM1 1 Acceptance Mask Bit 1 C0IDMR3.AM0 0 Acceptance Mask Bit 0 C0IDAR4 0x0118 msCAN12 Identifier Acceptance Register 4 C0IDAR4.AC7 7 Acceptance Code Bit 7 C0IDAR4.AC6 6 Acceptance Code Bit 6 C0IDAR4.AC5 5 Acceptance Code Bit 5 C0IDAR4.AC4 4 Acceptance Code Bit 4 C0IDAR4.AC3 3 Acceptance Code Bit 3 C0IDAR4.AC2 2 Acceptance Code Bit 2 C0IDAR4.AC1 1 Acceptance Code Bit 1 C0IDAR4.AC0 0 Acceptance Code Bit 0 C0IDAR5 0x0119 msCAN12 Identifier Acceptance Register 5 C0IDAR5.AC7 7 Acceptance Code Bit 7 C0IDAR5.AC6 6 Acceptance Code Bit 6 C0IDAR5.AC5 5 Acceptance Code Bit 5 C0IDAR5.AC4 4 Acceptance Code Bit 4 C0IDAR5.AC3 3 Acceptance Code Bit 3 C0IDAR5.AC2 2 Acceptance Code Bit 2 C0IDAR5.AC1 1 Acceptance Code Bit 1 C0IDAR5.AC0 0 Acceptance Code Bit 0 C0IDAR6 0x011A msCAN12 Identifier Acceptance Register 6 C0IDAR6.AC7 7 Acceptance Code Bit 7 C0IDAR6.AC6 6 Acceptance Code Bit 6 C0IDAR6.AC5 5 Acceptance Code Bit 5 C0IDAR6.AC4 4 Acceptance Code Bit 4 C0IDAR6.AC3 3 Acceptance Code Bit 3 C0IDAR6.AC2 2 Acceptance Code Bit 2 C0IDAR6.AC1 1 Acceptance Code Bit 1 C0IDAR6.AC0 0 Acceptance Code Bit 0 C0IDAR7 0x011B msCAN12 Identifier Acceptance Register 7 C0IDAR7.AC7 7 Acceptance Code Bit 7 C0IDAR7.AC6 6 Acceptance Code Bit 6 C0IDAR7.AC5 5 Acceptance Code Bit 5 C0IDAR7.AC4 4 Acceptance Code Bit 4 C0IDAR7.AC3 3 Acceptance Code Bit 3 C0IDAR7.AC2 2 Acceptance Code Bit 2 C0IDAR7.AC1 1 Acceptance Code Bit 1 C0IDAR7.AC0 0 Acceptance Code Bit 0 C0IDMR4 0x011C msCAN12 Identifier Mask Register 4 C0IDMR4.AM7 7 Acceptance Mask Bit 7 C0IDMR4.AM6 6 Acceptance Mask Bit 6 C0IDMR4.AM5 5 Acceptance Mask Bit 5 C0IDMR4.AM4 4 Acceptance Mask Bit 4 C0IDMR4.AM3 3 Acceptance Mask Bit 3 C0IDMR4.AM2 2 Acceptance Mask Bit 2 C0IDMR4.AM1 1 Acceptance Mask Bit 1 C0IDMR4.AM0 0 Acceptance Mask Bit 0 C0IDMR5 0x011D msCAN12 Identifier Mask Register 5 C0IDMR5.AM7 7 Acceptance Mask Bit 7 C0IDMR5.AM6 6 Acceptance Mask Bit 6 C0IDMR5.AM5 5 Acceptance Mask Bit 5 C0IDMR5.AM4 4 Acceptance Mask Bit 4 C0IDMR5.AM3 3 Acceptance Mask Bit 3 C0IDMR5.AM2 2 Acceptance Mask Bit 2 C0IDMR5.AM1 1 Acceptance Mask Bit 1 C0IDMR5.AM0 0 Acceptance Mask Bit 0 C0IDMR6 0x011E msCAN12 Identifier Mask Register 6 C0IDMR6.AM7 7 Acceptance Mask Bit 7 C0IDMR6.AM6 6 Acceptance Mask Bit 6 C0IDMR6.AM5 5 Acceptance Mask Bit 5 C0IDMR6.AM4 4 Acceptance Mask Bit 4 C0IDMR6.AM3 3 Acceptance Mask Bit 3 C0IDMR6.AM2 2 Acceptance Mask Bit 2 C0IDMR6.AM1 1 Acceptance Mask Bit 1 C0IDMR6.AM0 0 Acceptance Mask Bit 0 C0IDMR7 0x011F msCAN12 Identifier Mask Register 7 C0IDMR7.AM7 7 Acceptance Mask Bit 7 C0IDMR7.AM6 6 Acceptance Mask Bit 6 C0IDMR7.AM5 5 Acceptance Mask Bit 5 C0IDMR7.AM4 4 Acceptance Mask Bit 4 C0IDMR7.AM3 3 Acceptance Mask Bit 3 C0IDMR7.AM2 2 Acceptance Mask Bit 2 C0IDMR7.AM1 1 Acceptance Mask Bit 1 C0IDMR7.AM0 0 Acceptance Mask Bit 0 RESERVED0120 0x0120 RESERVED RESERVED0121 0x0121 RESERVED RESERVED0122 0x0122 RESERVED RESERVED0123 0x0123 RESERVED RESERVED0124 0x0124 RESERVED RESERVED0125 0x0125 RESERVED RESERVED0126 0x0126 RESERVED RESERVED0127 0x0127 RESERVED RESERVED0128 0x0128 RESERVED RESERVED0129 0x0129 RESERVED RESERVED012A 0x012A RESERVED RESERVED012B 0x012B RESERVED RESERVED012C 0x012C RESERVED RESERVED012D 0x012D RESERVED RESERVED012E 0x012E RESERVED RESERVED012F 0x012F RESERVED RESERVED0130 0x0130 RESERVED RESERVED0131 0x0131 RESERVED RESERVED0132 0x0132 RESERVED RESERVED0133 0x0133 RESERVED RESERVED0134 0x0134 RESERVED RESERVED0135 0x0135 RESERVED RESERVED0136 0x0136 RESERVED RESERVED0137 0x0137 RESERVED RESERVED0138 0x0138 RESERVED RESERVED0139 0x0139 RESERVED RESERVED013A 0x013A RESERVED RESERVED013B 0x013B RESERVED RESERVED013C 0x013C RESERVED PCTLCAN0 0x013D msCAN12 Port CAN Control Register PCTLCAN0.PUPCAN 1 Pull-Up Enable Port CAN PCTLCAN0.RDPCAN 0 Reduced Drive Port CAN PORTCAN0 0x013E msCAN12 Port CAN Data Register PORTCAN0.PCAN7 7 Port CAN Data Bit 7 PORTCAN0.PCAN6 6 Port CAN Data Bit 6 PORTCAN0.PCAN5 5 Port CAN Data Bit 5 PORTCAN0.PCAN4 4 Port CAN Data Bit 4 PORTCAN0.PCAN3 3 Port CAN Data Bit 3 PORTCAN0.PCAN2 2 Port CAN Data Bit 2 PORTCAN0.TxCAN 1 PORTCAN0.RxCAN 0 DDRCAN0 0x013F msCAN12 Port CAN Data Direction Register DDRCAN0.DDCAN7 7 DDRCAN0.DDCAN6 6 DDRCAN0.DDCAN5 5 DDRCAN0.DDCAN4 4 DDRCAN0.DDCAN3 3 DDRCAN0.DDCAN2 2 ATD1CTL2 0x01E2 ATD1 Control Register 2 ATD1CTL2.ADPU 7 ATD Disable ATD1CTL2.AFFC 6 ATD Fast Flag Clear All ATD1CTL2.ASWAI 5 ATD Wait Mode ATD1CTL2.DJM 4 Result Register Data Justification Mode ATD1CTL2.DSGN 3 Signed/Unsigned Result Data Mode ATD1CTL2.ASCIE 1 ATD Sequence Complete Interrupt Enable ATD1CTL2.ASCIF 0 ATD Sequence Complete Interrupt Flag ATD1CTL3 0x01E3 ATD1 Control Register 3 ATD1CTL3.S1C 3 Conversion Sequence Length (Least Significant Bit) ATD1CTL3.FIFO 2 Result Register FIFO Mode ATD1CTL3.FRZ1 1 Background Debug (Freeze) Enable 1 ATD1CTL3.FRZ0 0 Background Debug (Freeze) Enable 0 ATD1CTL4 0x01E4 ATD1 Control Register 4 ATD1CTL4.RES10 7 10 bit Mode ATD1CTL4.SMP1 6 Select Sample Time 1 ATD1CTL4.SMP0 5 Select Sample Time 0 ATD1CTL4.PRS4 4 Select Divide-By Factor for ATD P-Clock Prescaler 4 ATD1CTL4.PRS3 3 Select Divide-By Factor for ATD P-Clock Prescaler 3 ATD1CTL4.PRS2 2 Select Divide-By Factor for ATD P-Clock Prescaler 2 ATD1CTL4.PRS1 1 Select Divide-By Factor for ATD P-Clock Prescaler 1 ATD1CTL4.PRS0 0 Select Divide-By Factor for ATD P-Clock Prescaler 0 ATD1CTL5 0x01E5 ATD1 Control Register 5 ATD1CTL5.S8CM 6 Select 8 Channel Mode ATD1CTL5.SCAN 5 Enable Continuous Channel Scan ATD1CTL5.MULT 4 Enable Multichannel Conversion ATD1CTL5.CD 3 Channel Select for Conversion D ATD1CTL5.CC 2 Channel Select for Conversion C ATD1CTL5.CB 1 Channel Select for Conversion B ATD1CTL5.CA 0 Channel Select for Conversion A ATD1STAT0 0x01E6 ATD1 Status Register ATD1STAT0.SCF 7 Sequence Complete Flag ATD1STAT0.CC2 2 Conversion Counter for Current Sequence of Four or Eight Conversions 2 ATD1STAT0.CC1 1 Conversion Counter for Current Sequence of Four or Eight Conversions 1 ATD1STAT0.CC0 0 Conversion Counter for Current Sequence of Four or Eight Conversions 0 ATD1STAT1 0x01E7 ATD1 Status Register ATD1STAT1.CCF7 7 Conversion Complete Flag 7 ATD1STAT1.CCF6 6 Conversion Complete Flag 6 ATD1STAT1.CCF5 5 Conversion Complete Flag 5 ATD1STAT1.CCF4 4 Conversion Complete Flag 4 ATD1STAT1.CCF3 3 Conversion Complete Flag 3 ATD1STAT1.CCF2 2 Conversion Complete Flag 2 ATD1STAT1.CCF1 1 Conversion Complete Flag 1 ATD1STAT1.CCF0 0 Conversion Complete Flag 0 ATD1TESTH 0x01E8 ATD1 Test Register ATD1TESTH.SAR9 7 SAR Data 9 ATD1TESTH.SAR8 6 SAR Data 8 ATD1TESTH.SAR7 5 SAR Data 7 ATD1TESTH.SAR6 4 SAR Data 6 ATD1TESTH.SAR5 3 SAR Data 5 ATD1TESTH.SAR4 2 SAR Data 4 ATD1TESTH.SAR3 1 SAR Data 3 ATD1TESTH.SAR2 0 SAR Data 2 ATD1TESTL 0x01E9 ATD1 Test Register ATD1TESTL.SAR1 7 SAR Data 1 ATD1TESTL.SAR0 6 SAR Data 0 ATD1TESTL.RST 5 Module Reset Bit ATD1TESTL.TSTOUT 4 Multiplex Output of TST[3:0] (Factory Use) ATD1TESTL.TST3 3 Test Bit 3 ATD1TESTL.TST2 2 Test Bit 2 ATD1TESTL.TST1 1 Test Bit 1 ATD1TESTL.TST0 0 Test Bit 0 RESERVED01EA 0x01EA RESERVED RESERVED01EB 0x01EB RESERVED RESERVED01EC 0x01EC RESERVED RESERVED01ED 0x01ED RESERVED RESERVED01EE 0x01EE RESERVED PORTAD1 0x01EF Port AD1 Data Input Register PORTAD1.PAD17 7 Port AD1 Data Input Bit 7 PORTAD1.PAD16 6 Port AD1 Data Input Bit 6 PORTAD1.PAD15 5 Port AD1 Data Input Bit 5 PORTAD1.PAD14 4 Port AD1 Data Input Bit 4 PORTAD1.PAD13 3 Port AD1 Data Input Bit 3 PORTAD1.PAD12 2 Port AD1 Data Input Bit 2 PORTAD1.PAD11 1 Port AD1 Data Input Bit 1 PORTAD1.PAD10 0 Port AD1 Data Input Bit 0 ADR10H 0x01F0 A/D Conversion Result Register High 0 ADR10L 0x01F1 A/D Conversion Result Register Low 0 ADR11H 0x01F2 A/D Conversion Result Register High 1 ADR11L 0x01F3 A/D Conversion Result Register Low 1 ADR12H 0x01F4 A/D Conversion Result Register High 2 ADR12L 0x01F5 A/D Conversion Result Register Low 2 ADR13H 0x01F6 A/D Conversion Result Register High 3 ADR13L 0x01F7 A/D Conversion Result Register Low 3 ADR14H 0x01F8 A/D Conversion Result Register High 4 ADR14L 0x01F9 A/D Conversion Result Register Low 4 ADR15H 0x01FA A/D Conversion Result Register High 5 ADR15L 0x01FB A/D Conversion Result Register Low 5 ADR16H 0x01FC A/D Conversion Result Register High 6 ADR16L 0x01FD A/D Conversion Result Register Low 6 ADR17H 0x01FE A/D Conversion Result Register High 7 ADR17L 0x01FF A/D Conversion Result Register Low 7 C2MCR0 0x0200 msCAN12 Module Control Register 0 C2MCR0.CSWAI 5 CAN Stops in Wait Mode C2MCR0.SYNCH 4 Synchronized Status C2MCR0.TLNKEN 3 Timer Enable C2MCR0.SLPAK 2 SLEEP Mode Acknowledge C2MCR0.SLPRQ 1 SLEEP request C2MCR0.SFTRES 0 SOFT_RESET C2MCR1 0x0201 msCAN12 Module Control Register 1 C2MCR1.LOOPB 2 Loop Back Self Test Mode C2MCR1.WUPM 1 Wake-Up Mode C2MCR1.CLKSRC 0 msCAN12 Clock Source C2BTR0 0x0202 msCAN12 Bus Timing Register 0 C2BTR0.SJW1 7 Synchronization Jump Width 1 C2BTR0.SJW0 6 Synchronization Jump Width 0 C2BTR0.BRP5 5 Baud Rate Prescaler 5 C2BTR0.BRP4 4 Baud Rate Prescaler 4 C2BTR0.BRP3 3 Baud Rate Prescaler 3 C2BTR0.BRP2 2 Baud Rate Prescaler 2 C2BTR0.BRP1 1 Baud Rate Prescaler 1 C2BTR0.BRP0 0 Baud Rate Prescaler 0 C2BTR1 0x0203 msCAN12 Bus Timing Register 1 C2BTR1.SAMP 7 Sampling C2BTR1.TSEG22 6 Time Segment 22 C2BTR1.TSEG21 5 Time Segment 21 C2BTR1.TSEG20 4 Time Segment 20 C2BTR1.TSEG13 3 Time Segment 13 C2BTR1.TSEG12 2 Time Segment 12 C2BTR1.TSEG11 1 Time Segment 11 C2BTR1.TSEG10 0 Time Segment 10 C2RFLG 0x0204 msCAN12 Receiver Flag Register C2RFLG.WUPIF 7 Wake-up Interrupt Flag C2RFLG.RWRNIF 6 Receiver Warning Interrupt Flag C2RFLG.TWRNIF 5 Transmitter Warning Interrupt Flag C2RFLG.RERRIF 4 Receiver Error Passive Interrupt Flag C2RFLG.TERRIF 3 Transmitter Error Passive Interrupt Flag C2RFLG.BOFFIF 2 BUSOFF Interrupt Flag C2RFLG.OVRIF 1 Overrun Interrupt Flag C2RFLG.RXF 0 Receive Buffer Full C2RIER 0x0205 msCAN12 Receiver Interrupt Enable Register C2RIER.WUPIE 7 Wake-up Interrupt Enable C2RIER.RWRNIE 6 Receiver Warning Interrupt Enable C2RIER.TWRNIE 5 Transmitter Warning Interrupt Enable C2RIER.RERRIE 4 Receiver Error Passive Interrupt Enable C2RIER.TERRIE 3 Transmitter Error Passive Interrupt Enable C2RIER.BOFFIE 2 BUSOFF Interrupt Enable C2RIER.OVRIE 1 Overrun Interrupt Enable C2RIER.RXFIE 0 Receiver Full Interrupt Enable C2TFLG 0x0206 msCAN12 Transmitter Flag Register C2TFLG.ABTAK2 6 Abort Acknowledge 2 C2TFLG.ABTAK1 5 Abort Acknowledge 1 C2TFLG.ABTAK0 4 Abort Acknowledge 0 C2TFLG.TXE2 2 Transmitter Buffer Empty 2 C2TFLG.TXE1 1 Transmitter Buffer Empty 1 C2TFLG.TXE0 0 Transmitter Buffer Empty 0 C2TCR 0x0207 msCAN12 Transmitter Control Register C2TCR.ABTRQ2 6 Abort Request 2 C2TCR.ABTRQ1 5 Abort Request 1 C2TCR.ABTRQ0 4 Abort Request 0 C2TCR.TXEIE2 2 Transmitter Empty Interrupt Enable 2 C2TCR.TXEIE1 1 Transmitter Empty Interrupt Enable 1 C2TCR.TXEIE0 0 Transmitter Empty Interrupt Enable 0 C2IDAC 0x0208 msCAN12 Identifier Acceptance Control Register C2IDAC.IDAM1 5 Identifier Acceptance Mode 1 C2IDAC.IDAM0 4 Identifier Acceptance Mode 0 C2IDAC.IDHIT2 2 Identifier Acceptance Hit Indicator 2 C2IDAC.IDHIT1 1 Identifier Acceptance Hit Indicator 1 C2IDAC.IDHIT0 0 Identifier Acceptance Hit Indicator 0 RESERVED0209 0x0209 RESERVED RESERVED020A 0x020A RESERVED RESERVED020B 0x020B RESERVED RESERVED020C 0x020C RESERVED RESERVED020D 0x020D RESERVED C2RXERR 0x020E msCAN12 Receive Error Counter C2RXERR.RXERR7 7 C2RXERR.RXERR6 6 C2RXERR.RXERR5 5 C2RXERR.RXERR4 4 C2RXERR.RXERR3 3 C2RXERR.RXERR2 2 C2RXERR.RXERR1 1 C2RXERR.RXERR0 0 C2TXERR 0x020F msCAN12 Transmit Error Counter C2TXERR.TXERR7 7 C2TXERR.TXERR6 6 C2TXERR.TXERR5 5 C2TXERR.TXERR4 4 C2TXERR.TXERR3 3 C2TXERR.TXERR2 2 C2TXERR.TXERR1 1 C2TXERR.TXERR0 0 C2IDAR0 0x0210 msCAN12 Identifier Acceptance Register 0 C2IDAR0.AC7 7 Acceptance Code Bit 7 C2IDAR0.AC6 6 Acceptance Code Bit 6 C2IDAR0.AC5 5 Acceptance Code Bit 5 C2IDAR0.AC4 4 Acceptance Code Bit 4 C2IDAR0.AC3 3 Acceptance Code Bit 3 C2IDAR0.AC2 2 Acceptance Code Bit 2 C2IDAR0.AC1 1 Acceptance Code Bit 1 C2IDAR0.AC0 0 Acceptance Code Bit 0 C2IDAR1 0x0211 msCAN12 Identifier Acceptance Register 1 C2IDAR1.AC7 7 Acceptance Code Bit 7 C2IDAR1.AC6 6 Acceptance Code Bit 6 C2IDAR1.AC5 5 Acceptance Code Bit 5 C2IDAR1.AC4 4 Acceptance Code Bit 4 C2IDAR1.AC3 3 Acceptance Code Bit 3 C2IDAR1.AC2 2 Acceptance Code Bit 2 C2IDAR1.AC1 1 Acceptance Code Bit 1 C2IDAR1.AC0 0 Acceptance Code Bit 0 C2IDAR2 0x0212 msCAN12 Identifier Acceptance Register 2 C2IDAR2.AC7 7 Acceptance Code Bit 7 C2IDAR2.AC6 6 Acceptance Code Bit 6 C2IDAR2.AC5 5 Acceptance Code Bit 5 C2IDAR2.AC4 4 Acceptance Code Bit 4 C2IDAR2.AC3 3 Acceptance Code Bit 3 C2IDAR2.AC2 2 Acceptance Code Bit 2 C2IDAR2.AC1 1 Acceptance Code Bit 1 C2IDAR2.AC0 0 Acceptance Code Bit 0 C2IDAR3 0x0213 msCAN12 Identifier Acceptance Register 3 C2IDAR3.AC7 7 Acceptance Code Bit 7 C2IDAR3.AC6 6 Acceptance Code Bit 6 C2IDAR3.AC5 5 Acceptance Code Bit 5 C2IDAR3.AC4 4 Acceptance Code Bit 4 C2IDAR3.AC3 3 Acceptance Code Bit 3 C2IDAR3.AC2 2 Acceptance Code Bit 2 C2IDAR3.AC1 1 Acceptance Code Bit 1 C2IDAR3.AC0 0 Acceptance Code Bit 0 C2IDMR0 0x0214 msCAN12 Identifier Mask Register 0 C2IDMR0.AM7 7 Acceptance Mask Bit 7 C2IDMR0.AM6 6 Acceptance Mask Bit 6 C2IDMR0.AM5 5 Acceptance Mask Bit 5 C2IDMR0.AM4 4 Acceptance Mask Bit 4 C2IDMR0.AM3 3 Acceptance Mask Bit 3 C2IDMR0.AM2 2 Acceptance Mask Bit 2 C2IDMR0.AM1 1 Acceptance Mask Bit 1 C2IDMR0.AM0 0 Acceptance Mask Bit 0 C2IDMR1 0x0215 msCAN12 Identifier Mask Register 1 C2IDMR1.AM7 7 Acceptance Mask Bit 7 C2IDMR1.AM6 6 Acceptance Mask Bit 6 C2IDMR1.AM5 5 Acceptance Mask Bit 5 C2IDMR1.AM4 4 Acceptance Mask Bit 4 C2IDMR1.AM3 3 Acceptance Mask Bit 3 C2IDMR1.AM2 2 Acceptance Mask Bit 2 C2IDMR1.AM1 1 Acceptance Mask Bit 1 C2IDMR1.AM0 0 Acceptance Mask Bit 0 C2IDMR2 0x0216 msCAN12 Identifier Mask Register 2 C2IDMR2.AM7 7 Acceptance Mask Bit 7 C2IDMR2.AM6 6 Acceptance Mask Bit 6 C2IDMR2.AM5 5 Acceptance Mask Bit 5 C2IDMR2.AM4 4 Acceptance Mask Bit 4 C2IDMR2.AM3 3 Acceptance Mask Bit 3 C2IDMR2.AM2 2 Acceptance Mask Bit 2 C2IDMR2.AM1 1 Acceptance Mask Bit 1 C2IDMR2.AM0 0 Acceptance Mask Bit 0 C2IDMR3 0x0217 msCAN12 Identifier Mask Register 3 C2IDMR3.AM7 7 Acceptance Mask Bit 7 C2IDMR3.AM6 6 Acceptance Mask Bit 6 C2IDMR3.AM5 5 Acceptance Mask Bit 5 C2IDMR3.AM4 4 Acceptance Mask Bit 4 C2IDMR3.AM3 3 Acceptance Mask Bit 3 C2IDMR3.AM2 2 Acceptance Mask Bit 2 C2IDMR3.AM1 1 Acceptance Mask Bit 1 C2IDMR3.AM0 0 Acceptance Mask Bit 0 C2IDAR4 0x0218 msCAN12 Identifier Acceptance Register 4 C2IDAR4.AC7 7 Acceptance Code Bit 7 C2IDAR4.AC6 6 Acceptance Code Bit 6 C2IDAR4.AC5 5 Acceptance Code Bit 5 C2IDAR4.AC4 4 Acceptance Code Bit 4 C2IDAR4.AC3 3 Acceptance Code Bit 3 C2IDAR4.AC2 2 Acceptance Code Bit 2 C2IDAR4.AC1 1 Acceptance Code Bit 1 C2IDAR4.AC0 0 Acceptance Code Bit 0 C2IDAR5 0x0219 msCAN12 Identifier Acceptance Register 5 C2IDAR5.AC7 7 Acceptance Code Bit 7 C2IDAR5.AC6 6 Acceptance Code Bit 6 C2IDAR5.AC5 5 Acceptance Code Bit 5 C2IDAR5.AC4 4 Acceptance Code Bit 4 C2IDAR5.AC3 3 Acceptance Code Bit 3 C2IDAR5.AC2 2 Acceptance Code Bit 2 C2IDAR5.AC1 1 Acceptance Code Bit 1 C2IDAR5.AC0 0 Acceptance Code Bit 0 C2IDAR6 0x021A msCAN12 Identifier Acceptance Register 6 C2IDAR6.AC7 7 Acceptance Code Bit 7 C2IDAR6.AC6 6 Acceptance Code Bit 6 C2IDAR6.AC5 5 Acceptance Code Bit 5 C2IDAR6.AC4 4 Acceptance Code Bit 4 C2IDAR6.AC3 3 Acceptance Code Bit 3 C2IDAR6.AC2 2 Acceptance Code Bit 2 C2IDAR6.AC1 1 Acceptance Code Bit 1 C2IDAR6.AC0 0 Acceptance Code Bit 0 C2IDAR7 0x021B msCAN12 Identifier Acceptance Register 7 C2IDAR7.AC7 7 Acceptance Code Bit 7 C2IDAR7.AC6 6 Acceptance Code Bit 6 C2IDAR7.AC5 5 Acceptance Code Bit 5 C2IDAR7.AC4 4 Acceptance Code Bit 4 C2IDAR7.AC3 3 Acceptance Code Bit 3 C2IDAR7.AC2 2 Acceptance Code Bit 2 C2IDAR7.AC1 1 Acceptance Code Bit 1 C2IDAR7.AC0 0 Acceptance Code Bit 0 C2IDMR4 0x021C msCAN12 Identifier Mask Register 4 C2IDMR4.AM7 7 Acceptance Mask Bit 7 C2IDMR4.AM6 6 Acceptance Mask Bit 6 C2IDMR4.AM5 5 Acceptance Mask Bit 5 C2IDMR4.AM4 4 Acceptance Mask Bit 4 C2IDMR4.AM3 3 Acceptance Mask Bit 3 C2IDMR4.AM2 2 Acceptance Mask Bit 2 C2IDMR4.AM1 1 Acceptance Mask Bit 1 C2IDMR4.AM0 0 Acceptance Mask Bit 0 C2IDMR5 0x021D msCAN12 Identifier Mask Register 5 C2IDMR5.AM7 7 Acceptance Mask Bit 7 C2IDMR5.AM6 6 Acceptance Mask Bit 6 C2IDMR5.AM5 5 Acceptance Mask Bit 5 C2IDMR5.AM4 4 Acceptance Mask Bit 4 C2IDMR5.AM3 3 Acceptance Mask Bit 3 C2IDMR5.AM2 2 Acceptance Mask Bit 2 C2IDMR5.AM1 1 Acceptance Mask Bit 1 C2IDMR5.AM0 0 Acceptance Mask Bit 0 C2IDMR6 0x021E msCAN12 Identifier Mask Register 6 C2IDMR6.AM7 7 Acceptance Mask Bit 7 C2IDMR6.AM6 6 Acceptance Mask Bit 6 C2IDMR6.AM5 5 Acceptance Mask Bit 5 C2IDMR6.AM4 4 Acceptance Mask Bit 4 C2IDMR6.AM3 3 Acceptance Mask Bit 3 C2IDMR6.AM2 2 Acceptance Mask Bit 2 C2IDMR6.AM1 1 Acceptance Mask Bit 1 C2IDMR6.AM0 0 Acceptance Mask Bit 0 C2IDMR7 0x021F msCAN12 Identifier Mask Register 7 C2IDMR7.AM7 7 Acceptance Mask Bit 7 C2IDMR7.AM6 6 Acceptance Mask Bit 6 C2IDMR7.AM5 5 Acceptance Mask Bit 5 C2IDMR7.AM4 4 Acceptance Mask Bit 4 C2IDMR7.AM3 3 Acceptance Mask Bit 3 C2IDMR7.AM2 2 Acceptance Mask Bit 2 C2IDMR7.AM1 1 Acceptance Mask Bit 1 C2IDMR7.AM0 0 Acceptance Mask Bit 0 RESERVED0220 0x0220 RESERVED RESERVED0221 0x0221 RESERVED RESERVED0222 0x0222 RESERVED RESERVED0223 0x0223 RESERVED RESERVED0224 0x0224 RESERVED RESERVED0225 0x0225 RESERVED RESERVED0226 0x0226 RESERVED RESERVED0227 0x0227 RESERVED RESERVED0228 0x0228 RESERVED RESERVED0229 0x0229 RESERVED RESERVED022A 0x022A RESERVED RESERVED022B 0x022B RESERVED RESERVED022C 0x022C RESERVED RESERVED022D 0x022D RESERVED RESERVED022E 0x022E RESERVED RESERVED022F 0x022F RESERVED RESERVED0230 0x0230 RESERVED RESERVED0231 0x0231 RESERVED RESERVED0232 0x0232 RESERVED RESERVED0233 0x0233 RESERVED RESERVED0234 0x0234 RESERVED RESERVED0235 0x0235 RESERVED RESERVED0236 0x0236 RESERVED RESERVED0237 0x0237 RESERVED RESERVED0238 0x0238 RESERVED RESERVED0239 0x0239 RESERVED RESERVED023A 0x023A RESERVED RESERVED023B 0x023B RESERVED RESERVED023C 0x023C RESERVED PCTLCAN2 0x023D msCAN12 Port CAN Control Register PCTLCAN2.PUPCAN 1 Pull-Up Enable Port CAN PCTLCAN2.RDPCAN 0 Reduced Drive Port CAN PORTCAN2 0x023E msCAN12 Port CAN Data Register PORTCAN2.PCAN7 7 Port CAN Data Bit 7 PORTCAN2.PCAN6 6 Port CAN Data Bit 6 PORTCAN2.PCAN5 5 Port CAN Data Bit 5 PORTCAN2.PCAN4 4 Port CAN Data Bit 4 PORTCAN2.PCAN3 3 Port CAN Data Bit 3 PORTCAN2.PCAN2 2 Port CAN Data Bit 2 PORTCAN2.TxCAN 1 PORTCAN2.RxCAN 0 DDRCAN2 0x023F msCAN12 Port CAN Data Direction Register DDRCAN2.DDCAN7 7 DDRCAN2.DDCAN6 6 DDRCAN2.DDCAN5 5 DDRCAN2.DDCAN4 4 DDRCAN2.DDCAN3 3 DDRCAN2.DDCAN2 2 C1MCR0 0x0300 msCAN12 Module Control Register 0 C1MCR0.CSWAI 5 CAN Stops in Wait Mode C1MCR0.SYNCH 4 Synchronized Status C1MCR0.TLNKEN 3 Timer Enable C1MCR0.SLPAK 2 SLEEP Mode Acknowledge C1MCR0.SLPRQ 1 SLEEP request C1MCR0.SFTRES 0 SOFT_RESET C1MCR1 0x0301 msCAN12 Module Control Register 1 C1MCR1.LOOPB 2 Loop Back Self Test Mode C1MCR1.WUPM 1 Wake-Up Mode C1MCR1.CLKSRC 0 msCAN12 Clock Source C1BTR0 0x0302 msCAN12 Bus Timing Register 0 C1BTR0.SJW1 7 Synchronization Jump Width 1 C1BTR0.SJW0 6 Synchronization Jump Width 0 C1BTR0.BRP5 5 Baud Rate Prescaler 5 C1BTR0.BRP4 4 Baud Rate Prescaler 4 C1BTR0.BRP3 3 Baud Rate Prescaler 3 C1BTR0.BRP2 2 Baud Rate Prescaler 2 C1BTR0.BRP1 1 Baud Rate Prescaler 1 C1BTR0.BRP0 0 Baud Rate Prescaler 0 C1BTR1 0x0303 msCAN12 Bus Timing Register 1 C1BTR1.SAMP 7 Sampling C1BTR1.TSEG22 6 Time Segment 22 C1BTR1.TSEG21 5 Time Segment 21 C1BTR1.TSEG20 4 Time Segment 20 C1BTR1.TSEG13 3 Time Segment 13 C1BTR1.TSEG12 2 Time Segment 12 C1BTR1.TSEG11 1 Time Segment 11 C1BTR1.TSEG10 0 Time Segment 10 C1RFLG 0x0304 msCAN12 Receiver Flag Register C1RFLG.WUPIF 7 Wake-up Interrupt Flag C1RFLG.RWRNIF 6 Receiver Warning Interrupt Flag C1RFLG.TWRNIF 5 Transmitter Warning Interrupt Flag C1RFLG.RERRIF 4 Receiver Error Passive Interrupt Flag C1RFLG.TERRIF 3 Transmitter Error Passive Interrupt Flag C1RFLG.BOFFIF 2 BUSOFF Interrupt Flag C1RFLG.OVRIF 1 Overrun Interrupt Flag C1RFLG.RXF 0 Receive Buffer Full C1RIER 0x0305 msCAN12 Receiver Interrupt Enable Register C1RIER.WUPIE 7 Wake-up Interrupt Enable C1RIER.RWRNIE 6 Receiver Warning Interrupt Enable C1RIER.TWRNIE 5 Transmitter Warning Interrupt Enable C1RIER.RERRIE 4 Receiver Error Passive Interrupt Enable C1RIER.TERRIE 3 Transmitter Error Passive Interrupt Enable C1RIER.BOFFIE 2 BUSOFF Interrupt Enable C1RIER.OVRIE 1 Overrun Interrupt Enable C1RIER.RXFIE 0 Receiver Full Interrupt Enable C1TFLG 0x0306 msCAN12 Transmitter Flag Register C1TFLG.ABTAK2 6 Abort Acknowledge 2 C1TFLG.ABTAK1 5 Abort Acknowledge 1 C1TFLG.ABTAK0 4 Abort Acknowledge 0 C1TFLG.TXE2 2 Transmitter Buffer Empty 2 C1TFLG.TXE1 1 Transmitter Buffer Empty 1 C1TFLG.TXE0 0 Transmitter Buffer Empty 0 C1TCR 0x0307 msCAN12 Transmitter Control Register C1TCR.ABTRQ2 6 Abort Request 2 C1TCR.ABTRQ1 5 Abort Request 1 C1TCR.ABTRQ0 4 Abort Request 0 C1TCR.TXEIE2 2 Transmitter Empty Interrupt Enable 2 C1TCR.TXEIE1 1 Transmitter Empty Interrupt Enable 1 C1TCR.TXEIE0 0 Transmitter Empty Interrupt Enable 0 C1IDAC 0x0308 msCAN12 Identifier Acceptance Control Register C1IDAC.IDAM1 5 Identifier Acceptance Mode 1 C1IDAC.IDAM0 4 Identifier Acceptance Mode 0 C1IDAC.IDHIT2 2 Identifier Acceptance Hit Indicator 2 C1IDAC.IDHIT1 1 Identifier Acceptance Hit Indicator 1 C1IDAC.IDHIT0 0 Identifier Acceptance Hit Indicator 0 RESERVED0309 0x0309 RESERVED RESERVED030A 0x030A RESERVED RESERVED030B 0x030B RESERVED RESERVED030C 0x030C RESERVED RESERVED030D 0x030D RESERVED C1RXERR 0x030E msCAN12 Receive Error Counter C1RXERR.RXERR7 7 C1RXERR.RXERR6 6 C1RXERR.RXERR5 5 C1RXERR.RXERR4 4 C1RXERR.RXERR3 3 C1RXERR.RXERR2 2 C1RXERR.RXERR1 1 C1RXERR.RXERR0 0 C1TXERR 0x030F msCAN12 Transmit Error Counter C1TXERR.TXERR7 7 C1TXERR.TXERR6 6 C1TXERR.TXERR5 5 C1TXERR.TXERR4 4 C1TXERR.TXERR3 3 C1TXERR.TXERR2 2 C1TXERR.TXERR1 1 C1TXERR.TXERR0 0 C1IDAR0 0x0310 msCAN12 Identifier Acceptance Register 0 C1IDAR0.AC7 7 Acceptance Code Bit 7 C1IDAR0.AC6 6 Acceptance Code Bit 6 C1IDAR0.AC5 5 Acceptance Code Bit 5 C1IDAR0.AC4 4 Acceptance Code Bit 4 C1IDAR0.AC3 3 Acceptance Code Bit 3 C1IDAR0.AC2 2 Acceptance Code Bit 2 C1IDAR0.AC1 1 Acceptance Code Bit 1 C1IDAR0.AC0 0 Acceptance Code Bit 0 C1IDAR1 0x0311 msCAN12 Identifier Acceptance Register 1 C1IDAR1.AC7 7 Acceptance Code Bit 7 C1IDAR1.AC6 6 Acceptance Code Bit 6 C1IDAR1.AC5 5 Acceptance Code Bit 5 C1IDAR1.AC4 4 Acceptance Code Bit 4 C1IDAR1.AC3 3 Acceptance Code Bit 3 C1IDAR1.AC2 2 Acceptance Code Bit 2 C1IDAR1.AC1 1 Acceptance Code Bit 1 C1IDAR1.AC0 0 Acceptance Code Bit 0 C1IDAR2 0x0312 msCAN12 Identifier Acceptance Register 2 C1IDAR2.AC7 7 Acceptance Code Bit 7 C1IDAR2.AC6 6 Acceptance Code Bit 6 C1IDAR2.AC5 5 Acceptance Code Bit 5 C1IDAR2.AC4 4 Acceptance Code Bit 4 C1IDAR2.AC3 3 Acceptance Code Bit 3 C1IDAR2.AC2 2 Acceptance Code Bit 2 C1IDAR2.AC1 1 Acceptance Code Bit 1 C1IDAR2.AC0 0 Acceptance Code Bit 0 C1IDAR3 0x0313 msCAN12 Identifier Acceptance Register 3 C1IDAR3.AC7 7 Acceptance Code Bit 7 C1IDAR3.AC6 6 Acceptance Code Bit 6 C1IDAR3.AC5 5 Acceptance Code Bit 5 C1IDAR3.AC4 4 Acceptance Code Bit 4 C1IDAR3.AC3 3 Acceptance Code Bit 3 C1IDAR3.AC2 2 Acceptance Code Bit 2 C1IDAR3.AC1 1 Acceptance Code Bit 1 C1IDAR3.AC0 0 Acceptance Code Bit 0 C1IDMR0 0x0314 msCAN12 Identifier Mask Register 0 C1IDMR0.AM7 7 Acceptance Mask Bit 7 C1IDMR0.AM6 6 Acceptance Mask Bit 6 C1IDMR0.AM5 5 Acceptance Mask Bit 5 C1IDMR0.AM4 4 Acceptance Mask Bit 4 C1IDMR0.AM3 3 Acceptance Mask Bit 3 C1IDMR0.AM2 2 Acceptance Mask Bit 2 C1IDMR0.AM1 1 Acceptance Mask Bit 1 C1IDMR0.AM0 0 Acceptance Mask Bit 0 C1IDMR1 0x0315 msCAN12 Identifier Mask Register 1 C1IDMR1.AM7 7 Acceptance Mask Bit 7 C1IDMR1.AM6 6 Acceptance Mask Bit 6 C1IDMR1.AM5 5 Acceptance Mask Bit 5 C1IDMR1.AM4 4 Acceptance Mask Bit 4 C1IDMR1.AM3 3 Acceptance Mask Bit 3 C1IDMR1.AM2 2 Acceptance Mask Bit 2 C1IDMR1.AM1 1 Acceptance Mask Bit 1 C1IDMR1.AM0 0 Acceptance Mask Bit 0 C1IDMR2 0x0316 msCAN12 Identifier Mask Register 2 C1IDMR2.AM7 7 Acceptance Mask Bit 7 C1IDMR2.AM6 6 Acceptance Mask Bit 6 C1IDMR2.AM5 5 Acceptance Mask Bit 5 C1IDMR2.AM4 4 Acceptance Mask Bit 4 C1IDMR2.AM3 3 Acceptance Mask Bit 3 C1IDMR2.AM2 2 Acceptance Mask Bit 2 C1IDMR2.AM1 1 Acceptance Mask Bit 1 C1IDMR2.AM0 0 Acceptance Mask Bit 0 C1IDMR3 0x0317 msCAN12 Identifier Mask Register 3 C1IDMR3.AM7 7 Acceptance Mask Bit 7 C1IDMR3.AM6 6 Acceptance Mask Bit 6 C1IDMR3.AM5 5 Acceptance Mask Bit 5 C1IDMR3.AM4 4 Acceptance Mask Bit 4 C1IDMR3.AM3 3 Acceptance Mask Bit 3 C1IDMR3.AM2 2 Acceptance Mask Bit 2 C1IDMR3.AM1 1 Acceptance Mask Bit 1 C1IDMR3.AM0 0 Acceptance Mask Bit 0 C1IDAR4 0x0318 msCAN12 Identifier Acceptance Register 4 C1IDAR4.AC7 7 Acceptance Code Bit 7 C1IDAR4.AC6 6 Acceptance Code Bit 6 C1IDAR4.AC5 5 Acceptance Code Bit 5 C1IDAR4.AC4 4 Acceptance Code Bit 4 C1IDAR4.AC3 3 Acceptance Code Bit 3 C1IDAR4.AC2 2 Acceptance Code Bit 2 C1IDAR4.AC1 1 Acceptance Code Bit 1 C1IDAR4.AC0 0 Acceptance Code Bit 0 C1IDAR5 0x0319 msCAN12 Identifier Acceptance Register 5 C1IDAR5.AC7 7 Acceptance Code Bit 7 C1IDAR5.AC6 6 Acceptance Code Bit 6 C1IDAR5.AC5 5 Acceptance Code Bit 5 C1IDAR5.AC4 4 Acceptance Code Bit 4 C1IDAR5.AC3 3 Acceptance Code Bit 3 C1IDAR5.AC2 2 Acceptance Code Bit 2 C1IDAR5.AC1 1 Acceptance Code Bit 1 C1IDAR5.AC0 0 Acceptance Code Bit 0 C1IDAR6 0x031A msCAN12 Identifier Acceptance Register 6 C1IDAR6.AC7 7 Acceptance Code Bit 7 C1IDAR6.AC6 6 Acceptance Code Bit 6 C1IDAR6.AC5 5 Acceptance Code Bit 5 C1IDAR6.AC4 4 Acceptance Code Bit 4 C1IDAR6.AC3 3 Acceptance Code Bit 3 C1IDAR6.AC2 2 Acceptance Code Bit 2 C1IDAR6.AC1 1 Acceptance Code Bit 1 C1IDAR6.AC0 0 Acceptance Code Bit 0 C1IDAR7 0x031B msCAN12 Identifier Acceptance Register 7 C1IDAR7.AC7 7 Acceptance Code Bit 7 C1IDAR7.AC6 6 Acceptance Code Bit 6 C1IDAR7.AC5 5 Acceptance Code Bit 5 C1IDAR7.AC4 4 Acceptance Code Bit 4 C1IDAR7.AC3 3 Acceptance Code Bit 3 C1IDAR7.AC2 2 Acceptance Code Bit 2 C1IDAR7.AC1 1 Acceptance Code Bit 1 C1IDAR7.AC0 0 Acceptance Code Bit 0 C1IDMR4 0x031C msCAN12 Identifier Mask Register 4 C1IDMR4.AM7 7 Acceptance Mask Bit 7 C1IDMR4.AM6 6 Acceptance Mask Bit 6 C1IDMR4.AM5 5 Acceptance Mask Bit 5 C1IDMR4.AM4 4 Acceptance Mask Bit 4 C1IDMR4.AM3 3 Acceptance Mask Bit 3 C1IDMR4.AM2 2 Acceptance Mask Bit 2 C1IDMR4.AM1 1 Acceptance Mask Bit 1 C1IDMR4.AM0 0 Acceptance Mask Bit 0 C1IDMR5 0x031D msCAN12 Identifier Mask Register 5 C1IDMR5.AM7 7 Acceptance Mask Bit 7 C1IDMR5.AM6 6 Acceptance Mask Bit 6 C1IDMR5.AM5 5 Acceptance Mask Bit 5 C1IDMR5.AM4 4 Acceptance Mask Bit 4 C1IDMR5.AM3 3 Acceptance Mask Bit 3 C1IDMR5.AM2 2 Acceptance Mask Bit 2 C1IDMR5.AM1 1 Acceptance Mask Bit 1 C1IDMR5.AM0 0 Acceptance Mask Bit 0 C1IDMR6 0x031E msCAN12 Identifier Mask Register 6 C1IDMR6.AM7 7 Acceptance Mask Bit 7 C1IDMR6.AM6 6 Acceptance Mask Bit 6 C1IDMR6.AM5 5 Acceptance Mask Bit 5 C1IDMR6.AM4 4 Acceptance Mask Bit 4 C1IDMR6.AM3 3 Acceptance Mask Bit 3 C1IDMR6.AM2 2 Acceptance Mask Bit 2 C1IDMR6.AM1 1 Acceptance Mask Bit 1 C1IDMR6.AM0 0 Acceptance Mask Bit 0 C1IDMR7 0x031F msCAN12 Identifier Mask Register 7 C1IDMR7.AM7 7 Acceptance Mask Bit 7 C1IDMR7.AM6 6 Acceptance Mask Bit 6 C1IDMR7.AM5 5 Acceptance Mask Bit 5 C1IDMR7.AM4 4 Acceptance Mask Bit 4 C1IDMR7.AM3 3 Acceptance Mask Bit 3 C1IDMR7.AM2 2 Acceptance Mask Bit 2 C1IDMR7.AM1 1 Acceptance Mask Bit 1 C1IDMR7.AM0 0 Acceptance Mask Bit 0 RESERVED0320 0x0320 RESERVED RESERVED0321 0x0321 RESERVED RESERVED0322 0x0322 RESERVED RESERVED0323 0x0323 RESERVED RESERVED0324 0x0324 RESERVED RESERVED0325 0x0325 RESERVED RESERVED0326 0x0326 RESERVED RESERVED0327 0x0327 RESERVED RESERVED0328 0x0328 RESERVED RESERVED0329 0x0329 RESERVED RESERVED032A 0x032A RESERVED RESERVED032B 0x032B RESERVED RESERVED032C 0x032C RESERVED RESERVED032D 0x032D RESERVED RESERVED032E 0x032E RESERVED RESERVED032F 0x032F RESERVED RESERVED0330 0x0330 RESERVED RESERVED0331 0x0331 RESERVED RESERVED0332 0x0332 RESERVED RESERVED0333 0x0333 RESERVED RESERVED0334 0x0334 RESERVED RESERVED0335 0x0335 RESERVED RESERVED0336 0x0336 RESERVED RESERVED0337 0x0337 RESERVED RESERVED0338 0x0338 RESERVED RESERVED0339 0x0339 RESERVED RESERVED033A 0x033A RESERVED RESERVED033B 0x033B RESERVED RESERVED033C 0x033C RESERVED PCTLCAN1 0x033D msCAN12 Port CAN Control Register PCTLCAN1.PUPCAN 1 Pull-Up Enable Port CAN PCTLCAN1.RDPCAN 0 Reduced Drive Port CAN PORTCAN1 0x033E msCAN12 Port CAN Data Register PORTCAN1.PCAN7 7 Port CAN Data Bit 7 PORTCAN1.PCAN6 6 Port CAN Data Bit 6 PORTCAN1.PCAN5 5 Port CAN Data Bit 5 PORTCAN1.PCAN4 4 Port CAN Data Bit 4 PORTCAN1.PCAN3 3 Port CAN Data Bit 3 PORTCAN1.PCAN2 2 Port CAN Data Bit 2 PORTCAN1.TxCAN 1 PORTCAN1.RxCAN 0 DDRCAN1 0x033F msCAN12 Port CAN Data Direction Register DDRCAN1.DDCAN7 7 DDRCAN1.DDCAN6 6 DDRCAN1.DDCAN5 5 DDRCAN1.DDCAN4 4 DDRCAN1.DDCAN3 3 DDRCAN1.DDCAN2 2 .68HC812A4 ; ; MC68HC812A4.pdf ; MEMORY MAP area DATA FSR 0x0000:0x00F4 area BSS RESERVED 0x00F4:0x0800 area DATA RAM 0x0800:0x0C00 area BSS RESERVED 0x0C00:0x0F00 area DATA EEPROM 0x0F00:0xFFC0 area DATA USER_VEC 0xFFC0:0x10000 ; Interrupt and reset vector assignments interrupt __RESET 0xFFFE Power-on reset interrupt CME_FCME 0xFFFC COP clock monitor fail reset interrupt COP_R 0xFFFA COP reset interrupt UIT 0xFFF8 Unimplemented instruction trap interrupt SWI 0xFFF6 SWI interrupt XIRQ 0xFFF4 XIRQ pin interrupt IRQEN_KWIED 0xFFF2 IRQ pin or key wakeup D interrupt RTIE 0xFFF0 Real-time interrupt interrupt C0I 0xFFEE Timer channel 0 interrupt C1I 0xFFEC Timer channel 1 interrupt C2I 0xFFEA Timer channel 2 interrupt C3I 0xFFE8 Timer channel 3 interrupt C4I 0xFFE6 Timer channel 4 interrupt C5I 0xFFE4 Timer channel 5 interrupt C6I 0xFFE2 Timer channel 6 interrupt C7I 0xFFE0 Timer channel 7 interrupt TOI 0xFFDE Timer overflow interrupt PAOVI 0xFFDC Pulse accumulator overflow interrupt PAI 0xFFDA Pulse accumulator input edge interrupt SPI0E 0xFFD8 SPI serial transfer complete Mode fault interrupt SCI0 0xFFD6 SCI0 interrupt SCI1 0xFFD4 SCI1 interrupt ASCIE 0xFFD2 ATD interrupt KWIEJ 0xFFD0 Key wakeup J (stop wakeup) interrupt KWIEH 0xFFCE Key wakeup H (stop wakeup) ; INPUT/ OUTPUT PORTS PORTA 0x0000 Port A Data Register PORTA.PA7 7 Port A Data Bit 7 PORTA.PA6 6 Port A Data Bit 6 PORTA.PA5 5 Port A Data Bit 5 PORTA.PA4 4 Port A Data Bit 4 PORTA.PA3 3 Port A Data Bit 3 PORTA.PA2 2 Port A Data Bit 2 PORTA.PA1 1 Port A Data Bit 1 PORTA.PA0 0 Port A Data Bit 0 PORTB 0x0001 Port B Data Register PORTB.PB7 7 Port B Data Bit 7 PORTB.PB6 6 Port B Data Bit 6 PORTB.PB5 5 Port B Data Bit 5 PORTB.PB4 4 Port B Data Bit 4 PORTB.PB3 3 Port B Data Bit 3 PORTB.PB2 2 Port B Data Bit 2 PORTB.PB1 1 Port B Data Bit 1 PORTB.PB0 0 Port B Data Bit 0 DDRA 0x0002 Port A Data Direction Register DDRA.DDRA7 7 Port A Data Direction Bit 7 DDRA.DDRA6 6 Port A Data Direction Bit 6 DDRA.DDRA5 5 Port A Data Direction Bit 5 DDRA.DDRA4 4 Port A Data Direction Bit 4 DDRA.DDRA3 3 Port A Data Direction Bit 3 DDRA.DDRA2 2 Port A Data Direction Bit 2 DDRA.DDRA1 1 Port A Data Direction Bit 1 DDRA.DDRA0 0 Port A Data Direction Bit 0 DDRB 0x0003 Port B Data Direction Register DDRB.DDRB7 7 Port B Data Direction Bit 7 DDRB.DDRB6 6 Port B Data Direction Bit 6 DDRB.DDRB5 5 Port B Data Direction Bit 5 DDRB.DDRB4 4 Port B Data Direction Bit 4 DDRB.DDRB3 3 Port B Data Direction Bit 3 DDRB.DDRB2 2 Port B Data Direction Bit 2 DDRB.DDRB1 1 Port B Data Direction Bit 1 DDRB.DDRB0 0 Port B Data Direction Bit 0 PORTC 0x0004 Port C Data Register PORTC.PC7 7 Port C Data Bit 7 PORTC.PC6 6 Port C Data Bit 6 PORTC.PC5 5 Port C Data Bit 5 PORTC.PC4 4 Port C Data Bit 4 PORTC.PC3 3 Port C Data Bit 3 PORTC.PC2 2 Port C Data Bit 2 PORTC.PC1 1 Port C Data Bit 1 PORTC.PC0 0 Port C Data Bit 0 PORTD 0x0005 Port D Data Register PORTD.PD7 7 Port D Data Bit 7 PORTD.PD6 6 Port D Data Bit 6 PORTD.PD5 5 Port D Data Bit 5 PORTD.PD4 4 Port D Data Bit 4 PORTD.PD3 3 Port D Data Bit 3 PORTD.PD2 2 Port D Data Bit 2 PORTD.PD1 1 Port D Data Bit 1 PORTD.PD0 0 Port D Data Bit 0 DDRC 0x0006 Port C Data Direction Register DDRC.DDRC7 7 Port C Data Direction Bit 7 DDRC.DDRC6 6 Port C Data Direction Bit 6 DDRC.DDRC5 5 Port C Data Direction Bit 5 DDRC.DDRC4 4 Port C Data Direction Bit 4 DDRC.DDRC3 3 Port C Data Direction Bit 3 DDRC.DDRC2 2 Port C Data Direction Bit 2 DDRC.DDRC1 1 Port C Data Direction Bit 1 DDRC.DDRC0 0 Port C Data Direction Bit 0 DDRD 0x0007 Port D Data Direction Register DDRD.DDRD7 7 Port D Data Direction Bit 7 DDRD.DDRD6 6 Port D Data Direction Bit 6 DDRD.DDRD5 5 Port D Data Direction Bit 5 DDRD.DDRD4 4 Port D Data Direction Bit 4 DDRD.DDRD3 3 Port D Data Direction Bit 3 DDRD.DDRD2 2 Port D Data Direction Bit 2 DDRD.DDRD1 1 Port D Data Direction Bit 1 DDRD.DDRD0 0 Port D Data Direction Bit 0 PORTE 0x0008 Port E Data Register PORTE.PE7 7 Port E Data Bit 7 PORTE.PE6 6 Port E Data Bit 6 PORTE.PE5 5 Port E Data Bit 5 PORTE.PE4 4 Port E Data Bit 4 PORTE.PE3 3 Port E Data Bit 3 PORTE.PE2 2 Port E Data Bit 2 PORTE.PE1 1 Port E Data Bit 1 PORTE.PE0 0 Port E Data Bit 0 DDRE 0x0009 Port E Data Direction Register DDRE.DDRE7 7 Port E Data Direction Bit 7 DDRE.DDRE6 6 Port E Data Direction Bit 6 DDRE.DDRE5 5 Port E Data Direction Bit 5 DDRE.DDRE4 4 Port E Data Direction Bit 4 DDRE.DDRE3 3 Port E Data Direction Bit 3 DDRE.DDRE2 2 Port E Data Direction Bit 2 DDRE.DDRE1 1 Port E Data Direction Bit 1 DDRE.DDRE0 0 Port E Data Direction Bit 0 PEAR 0x000A Port E Assignment Register PEAR.ARSIE 7 Auxiliary Reset Input Enable Bit PEAR.PLLTE 6 PLL Testing Enable Bit PEAR.PIPOE 5 Pipe Status Signal Output Enable Bit PEAR.NECLK 4 No External E Clock Bit PEAR.LSTRE 3 Low Strobe (LSTRB) Enable Bit PEAR.RDWE 2 Read/Write Enable Bit MODE 0x000B Mode Register MODE.SMODN 7 Mode Select Special Bit MODE.MODB 6 Mode Select B Bit MODE.MODA 5 Mode Select A Bit MODE.ESTR 4 E-Clock Stretch Enable Bit MODE.IVIS 3 Internal Visibility Bit MODE.EMD 1 Emulate Port D Bit MODE.EME 0 Emulate Port E Bit PUCR 0x000C Pullup Control Register PUCR.PUPH 7 Pullup Port H Enable Bit PUCR.PUPG 6 Pullup Port G Enable Bit PUCR.PUPF 5 Pullup Port F Enable Bit PUCR.PUPE 4 Pullup Port E Enable Bit PUCR.PUPD 3 Pullup Port D Enable Bit PUCR.PUC 2 Pullup Port C Enable Bit PUCR.PUPB 1 Pullup Port B Enable Bit PUCR.PUPA 0 Pullup Port A Enable Bit RDRIV 0x000D Reduced Drive Register RDRIV.RDPJ 7 Reduced Drive of Port J Bit RDRIV.RDPH 6 Reduced Drive of Port H Bit RDRIV.RDPG 5 Reduced Drive of Port G Bit RDRIV.RDPF 4 Reduced Drive of Port F Bit RDRIV.RDPE 3 Reduced Drive of Port E Bit RDRIV.PRPD 2 Reduced Drive of Port D Bit RDRIV.RDPC 1 Reduced Drive of Port C Bit RDRIV.RDPAB 0 Reduced Drive of Port A and Port B Bit RESERVED000E 0x000E RESERVED RESERVED000F 0x000F RESERVED INITRM 0x0010 RAM Initialization Register INITRM.RAM15 7 RAM Position Bit 15 INITRM.RAM14 6 RAM Position Bit 14 INITRM.RAM13 5 RAM Position Bit 13 INITRM.RAM12 4 RAM Position Bit 12 INITRM.RAM11 3 RAM Position Bit 11 INITRG 0x0011 Register Initialization Register INITRG.REG15 7 Register Position Bit 15 INITRG.REG14 6 Register Position Bit 14 INITRG.REG13 5 Register Position Bit 13 INITRG.REG12 4 Register Position Bit 12 INITRG.REG11 3 Register Position Bit 11 INITEE 0x0012 EEPROM Initialization Register INITEE.EE15 7 EEPROM Position Bit 15 INITEE.EE14 6 EEPROM Position Bit 14 INITEE.EE13 5 EEPROM Position Bit 13 INITEE.EE12 4 EEPROM Position Bit 12 INITEE.EEON 0 EEPROM On Bit MISC 0x0013 Miscellaneous Mapping Control Register MISC.EWDIR 7 Extra Window Positioned in Direct Space Bit MISC.NDRC 6 Narrow Data Bus for Register Chip-Select Space Bit RTICTL 0x0014 Real-Tme Interrupt Control Reg. RTICTL.RTIE 7 Real-Time Interrupt Enable Bit RTICTL.RSWAI 6 RTI Stop in Wait Bit RTICTL.RSBCK 5 RTI Stop in Background Mode Bit RTICTL.RTBYP 3 RTI Bypass Bit RTICTL.RTR2 2 Real-Time Interrupt Rate Select Bit 2 RTICTL.RTR1 1 Real-Time Interrupt Rate Select Bit 1 RTICTL.RTR0 0 Real-Time Interrupt Rate Select Bit 0 RTIFLG 0x0015 Real-Time Interrupt Flag Register RTIFLG.RTIF 7 Real-Time Interrupt Flag COPCTL 0x0016 COP Control Register COPCTL.CME 7 Clock Monitor Enable Bit COPCTL.FCME 6 Force Clock Monitor Enable Bit COPCTL.FCM 5 Force Clock Monitor Reset Bit COPCTL.FCOP 4 Force COP Reset Bit COPCTL.DISR 3 Disable Reset Bit COPCTL.CR2 2 COP Watchdog Timer Rate Select Bit 2 COPCTL.CR1 1 COP Watchdog Timer Rate Select Bit 1 COPCTL.CR0 0 COP Watchdog Timer Rate Select Bit 0 COPRST 0x0017 Arm/Reset COP Register RESERVED0018 0x0018 RESERVED RESERVED0019 0x0019 RESERVED RESERVED001A 0x001A RESERVED RESERVED001B 0x001B RESERVED RESERVED001C 0x001C RESERVED RESERVED001D 0x001D RESERVED INTCR 0x001E Interrupt Control Register INTCR.IRQE 7 IRQ Edge-Sensitive-Only Bit INTCR.IRQEN 6 IRQ Enable Bit INTCR.DLY 5 Oscillator Startup Delay on Exit from Stop Mode Bit HPRIO 0x001F Highest Priority I Interrupt Reg. HPRIO.PSEL5 5 HPRIO.PSEL4 4 HPRIO.PSEL3 3 HPRIO.PSEL2 2 HPRIO.PSEL1 1 HPRIO.PSEL0 0 KWIED 0x0020 Port D Key Wakeup Interrupt Enable Reg. KWIED.KWIED7 7 Key Wakeup Port D Interrupt Enable Bit 7 KWIED.KWIED6 6 Key Wakeup Port D Interrupt Enable Bit 6 KWIED.KWIED5 5 Key Wakeup Port D Interrupt Enable Bit 5 KWIED.KWIED4 4 Key Wakeup Port D Interrupt Enable Bit 4 KWIED.KWIED3 3 Key Wakeup Port D Interrupt Enable Bit 3 KWIED.KWIED2 2 Key Wakeup Port D Interrupt Enable Bit 2 KWIED.KWIED1 1 Key Wakeup Port D Interrupt Enable Bit 1 KWIED.KWIED0 0 Key Wakeup Port D Interrupt Enable Bit 0 KWIFD 0x0021 Port D Key Wakeup Flag Register KWIFD.KWIFD7 7 Key Wakeup Port D Flag 7 KWIFD.KWIFD6 6 Key Wakeup Port D Flag 6 KWIFD.KWIFD5 5 Key Wakeup Port D Flag 5 KWIFD.KWIFD4 4 Key Wakeup Port D Flag 4 KWIFD.KWIFD3 3 Key Wakeup Port D Flag 3 KWIFD.KWIFD2 2 Key Wakeup Port D Flag 2 KWIFD.KWIFD1 1 Key Wakeup Port D Flag 1 KWIFD.KWIFD0 0 Key Wakeup Port D Flag 0 RESERVED0022 0x0022 RESERVED RESERVED0023 0x0023 RESERVED PORTH 0x0024 Port H Data Register PORTH.PH7 7 Port H Data Bit 7 PORTH.PH6 6 Port H Data Bit 6 PORTH.PH5 5 Port H Data Bit 5 PORTH.PH4 4 Port H Data Bit 4 PORTH.PH3 3 Port H Data Bit 3 PORTH.PH2 2 Port H Data Bit 2 PORTH.PH1 1 Port H Data Bit 1 PORTH.PH0 0 Port H Data Bit 0 DDRH 0x0025 Port H Data Direction Register DDRH.DDRH7 7 Data Direction Port H Bit 7 DDRH.DDRH6 6 Data Direction Port H Bit 6 DDRH.DDRH5 5 Data Direction Port H Bit 5 DDRH.DDRH4 4 Data Direction Port H Bit 4 DDRH.DDRH3 3 Data Direction Port H Bit 3 DDRH.DDRH2 2 Data Direction Port H Bit 2 DDRH.DDRH1 1 Data Direction Port H Bit 1 DDRH.DDRH0 0 Data Direction Port H Bit 0 KWIEH 0x0026 Port H Key Wakeup Interrupt Enable Reg. KWIEH.KWIEH7 7 Key Wakeup Port H Interrupt Enable Bit 7 KWIEH.KWIEH6 6 Key Wakeup Port H Interrupt Enable Bit 6 KWIEH.KWIEH5 5 Key Wakeup Port H Interrupt Enable Bit 5 KWIEH.KWIEH4 4 Key Wakeup Port H Interrupt Enable Bit 4 KWIEH.KWIEH3 3 Key Wakeup Port H Interrupt Enable Bit 3 KWIEH.KWIEH2 2 Key Wakeup Port H Interrupt Enable Bit 2 KWIEH.KWIEH1 1 Key Wakeup Port H Interrupt Enable Bit 1 KWIEH.KWIEH0 0 Key Wakeup Port H Interrupt Enable Bit 0 KWIFH 0x0027 Port H Key Wakeup Flag Register KWIFH.KWIFH7 7 Key Wakeup Port H Flag 7 KWIFH.KWIFH6 6 Key Wakeup Port H Flag 6 KWIFH.KWIFH5 5 Key Wakeup Port H Flag 5 KWIFH.KWIFH4 4 Key Wakeup Port H Flag 4 KWIFH.KWIFH3 3 Key Wakeup Port H Flag 3 KWIFH.KWIFH2 2 Key Wakeup Port H Flag 2 KWIFH.KWIFH1 1 Key Wakeup Port H Flag 1 KWIFH.KWIFH0 0 Key Wakeup Port H Flag 0 PORTJ 0x0028 Port J Data Register PORTJ.PJ7 7 Port J Data Bit 7 PORTJ.PJ6 6 Port J Data Bit 6 PORTJ.PJ5 5 Port J Data Bit 5 PORTJ.PJ4 4 Port J Data Bit 4 PORTJ.PJ3 3 Port J Data Bit 3 PORTJ.PJ2 2 Port J Data Bit 2 PORTJ.PJ1 1 Port J Data Bit 1 PORTJ.PJ0 0 Port J Data Bit 0 DDRJ 0x0029 Port J Data Direction Register DDRJ.DDRJ7 7 Data Direction Port J Bit 7 DDRJ.DDRJ6 6 Data Direction Port J Bit 6 DDRJ.DDRJ5 5 Data Direction Port J Bit 5 DDRJ.DDRJ4 4 Data Direction Port J Bit 4 DDRJ.DDRJ3 3 Data Direction Port J Bit 3 DDRJ.DDRJ2 2 Data Direction Port J Bit 2 DDRJ.DDRJ1 1 Data Direction Port J Bit 1 DDRJ.DDRJ0 0 Data Direction Port J Bit 0 KWIEJ 0x002A Port J Key Wakeup Interrupt Enable Register KWIEJ.KWIEJ7 7 Key Wakeup Port J Interrupt Enable Bit 7 KWIEJ.KWIEJ6 6 Key Wakeup Port J Interrupt Enable Bit 6 KWIEJ.KWIEJ5 5 Key Wakeup Port J Interrupt Enable Bit 5 KWIEJ.KWIEJ4 4 Key Wakeup Port J Interrupt Enable Bit 4 KWIEJ.KWIEJ3 3 Key Wakeup Port J Interrupt Enable Bit 3 KWIEJ.KWIEJ2 2 Key Wakeup Port J Interrupt Enable Bit 2 KWIEJ.KWIEJ1 1 Key Wakeup Port J Interrupt Enable Bit 1 KWIEJ.KWIEJ0 0 Key Wakeup Port J Interrupt Enable Bit 0 KWIFJ 0x002B Port J Key Wakeup Flag Register KWIFJ.KWIFJ7 7 Key Wakeup Port J Flag 7 KWIFJ.KWIFJ6 6 Key Wakeup Port J Flag 6 KWIFJ.KWIFJ5 5 Key Wakeup Port J Flag 5 KWIFJ.KWIFJ4 4 Key Wakeup Port J Flag 4 KWIFJ.KWIFJ3 3 Key Wakeup Port J Flag 3 KWIFJ.KWIFJ2 2 Key Wakeup Port J Flag 2 KWIFJ.KWIFJ1 1 Key Wakeup Port J Flag 1 KWIFJ.KWIFJ0 0 Key Wakeup Port J Flag 0 KPOLJ 0x002C Port J Key Wakeup Polarity Register KPOLJ.KPOLJ7 7 Key Wakeup Port J Polarity Select Bit 7 KPOLJ.KPOLJ6 6 Key Wakeup Port J Polarity Select Bit 6 KPOLJ.KPOLJ5 5 Key Wakeup Port J Polarity Select Bit 5 KPOLJ.KPOLJ4 4 Key Wakeup Port J Polarity Select Bit 4 KPOLJ.KPOLJ3 3 Key Wakeup Port J Polarity Select Bit 3 KPOLJ.KPOLJ2 2 Key Wakeup Port J Polarity Select Bit 2 KPOLJ.KPOLJ1 1 Key Wakeup Port J Polarity Select Bit 1 KPOLJ.KPOLJ0 0 Key Wakeup Port J Polarity Select Bit 0 PUPSJ 0x002D Port J Key Wakeup Pullup/Pulldown Select Register PUPSJ.PUPSJ7 7 Key Wakeup Port J Pullup/Pulldown Select Bit 7 PUPSJ.PUPSJ6 6 Key Wakeup Port J Pullup/Pulldown Select Bit 6 PUPSJ.PUPSJ5 5 Key Wakeup Port J Pullup/Pulldown Select Bit 5 PUPSJ.PUPSJ4 4 Key Wakeup Port J Pullup/Pulldown Select Bit 4 PUPSJ.PUPSJ3 3 Key Wakeup Port J Pullup/Pulldown Select Bit 3 PUPSJ.PUPSJ2 2 Key Wakeup Port J Pullup/Pulldown Select Bit 2 PUPSJ.PUPSJ1 1 Key Wakeup Port J Pullup/Pulldown Select Bit 1 PUPSJ.PUPSJ0 0 Key Wakeup Port J Pullup/Pulldown Select Bit 0 PULEJ 0x002E Port J Key Wakeup Pullup/Pulldown Enable Register PULEJ.PULEJ7 7 Key Wakeup Port J Pullup/Pulldown Enable Bit 7 PULEJ.PULEJ6 6 Key Wakeup Port J Pullup/Pulldown Enable Bit 6 PULEJ.PULEJ5 5 Key Wakeup Port J Pullup/Pulldown Enable Bit 5 PULEJ.PULEJ4 4 Key Wakeup Port J Pullup/Pulldown Enable Bit 4 PULEJ.PULEJ3 3 Key Wakeup Port J Pullup/Pulldown Enable Bit 3 PULEJ.PULEJ2 2 Key Wakeup Port J Pullup/Pulldown Enable Bit 2 PULEJ.PULEJ1 1 Key Wakeup Port J Pullup/Pulldown Enable Bit 1 PULEJ.PULEJ0 0 Key Wakeup Port J Pullup/Pulldown Enable Bit 0 RESERVED002F 0x002F RESERVED PORTF 0x0030 Port F Data Register PORTF.PF6 6 Port F Data Bit 6 PORTF.PF5 5 Port F Data Bit 5 PORTF.PF4 4 Port F Data Bit 4 PORTF.PF3 3 Port F Data Bit 3 PORTF.PF2 2 Port F Data Bit 2 PORTF.PF1 1 Port F Data Bit 1 PORTF.PF0 0 Port F Data Bit 0 PORTG 0x0031 Port G Data Register PORTG.PG5 5 Port G Data Bit 5 PORTG.PG4 4 Port G Data Bit 4 PORTG.PG3 3 Port G Data Bit 3 PORTG.PG2 2 Port G Data Bit 2 PORTG.PG1 1 Port G Data Bit 1 PORTG.PG0 0 Port G Data Bit 0 DDRF 0x0032 Port F Data Direction Register DDRF.DDRF6 6 Data Direction Port F Bit 6 DDRF.DDRF5 5 Data Direction Port F Bit 5 DDRF.DDRF4 4 Data Direction Port F Bit 4 DDRF.DDRF3 3 Data Direction Port F Bit 3 DDRF.DDRF2 2 Data Direction Port F Bit 2 DDRF.DDRF1 1 Data Direction Port F Bit 1 DDRF.DDRF0 0 Data Direction Port F Bit 0 DDRG 0x0033 Port G Data Direction Register DDRG.DDRG5 5 Data Direction Port G Bit 5 DDRG.DDRG4 4 Data Direction Port G Bit 4 DDRG.DDRG3 3 Data Direction Port G Bit 3 DDRG.DDRG2 2 Data Direction Port G Bit 2 DDRG.DDRG1 1 Data Direction Port G Bit 1 DDRG.DDRG0 0 Data Direction Port G Bit 0 DPAGE 0x0034 Data Page Register DPAGE.PD19 7 DPAGE.PD18 6 DPAGE.PD17 5 DPAGE.PD16 4 DPAGE.PD15 3 DPAGE.PD14 2 DPAGE.PD13 1 DPAGE.PD12 0 PPAGE 0x0035 Program Page Register PPAGE.PPA21 7 PPAGE.PPA20 6 PPAGE.PPA19 5 PPAGE.PPA18 4 PPAGE.PPA17 3 PPAGE.PPA16 2 PPAGE.PPA15 1 PPAGE.PPA14 0 EPAGE 0x0036 Extra Page Register EPAGE.PEA17 7 EPAGE.PEA16 6 EPAGE.PEA15 5 EPAGE.PEA14 4 EPAGE.PEA13 3 EPAGE.PEA12 2 EPAGE.PEA11 1 EPAGE.PEA10 0 WINDEF 0x0037 Window Definition Register WINDEF.DWEN 7 Data Window Enable Bit WINDEF.PWEN 6 Program Window Enable Bit WINDEF.EWEN 5 Extra Window Enable Bit MXAR 0x0038 Memory Expansion Assignment Register MXAR.A21E 5 MXAR.A20E 4 MXAR.A19E 3 MXAR.A18E 2 MXAR.A17E 1 MXAR.A16E 0 RESERVED0039 0x0039 RESERVED RESERVED003A 0x003A RESERVED RESERVED003B 0x003B RESERVED CSCTL0 0x003C Chip-Select Control Register 0 CSCTL0.CSP1E 6 Chip-Select Program 1 Enable Bit CSCTL0.CSP0E 5 Chip-Select Program 0 Enable Bit CSCTL0.CSDE 4 Chip-Select Data Enable Bit CSCTL0.CS3E 3 Chip-Select 3 Enable Bit CSCTL0.CS2E 2 Chip-Select 2 Enable Bit CSCTL0.CS1E 1 Chip-Select 1 Enable Bit CSCTL0.CS0E 0 Chip-Select 0 Enable Bit CSCTL1 0x003D Chip-Select Control Register 1 CSCTL1.CSP1FL 6 Program Chip-Select 1 Covers Full Map CSCTL1.CSPA21 5 Program Chip-Select Split Based on ADDR21 CSCTL1.CSDHF 4 Data Chip-Select Covers Half the Map CSCTL1.CS3EP 3 Chip-Select 3 Follows Extra Page CSSTR0 0x003E Chip-Select Stretch Register 0 CSSTR0.SRP1A 5 CSSTR0.SRP1B 4 CSSTR0.SRP0A 3 CSSTR0.SRP0B 2 CSSTR0.STRDA 1 CSSTR0.STRDB 0 CSSTR1 0x003F Chip-Select Stretch Register 1 CSSTR1.STR3A 7 CSSTR1.STR3B 6 CSSTR1.STR2A 5 CSSTR1.STR2B 4 CSSTR1.STR1A 3 CSSTR1.STR1B 2 CSSTR1.STR0A 1 CSSTR1.STR0B 0 LDVH 0x0040 Loop Divider Register High LDVH.LDV11 3 LDVH.LDV10 2 LDVH.LDV9 1 LDVH.LDV8 0 LDVL 0x0041 Loop Divider Register Low LDVL.LDV7 7 LDVL.LDV6 6 LDVL.LDV5 5 LDVL.LDV4 4 LDVL.LDV3 3 LDVL.LDV2 2 LDVL.LDV1 1 LDVL.LDV0 0 RDVH 0x0042 Reference Divider Register High RDVH.RDV11 3 RDVH.RDV10 2 RDVH.RDV9 1 RDVH.RDV8 0 RDVL 0x0043 Reference Divider Register Low RDVL.RDV7 7 RDVL.RDV6 6 RDVL.RDV5 5 RDVL.RDV4 4 RDVL.RDV3 3 RDVL.RDV2 2 RDVL.RDV1 1 RDVL.RDV0 0 RESERVED0044 0x0044 RESERVED RESERVED0045 0x0045 RESERVED RESERVED0046 0x0046 RESERVED CLKCTL 0x0047 Clock Control Register CLKCTL.LCKF 7 Lock Flag CLKCTL.PLLON 6 PLL On Bit CLKCTL.PLLS 5 PLL Select Bit (PLL output or crystal input frequency) CLKCTL.BCSC 4 Base Clock Select Bit C CLKCTL.BCSB 3 Base Clock Select Bit B CLKCTL.BCSA 2 Base Clock Select Bit A CLKCTL.MCSB 1 Module Clock Select Bit B CLKCTL.MCSA 0 Module Clock Select Bit A RESERVED0048 0x0048 RESERVED RESERVED0049 0x0049 RESERVED RESERVED004A 0x004A RESERVED RESERVED004B 0x004B RESERVED RESERVED004C 0x004C RESERVED RESERVED004D 0x004D RESERVED RESERVED004E 0x004E RESERVED RESERVED004F 0x004F RESERVED RESERVED0050 0x0050 RESERVED RESERVED0051 0x0051 RESERVED RESERVED0052 0x0052 RESERVED RESERVED0053 0x0053 RESERVED RESERVED0054 0x0054 RESERVED RESERVED0055 0x0055 RESERVED RESERVED0056 0x0056 RESERVED RESERVED0057 0x0057 RESERVED RESERVED0058 0x0058 RESERVED RESERVED0059 0x0059 RESERVED RESERVED005A 0x005A RESERVED RESERVED005B 0x005B RESERVED RESERVED005C 0x005C RESERVED RESERVED005D 0x005D RESERVED RESERVED005E 0x005E RESERVED RESERVED005F 0x005F RESERVED ATDCTL0 0x0060 ATD Control Register 0 ATDCTL1 0x0061 ATD Control Register 1 ATDCTL2 0x0062 ATD Control Register 2 ATDCTL2.ADPU 7 ATD Power-up Bit ATDCTL2.AFFC 6 ATD Fast Flag Clear Bit ATDCTL2.AWAI 5 ATD Stop in Wait Mode Bit ATDCTL2.ASCIE 1 ATD Sequence Complete Interrupt Enable Bit ATDCTL2.ASCIF 0 ATD Sequence Complete Interrupt Flag ATDCTL3 0x0063 ATD Control Register 3 ATDCTL3.FRZ1 1 Freeze Bit 1 ATDCTL3.FRZ0 0 Freeze Bit 0 ATDCTL4 0x0064 ATD Control Register 4 ATDCTL4.SMP1 6 Sample Time Select Bit 1 ATDCTL4.SMP0 5 Sample Time Select Bit 0 ATDCTL4.PRS4 4 Prescaler Select Bit 4 ATDCTL4.PRS3 3 Prescaler Select Bit 3 ATDCTL4.PRS2 2 Prescaler Select Bit 2 ATDCTL4.PRS1 1 Prescaler Select Bit 1 ATDCTL4.PRS0 0 Prescaler Select Bit 0 ATDCTL5 0x0065 ATD Control Register 5 ATDCTL5.S8CM 6 Select Eight Conversions Mode Bit ATDCTL5.SCAN 5 Continuous Channel Scan Bit ATDCTL5.MULT 4 Multichannel Conversion Bit ATDCTL5.CD 3 Channel Select Bit D ATDCTL5.CC 2 Channel Select Bit C ATDCTL5.CB 1 Channel Select Bit B ATDCTL5.CA 0 Channel Select Bit A ATDSTAT1 0x0066 ATD Status Register 1 ATDSTAT1.SCF 7 Sequence Complete Flag ATDSTAT1.CC2 2 Conversion Counter Bit 2 ATDSTAT1.CC1 1 Conversion Counter Bit 1 ATDSTAT1.CC0 0 Conversion Counter Bit 0 ATDSTAT2 0x0067 ATD Status Register 2 ATDSTAT2.CCF7 7 Conversion Complete Flag 7 ATDSTAT2.CCF6 6 Conversion Complete Flag 6 ATDSTAT2.CCF5 5 Conversion Complete Flag 5 ATDSTAT2.CCF4 4 Conversion Complete Flag 4 ATDSTAT2.CCF3 3 Conversion Complete Flag 3 ATDSTAT2.CCF2 2 Conversion Complete Flag 2 ATDSTAT2.CCF1 1 Conversion Complete Flag 1 ATDSTAT2.CCF0 0 Conversion Complete Flag 0 ATDTEST1 0x0068 ATD Test Register 1 ATDTEST1.SAR9 7 SAR Data Bit 9 ATDTEST1.SAR8 6 SAR Data Bit 8 ATDTEST1.SAR7 5 SAR Data Bit 7 ATDTEST1.SAR6 4 SAR Data Bit 6 ATDTEST1.SAR5 3 SAR Data Bit 5 ATDTEST1.SAR4 2 SAR Data Bit 4 ATDTEST1.SAR3 1 SAR Data Bit 3 ATDTEST1.SAR2 0 SAR Data Bit 2 ATDTEST2 0x0069 ATD Test Register 2 ATDTEST2.SAR1 7 SAR Data Bit 1 ATDTEST2.SAR0 6 SAR Data Bit 0 ATDTEST2.RST 5 Reset Bit ATDTEST2.TSTOUT 4 Multiplex Output of TST3-TST0 (factory use) ATDTEST2.TST3 3 Test Bit 3 ATDTEST2.TST2 2 Test Bit 2 ATDTEST2.TST1 1 Test Bit 1 ATDTEST2.TST0 0 Test Bit 0 RESERVED006A 0x006A RESERVED RESERVED006B 0x006B RESERVED RESERVED006C 0x006C RESERVED RESERVED006D 0x006D RESERVED RESERVED006E 0x006E RESERVED PORTAD 0x006F Port AD Data Input Register PORTAD.PAD7 7 Port AD Data Input Bit 7 PORTAD.PAD6 6 Port AD Data Input Bit 6 PORTAD.PAD5 5 Port AD Data Input Bit 5 PORTAD.PAD4 4 Port AD Data Input Bit 4 PORTAD.PAD3 3 Port AD Data Input Bit 3 PORTAD.PAD2 2 Port AD Data Input Bit 2 PORTAD.PAD1 1 Port AD Data Input Bit 1 PORTAD.PAD0 0 Port AD Data Input Bit 0 ADR0H 0x0070 ATD Result Register 0 ADR0H.ADRxH7 7 ATD Conversion Result Bit 7 ADR0H.ADRxH6 6 ATD Conversion Result Bit 6 ADR0H.ADRxH5 5 ATD Conversion Result Bit 5 ADR0H.ADRxH4 4 ATD Conversion Result Bit 4 ADR0H.ADRxH3 3 ATD Conversion Result Bit 3 ADR0H.ADRxH2 2 ATD Conversion Result Bit 2 ADR0H.ADRxH1 1 ATD Conversion Result Bit 1 ADR0H.ADRxH0 0 ATD Conversion Result Bit 0 RESERVED0071 0x0071 RESERVED ADR1H 0x0072 ATD Result Register 1 ADR1H.ADRxH7 7 ATD Conversion Result Bit 7 ADR1H.ADRxH6 6 ATD Conversion Result Bit 6 ADR1H.ADRxH5 5 ATD Conversion Result Bit 5 ADR1H.ADRxH4 4 ATD Conversion Result Bit 4 ADR1H.ADRxH3 3 ATD Conversion Result Bit 3 ADR1H.ADRxH2 2 ATD Conversion Result Bit 2 ADR1H.ADRxH1 1 ATD Conversion Result Bit 1 ADR1H.ADRxH0 0 ATD Conversion Result Bit 0 RESERVED0073 0x0073 RESERVED ADR2H 0x0074 ATD Result Register 2 ADR2H.ADRxH7 7 ATD Conversion Result Bit 7 ADR2H.ADRxH6 6 ATD Conversion Result Bit 6 ADR2H.ADRxH5 5 ATD Conversion Result Bit 5 ADR2H.ADRxH4 4 ATD Conversion Result Bit 4 ADR2H.ADRxH3 3 ATD Conversion Result Bit 3 ADR2H.ADRxH2 2 ATD Conversion Result Bit 2 ADR2H.ADRxH1 1 ATD Conversion Result Bit 1 ADR2H.ADRxH0 0 ATD Conversion Result Bit 0 RESERVED0075 0x0075 RESERVED ADR3H 0x0076 ATD Result Register 3 ADR3H.ADRxH7 7 ATD Conversion Result Bit 7 ADR3H.ADRxH6 6 ATD Conversion Result Bit 6 ADR3H.ADRxH5 5 ATD Conversion Result Bit 5 ADR3H.ADRxH4 4 ATD Conversion Result Bit 4 ADR3H.ADRxH3 3 ATD Conversion Result Bit 3 ADR3H.ADRxH2 2 ATD Conversion Result Bit 2 ADR3H.ADRxH1 1 ATD Conversion Result Bit 1 ADR3H.ADRxH0 0 ATD Conversion Result Bit 0 RESERVED0077 0x0077 RESERVED ADR4H 0x0078 ATD Result Register 4 ADR4H.ADRxH7 7 ATD Conversion Result Bit 7 ADR4H.ADRxH6 6 ATD Conversion Result Bit 6 ADR4H.ADRxH5 5 ATD Conversion Result Bit 5 ADR4H.ADRxH4 4 ATD Conversion Result Bit 4 ADR4H.ADRxH3 3 ATD Conversion Result Bit 3 ADR4H.ADRxH2 2 ATD Conversion Result Bit 2 ADR4H.ADRxH1 1 ATD Conversion Result Bit 1 ADR4H.ADRxH0 0 ATD Conversion Result Bit 0 RESERVED0079 0x0079 RESERVED ADR5H 0x007A ATD Result Register 5 ADR5H.ADRxH7 7 ATD Conversion Result Bit 7 ADR5H.ADRxH6 6 ATD Conversion Result Bit 6 ADR5H.ADRxH5 5 ATD Conversion Result Bit 5 ADR5H.ADRxH4 4 ATD Conversion Result Bit 4 ADR5H.ADRxH3 3 ATD Conversion Result Bit 3 ADR5H.ADRxH2 2 ATD Conversion Result Bit 2 ADR5H.ADRxH1 1 ATD Conversion Result Bit 1 ADR5H.ADRxH0 0 ATD Conversion Result Bit 0 RESERVED007B 0x007B RESERVED ADR6H 0x007C ATD Result Register 6 ADR6H.ADRxH7 7 ATD Conversion Result Bit 7 ADR6H.ADRxH6 6 ATD Conversion Result Bit 6 ADR6H.ADRxH5 5 ATD Conversion Result Bit 5 ADR6H.ADRxH4 4 ATD Conversion Result Bit 4 ADR6H.ADRxH3 3 ATD Conversion Result Bit 3 ADR6H.ADRxH2 2 ATD Conversion Result Bit 2 ADR6H.ADRxH1 1 ATD Conversion Result Bit 1 ADR6H.ADRxH0 0 ATD Conversion Result Bit 0 RESERVED007D 0x007D RESERVED ADR7H 0x007E ATD Result Register 7 ADR7H.ADRxH7 7 ATD Conversion Result Bit 7 ADR7H.ADRxH6 6 ATD Conversion Result Bit 6 ADR7H.ADRxH5 5 ATD Conversion Result Bit 5 ADR7H.ADRxH4 4 ATD Conversion Result Bit 4 ADR7H.ADRxH3 3 ATD Conversion Result Bit 3 ADR7H.ADRxH2 2 ATD Conversion Result Bit 2 ADR7H.ADRxH1 1 ATD Conversion Result Bit 1 ADR7H.ADRxH0 0 ATD Conversion Result Bit 0 RESERVED007F 0x007F RESERVED TIOS 0x0080 Timer IC/OC Select Register TIOS.IOS7 7 Input Capture or Output Compare Select Bit 7 TIOS.IOS6 6 Input Capture or Output Compare Select Bit 6 TIOS.IOS5 5 Input Capture or Output Compare Select Bit 5 TIOS.IOS4 4 Input Capture or Output Compare Select Bit 4 TIOS.IOS3 3 Input Capture or Output Compare Select Bit 3 TIOS.IOS2 2 Input Capture or Output Compare Select Bit 2 TIOS.IOS1 1 Input Capture or Output Compare Select Bit 1 TIOS.IOS0 0 Input Capture or Output Compare Select Bit 0 CFORC 0x0081 Timer Compare Force Register CFORC.FOC7 7 Force Output Compare Bit 7 CFORC.FOC6 6 Force Output Compare Bit 6 CFORC.FOC5 5 Force Output Compare Bit 5 CFORC.FOC4 4 Force Output Compare Bit 4 CFORC.FOC3 3 Force Output Compare Bit 3 CFORC.FOC2 2 Force Output Compare Bit 2 CFORC.FOC1 1 Force Output Compare Bit 1 CFORC.FOC0 0 Force Output Compare Bit 0 OC7M 0x0082 Timer Output Compare 7 Mask Register OC7M.OC7M7 7 Output Compare 7 Mask Bit 7 OC7M.OC7M6 6 Output Compare 7 Mask Bit 6 OC7M.OC7M5 5 Output Compare 7 Mask Bit 5 OC7M.OC7M4 4 Output Compare 7 Mask Bit 4 OC7M.OC7M3 3 Output Compare 7 Mask Bit 3 OC7M.OC7M2 2 Output Compare 7 Mask Bit 2 OC7M.OC7M1 1 Output Compare 7 Mask Bit 1 OC7M.OC7M0 0 Output Compare 7 Mask Bit 0 OC7D 0x0083 Timer Output Compare 7 Data Register OC7D.OC7D7 7 Output Compare Data Bit 7 OC7D.OC7D6 6 Output Compare Data Bit 6 OC7D.OC7D5 5 Output Compare Data Bit 5 OC7D.OC7D4 4 Output Compare Data Bit 4 OC7D.OC7D3 3 Output Compare Data Bit 3 OC7D.OC7D2 2 Output Compare Data Bit 2 OC7D.OC7D1 1 Output Compare Data Bit 1 OC7D.OC7D0 0 Output Compare Data Bit 0 TCNTH 0x0084 Timer Counter Register High TCNTL 0x0085 Timer Counter Register Low TSCR 0x0086 Timer System Control Register TSCR.TEN 7 Timer Enable Bit TSCR.TSWAI 6 Timer Stop in Wait Mode Bit TSCR.TSBCK 5 Timer Stop in Background Mode Bit TSCR.TFFCA 4 Timer Fast Flag Clear-All Bit RESERVED0087 0x0087 RESERVED TCTL1 0x0088 Timer Control Register 1 TCTL1.OM7 7 Output Mode Bit 7 TCTL1.OL7 6 Output Level Bit 7 TCTL1.OM6 5 Output Mode Bit 6 TCTL1.OL6 4 Output Level Bit 6 TCTL1.OM5 3 Output Mode Bit 5 TCTL1.OL5 2 Output Level Bit 5 TCTL1.OM4 1 Output Mode Bit 4 TCTL1.OL4 0 Output Level Bit 4 TCTL2 0x0089 Timer Control Register 2 TCTL2.OM3 7 Output Mode Bit 3 TCTL2.OL3 6 Output Level Bit 3 TCTL2.OM2 5 Output Mode Bit 2 TCTL2.OL2 4 Output Level Bit 2 TCTL2.OM1 3 Output Mode Bit 1 TCTL2.OL1 2 Output Level Bit 1 TCTL2.OM0 1 Output Mode Bit 0 TCTL2.OL0 0 Output Level Bit 0 TCTL3 0x008A Timer Control Register 3 TCTL3.EDG7B 7 Input Capture Edge Control Bit 7B TCTL3.EDG7A 6 Input Capture Edge Control Bit 7A TCTL3.EDG6B 5 Input Capture Edge Control Bit 6B TCTL3.EDG6A 4 Input Capture Edge Control Bit 6A TCTL3.EDG5B 3 Input Capture Edge Control Bit 5B TCTL3.EDG5A 2 Input Capture Edge Control Bit 5A TCTL3.EDG4B 1 Input Capture Edge Control Bit 4B TCTL3.EDG4A 0 Input Capture Edge Control Bit 4A TCTL4 0x008B Timer Control Register 4 TCTL4.EDG3B 7 Input Capture Edge Control Bit 3B TCTL4.EDG3A 6 Input Capture Edge Control Bit 3A TCTL4.EDG2B 5 Input Capture Edge Control Bit 2B TCTL4.EDG2A 4 Input Capture Edge Control Bit 2A TCTL4.EDG1B 3 Input Capture Edge Control Bit 1B TCTL4.EDG1A 2 Input Capture Edge Control Bit 1A TCTL4.EDG0B 1 Input Capture Edge Control Bit 0B TCTL4.EDG0A 0 Input Capture Edge Control Bit 0A TMSK1 0x008C Timer Mask Register 1 TMSK1.C7I 7 Channel Interrupt Enable Bit 7 TMSK1.C6I 6 Channel Interrupt Enable Bit 6 TMSK1.C5I 5 Channel Interrupt Enable Bit 5 TMSK1.C4I 4 Channel Interrupt Enable Bit 4 TMSK1.C3I 3 Channel Interrupt Enable Bit 3 TMSK1.C2I 2 Channel Interrupt Enable Bit 2 TMSK1.C1I 1 Channel Interrupt Enable Bit 1 TMSK1.C0I 0 Channel Interrupt Enable Bit 0 TMSK2 0x008D Timer Mask Register 2 TMSK2.TOI 7 Timer Overflow Interrupt Enable Bit TMSK2.PUPT 5 Port T Pullup Enable Bit TMSK2.RDPT 4 Port T Reduced Drive Bit TMSK2.TCRE 3 Timer Counter Reset Enable Bit TMSK2.PR2 2 Timer Prescaler Select Bit 2 TMSK2.PR1 1 Timer Prescaler Select Bit 1 TMSK2.PR0 0 Timer Prescaler Select Bit 0 TFLG1 0x008E Timer Flag Register 1 TFLG1.C7F 7 Channel Flag 7 TFLG1.C6F 6 Channel Flag 6 TFLG1.C5F 5 Channel Flag 5 TFLG1.C4F 4 Channel Flag 4 TFLG1.C3F 3 Channel Flag 3 TFLG1.C2F 2 Channel Flag 2 TFLG1.C1F 1 Channel Flag 1 TFLG1.C0F 0 Channel Flag 0 TFLG2 0x008F Timer Flag Register 2 TFLG2.TOF 7 Timer Overflow Flag TC0H 0x0090 Timer Channel 0 Register High TC0L 0x0091 Timer Channel 0 Register Low TC1H 0x0092 Timer Channel 1 Register High TC1L 0x0093 Timer Channel 1 Register Low TC2H 0x0094 Timer Channel 2 Register High TC2L 0x0095 Timer Channel 2 Register Low TC3H 0x0096 Timer Channel 3 Register High TC3L 0x0097 Timer Channel 3 Register Low TC4H 0x0098 Timer Channel 4 Register High TC4L 0x0099 Timer Channel 4 Register Low TC5H 0x009A Timer Channel 5 Register High TC5L 0x009B Timer Channel 5 Register Low TC6H 0x009C Timer Channel 6 Register High TC6L 0x009D Timer Channel 6 Register Low TC7H 0x009E Timer Channel 7 Register High TC7L 0x009F Timer Channel 7 Register Low PACTL 0x00A0 Pulse Accumulator Control Register PACTL.PAEN 6 Pulse Accumulator Enable Bit PACTL.PAMOD 5 Pulse Accumulator Mode Bit PACTL.PEDGE 4 Pulse Accumulator Edge Bit PACTL.CLK1 3 Clock Select Bit 1 PACTL.CLK0 2 Clock Select Bit 0 PACTL.PAOVI 1 Pulse Accumulator Overflow Interrupt Enable Bit PACTL.PAI 0 Pulse Accumulator Interrupt Enable Bit PAFLG 0x00A1 Pulse Accumulator Flag Register PAFLG.PAOVF 1 Pulse Accumulator Overflow Flag PAFLG.PAIF 0 Pulse Accumulator Input Flag PACNTH 0x00A2 Pulse Accumulator Counter Register High PACNTL 0x00A3 Pulse Accumulator Counter Register Low RESERVED00A4 0x00A4 RESERVED RESERVED00A5 0x00A5 RESERVED RESERVED00A6 0x00A6 RESERVED RESERVED00A7 0x00A7 RESERVED RESERVED00A8 0x00A8 RESERVED RESERVED00A9 0x00A9 RESERVED RESERVED00AA 0x00AA RESERVED RESERVED00AB 0x00AB RESERVED RESERVED00AC 0x00AC RESERVED TIMTST 0x00AD Timer Test Register TIMTST.TCBYP 1 Timer Divider Chain Bypass Bit TIMTST.PCBYP 0 Pulse Accumulator Divider Chain Bypass Bit PORTT 0x00AE Timer Port Data Register PORTT.PT7 7 Timer Port Data Bit 7 PORTT.PT6 6 Timer Port Data Bit 6 PORTT.PT5 5 Timer Port Data Bit 5 PORTT.PT4 4 Timer Port Data Bit 4 PORTT.PT3 3 Timer Port Data Bit 3 PORTT.PT2 2 Timer Port Data Bit 2 PORTT.PT1 1 Timer Port Data Bit 1 PORTT.PT0 0 Timer Port Data Bit 0 DDRT 0x00AF Timer Port Data Direction Register DDRT.DDRT7 7 TIMPORT Data Direction Bit 7 DDRT.DDRT6 6 TIMPORT Data Direction Bit 6 DDRT.DDRT5 5 TIMPORT Data Direction Bit 5 DDRT.DDRT4 4 TIMPORT Data Direction Bit 4 DDRT.DDRT3 3 TIMPORT Data Direction Bit 3 DDRT.DDRT2 2 TIMPORT Data Direction Bit 2 DDRT.DDRT1 1 TIMPORT Data Direction Bit 1 DDRT.DDRT0 0 TIMPORT Data Direction Bit 0 RESERVED00B0 0x00B0 RESERVED RESERVED00B1 0x00B1 RESERVED RESERVED00B2 0x00B2 RESERVED RESERVED00B3 0x00B3 RESERVED RESERVED00B4 0x00B4 RESERVED RESERVED00B5 0x00B5 RESERVED RESERVED00B6 0x00B6 RESERVED RESERVED00B7 0x00B7 RESERVED RESERVED00B8 0x00B8 RESERVED RESERVED00B9 0x00B9 RESERVED RESERVED00BA 0x00BA RESERVED RESERVED00BB 0x00BB RESERVED RESERVED00BC 0x00BC RESERVED RESERVED00BD 0x00BD RESERVED RESERVED00BE 0x00BE RESERVED RESERVED00BF 0x00BF RESERVED SC0BDH 0x00C0 SCI 0 Baud Rate Register High SC0BDH.BTST 7 Reserved for test function SC0BDH.BSPL 6 Reserved for test function SC0BDH.BRLD 5 Reserved for test function SC0BDH.SBR12 4 SCI Baud Rate Bit 12 SC0BDH.SBR11 3 SCI Baud Rate Bit 11 SC0BDH.SBR10 2 SCI Baud Rate Bit 10 SC0BDH.SBR9 1 SCI Baud Rate Bit 9 SC0BDH.SBR8 0 SCI Baud Rate Bit 8 SC0BDL 0x00C1 SCI 0 Baud Rate Register Low SC0BDL.SBR7 7 SCI Baud Rate Bit 7 SC0BDL.SBR6 6 SCI Baud Rate Bit 6 SC0BDL.SBR5 5 SCI Baud Rate Bit 5 SC0BDL.SBR4 4 SCI Baud Rate Bit 4 SC0BDL.SBR3 3 SCI Baud Rate Bit 3 SC0BDL.SBR2 2 SCI Baud Rate Bit 2 SC0BDL.SBR1 1 SCI Baud Rate Bit 1 SC0BDL.SBR0 0 SCI Baud Rate Bit 0 SC0CR1 0x00C2 SCI 0 Control Register 1 SC0CR1.LOOPS 7 Loop Select Bit SC0CR1.WOMS 6 Wired-OR Mode Select Bit SC0CR1.RSRC 5 Receiver Source Bit SC0CR1.M 4 Mode Bit SC0CR1.WAKE 3 Wakeup Bit SC0CR1.ILT 2 Idle Line Type Bit SC0CR1.PE 1 Parity Enable Bit SC0CR1.PT 0 Parity Type Bit SC0CR2 0x00C3 SCI 0 Control Register 2 SC0CR2.TIE 7 Transmitter Interrupt Enable Bit SC0CR2.TCIE 6 Transmission Complete Interrupt Enable Bit SC0CR2.RIE 5 Receiver Interrupt Enable Bit SC0CR2.ILIE 4 Idle Line Interrupt Enable Bit SC0CR2.TE 3 Transmitter Enable Bit SC0CR2.RE 2 Receiver Enable Bit SC0CR2.RWU 1 Receiver Wakeup Bit SC0CR2.SBK 0 Send Break Bit SC0SR1 0x00C4 SCI 0 Status Register 1 SC0SR1.TDRE 7 Transmit Data Register Empty Flag SC0SR1.TC 6 Transmission Complete Flag SC0SR1.RDRF 5 Receive Data Register Full Flag SC0SR1.IDLE 4 Idle Line Flag SC0SR1.OR 3 Overrun Flag SC0SR1.NF 2 Noise Flag SC0SR1.FE 1 Framing Error Flag SC0SR1.PF 0 Parity Error Flag SC0SR2 0x00C5 SCI 0 Status Register 2 SC0SR2.RAF 0 Receiver Active Flag SC0DRH 0x00C6 SCI 0 Data Register High SC0DRH.R8 7 Received Bit 8 SC0DRH.T8 6 Transmitted Bit 8 SC0DRL 0x00C7 SCI 0 Data Register Low SC0DRL.R7_T7 7 Received/Transmitted Bit 7 SC0DRL.R6_T6 6 Received/Transmitted Bit 6 SC0DRL.R5_T5 5 Received/Transmitted Bit 5 SC0DRL.R4_T4 4 Received/Transmitted Bit 4 SC0DRL.R3_T3 3 Received/Transmitted Bit 3 SC0DRL.R2_T2 2 Received/Transmitted Bit 2 SC0DRL.R1_T1 1 Received/Transmitted Bit 1 SC0DRL.R0_T0 0 Received/Transmitted Bit 0 SC1BDH 0x00C8 SCI 1 Baud Rate Register High SC1BDH.BTST 7 Reserved for test function SC1BDH.BSPL 6 Reserved for test function SC1BDH.BRLD 5 Reserved for test function SC1BDH.SBR12 4 SCI Baud Rate Bit 12 SC1BDH.SBR11 3 SCI Baud Rate Bit 11 SC1BDH.SBR10 2 SCI Baud Rate Bit 10 SC1BDH.SBR9 1 SCI Baud Rate Bit 9 SC1BDH.SBR8 0 SCI Baud Rate Bit 8 SC1BDL 0x00C9 SCI 1 Baud Rate Register Low SC1BDL.SBR7 7 SCI Baud Rate Bit 7 SC1BDL.SBR6 6 SCI Baud Rate Bit 6 SC1BDL.SBR5 5 SCI Baud Rate Bit 5 SC1BDL.SBR4 4 SCI Baud Rate Bit 4 SC1BDL.SBR3 3 SCI Baud Rate Bit 3 SC1BDL.SBR2 2 SCI Baud Rate Bit 2 SC1BDL.SBR1 1 SCI Baud Rate Bit 1 SC1BDL.SBR0 0 SCI Baud Rate Bit 0 SC1CR1 0x00CA SCI 1 Control Register 1 SC1CR1.LOOPS 7 Loop Select Bit SC1CR1.WOMS 6 Wired-OR Mode Select Bit SC1CR1.RSRC 5 Receiver Source Bit SC1CR1.M 4 Mode Bit SC1CR1.WAKE 3 Wakeup Bit SC1CR1.ILT 2 Idle Line Type Bit SC1CR1.PE 1 Parity Enable Bit SC1CR1.PT 0 Parity Type Bit SC1CR2 0x00CB SCI 1 Control Register 2 SC1CR2.TIE 7 Transmitter Interrupt Enable Bit SC1CR2.TCIE 6 Transmission Complete Interrupt Enable Bit SC1CR2.RIE 5 Receiver Interrupt Enable Bit SC1CR2.ILIE 4 Idle Line Interrupt Enable Bit SC1CR2.TE 3 Transmitter Enable Bit SC1CR2.RE 2 Receiver Enable Bit SC1CR2.RWU 1 Receiver Wakeup Bit SC1CR2.SBK 0 Send Break Bit SC1SR1 0x00CC SCI 1 Status Register 1 SC1SR1.TDRE 7 Transmit Data Register Empty Flag SC1SR1.TC 6 Transmission Complete Flag SC1SR1.RDRF 5 Receive Data Register Full Flag SC1SR1.IDLE 4 Idle Line Flag SC1SR1.OR 3 Overrun Flag SC1SR1.NF 2 Noise Flag SC1SR1.FE 1 Framing Error Flag SC1SR1.PF 0 Parity Error Flag SC1SR2 0x00CD SCI 1 Status Register 2 SC1SR2.RAF 0 Receiver Active Flag SC1DRH 0x00CE SCI 1 Data Register High SC1DRH.R8 7 Received Bit 8 SC1DRH.T8 6 Transmitted Bit 8 SC1DRL 0x00CF SCI 1 Data Register Low SC1DRL.R7_T7 7 Received/Transmitted Bit 7 SC1DRL.R6_T6 6 Received/Transmitted Bit 6 SC1DRL.R5_T5 5 Received/Transmitted Bit 5 SC1DRL.R4_T4 4 Received/Transmitted Bit 4 SC1DRL.R3_T3 3 Received/Transmitted Bit 3 SC1DRL.R2_T2 2 Received/Transmitted Bit 2 SC1DRL.R1_T1 1 Received/Transmitted Bit 1 SC1DRL.R0_T0 0 Received/Transmitted Bit 0 SP0CR1 0x00D0 SPI 0 Control Register 1 SP0CR1.SPIE 7 SPI Interrupt Enable Bit SP0CR1.SPE 6 SPI Enable Bit SP0CR1.SWOM 5 Port S Wired-OR Mode Bit SP0CR1.MSTR 4 Master Mode Bit SP0CR1.CPOL 3 Clock Polarity Bit SP0CR1.CPHA 2 Clock Phase Bit SP0CR1.SSOE 1 Slave Select Output Enable Bit SP0CR1.LSBF 0 LSB First Bit SP0CR2 0x00D1 SPI 0 Control Register 2 SP0CR2.PUPS 3 Pullup Port S Bit SP0CR2.RDS 2 Reduced Drive Port S Bit SP0CR2.SPC0 0 Serial Pin Control Bit 0 SP0BR 0x00D2 SPI Baud Rate Register SP0BR.SPR2 2 SPI Clock Rate Select Bit 2 SP0BR.SPR1 1 SPI Clock Rate Select Bit 1 SP0BR.SPR0 0 SPI Clock Rate Select Bit 0 SP0SR 0x00D3 SPI Status Register SP0SR.SPIF 7 SPI Flag SP0SR.WCOL 6 Write Collision Flag SP0SR.MODF 4 Mode Fault Flag RESERVED00D4 0x00D4 RESERVED SP0DR 0x00D5 SPI Data Register PORTS 0x00D6 Port S Data Register PORTS.PS7 7 Port S Data Bit 7 PORTS.PS6 6 Port S Data Bit 6 PORTS.PS5 5 Port S Data Bit 5 PORTS.PS4 4 Port S Data Bit 4 PORTS.PS3 3 Port S Data Bit 3 PORTS.PS2 2 Port S Data Bit 2 PORTS.PS1 1 Port S Data Bit 1 PORTS.PS0 0 Port S Data Bit 0 DDRS 0x00D7 Port S Data Direction Register DDRS.DDRS7 7 Port S Data Direction Bit 7 DDRS.DDRS6 6 Port S Data Direction Bit 6 DDRS.DDRS5 5 Port S Data Direction Bit 5 DDRS.DDRS4 4 Port S Data Direction Bit 4 DDRS.DDRS3 3 Port S Data Direction Bit 3 DDRS.DDRS2 2 Port S Data Direction Bit 2 DDRS.DDRS1 1 Port S Data Direction Bit 1 DDRS.DDRS0 0 Port S Data Direction Bit 0 RESERVED00D8 0x00D8 RESERVED RESERVED00D9 0x00D9 RESERVED RESERVED00DA 0x00DA RESERVED RESERVED00DB 0x00DB RESERVED RESERVED00DC 0x00DC RESERVED RESERVED00DD 0x00DD RESERVED RESERVED00DE 0x00DE RESERVED RESERVED00DF 0x00DF RESERVED RESERVED00E0 0x00E0 RESERVED RESERVED00E1 0x00E1 RESERVED RESERVED00E2 0x00E2 RESERVED RESERVED00E3 0x00E3 RESERVED RESERVED00E4 0x00E4 RESERVED RESERVED00E5 0x00E5 RESERVED RESERVED00E6 0x00E6 RESERVED RESERVED00E7 0x00E7 RESERVED RESERVED00E8 0x00E8 RESERVED RESERVED00E9 0x00E9 RESERVED RESERVED00EA 0x00EA RESERVED RESERVED00EB 0x00EB RESERVED RESERVED00EC 0x00EC RESERVED RESERVED00ED 0x00ED RESERVED RESERVED00EE 0x00EE RESERVED RESERVED00EF 0x00EF RESERVED EEMCR 0x00F0 EEPROM Configuration Register EEMCR.EESWAI 2 EEPROM Stops in Wait Mode Bit EEMCR.PROTLCK 1 Block Protect Write Lock Bit EEMCR.EERC 0 EEPROM Charge Pump Clock Bit EEPROT 0x00F1 EEPROM Block Protect Register EEPROT.BPROT6 6 EEPROM Block Protection Bit 6 EEPROT.BPROT5 5 EEPROM Block Protection Bit 5 EEPROT.BPROT4 4 EEPROM Block Protection Bit 4 EEPROT.BPROT3 3 EEPROM Block Protection Bit 3 EEPROT.BPROT2 2 EEPROM Block Protection Bit 2 EEPROT.BPROT1 1 EEPROM Block Protection Bit 1 EEPROT.BPROT0 0 EEPROM Block Protection Bit 0 EETST 0x00F2 EEPROM Test Register EETST.EEODD 7 Odd Row Programming Bit EETST.EEVEN 6 Even Row Programming Bit EETST.MARG 5 Program and Erase Voltage Margin Test Enable Bit EETST.EECPD 4 Charge Pump Disable Bit EETST.EECPRD 3 Charge Pump Ramp Disable Bit EETST.EECPM 1 Charge Pump Monitor Enable Bit EEPROG 0x00F3 EEPROM Programming Register EEPROG.BULKP 7 Bulk Erase Protection Bit EEPROG.BYTE 4 Byte and Aligned Word Erase Bit EEPROG.ROW 3 Row or Bulk Erase Bit EEPROG.ERASE 2 Erase Control Bit EEPROG.EELAT 1 EEPROM Latch Control Bit EEPROG.EEPGM 0 Program and Erase Enable Bit .68HC912D60 ; ; MC68HC912D60.pdf ; MEMORY MAP area DATA FSR0 0x0000:0x0140 area DATA R_BUFFER 0x0140:0x0150 RECEIVE BUFFER area DATA T_BUFFER0 0x0150:0x0160 TRANSMIT BUFFER 0 area DATA T_BUFFER1 0x0160:0x0170 TRANSMIT BUFFER 1 area DATA T_BUFFER2 0x0170:0x0180 TRANSMIT BUFFER 2 area BSS RESERVED 0x0180:0x01E1 area DATA FSR1 0x01E1:0x0200 area DATA RAM 0x0200:0x0800 area BSS RESERVED 0x0800:0x0C00 area DATA EEPROM_1 0x0C00:0x1000 area DATA EEPROM_2 0x1000:0x8000 area DATA EEPROM_3 0x8000:0xFF00 area DATA USER_VEC 0xFF00:0x10000 ; Interrupt and reset vector assignments interrupt __RESET 0xFFFE Reset interrupt _COPCTL 0xFFFC Clock monitor fail reset interrupt COP_FR 0xFFFA COP failure reset interrupt UIT 0xFFF8 Unimplemented instruction trap interrupt SWI 0xFFF6 SWI interrupt XIRQ 0xFFF4 XIRQ interrupt _INTCR_IRQEN 0xFFF2 IRQ interrupt RTICTL_RTIE 0xFFF0 Real time interrupt interrupt TMSK1_C0I 0xFFEE Timer channel 0 interrupt TMSK1_C1I 0xFFEC Timer channel 1 interrupt TMSK1_C2I 0xFFEA Timer channel 2 interrupt TMSK1_C3I 0xFFE8 Timer channel 3 interrupt TMSK1_C4I 0xFFE6 Timer channel 4 interrupt TMSK1_C5I 0xFFE4 Timer channel 5 interrupt TMSK1_C6I 0xFFE2 Timer channel 6 interrupt TMSK1_C7I 0xFFE0 Timer channel 7 interrupt TMSK2_TOI 0xFFDE Timer overflow interrupt PACTL_PAOVI 0xFFDC Pulse accumulator overflow interrupt PACTL_PAI 0xFFDA Pulse accumulator input edge interrupt SP0CR1_SPIE 0xFFD8 SPI serial transfer complete interrupt _SC0CR2 0xFFD6 SCI 0 interrupt _SC1CR2 0xFFD4 SCI 1 interrupt ATDxCTL2_ASCIE 0xFFD2 ATD0 or ATD1 interrupt CRIER_WUPIE 0xFFD0 MSCAN wake-up interrupt KWIEG_KWIEH 0xFFCE Key wake-up G or H interrupt MCCTL_MCZI 0xFFCC Modulus down counter underflow interrupt PBCTL_PBOVI 0xFFCA Pulse Accumulator B Overflow interrupt CRIER_ERR 0xFFC8 MSCAN errors interrupt CRIER_RXFIE 0xFFC6 MSCAN receive interrupt CTCR_TXEIE 0xFFC4 MSCAN transmit interrupt _PLLCR_LOCKIE_LHIE 0xFFC2 CGM lock and limp home ; INPUT/ OUTPUT PORTS PORTA 0x0000 Port A Data Register PORTA.PA7 7 Port A Data Bit 7 PORTA.PA6 6 Port A Data Bit 6 PORTA.PA5 5 Port A Data Bit 5 PORTA.PA4 4 Port A Data Bit 4 PORTA.PA3 3 Port A Data Bit 3 PORTA.PA2 2 Port A Data Bit 2 PORTA.PA1 1 Port A Data Bit 1 PORTA.PA0 0 Port A Data Bit 0 PORTB 0x0001 Port B Data Register PORTB.PB7 7 Port B Data Bit 7 PORTB.PB6 6 Port B Data Bit 6 PORTB.PB5 5 Port B Data Bit 5 PORTB.PB4 4 Port B Data Bit 4 PORTB.PB3 3 Port B Data Bit 3 PORTB.PB2 2 Port B Data Bit 2 PORTB.PB1 1 Port B Data Bit 1 PORTB.PB0 0 Port B Data Bit 0 DDRA 0x0002 Port A Data Direction Register DDRA.DDA7 7 Port A Data Direction Bit 7 DDRA.DDA6 6 Port A Data Direction Bit 6 DDRA.DDA5 5 Port A Data Direction Bit 5 DDRA.DDA4 4 Port A Data Direction Bit 4 DDRA.DDA3 3 Port A Data Direction Bit 3 DDRA.DDA2 2 Port A Data Direction Bit 2 DDRA.DDA1 1 Port A Data Direction Bit 1 DDRA.DDA0 0 Port A Data Direction Bit 0 DDRB 0x0003 Port B Data Direction Register DDRB.DDB7 7 Port B Data Direction Bit 7 DDRB.DDB6 6 Port B Data Direction Bit 6 DDRB.DDB5 5 Port B Data Direction Bit 5 DDRB.DDB4 4 Port B Data Direction Bit 4 DDRB.DDB3 3 Port B Data Direction Bit 3 DDRB.DDB2 2 Port B Data Direction Bit 2 DDRB.DDB1 1 Port B Data Direction Bit 1 DDRB.DDB0 0 Port B Data Direction Bit 0 RESERVED0004 0x0004 RESERVED RESERVED0005 0x0005 RESERVED RESERVED0006 0x0006 RESERVED RESERVED0007 0x0007 RESERVED PORTE 0x0008 Port E Data Register PORTE.PE7 7 Port E Data Bit 7 PORTE.PE6 6 Port E Data Bit 6 PORTE.PE5 5 Port E Data Bit 5 PORTE.PE4 4 Port E Data Bit 4 PORTE.PE3 3 Port E Data Bit 3 PORTE.PE2 2 Port E Data Bit 2 PORTE.PE1 1 Port E Data Bit 1 PORTE.PE0 0 Port E Data Bit 0 DDRE 0x0009 Port E Data Direction Register DDRE.DDE7 7 Port E Data Direction Bit 7 DDRE.DDE6 6 Port E Data Direction Bit 6 DDRE.DDE5 5 Port E Data Direction Bit 5 DDRE.DDE4 4 Port E Data Direction Bit 4 DDRE.DDE3 3 Port E Data Direction Bit 3 DDRE.DDE2 2 Port E Data Direction Bit 2 PEAR 0x000A Port E Assignment Register PEAR.NDBE 7 No Data Bus Enable PEAR.CGMTE 6 Clock Generator Module Testing Enable PEAR.PIPOE 5 Pipe Status Signal Output Enable PEAR.NECLK 4 No External E Clock PEAR.LSTRE 3 Low Strobe (LSTRB) Enable PEAR.RDWE 2 Read/Write Enable PEAR.CALE 1 Calibration Reference Enable PEAR.DBENE 0 DBE or Inverted E Clock on Port E MODE 0x000B Mode Register MODE.SMODN 7 Mode Select Special MODE.MODB 6 Mode Select B MODE.MODA 5 Mode Select A MODE.ESTR 4 E Clock Stretch Enable MODE.IVIS 3 Internal Visibility MODE.EBSWAI 2 External Bus Module Stop in Wait Control MODE.EME 0 Emulate Port E PUCR 0x000C Pull-Up Control Register PUCR.PUPH 7 Pull-Up or Pull-Down Port H Enable PUCR.PUPG 6 Pull-Up or Pull-Down Port G Enable PUCR.PUPE 4 Pull-Up Port E Enable PUCR.PUPB 1 Pull-Up Port B Enable PUCR.PUPA 0 Pull-Up Port A Enable RDRIV 0x000D Reduced Drive of I/O Lines RDRIV.RDPH 6 Reduced Drive of Port H RDRIV.RDPG 5 Reduced Drive of Port G RDRIV.RDPE 3 Reduced Drive of Port E RDRIV.RDPB 1 Reduced Drive of Port B RDRIV.RDPA 0 Reduced Drive of Port A RESERVED000E 0x000E RESERVED RESERVED000F 0x000F RESERVED INITRM 0x0010 Initialization of Internal RAM Position Register INITRM.RAM15 7 Internal RAM map position 15 INITRM.RAM14 6 Internal RAM map position 14 INITRM.RAM13 5 Internal RAM map position 13 INITRM.RAM12 4 Internal RAM map position 12 INITRM.RAM11 3 Internal RAM map position 11 INITRG 0x0011 Initialization of Internal Register Position Register INITRG.REG15 7 Internal register map position 15 INITRG.REG14 6 Internal register map position 14 INITRG.REG13 5 Internal register map position 13 INITRG.REG12 4 Internal register map position 12 INITRG.REG11 3 Internal register map position 11 INITRG.MMSWAI 0 Memory Mapping Interface Stop in Wait Control INITEE 0x0012 Initialization of Internal EEPROM Position Register INITEE.EE15 7 Internal EEPROM map position 15 INITEE.EE14 6 Internal EEPROM map position 14 INITEE.EE13 5 Internal EEPROM map position 13 INITEE.EE12 4 Internal EEPROM map position 12 INITEE.EEON 0 internal EEPROM On (Enabled) MISC 0x0013 Miscellaneous Mapping Control Register MISC.MAPROM 7 Map Location of ROM MISC.NDRF 6 Narrow Data Bus for Register-Following Map Space MISC.RFSTR1 5 Register Following Stretch 1 MISC.RFSTR0 4 Register Following Stretch 0 MISC.EXSTR1 3 External Access Stretch 1 MISC.EXSTR0 2 External Access Stretch 0 MISC.ROMON28 1 Enable bits for ROM 28 MISC.ROMON32 0 Enable bits for ROM 32 RTICTL 0x0014 Real-Time Interrupt Control Register RTICTL.RTIE 7 Real Time Interrupt Enable RTICTL.RSWAI 6 RTI and COP Stop While in Wait RTICTL.RSBCK 5 RTI and COP Stop While in Background Debug Mode RTICTL.RTBYP 3 Real Time Interrupt Divider Chain Bypass RTICTL.RTR2 2 Real-Time Interrupt Rate Select 2 RTICTL.RTR1 1 Real-Time Interrupt Rate Select 1 RTICTL.RTR0 0 Real-Time Interrupt Rate Select 0 RTIFLG 0x0015 Real Time Interrupt Flag Register RTIFLG.RTIF 7 Real Time Interrupt Flag COPCTL 0x0016 COP Control Register COPCTL.CME 7 Clock Monitor Enable COPCTL.FCME 6 Force Clock Monitor Enable COPCTL.FCMCOP 5 Force Clock Monitor Reset or COP Watchdog Reset COPCTL.WCOP 4 Window COP mode COPCTL.DISR 3 Disable Resets from COP Watchdog and Clock Monitor COPCTL.CR2 2 COP Watchdog Timer Rate select bit 2 COPCTL.CR1 1 COP Watchdog Timer Rate select bit 1 COPCTL.CR0 0 COP Watchdog Timer Rate select bit 0 COPRST 0x0017 Arm/Reset COP Timer Register RESERVED0018 0x0018 RESERVED RESERVED0019 0x0019 RESERVED RESERVED001A 0x001A RESERVED RESERVED001B 0x001B RESERVED RESERVED001C 0x001C RESERVED RESERVED001D 0x001D RESERVED INTCR 0x001E Interrupt Control Register INTCR.IRQE 7 IRQ Select Edge Sensitive Only INTCR.IRQEN 6 External IRQ Enable INTCR.DLY 5 Enable Oscillator Start-up Delay on Exit from STOP HPRIO 0x001F Highest Priority I Interrupt HPRIO.PSEL5 5 HPRIO.PSEL4 4 HPRIO.PSEL3 3 HPRIO.PSEL2 2 HPRIO.PSEL1 1 BRKCT0 0x0020 Breakpoint Control Register 0 BRKCT0.BKEN1 7 Breakpoint Mode Enable 1 BRKCT0.BKEN0 6 Breakpoint Mode Enable 0 BRKCT0.BKPM 5 Break on Program Addresses BRKCT0.BK1ALE 3 Breakpoint 1 Range Control BRKCT0.BK0ALE 2 Breakpoint 0 Range Control BRKCT1 0x0021 Breakpoint Control Register 1 BRKCT1.BKDBE 6 Enable Data Bus BRKCT1.BKMBH 5 Breakpoint Mask High BRKCT1.BKMBL 4 Breakpoint Mask Low BRKCT1.BK1RWE 3 R/W Compare Enable BRKCT1.BK1RW 2 R/W Compare Value BRKCT1.BK0RWE 1 R/W Compare Enable BRKCT1.BK0RW 0 R/W Compare Value BRKAH 0x0022 Breakpoint Address Register, High Byte BRKAL 0x0023 Breakpoint Address Register, Low Byte BRKDH 0x0024 Breakpoint Data Register, High Byte BRKDL 0x0025 Breakpoint Data Register, Low Byte RESERVED0026 0x0026 RESERVED RESERVED0027 0x0027 RESERVED PORTG 0x0028 Port G Data Register PORTG.PG7 7 Port G Data Bit 7 PORTG.PG6 6 Port G Data Bit 6 PORTG.PG5 5 Port G Data Bit 5 PORTG.PG4 4 Port G Data Bit 4 PORTG.PG3 3 Port G Data Bit 3 PORTG.PG2 2 Port G Data Bit 2 PORTG.PG1 1 Port G Data Bit 1 PORTG.PG0 0 Port G Data Bit 0 PORTH 0x0029 Port H Data Register PORTH.PH7 7 Port H Data Bit 7 PORTH.PH6 6 Port H Data Bit 6 PORTH.PH5 5 Port H Data Bit 5 PORTH.PH4 4 Port H Data Bit 4 PORTH.PH3 3 Port H Data Bit 3 PORTH.PH2 2 Port H Data Bit 2 PORTH.PH1 1 Port H Data Bit 1 PORTH.PH0 0 Port H Data Bit 0 DDRG 0x002A Port G Data Direction Register DDRG.DDG7 7 Port G Data Direction Bit 7 DDRG.DDG6 6 Port G Data Direction Bit 6 DDRG.DDG5 5 Port G Data Direction Bit 5 DDRG.DDG4 4 Port G Data Direction Bit 4 DDRG.DDG3 3 Port G Data Direction Bit 3 DDRG.DDG2 2 Port G Data Direction Bit 2 DDRG.DDG1 1 Port G Data Direction Bit 1 DDRG.DDG0 0 Port G Data Direction Bit 0 DDRH 0x002B Port H Data Direction Register DDRH.DDH7 7 Port H Data Direction Bit 7 DDRH.DDH6 6 Port H Data Direction Bit 6 DDRH.DDH5 5 Port H Data Direction Bit 5 DDRH.DDH4 4 Port H Data Direction Bit 4 DDRH.DDH3 3 Port H Data Direction Bit 3 DDRH.DDH2 2 Port H Data Direction Bit 2 DDRH.DDH1 1 Port H Data Direction Bit 1 DDRH.DDH0 0 Port H Data Direction Bit 0 KWIEG 0x002C Key Wake-up Port G Interrupt Enable Register KWIEG.WI2CE 7 Wake-up I2C Enable KWIEG.KWIEG6 6 Key Wake-up Port G Interrupt Enables 6 KWIEG.KWIEG5 5 Key Wake-up Port G Interrupt Enables 5 KWIEG.KWIEG4 4 Key Wake-up Port G Interrupt Enables 4 KWIEG.KWIEG3 3 Key Wake-up Port G Interrupt Enables 3 KWIEG.KWIEG2 2 Key Wake-up Port G Interrupt Enables 2 KWIEG.KWIEG1 1 Key Wake-up Port G Interrupt Enables 1 KWIEG.KWIEG0 0 Key Wake-up Port G Interrupt Enables 0 KWIEH 0x002D Key Wake-up Port H Interrupt Enable Register KWIEH.KWIEH7 7 Key Wake-up Port H Interrupt Enables 7 KWIEH.KWIEH6 6 Key Wake-up Port H Interrupt Enables 6 KWIEH.KWIEH5 5 Key Wake-up Port H Interrupt Enables 5 KWIEH.KWIEH4 4 Key Wake-up Port H Interrupt Enables 4 KWIEH.KWIEH3 3 Key Wake-up Port H Interrupt Enables 3 KWIEH.KWIEH2 2 Key Wake-up Port H Interrupt Enables 2 KWIEH.KWIEH1 1 Key Wake-up Port H Interrupt Enables 1 KWIEH.KWIEH0 0 Key Wake-up Port H Interrupt Enables 0 KWIFG 0x002E Key Wake-up Port G Flag Register KWIFG.KWIFG6 6 Key Wake-up Port G Flag 6 KWIFG.KWIFG5 5 Key Wake-up Port G Flag 5 KWIFG.KWIFG4 4 Key Wake-up Port G Flag 4 KWIFG.KWIFG3 3 Key Wake-up Port G Flag 3 KWIFG.KWIFG2 2 Key Wake-up Port G Flag 2 KWIFG.KWIFG1 1 Key Wake-up Port G Flag 1 KWIFG.KWIFG0 0 Key Wake-up Port G Flag 0 KWIFH 0x002F Key Wake-up Port H Flag Register KWIFH.KWIFH7 7 Key Wake-up Port H Flag 7 KWIFH.KWIFH6 6 Key Wake-up Port H Flag 6 KWIFH.KWIFH5 5 Key Wake-up Port H Flag 5 KWIFH.KWIFH4 4 Key Wake-up Port H Flag 4 KWIFH.KWIFH3 3 Key Wake-up Port H Flag 3 KWIFH.KWIFH2 2 Key Wake-up Port H Flag 2 KWIFH.KWIFH1 1 Key Wake-up Port H Flag 1 KWIFH.KWIFH0 0 Key Wake-up Port H Flag 0 RESERVED0030 0x0030 RESERVED RESERVED0031 0x0031 RESERVED RESERVED0032 0x0032 RESERVED RESERVED0033 0x0033 RESERVED RESERVED0034 0x0034 RESERVED RESERVED0035 0x0035 RESERVED RESERVED0036 0x0036 RESERVED RESERVED0037 0x0037 RESERVED SYNR 0x0038 Synthesizer Register SYNR.SYN5 5 SYNR.SYN4 4 SYNR.SYN3 3 SYNR.SYN2 2 SYNR.SYN1 1 SYNR.SYN0 0 REFDV 0x0039 Reference Divider Register REFDV.REFDV2 2 REFDV.REFDV1 1 REFDV.REFDV0 0 RESERVED003A 0x003A RESERVED PLLFLG 0x003B PLL Flags PLLFLG.LOCKIF 7 PLL Flags PLLFLG.LOCK 6 Locked Phase Lock Loop Circuit PLLFLG.LHIF 1 Limp-Home Interrupt Flag PLLFLG.LHOME 0 Limp-Home Mode Status PLLCR 0x003C PLL Control Register PLLCR.LOCKIE 7 PLL LOCK Interrupt Enable PLLCR.PLLON 6 Phase Lock Loop On PLLCR.AUTO 5 Automatic Bandwidth Control PLLCR.ACQ 4 Not in Acquisition PLLCR.PSTP 2 Pseudo-STOP Enable PLLCR.LHIE 1 Limp-Home Interrupt Enable PLLCR.NOLHM 0 No Limp-Home Mode CLKSEL 0x003D Clock Generator Clock select Register CLKSEL.BCSP 6 Bus Clock Select PLL CLKSEL.BCSS 5 Bus Clock Select Slow CLKSEL.MCS 2 Module Clock Select SLOW 0x003E Slow mode Divider Register SLOW.SLDV5 5 SLOW.SLDV4 4 SLOW.SLDV3 3 SLOW.SLDV2 2 SLOW.SLDV1 1 SLOW.SLDV0 0 RESERVED003F 0x003F RESERVED PWCLK 0x0040 PWM Clocks and Concatenate PWCLK.CON23 7 Concatenate PWM Channels 2 and 3 PWCLK.CON01 6 Concatenate PWM Channels 0 and 1 PWCLK.PCKA2 5 Prescaler for Clock A 2 PWCLK.PCKA1 4 Prescaler for Clock A 1 PWCLK.PCKA0 3 Prescaler for Clock A 0 PWCLK.PCKB2 2 Prescaler for Clock B 2 PWCLK.PCKB1 1 Prescaler for Clock B 1 PWCLK.PCKB0 0 Prescaler for Clock B 0 PWPOL 0x0041 PWM Clock Select and Polarity PWPOL.PCLK3 7 PWM Channel 3 Clock Select PWPOL.PCLK2 6 PWM Channel 2 Clock Select PWPOL.PCLK1 5 PWM Channel 1 Clock Select PWPOL.PCLK0 4 PWM Channel 0 Clock Select PWPOL.PPOL3 3 PWM Channel 3 Polarity PWPOL.PPOL2 2 PWM Channel 2 Polarity PWPOL.PPOL1 1 PWM Channel 1 Polarity PWPOL.PPOL0 0 PWM Channel 0 Polarity PWEN 0x0042 PWM Enable PWEN.PWEN3 3 PWM Channel 3 Enable PWEN.PWEN2 2 PWM Channel 2 Enable PWEN.PWEN1 1 PWM Channel 1 Enable PWEN.PWEN0 0 PWM Channel 0 Enable PWPRES 0x0043 PWM Prescale Counter PWSCAL0 0x0044 PWM Scale Register 0 PWSCNT0 0x0045 PWM Scale Counter 0 Value PWSCAL1 0x0046 PWM Scale Register 1 PWSCNT1 0x0047 PWM Scale Counter 1 Value PWCNT0 0x0048 PWM Channel Counter 0 PWCNT1 0x0049 PWM Channel Counter 1 PWCNT2 0x004A PWM Channel Counter 2 PWCNT3 0x004B PWM Channel Counter 3 PWPER0 0x004C PWM Channel Period Register 0 PWPER1 0x004D PWM Channel Period Register 1 PWPER2 0x004E PWM Channel Period Register 2 PWPER3 0x004F PWM Channel Period Register 3 PWDTY0 0x0050 PWM Channel Duty Register 0 PWDTY1 0x0051 PWM Channel Duty Register 1 PWDTY2 0x0052 PWM Channel Duty Register 2 PWDTY3 0x0053 PWM Channel Duty Register 3 PWCTL 0x0054 PWM Control Register PWCTL.PSWAI 4 PWM Halts while in Wait Mode PWCTL.CENTR 3 Center-Aligned Output Mode PWCTL.RDPP 2 Reduced Drive of Port P PWCTL.PUPP 1 Pull-Up Port P Enable PWCTL.PSBCK 0 PWM Stops while in Background Mode PWTST 0x0055 PWM Special Mode Register ("Test") PWTST.DISCR 7 Disable Reset of Channel Counter on Write to Channel Counter PWTST.DISCP 6 Disable Compare Count Period PWTST.DISCAL 5 Disable Load of Scale-Counters on Write to the Associated Scale-Registers PORTP 0x0056 Port P Data Register PORTP.PP7 7 Port P Data Bit 7 PORTP.PP6 6 Port P Data Bit 6 PORTP.PP5 5 Port P Data Bit 5 PORTP.PP4 4 Port P Data Bit 4 PORTP.PP3 3 Port P Data Bit 3 PORTP.PP2 2 Port P Data Bit 2 PORTP.PP1 1 Port P Data Bit 1 PORTP.PP0 0 Port P Data Bit 0 DDRP 0x0057 Port P Data Direction Register DDRP.DDP7 7 Port P Data Direction Bit 7 DDRP.DDP6 6 Port P Data Direction Bit 6 DDRP.DDP5 5 Port P Data Direction Bit 5 DDRP.DDP4 4 Port P Data Direction Bit 4 DDRP.DDP3 3 Port P Data Direction Bit 3 DDRP.DDP2 2 Port P Data Direction Bit 2 DDRP.DDP1 1 Port P Data Direction Bit 1 DDRP.DDP0 0 Port P Data Direction Bit 0 RESERVED0058 0x0058 RESERVED RESERVED0059 0x0059 RESERVED RESERVED005A 0x005A RESERVED RESERVED005B 0x005B RESERVED RESERVED005C 0x005C RESERVED RESERVED005D 0x005D RESERVED RESERVED005E 0x005E RESERVED RESERVED005F 0x005F RESERVED RESERVED0060 0x0060 RESERVED RESERVED0061 0x0061 RESERVED ATD0CTL2 0x0062 ATD0 Control Register 2 ATD0CTL2.ADPU 7 ATD Disable ATD0CTL2.AFFC 6 ATD Fast Flag Clear All ATD0CTL2.AWAI 5 ATD Wait Mode ATD0CTL2.ASCIE 1 ATD Sequence Complete Interrupt Enable ATD0CTL2.ASCIF 0 ATD Sequence Complete Interrupt Flag ATD0CTL3 0x0063 ATD0 Control Register 3 ATD0CTL3.FRZ1 1 Background Debug (Freeze) Enable 1 ATD0CTL3.FRZ0 0 Background Debug (Freeze) Enable 0 ATD0CTL4 0x0064 ATD0 Control Register 4 ATD0CTL4.S10BM 7 10 bit Mode ATD0CTL4.SMP1 6 Select Sample Time 1 ATD0CTL4.SMP0 5 Select Sample Time 0 ATD0CTL4.PRS4 4 Select Divide-By Factor for ATD P-Clock Prescaler 4 ATD0CTL4.PRS3 3 Select Divide-By Factor for ATD P-Clock Prescaler 3 ATD0CTL4.PRS2 2 Select Divide-By Factor for ATD P-Clock Prescaler 2 ATD0CTL4.PRS1 1 Select Divide-By Factor for ATD P-Clock Prescaler 1 ATD0CTL4.PRS0 0 Select Divide-By Factor for ATD P-Clock Prescaler 0 ATD0CTL5 0x0065 ATD0 Control Register 5 ATD0CTL5.S8CM 6 Select 8 Channel Mode ATD0CTL5.SCAN 5 Enable Continuous Channel Scan ATD0CTL5.MULT 4 Enable Multichannel Conversion ATD0CTL5.CD 3 Channel D Select for Conversion ATD0CTL5.CC 2 Channel C Select for Conversion ATD0CTL5.CB 1 Channel B Select for Conversion ATD0CTL5.CA 0 Channel A Select for Conversion ATD0STAT0 0x0066 ATD0 Status Register 0 ATD0STAT0.SCF 7 Sequence Complete Flag ATD0STAT0.CC2 2 Conversion Counter 2 for Current Sequence of Four or Eight Conversions ATD0STAT0.CC1 1 Conversion Counter 1 for Current Sequence of Four or Eight Conversions ATD0STAT0.CC0 0 Conversion Counter 0 for Current Sequence of Four or Eight Conversions ATD0STAT1 0x0067 ATD Status Register 1 ATD0STAT1.CCF7 7 Conversion Complete Flag 7 ATD0STAT1.CCF6 6 Conversion Complete Flag 6 ATD0STAT1.CCF5 5 Conversion Complete Flag 5 ATD0STAT1.CCF4 4 Conversion Complete Flag 4 ATD0STAT1.CCF3 3 Conversion Complete Flag 3 ATD0STAT1.CCF2 2 Conversion Complete Flag 2 ATD0STAT1.CCF1 1 Conversion Complete Flag 1 ATD0STAT1.CCF0 0 Conversion Complete Flag 0 ATD0TESTH 0x0068 ATD0 Test Register H ATD0TESTH.SAR9 7 SAR Data 9 ATD0TESTH.SAR8 6 SAR Data 8 ATD0TESTH.SAR7 5 SAR Data 7 ATD0TESTH.SAR6 4 SAR Data 6 ATD0TESTH.SAR5 3 SAR Data 5 ATD0TESTH.SAR4 2 SAR Data 4 ATD0TESTH.SAR3 1 SAR Data 3 ATD0TESTH.SAR2 0 SAR Data 2 ATD0TESTL 0x0069 ATD0 Test Register L ATD0TESTL.SAR1 7 SAR Data 1 ATD0TESTL.SAR0 6 SAR Data 0 ATD0TESTL.RST 5 Module Reset Bit ATD0TESTL.TSTOUT 4 Multiplex Output of TST ATD0TESTL.TST3 3 Test Bit 3 ATD0TESTL.TST2 2 Test Bit 2 ATD0TESTL.TST1 1 Test Bit 1 ATD0TESTL.TST0 0 Test Bit 0 RESERVED006A 0x006A RESERVED RESERVED006B 0x006B RESERVED RESERVED006C 0x006C RESERVED RESERVED006D 0x006D RESERVED RESERVED006E 0x006E RESERVED PORTAD0 0x006F Port AD0 Data Input Register PORTAD0.PAD07 7 Port AD0 Data Input Bit 7 PORTAD0.PAD06 6 Port AD0 Data Input Bit 6 PORTAD0.PAD05 5 Port AD0 Data Input Bit 5 PORTAD0.PAD04 4 Port AD0 Data Input Bit 4 PORTAD0.PAD03 3 Port AD0 Data Input Bit 3 PORTAD0.PAD02 2 Port AD0 Data Input Bit 2 PORTAD0.PAD01 1 Port AD0 Data Input Bit 1 PORTAD0.PAD00 0 Port AD0 Data Input Bit 0 ADR00H 0x0070 A/D Conversion Result Register High 0 ADR00L 0x0071 A/D Conversion Result Register Low 0 ADR01H 0x0072 A/D Conversion Result Register High 1 ADR01L 0x0073 A/D Conversion Result Register Low 1 ADR02H 0x0074 A/D Conversion Result Register High 2 ADR02L 0x0075 A/D Conversion Result Register Low 2 ADR03H 0x0076 A/D Conversion Result Register High 3 ADR03L 0x0077 A/D Conversion Result Register Low 3 ADR04H 0x0078 A/D Conversion Result Register High 4 ADR04L 0x0079 A/D Conversion Result Register Low 4 ADR05H 0x007A A/D Conversion Result Register High 5 ADR05L 0x007B A/D Conversion Result Register Low 5 ADR06H 0x007C A/D Conversion Result Register High 6 ADR06L 0x007D A/D Conversion Result Register Low 6 ADR07H 0x007E A/D Conversion Result Register High 7 ADR07L 0x007F A/D Conversion Result Register Low 7 TIOS 0x0080 Timer Input Capture/Output Compare Select TIOS.IOS7 7 Input Capture or Output Compare Channel 7 Configuration 7 TIOS.IOS6 6 Input Capture or Output Compare Channel 6 Configuration 6 TIOS.IOS5 5 Input Capture or Output Compare Channel 5 Configuration 5 TIOS.IOS4 4 Input Capture or Output Compare Channel 4 Configuration 4 TIOS.IOS3 3 Input Capture or Output Compare Channel 3 Configuration 3 TIOS.IOS2 2 Input Capture or Output Compare Channel 2 Configuration 2 TIOS.IOS1 1 Input Capture or Output Compare Channel 1 Configuration 1 TIOS.IOS0 0 Input Capture or Output Compare Channel 0 Configuration 0 CFORC 0x0081 Timer Compare Force Register CFORC.FOC7 7 Force Output Compare Action for Channel 7 CFORC.FOC6 6 Force Output Compare Action for Channel 6 CFORC.FOC5 5 Force Output Compare Action for Channel 5 CFORC.FOC4 4 Force Output Compare Action for Channel 4 CFORC.FOC3 3 Force Output Compare Action for Channel 3 CFORC.FOC2 2 Force Output Compare Action for Channel 2 CFORC.FOC1 1 Force Output Compare Action for Channel 1 CFORC.FOC0 0 Force Output Compare Action for Channel 0 OC7M 0x0082 Output Compare 7 Mask Register OC7M.OC7M7 7 OC7M.OC7M6 6 OC7M.OC7M5 5 OC7M.OC7M4 4 OC7M.OC7M3 3 OC7M.OC7M2 2 OC7M.OC7M1 1 OC7M.OC7M0 0 OC7D 0x0083 Output Compare 7 Data Register OC7D.OC7D7 7 OC7D.OC7D6 6 OC7D.OC7D5 5 OC7D.OC7D4 4 OC7D.OC7D3 3 OC7D.OC7D2 2 OC7D.OC7D1 1 OC7D.OC7D0 0 TCNTH 0x0084 Timer Count Register High TCNTL 0x0085 Timer Count Register Low TSCR 0x0086 Timer System Control Register TSCR.TEN 7 Timer Enable TSCR.TSWAI 6 Timer Module Stops While in Wait TSCR.TSBCK 5 Timer and Modulus Counter Stop While in Background Mode TSCR.TFFCA 4 Timer Fast Flag Clear All RESERVED0087 0x0087 RESERVED TCTL1 0x0088 Timer Control Register 1 TCTL1.OM7 7 Output Mode 7 TCTL1.OL7 6 Output Level 7 TCTL1.OM6 5 Output Mode 6 TCTL1.OL6 4 Output Level 6 TCTL1.OM5 3 Output Mode 5 TCTL1.OL5 2 Output Level 5 TCTL1.OM4 1 Output Mode 4 TCTL1.OL4 0 Output Level 4 TCTL2 0x0089 Timer Control Register 2 TCTL2.OM3 7 Output Mode 3 TCTL2.OL3 6 Output Level 3 TCTL2.OM2 5 Output Mode 2 TCTL2.OL2 4 Output Level 2 TCTL2.OM1 3 Output Mode 1 TCTL2.OL1 2 Output Level 1 TCTL2.OM0 1 Output Mode 0 TCTL2.OL0 0 Output Level 0 TCTL3 0x008A Timer Control Register 3 TCTL3.EDG7B 7 Input Capture Edge Control 7B TCTL3.EDG7A 6 Input Capture Edge Control 7A TCTL3.EDG6B 5 Input Capture Edge Control 6B TCTL3.EDG6A 4 Input Capture Edge Control 6A TCTL3.EDG5B 3 Input Capture Edge Control 5B TCTL3.EDG5A 2 Input Capture Edge Control 5A TCTL3.EDG4B 1 Input Capture Edge Control 4B TCTL3.EDG4A 0 Input Capture Edge Control 4A TCTL4 0x008B Timer Control Register 4 TCTL4.EDG3B 7 Input Capture Edge Control 3B TCTL4.EDG3A 6 Input Capture Edge Control 3A TCTL4.EDG2B 5 Input Capture Edge Control 2B TCTL4.EDG2A 4 Input Capture Edge Control 2A TCTL4.EDG1B 3 Input Capture Edge Control 1B TCTL4.EDG1A 2 Input Capture Edge Control 1A TCTL4.EDG0B 1 Input Capture Edge Control 0B TCTL4.EDG0A 0 Input Capture Edge Control 0A TMSK1 0x008C Timer Interrupt Mask 1 TMSK1.C7I 7 Input Capture/Output Compare 7 Interrupt Enable TMSK1.C6I 6 Input Capture/Output Compare 6 Interrupt Enable TMSK1.C5I 5 Input Capture/Output Compare 5 Interrupt Enable TMSK1.C4I 4 Input Capture/Output Compare 4 Interrupt Enable TMSK1.C3I 3 Input Capture/Output Compare 3 Interrupt Enable TMSK1.C2I 2 Input Capture/Output Compare 2 Interrupt Enable TMSK1.C1I 1 Input Capture/Output Compare 1 Interrupt Enable TMSK1.C0I 0 Input Capture/Output Compare 0 Interrupt Enable TMSK2 0x008D Timer Interrupt Mask 2 TMSK2.TOI 7 Timer Overflow Interrupt Enable TMSK2.PUPT 5 Timer Port Pull-Up Resistor Enable TMSK2.RDPT 4 Timer Port Drive Reduction TMSK2.TCRE 3 Timer Counter Reset Enable TMSK2.PR2 2 Timer Prescaler Select 2 TMSK2.PR1 1 Timer Prescaler Select 1 TMSK2.PR0 0 Timer Prescaler Select 0 TFLG1 0x008E Main Timer Interrupt Flag 1 TFLG1.C7F 7 Input Capture/Output Compare Channel 7 Flag TFLG1.C6F 6 Input Capture/Output Compare Channel 6 Flag TFLG1.C5F 5 Input Capture/Output Compare Channel 5 Flag TFLG1.C4F 4 Input Capture/Output Compare Channel 4 Flag TFLG1.C3F 3 Input Capture/Output Compare Channel 3 Flag TFLG1.C2F 2 Input Capture/Output Compare Channel 2 Flag TFLG1.C1F 1 Input Capture/Output Compare Channel 1 Flag TFLG1.C0F 0 Input Capture/Output Compare Channel 0 Flag TFLG2 0x008F Main Timer Interrupt Flag 2 TFLG2.TOF 7 Timer Overflow Flag TC0H 0x0090 Timer Input Capture/Output Compare Register 0 H TC0L 0x0091 Timer Input Capture/Output Compare Register 0 L TC1H 0x0092 Timer Input Capture/Output Compare Register 1 H TC1L 0x0093 Timer Input Capture/Output Compare Register 1 L TC2H 0x0094 Timer Input Capture/Output Compare Register 2 H TC2L 0x0095 Timer Input Capture/Output Compare Register 2 L TC3H 0x0096 Timer Input Capture/Output Compare Register 3 H TC3L 0x0097 Timer Input Capture/Output Compare Register 3 L TC4H 0x0098 Timer Input Capture/Output Compare Register 4 H TC4L 0x0099 Timer Input Capture/Output Compare Register 4 L TC5H 0x009A Timer Input Capture/Output Compare Register 5 H TC5L 0x009B Timer Input Capture/Output Compare Register 5 L TC6H 0x009C Timer Input Capture/Output Compare Register 6 H TC6L 0x009D Timer Input Capture/Output Compare Register 6 L TC7H 0x009E Timer Input Capture/Output Compare Register 7 H TC7L 0x009F Timer Input Capture/Output Compare Register 7 L PACTL 0x00A0 16-Bit Pulse Accumulator A Control Register PACTL.PAEN 6 Pulse Accumulator A System Enable PACTL.PAMOD 5 Pulse Accumulator Mode PACTL.PEDGE 4 Pulse Accumulator Edge Control PACTL.CLK1 3 Clock Select Bit 1 PACTL.CLK0 2 Clock Select Bit 0 PACTL.PAOVI 1 Pulse Accumulator A Overflow Interrupt enable PACTL.PAI 0 Pulse Accumulator Input Interrupt enable PAFLG 0x00A1 Pulse Accumulator A Flag Register PAFLG.PAOVF 1 Pulse Accumulator A Overflow Flag PAFLG.PAIF 0 Pulse Accumulator Input edge Flag PACN3 0x00A2 Pulse Accumulators Count Register 3 PACN2 0x00A3 Pulse Accumulators Count Register 2 PACN1 0x00A4 Pulse Accumulators Count Register 1 PACN0 0x00A5 Pulse Accumulators Count Register 0 MCCTL 0x00A6 16-Bit Modulus Down-Counter Control Register MCCTL.MCZI 7 Modulus Counter Underflow Interrupt Enable MCCTL.MODMC 6 Modulus Mode Enable MCCTL.RDMCL 5 Read Modulus Down-Counter Load MCCTL.ICLAT 4 Input Capture Force Latch Action MCCTL.FLMC 3 Force Load Register into the Modulus Counter Count Register MCCTL.MCEN 2 Modulus Down-Counter Enable MCCTL.MCPR1 1 Modulus Counter Prescaler select 1 MCCTL.MCPR0 0 Modulus Counter Prescaler select 0 MCFLG 0x00A7 16-Bit Modulus Down-Counter FLAG Register MCFLG.MCZF 7 Modulus Counter Underflow Interrupt Flag MCFLG.POLF3 3 First Input Capture Polarity Status 3 MCFLG.POLF2 2 First Input Capture Polarity Status 2 MCFLG.POLF1 1 First Input Capture Polarity Status 1 MCFLG.POLF0 0 First Input Capture Polarity Status 0 ICPACR 0x00A8 Input Control Pulse Accumulators Control Register ICPACR.0PA3EN 3 8-Bit Pulse Accumulator 3 Enable ICPACR.0PA2EN 2 8-Bit Pulse Accumulator 2 Enable ICPACR.0PA1EN 1 8-Bit Pulse Accumulator 1 Enable ICPACR.0PA0EN 0 8-Bit Pulse Accumulator 0 Enable DLYCT 0x00A9 Delay Counter Control Register DLYCT.DLY1 1 Delay Counter Select 1 DLYCT.DLY0 0 Delay Counter Select 0 ICOVW 0x00AA Input Control Overwrite Register ICOVW.NOVW7 7 No Input Capture Overwrite 7 ICOVW.NOVW6 6 No Input Capture Overwrite 6 ICOVW.NOVW5 5 No Input Capture Overwrite 5 ICOVW.NOVW4 4 No Input Capture Overwrite 4 ICOVW.NOVW3 3 No Input Capture Overwrite 3 ICOVW.NOVW2 2 No Input Capture Overwrite 2 ICOVW.NOVW1 1 No Input Capture Overwrite 1 ICOVW.NOVW0 0 No Input Capture Overwrite 0 ICSYS 0x00AB Input Control System Control Register ICSYS.SH37 7 Share Input action of Input Capture Channels 3 and 7 ICSYS.SH26 6 Share Input action of Input Capture Channels 2 and 6 ICSYS.SH15 5 Share Input action of Input Capture Channels 1 and 5 ICSYS.SH04 4 Share Input action of Input Capture Channels 0 and 4 ICSYS.TFMOD 3 Timer Flag-setting Mode ICSYS.PACMX 2 8-Bit Pulse Accumulators Maximum Count ICSYS.BUFEN 1 IC Buffer Enable ICSYS.LATQ 0 Input Control Latch or Queue Mode Enable RESERVED00AC 0x00AC RESERVED TIMTST 0x00AD Timer Test Register TIMTST.TCBYP 1 Main Timer Divider Chain Bypass PORTT 0x00AE Port T Data Register PORTT.PT7 7 Port T Data Bit 7 PORTT.PT6 6 Port T Data Bit 6 PORTT.PT5 5 Port T Data Bit 5 PORTT.PT4 4 Port T Data Bit 4 PORTT.PT3 3 Port T Data Bit 3 PORTT.PT2 2 Port T Data Bit 2 PORTT.PT1 1 Port T Data Bit 1 PORTT.PT0 0 Port T Data Bit 0 DDRT 0x00AF Port T Data Direction Register DDRT.DDT7 7 Port T Data Direction Bit 7 DDRT.DDT6 6 Port T Data Direction Bit 6 DDRT.DDT5 5 Port T Data Direction Bit 5 DDRT.DDT4 4 Port T Data Direction Bit 4 DDRT.DDT3 3 Port T Data Direction Bit 3 DDRT.DDT2 2 Port T Data Direction Bit 2 DDRT.DDT1 1 Port T Data Direction Bit 1 DDRT.DDT0 0 Port T Data Direction Bit 0 PBCTL 0x00B0 16-Bit Pulse Accumulator B Control Register PBCTL.PBEN 6 Pulse Accumulator B System Enable PBCTL.PBOVI 1 Pulse Accumulator B Overflow Interrupt enable PBFLG 0x00B1 Pulse Accumulator B Flag Register PBFLG.PBOVF 1 Pulse Accumulator B Overflow Flag PA3H 0x00B2 8-Bit Pulse Accumulators Holding Register 3 H PA2H 0x00B3 8-Bit Pulse Accumulators Holding Register 2 H PA1H 0x00B4 8-Bit Pulse Accumulators Holding Register 1 H PA0H 0x00B5 8-Bit Pulse Accumulators Holding Register 0 H MCCNTH 0x00B6 Modulus Down-Counter Count Register H MCCNTL 0x00B7 Modulus Down-Counter Count Register L TC0HH 0x00B8 Timer Input Capture Holding Register 0 H TC0HL 0x00B9 Timer Input Capture Holding Register 0 L TC1HH 0x00BA Timer Input Capture Holding Register 1 H TC1HL 0x00BB Timer Input Capture Holding Register 1 L TC2HH 0x00BC Timer Input Capture Holding Register 2 H TC2HL 0x00BD Timer Input Capture Holding Register 2 L TC3HH 0x00BE Timer Input Capture Holding Register 3 H TC3HL 0x00BF Timer Input Capture Holding Register 3 L SC0BDH 0x00C0 SCI Baud Rate Control Register SC0BDH.BTST 7 Reserved for test function SC0BDH.BSPL 6 Reserved for test function SC0BDH.BRLD 5 Reserved for test function SC0BDH.SBR12 4 SC0BDH.SBR11 3 SC0BDH.SBR10 2 SC0BDH.SBR9 1 SC0BDH.SBR8 0 SC0BDL 0x00C1 SCI Baud Rate Control Register SC0BDL.SBR7 7 SC0BDL.SBR6 6 SC0BDL.SBR5 5 SC0BDL.SBR4 4 SC0BDL.SBR3 3 SC0BDL.SBR2 2 SC0BDL.SBR1 1 SC0BDL.SBR0 0 SC0CR1 0x00C2 SCI Control Register 1 SC0CR1.LOOPS 7 SCI LOOP Mode/Single Wire Mode Enable SC0CR1.WOMS 6 Wired-Or Mode for Serial Pins SC0CR1.RSRC 5 Receiver Source SC0CR1.M 4 Mode (select character format) SC0CR1.WAKE 3 Wake-up by Address Mark/Idle SC0CR1.ILT 2 Idle Line Type SC0CR1.PE 1 Parity Enable SC0CR1.PT 0 Parity Type SC0CR2 0x00C3 SCI Control Register 2 SC0CR2.TIE 7 Transmit Interrupt Enable SC0CR2.TCIE 6 Transmit Complete Interrupt Enable SC0CR2.RIE 5 Receiver Interrupt Enable SC0CR2.ILIE 4 Idle Line Interrupt Enable SC0CR2.TE 3 Transmitter Enable SC0CR2.RE 2 Receiver Enable SC0CR2.RWU 1 Receiver Wake-Up Control SC0CR2.SBK 0 Send Break SC0SR1 0x00C4 SCI Status Register 1 SC0SR1.TDRE 7 Transmit Data Register Empty Flag SC0SR1.TC 6 Transmit Complete Flag SC0SR1.RDRF 5 Receive Data Register Full Flag SC0SR1.IDLE 4 Idle Line Detected Flag SC0SR1.OR 3 Overrun Error Flag SC0SR1.NF 2 Noise Error Flag SC0SR1.FE 1 Framing Error Flag SC0SR1.PF 0 Parity Error Flag SC0SR2 0x00C5 SCI Status Register 2 SC0SR2.SCSWAI 7 Serial Communications Interface Stop in WAIT Mode SC0SR2.MIE 6 SC0SR2.MDL1 5 SC0SR2.MDL0 4 SC0SR2.RAF 0 Receiver Active Flag SC0DRH 0x00C6 SCI Data Register High SC0DRH.R8 7 Receive Bit 8 SC0DRH.T8 6 Transmit Bit 8 SC0DRL 0x00C7 SCI Data Register Low SC0DRL.R7_T7 7 Receive/Transmit Data Bit 7 SC0DRL.R6_T6 6 Receive/Transmit Data Bit 6 SC0DRL.R5_T5 5 Receive/Transmit Data Bit 5 SC0DRL.R4_T4 4 Receive/Transmit Data Bit 4 SC0DRL.R3_T3 3 Receive/Transmit Data Bit 3 SC0DRL.R2_T2 2 Receive/Transmit Data Bit 2 SC0DRL.R1_T1 1 Receive/Transmit Data Bit 1 SC0DRL.R0_T0 0 Receive/Transmit Data Bit 0 SC1BDH 0x00C8 SCI Baud Rate Control Register SC1BDH.BTST 7 Reserved for test function SC1BDH.BSPL 6 Reserved for test function SC1BDH.BRLD 5 Reserved for test function SC1BDH.SBR12 4 SC1BDH.SBR11 3 SC1BDH.SBR10 2 SC1BDH.SBR9 1 SC1BDH.SBR8 0 SC1BDL 0x00C9 SCI Baud Rate Control Register SC1BDL.SBR7 7 SC1BDL.SBR6 6 SC1BDL.SBR5 5 SC1BDL.SBR4 4 SC1BDL.SBR3 3 SC1BDL.SBR2 2 SC1BDL.SBR1 1 SC1BDL.SBR0 0 SC1CR1 0x00CA SCI Control Register 1 SC1CR1.LOOPS 7 SCI LOOP Mode/Single Wire Mode Enable SC1CR1.WOMS 6 Wired-Or Mode for Serial Pins SC1CR1.RSRC 5 Receiver Source SC1CR1.M 4 Mode (select character format) SC1CR1.WAKE 3 Wake-up by Address Mark/Idle SC1CR1.ILT 2 Idle Line Type SC1CR1.PE 1 Parity Enable SC1CR1.PT 0 Parity Type SC1CR2 0x00CB SCI Control Register 2 SC1CR2.TIE 7 Transmit Interrupt Enable SC1CR2.TCIE 6 Transmit Complete Interrupt Enable SC1CR2.RIE 5 Receiver Interrupt Enable SC1CR2.ILIE 4 Idle Line Interrupt Enable SC1CR2.TE 3 Transmitter Enable SC1CR2.RE 2 Receiver Enable SC1CR2.RWU 1 Receiver Wake-Up Control SC1CR2.SBK 0 Send Break SC1SR1 0x00CC SCI Status Register 1 SC1SR1.TDRE 7 Transmit Data Register Empty Flag SC1SR1.TC 6 Transmit Complete Flag SC1SR1.RDRF 5 Receive Data Register Full Flag SC1SR1.IDLE 4 Idle Line Detected Flag SC1SR1.OR 3 Overrun Error Flag SC1SR1.NF 2 Noise Error Flag SC1SR1.FE 1 Framing Error Flag SC1SR1.PF 0 Parity Error Flag SC1SR2 0x00CD SCI Status Register 2 SC1SR2.SCSWAI 7 Serial Communications Interface Stop in WAIT Mode SC1SR2.RAF 0 Receiver Active Flag SC1DRH 0x00CE SCI Data Register High SC1DRH.R8 7 Receive Bit 8 SC1DRH.T8 6 Transmit Bit 8 SC1DRL 0x00CF SCI Data Register Low SC1DRL.R7_T7 7 Receive/Transmit Data Bit 7 SC1DRL.R6_T6 6 Receive/Transmit Data Bit 6 SC1DRL.R5_T5 5 Receive/Transmit Data Bit 5 SC1DRL.R4_T4 4 Receive/Transmit Data Bit 4 SC1DRL.R3_T3 3 Receive/Transmit Data Bit 3 SC1DRL.R2_T2 2 Receive/Transmit Data Bit 2 SC1DRL.R1_T1 1 Receive/Transmit Data Bit 1 SC1DRL.R0_T0 0 Receive/Transmit Data Bit 0 SP0CR1 0x00D0 SPI Control Register 1 SP0CR1.SPIE 7 SPI Interrupt Enable SP0CR1.SPE 6 SPI System Enable SP0CR1.SWOM 5 Port S Wired-OR Mode SP0CR1.MSTR 4 SPI Master/Slave Mode Select SP0CR1.CPOL 3 SPI Clock Polarity SP0CR1.CPHA 2 Clock Phase SP0CR1.SSOE 1 Slave Select Output Enable SP0CR1.LSBF 0 SPI LSB First enable SP0CR2 0x00D1 SPI Control Register 2 SP0CR2.SPSWAI 1 Serial Interface Stop in WAIT mode SP0CR2.SPC0 0 Serial Pin Control 0 SP0BR 0x00D2 SPI Baud Rate Register SP0BR.SPR2 2 SPI Clock (SCK) Rate Select Bit 2 SP0BR.SPR1 1 SPI Clock (SCK) Rate Select Bit 1 SP0BR.SPR0 0 SPI Clock (SCK) Rate Select Bit 0 SP0SR 0x00D3 SPI Status Register SP0SR.SPIF 7 SPI Interrupt Request SP0SR.WCOL 6 Write Collision Status Flag SP0SR.MODF 4 SPI Mode Error Interrupt Status Flag RESERVED00D4 0x00D4 RESERVED SP0DR 0x00D5 SPI Data Register PORTS 0x00D6 Port S Data Register PORTS.PS7 7 Port S Data Bit 7 PORTS.PS6 6 Port S Data Bit 6 PORTS.PS5 5 Port S Data Bit 5 PORTS.PS4 4 Port S Data Bit 4 PORTS.PS3 3 Port S Data Bit 3 PORTS.PS2 2 Port S Data Bit 2 PORTS.PS1 1 Port S Data Bit 1 PORTS.PS0 0 Port S Data Bit 0 DDRS 0x00D7 Port S Data Direction Register DDRS.DDS7 7 Port S Data Direction Bit 7 DDRS.DDS6 6 Port S Data Direction Bit 6 DDRS.DDS5 5 Port S Data Direction Bit 5 DDRS.DDS4 4 Port S Data Direction Bit 4 DDRS.DDS3 3 Port S Data Direction Bit 3 DDRS.DDS2 2 Port S Data Direction Bit 2 DDRS.DDS1 1 Port S Data Direction Bit 1 DDRS.DDS0 0 Port S Data Direction Bit 0 RESERVED00D8 0x00D8 RESERVED PURDS 0x00D9 Pull-Up Register for Port S PURDS.RDPS2 6 Reduce Drive of Port S[7:4] PURDS.RDPS1 5 Reduce Drive of Port S[3:2] PURDS.RDPS0 4 Reduce Drive of Port S[1:0] PURDS.PUPS2 2 Pull-up Port S[7:4] Enable PURDS.PUPS1 1 Pull-up Port S[3:2] Enable PURDS.PUPS0 0 Pull-up Port S[1:0] Enable RESERVED00DA 0x00DA RESERVED RESERVED00DB 0x00DB RESERVED RESERVED00DC 0x00DC RESERVED RESERVED00DD 0x00DD RESERVED RESERVED00DE 0x00DE RESERVED RESERVED00DF 0x00DF RESERVED RESERVED00E0 0x00E0 RESERVED RESERVED00E1 0x00E1 RESERVED RESERVED00E2 0x00E2 RESERVED RESERVED00E3 0x00E3 RESERVED RESERVED00E4 0x00E4 RESERVED RESERVED00E5 0x00E5 RESERVED RESERVED00E6 0x00E6 RESERVED RESERVED00E7 0x00E7 RESERVED RESERVED00E8 0x00E8 RESERVED RESERVED00E9 0x00E9 RESERVED RESERVED00EA 0x00EA RESERVED RESERVED00EB 0x00EB RESERVED RESERVED00EC 0x00EC RESERVED RESERVED00ED 0x00ED RESERVED RESERVED00EE 0x00EE RESERVED RESERVED00EF 0x00EF RESERVED EEMCR 0x00F0 EEPROM Module Configuration EEMCR.NOBDML 7 Background Debug Mode Lockout Disable EEMCR.NOSHB 6 SHADOW Byte Disable EEMCR.EESWAI 2 EEPROM Stops in Wait Mode EEMCR.PROTLCK 1 Block Protect Write Lock EEMCR.EERC 0 EEPROM Charge Pump Clock EEPROT 0x00F1 EEPROM Block Protect EEPROT.SHPROT 7 SHADOW Byte Protection EEPROT.BPROT4 4 EEPROM Block Protection 4 EEPROT.BPROT3 3 EEPROM Block Protection 3 EEPROT.BPROT2 2 EEPROM Block Protection 2 EEPROT.BPROT1 1 EEPROM Block Protection 1 EEPROT.BPROT0 0 EEPROM Block Protection 0 RESERVED00F2 0x00F2 RESERVED EEPROG 0x00F3 EEPROM Control EEPROG.BULKP 7 Bulk Erase Protection EEPROG.BYTE 4 Byte and Aligned Word Erase EEPROG.ROW 3 Row or Bulk Erase (when BYTE = 0) EEPROG.ERASE 2 Erase Control EEPROG.EELAT 1 EEPROM Latch Control EEPROG.EEPGM 0 Program and Erase Enable FEE32LCK 0x00F4 Flash EEPROM Lock Control Register FEE32LCK.LOCK 0 FEE32MCR 0x00F5 Flash EEPROM Module Configuration Register FEE32MCR.BOOTP 0 FEETST0 0x00F6 FEETST0.FSTE 7 FEETST0.GADR 6 FEETST0.HVT 5 FEETST0.FENLV 4 FEETST0.FDISVFP 3 FEETST0.VTCK 2 FEETST0.STRE 1 FEETST0.MWPR 0 FEE32CTL 0x00F7 Flash EEPROM Control Register FEE32CTL.FEESWAI 4 Flash EEPROM Stop in Wait Control FEE32CTL.SVFP 3 Status V FP Voltage FEE32CTL.ERAS 2 Erase Control FEE32CTL.LAT 1 Latch Control FEE32CTL.ENPE 0 Enable Programming/Erase FEE28LCK 0x00F8 Flash EEPROM Lock Control Register FEE28LCK.LOCK 0 FEE28MCR 0x00F9 Flash EEPROM Module Configuration Register FEE28MCR.BOOTP 0 FEETST1 0x00FA FEETST1.FSTE 7 FEETST1.GADR 6 FEETST1.HVT 5 FEETST1.FENLV 4 FEETST1.FDISVFP 3 FEETST1.VTCK 2 FEETST1.STRE 1 FEETST1.MWPR 0 FEE28CTL 0x00FB Flash EEPROM Control Register FEE28CTL.FEESWAI 4 Flash EEPROM Stop in Wait Control FEE28CTL.SVFP 3 Status V FP Voltage FEE28CTL.ERAS 2 Erase Control FEE28CTL.LAT 1 Latch Control FEE28CTL.ENPE 0 Enable Programming/Erase RESERVED00FC 0x00FC RESERVED RESERVED00FD 0x00FD RESERVED RESERVED00FE 0x00FE RESERVED RESERVED00FF 0x00FF RESERVED CMCR0 0x0100 msCAN12 Module Control Register 0 CMCR0.CSWAI 5 CAN Stops in Wait Mode CMCR0.SYNCH 4 Synchronized Status CMCR0.TLNKEN 3 Timer Enable CMCR0.SLPAK 2 SLEEP Mode Acknowledge CMCR0.SLPRQ 1 SLEEP request CMCR0.SFTRES 0 SOFT_RESET CMCR1 0x0101 msCAN12 Module Control Register 1 CMCR1.LOOPB 2 Loop Back Self Test Mode CMCR1.WUPM 1 Wake-Up Mode CMCR1.CLKSRC 0 msCAN12 Clock Source CBTR0 0x0102 msCAN12 Bus Timing Register 0 CBTR0.SJW1 7 Synchronization Jump Width 1 CBTR0.SJW0 6 Synchronization Jump Width 0 CBTR0.BRP5 5 Baud Rate Prescaler 5 CBTR0.BRP4 4 Baud Rate Prescaler 4 CBTR0.BRP3 3 Baud Rate Prescaler 3 CBTR0.BRP2 2 Baud Rate Prescaler 2 CBTR0.BRP1 1 Baud Rate Prescaler 1 CBTR0.BRP0 0 Baud Rate Prescaler 0 CBTR1 0x0103 msCAN12 Bus Timing Register 1 CBTR1.SAMP 7 Sampling CBTR1.TSEG22 6 Time Segment 22 CBTR1.TSEG21 5 Time Segment 21 CBTR1.TSEG20 4 Time Segment 20 CBTR1.TSEG13 3 Time Segment 13 CBTR1.TSEG12 2 Time Segment 12 CBTR1.TSEG11 1 Time Segment 11 CBTR1.TSEG10 0 Time Segment 10 CRFLG 0x0104 msCAN12 Receiver Flag Register CRFLG.WUPIF 7 Wake-up Interrupt Flag CRFLG.RWRNIF 6 Receiver Warning Interrupt Flag CRFLG.TWRNIF 5 Transmitter Warning Interrupt Flag CRFLG.RERRIF 4 Receiver Error Passive Interrupt Flag CRFLG.TERRIF 3 Transmitter Error Passive Interrupt Flag CRFLG.BOFFIF 2 BUSOFF Interrupt Flag CRFLG.OVRIF 1 Overrun Interrupt Flag CRFLG.RXF 0 Receive Buffer Full CRIER 0x0105 msCAN12 Receiver Interrupt Enable Register CRIER.WUPIE 7 Wake-up Interrupt Enable CRIER.RWRNIE 6 Receiver Warning Interrupt Enable CRIER.TWRNIE 5 Transmitter Warning Interrupt Enable CRIER.RERRIE 4 Receiver Error Passive Interrupt Enable CRIER.TERRIE 3 Transmitter Error Passive Interrupt Enable CRIER.BOFFIE 2 BUSOFF Interrupt Enable CRIER.OVRIE 1 Overrun Interrupt Enable CRIER.RXFIE 0 Receiver Full Interrupt Enable CTFLG 0x0106 msCAN12 Transmitter Flag Register CTFLG.ABTAK2 6 Abort Acknowledge 2 CTFLG.ABTAK1 5 Abort Acknowledge 1 CTFLG.ABTAK0 4 Abort Acknowledge 0 CTFLG.TXE2 2 Transmitter Buffer Empty 2 CTFLG.TXE1 1 Transmitter Buffer Empty 1 CTFLG.TXE0 0 Transmitter Buffer Empty 0 CTCR 0x0107 msCAN12 Transmitter Control Register CTCR.ABTRQ2 6 Abort Request 2 CTCR.ABTRQ1 5 Abort Request 1 CTCR.ABTRQ0 4 Abort Request 0 CTCR.TXEIE2 2 Transmitter Empty Interrupt Enable 2 CTCR.TXEIE1 1 Transmitter Empty Interrupt Enable 1 CTCR.TXEIE0 0 Transmitter Empty Interrupt Enable 0 CIDAC 0x0108 msCAN12 Identifier Acceptance Control Register CIDAC.IDAM1 5 Identifier Acceptance Mode 1 CIDAC.IDAM0 4 Identifier Acceptance Mode 0 CIDAC.IDHIT2 2 Identifier Acceptance Hit Indicator 2 CIDAC.IDHIT1 1 Identifier Acceptance Hit Indicator 1 CIDAC.IDHIT0 0 Identifier Acceptance Hit Indicator 0 RESERVED0109 0x0109 RESERVED RESERVED010A 0x010A RESERVED RESERVED010B 0x010B RESERVED RESERVED010C 0x010C RESERVED RESERVED010D 0x010D RESERVED CRXERR 0x010E msCAN12 Receive Error Counter CRXERR.RXERR7 7 CRXERR.RXERR6 6 CRXERR.RXERR5 5 CRXERR.RXERR4 4 CRXERR.RXERR3 3 CRXERR.RXERR2 2 CRXERR.RXERR1 1 CRXERR.RXERR0 0 CTXERR 0x010F msCAN12 Transmit Error Counter CTXERR.TXERR7 7 CTXERR.TXERR6 6 CTXERR.TXERR5 5 CTXERR.TXERR4 4 CTXERR.TXERR3 3 CTXERR.TXERR2 2 CTXERR.TXERR1 1 CTXERR.TXERR0 0 CIDAR0 0x0110 msCAN12 Identifier Acceptance Register 0 CIDAR0.AC7 7 Acceptance Code Bit 7 CIDAR0.AC6 6 Acceptance Code Bit 6 CIDAR0.AC5 5 Acceptance Code Bit 5 CIDAR0.AC4 4 Acceptance Code Bit 4 CIDAR0.AC3 3 Acceptance Code Bit 3 CIDAR0.AC2 2 Acceptance Code Bit 2 CIDAR0.AC1 1 Acceptance Code Bit 1 CIDAR0.AC0 0 Acceptance Code Bit 0 CIDAR1 0x0111 msCAN12 Identifier Acceptance Register 1 CIDAR1.AC7 7 Acceptance Code Bit 7 CIDAR1.AC6 6 Acceptance Code Bit 6 CIDAR1.AC5 5 Acceptance Code Bit 5 CIDAR1.AC4 4 Acceptance Code Bit 4 CIDAR1.AC3 3 Acceptance Code Bit 3 CIDAR1.AC2 2 Acceptance Code Bit 2 CIDAR1.AC1 1 Acceptance Code Bit 1 CIDAR1.AC0 0 Acceptance Code Bit 0 CIDAR2 0x0112 msCAN12 Identifier Acceptance Register 2 CIDAR2.AC7 7 Acceptance Code Bit 7 CIDAR2.AC6 6 Acceptance Code Bit 6 CIDAR2.AC5 5 Acceptance Code Bit 5 CIDAR2.AC4 4 Acceptance Code Bit 4 CIDAR2.AC3 3 Acceptance Code Bit 3 CIDAR2.AC2 2 Acceptance Code Bit 2 CIDAR2.AC1 1 Acceptance Code Bit 1 CIDAR2.AC0 0 Acceptance Code Bit 0 CIDAR3 0x0113 msCAN12 Identifier Acceptance Register 3 CIDAR3.AC7 7 Acceptance Code Bit 7 CIDAR3.AC6 6 Acceptance Code Bit 6 CIDAR3.AC5 5 Acceptance Code Bit 5 CIDAR3.AC4 4 Acceptance Code Bit 4 CIDAR3.AC3 3 Acceptance Code Bit 3 CIDAR3.AC2 2 Acceptance Code Bit 2 CIDAR3.AC1 1 Acceptance Code Bit 1 CIDAR3.AC0 0 Acceptance Code Bit 0 CIDMR0 0x0114 msCAN12 Identifier Mask Register 0 CIDMR0.AM7 7 Acceptance Mask Bit 7 CIDMR0.AM6 6 Acceptance Mask Bit 6 CIDMR0.AM5 5 Acceptance Mask Bit 5 CIDMR0.AM4 4 Acceptance Mask Bit 4 CIDMR0.AM3 3 Acceptance Mask Bit 3 CIDMR0.AM2 2 Acceptance Mask Bit 2 CIDMR0.AM1 1 Acceptance Mask Bit 1 CIDMR0.AM0 0 Acceptance Mask Bit 0 CIDMR1 0x0115 msCAN12 Identifier Mask Register 1 CIDMR1.AM7 7 Acceptance Mask Bit 7 CIDMR1.AM6 6 Acceptance Mask Bit 6 CIDMR1.AM5 5 Acceptance Mask Bit 5 CIDMR1.AM4 4 Acceptance Mask Bit 4 CIDMR1.AM3 3 Acceptance Mask Bit 3 CIDMR1.AM2 2 Acceptance Mask Bit 2 CIDMR1.AM1 1 Acceptance Mask Bit 1 CIDMR1.AM0 0 Acceptance Mask Bit 0 CIDMR2 0x0116 msCAN12 Identifier Mask Register 2 CIDMR2.AM7 7 Acceptance Mask Bit 7 CIDMR2.AM6 6 Acceptance Mask Bit 6 CIDMR2.AM5 5 Acceptance Mask Bit 5 CIDMR2.AM4 4 Acceptance Mask Bit 4 CIDMR2.AM3 3 Acceptance Mask Bit 3 CIDMR2.AM2 2 Acceptance Mask Bit 2 CIDMR2.AM1 1 Acceptance Mask Bit 1 CIDMR2.AM0 0 Acceptance Mask Bit 0 CIDMR3 0x0117 msCAN12 Identifier Mask Register 3 CIDMR3.AM7 7 Acceptance Mask Bit 7 CIDMR3.AM6 6 Acceptance Mask Bit 6 CIDMR3.AM5 5 Acceptance Mask Bit 5 CIDMR3.AM4 4 Acceptance Mask Bit 4 CIDMR3.AM3 3 Acceptance Mask Bit 3 CIDMR3.AM2 2 Acceptance Mask Bit 2 CIDMR3.AM1 1 Acceptance Mask Bit 1 CIDMR3.AM0 0 Acceptance Mask Bit 0 CIDAR4 0x0118 msCAN12 Identifier Acceptance Register 4 CIDAR4.AC7 7 Acceptance Code Bit 7 CIDAR4.AC6 6 Acceptance Code Bit 6 CIDAR4.AC5 5 Acceptance Code Bit 5 CIDAR4.AC4 4 Acceptance Code Bit 4 CIDAR4.AC3 3 Acceptance Code Bit 3 CIDAR4.AC2 2 Acceptance Code Bit 2 CIDAR4.AC1 1 Acceptance Code Bit 1 CIDAR4.AC0 0 Acceptance Code Bit 0 CIDAR5 0x0119 msCAN12 Identifier Acceptance Register 5 CIDAR5.AC7 7 Acceptance Code Bit 7 CIDAR5.AC6 6 Acceptance Code Bit 6 CIDAR5.AC5 5 Acceptance Code Bit 5 CIDAR5.AC4 4 Acceptance Code Bit 4 CIDAR5.AC3 3 Acceptance Code Bit 3 CIDAR5.AC2 2 Acceptance Code Bit 2 CIDAR5.AC1 1 Acceptance Code Bit 1 CIDAR5.AC0 0 Acceptance Code Bit 0 CIDAR6 0x011A msCAN12 Identifier Acceptance Register 6 CIDAR6.AC7 7 Acceptance Code Bit 7 CIDAR6.AC6 6 Acceptance Code Bit 6 CIDAR6.AC5 5 Acceptance Code Bit 5 CIDAR6.AC4 4 Acceptance Code Bit 4 CIDAR6.AC3 3 Acceptance Code Bit 3 CIDAR6.AC2 2 Acceptance Code Bit 2 CIDAR6.AC1 1 Acceptance Code Bit 1 CIDAR6.AC0 0 Acceptance Code Bit 0 CIDAR7 0x011B msCAN12 Identifier Acceptance Register 7 CIDAR7.AC7 7 Acceptance Code Bit 7 CIDAR7.AC6 6 Acceptance Code Bit 6 CIDAR7.AC5 5 Acceptance Code Bit 5 CIDAR7.AC4 4 Acceptance Code Bit 4 CIDAR7.AC3 3 Acceptance Code Bit 3 CIDAR7.AC2 2 Acceptance Code Bit 2 CIDAR7.AC1 1 Acceptance Code Bit 1 CIDAR7.AC0 0 Acceptance Code Bit 0 CIDMR4 0x011C msCAN12 Identifier Mask Register 4 CIDMR4.AM7 7 Acceptance Mask Bit 7 CIDMR4.AM6 6 Acceptance Mask Bit 6 CIDMR4.AM5 5 Acceptance Mask Bit 5 CIDMR4.AM4 4 Acceptance Mask Bit 4 CIDMR4.AM3 3 Acceptance Mask Bit 3 CIDMR4.AM2 2 Acceptance Mask Bit 2 CIDMR4.AM1 1 Acceptance Mask Bit 1 CIDMR4.AM0 0 Acceptance Mask Bit 0 CIDMR5 0x011D msCAN12 Identifier Mask Register 5 CIDMR5.AM7 7 Acceptance Mask Bit 7 CIDMR5.AM6 6 Acceptance Mask Bit 6 CIDMR5.AM5 5 Acceptance Mask Bit 5 CIDMR5.AM4 4 Acceptance Mask Bit 4 CIDMR5.AM3 3 Acceptance Mask Bit 3 CIDMR5.AM2 2 Acceptance Mask Bit 2 CIDMR5.AM1 1 Acceptance Mask Bit 1 CIDMR5.AM0 0 Acceptance Mask Bit 0 CIDMR6 0x011E msCAN12 Identifier Mask Register 6 CIDMR6.AM7 7 Acceptance Mask Bit 7 CIDMR6.AM6 6 Acceptance Mask Bit 6 CIDMR6.AM5 5 Acceptance Mask Bit 5 CIDMR6.AM4 4 Acceptance Mask Bit 4 CIDMR6.AM3 3 Acceptance Mask Bit 3 CIDMR6.AM2 2 Acceptance Mask Bit 2 CIDMR6.AM1 1 Acceptance Mask Bit 1 CIDMR6.AM0 0 Acceptance Mask Bit 0 CIDMR7 0x011F msCAN12 Identifier Mask Register 7 CIDMR7.AM7 7 Acceptance Mask Bit 7 CIDMR7.AM6 6 Acceptance Mask Bit 6 CIDMR7.AM5 5 Acceptance Mask Bit 5 CIDMR7.AM4 4 Acceptance Mask Bit 4 CIDMR7.AM3 3 Acceptance Mask Bit 3 CIDMR7.AM2 2 Acceptance Mask Bit 2 CIDMR7.AM1 1 Acceptance Mask Bit 1 CIDMR7.AM0 0 Acceptance Mask Bit 0 RESERVED0120 0x0120 RESERVED RESERVED0121 0x0121 RESERVED RESERVED0122 0x0122 RESERVED RESERVED0123 0x0123 RESERVED RESERVED0124 0x0124 RESERVED RESERVED0125 0x0125 RESERVED RESERVED0126 0x0126 RESERVED RESERVED0127 0x0127 RESERVED RESERVED0128 0x0128 RESERVED RESERVED0129 0x0129 RESERVED RESERVED012A 0x012A RESERVED RESERVED012B 0x012B RESERVED RESERVED012C 0x012C RESERVED RESERVED012D 0x012D RESERVED RESERVED012E 0x012E RESERVED RESERVED012F 0x012F RESERVED RESERVED0130 0x0130 RESERVED RESERVED0131 0x0131 RESERVED RESERVED0132 0x0132 RESERVED RESERVED0133 0x0133 RESERVED RESERVED0134 0x0134 RESERVED RESERVED0135 0x0135 RESERVED RESERVED0136 0x0136 RESERVED RESERVED0137 0x0137 RESERVED RESERVED0138 0x0138 RESERVED RESERVED0139 0x0139 RESERVED RESERVED013A 0x013A RESERVED RESERVED013B 0x013B RESERVED RESERVED013C 0x013C RESERVED PCTLCAN 0x013D msCAN12 Port CAN Control Register PCTLCAN.PUPCAN 1 Pull-Up Enable Port CAN PCTLCAN.RDPCAN 0 Reduced Drive Port CAN PORTCAN 0x013E msCAN12 Port CAN Data Register PORTCAN.PCAN7 7 Port CAN Data Bit 7 (not available in 80QFP) PORTCAN.PCAN6 6 Port CAN Data Bit 6 (not available in 80QFP) PORTCAN.PCAN5 5 Port CAN Data Bit 5 (not available in 80QFP) PORTCAN.PCAN4 4 Port CAN Data Bit 4 (not available in 80QFP) PORTCAN.PCAN3 3 Port CAN Data Bit 3 (not available in 80QFP) PORTCAN.PCAN2 2 Port CAN Data Bit 2 (not available in 80QFP) PORTCAN.TxCAN 1 PORTCAN.RxCAN 0 DDRCAN 0x013F msCAN12 Port CAN Data Direction Register DDRCAN.DDCAN7 7 Data Direction Port CAN Bit 7 DDRCAN.DDCAN6 6 Data Direction Port CAN Bit 6 DDRCAN.DDCAN5 5 Data Direction Port CAN Bit 5 DDRCAN.DDCAN4 4 Data Direction Port CAN Bit 4 DDRCAN.DDCAN3 3 Data Direction Port CAN Bit 3 DDRCAN.DDCAN2 2 Data Direction Port CAN Bit 2 ATD1CTL2 0x01E2 ATD1 Control Register 2 ATD1CTL2.ADPU 7 ATD Disable ATD1CTL2.AFFC 6 ATD Fast Flag Clear All ATD1CTL2.AWAI 5 ATD Wait Mode ATD1CTL2.ASCIE 1 ATD Sequence Complete Interrupt Enable ATD1CTL2.ASCIF 0 ATD Sequence Complete Interrupt Flag ATD1CTL3 0x01E3 ATD1 Control Register 3 ATD1CTL3.FRZ1 1 Background Debug (Freeze) Enable 1 ATD1CTL3.FRZ0 0 Background Debug (Freeze) Enable 0 ATD1CTL4 0x01E4 ATD1 Control Register 4 ATD1CTL4.S10BM 7 10 bit Mode ATD1CTL4.SMP1 6 Select Sample Time 1 ATD1CTL4.SMP0 5 Select Sample Time 0 ATD1CTL4.PRS4 4 Select Divide-By Factor for ATD P-Clock Prescaler 4 ATD1CTL4.PRS3 3 Select Divide-By Factor for ATD P-Clock Prescaler 3 ATD1CTL4.PRS2 2 Select Divide-By Factor for ATD P-Clock Prescaler 2 ATD1CTL4.PRS1 1 Select Divide-By Factor for ATD P-Clock Prescaler 1 ATD1CTL4.PRS0 0 Select Divide-By Factor for ATD P-Clock Prescaler 0 ATD1CTL5 0x01E5 ATD1 Control Register 5 ATD1CTL5.S8CM 6 Select 8 Channel Mode ATD1CTL5.SCAN 5 Enable Continuous Channel Scan ATD1CTL5.MULT 4 Enable Multichannel Conversion ATD1CTL5.CD 3 Channel D Select for Conversion ATD1CTL5.CC 2 Channel C Select for Conversion ATD1CTL5.CB 1 Channel B Select for Conversion ATD1CTL5.CA 0 Channel A Select for Conversion ATD1STAT0 0x01E6 ATD1 Status Register 0 ATD1STAT0.SCF 7 Sequence Complete Flag ATD1STAT0.CC2 2 Conversion Counter 2 for Current Sequence of Four or Eight Conversions ATD1STAT0.CC1 1 Conversion Counter 1 for Current Sequence of Four or Eight Conversions ATD1STAT0.CC0 0 Conversion Counter 0 for Current Sequence of Four or Eight Conversions ATD1STAT1 0x01E7 ATD Status Register 1 ATD1STAT1.CCF7 7 Conversion Complete Flag 7 ATD1STAT1.CCF6 6 Conversion Complete Flag 6 ATD1STAT1.CCF5 5 Conversion Complete Flag 5 ATD1STAT1.CCF4 4 Conversion Complete Flag 4 ATD1STAT1.CCF3 3 Conversion Complete Flag 3 ATD1STAT1.CCF2 2 Conversion Complete Flag 2 ATD1STAT1.CCF1 1 Conversion Complete Flag 1 ATD1STAT1.CCF0 0 Conversion Complete Flag 0 ATD1TESTH 0x01E8 ATD1 Test Register H ATD1TESTH.SAR9 7 SAR Data 9 ATD1TESTH.SAR8 6 SAR Data 8 ATD1TESTH.SAR7 5 SAR Data 7 ATD1TESTH.SAR6 4 SAR Data 6 ATD1TESTH.SAR5 3 SAR Data 5 ATD1TESTH.SAR4 2 SAR Data 4 ATD1TESTH.SAR3 1 SAR Data 3 ATD1TESTH.SAR2 0 SAR Data 2 ATD1TESTL 0x01E9 ATD1 Test Register L ATD1TESTL.SAR1 7 SAR Data 1 ATD1TESTL.SAR0 6 SAR Data 0 ATD1TESTL.RST 5 Module Reset Bit ATD1TESTL.TSTOUT 4 Multiplex Output of TST ATD1TESTL.TST3 3 Test Bit 3 ATD1TESTL.TST2 2 Test Bit 2 ATD1TESTL.TST1 1 Test Bit 1 ATD1TESTL.TST0 0 Test Bit 0 RESERVED01EA 0x01EA RESERVED RESERVED01EB 0x01EB RESERVED RESERVED01EC 0x01EC RESERVED RESERVED01ED 0x01ED RESERVED RESERVED01EE 0x01EE RESERVED PORTAD1 0x01EF Port AD1 Data Input Register PORTAD1.PAD17 7 Port AD1 Data Input Bit 7 PORTAD1.PAD16 6 Port AD1 Data Input Bit 6 PORTAD1.PAD15 5 Port AD1 Data Input Bit 5 PORTAD1.PAD14 4 Port AD1 Data Input Bit 4 PORTAD1.PAD13 3 Port AD1 Data Input Bit 3 PORTAD1.PAD12 2 Port AD1 Data Input Bit 2 PORTAD1.PAD11 1 Port AD1 Data Input Bit 1 PORTAD1.PAD10 0 Port AD1 Data Input Bit 0 ADR10H 0x01F0 A/D Conversion Result Register High 0 ADR10L 0x01F1 A/D Conversion Result Register Low 0 ADR11H 0x01F2 A/D Conversion Result Register High 1 ADR11L 0x01F3 A/D Conversion Result Register Low 1 ADR12H 0x01F4 A/D Conversion Result Register High 2 ADR12L 0x01F5 A/D Conversion Result Register Low 2 ADR13H 0x01F6 A/D Conversion Result Register High 3 ADR13L 0x01F7 A/D Conversion Result Register Low 3 ADR14H 0x01F8 A/D Conversion Result Register High 4 ADR14L 0x01F9 A/D Conversion Result Register Low 4 ADR15H 0x01FA A/D Conversion Result Register High 5 ADR15L 0x01FB A/D Conversion Result Register Low 5 ADR16H 0x01FC A/D Conversion Result Register High 6 ADR16L 0x01FD A/D Conversion Result Register Low 6 ADR17H 0x01FE A/D Conversion Result Register High 7 ADR17L 0x01FF A/D Conversion Result Register Low 7